TWI784266B - Semiconductor device and the manufacturing method thereof - Google Patents

Abstract

The present disclosure provides a semiconductor device comprising a substrate, a first semiconductor contact layer disposed on the substrate, an active structure disposed on the first semiconductor contact layer, and an electrode disposed on the first semiconductor contact layer. The first semiconductor contact layer includes a first region, a second region, and a dopant. The active structure is disposed on the first region and not disposed on the second region. The second region further includes a first sub-region and a second sub-region wherein the electrode is disposed on the first sub-region and not disposed on the second sub-region. The first sub-region is lower than the second sub-region. The present disclosure further provides a method for manufacturing the above-mentioned semiconductor device.

Description

Semiconductor element and its manufacturing method

The present disclosure relates to a semiconductor device and a manufacturing method thereof, in particular to a semiconductor device with a processing region and a manufacturing method thereof.

With the development of science and technology, III-V semiconductor materials can be manufactured into various semiconductor components, and are widely used in lighting, medical treatment, display, communication, sensing, power supply systems and other fields. This disclosure proposes a novel semiconductor device and its manufacturing method to improve the electrical properties of the device.

The present disclosure provides a semiconductor element, which includes a substrate, a first semiconductor contact layer on the substrate, an active structure on the first semiconductor contact layer, and an electrode on the active structure. Wherein, the first semiconductor contact layer includes a first region, a second region, and a dopant, and the active structure is located in the first region and not in the second region. Wherein, the second region further includes a first subregion and a second subregion, the electrode is located in the first subregion and not in the second subregion, and the The first sub-section is lower than said second sub-section.

In one embodiment, the active structure includes a quantum well layer including AlxGa1-xN, where 0.05≤x≤0.5. In one embodiment, in a cross section of the semiconductor device, a surface of the first sub-region is 6-30 nm lower than a surface of the second sub-region. In one embodiment, the first sub-region has a cross-sectional shape of approximately a shallow dish. In one embodiment, the second sub-region surrounds the first sub-region. In one embodiment, in a cross section of the semiconductor device, the first sub-region has a processing region extending from a surface of the first sub-region to the substrate. In one embodiment, in the first semiconductor contact layer, a doping concentration of the dopant in the processing region is greater than a doping concentration in a region beyond the processing region. In one embodiment, the first semiconductor contact layer includes AlxGa1-xN, 0.3≤x≤0.7. In one embodiment, the semiconductor device further includes a highly doped semiconductor contact layer formed between the first semiconductor contact layer and the electrode. In one embodiment, the highly doped semiconductor contact layer does not contain aluminum or contains an aluminum content smaller than that of the first semiconductor contact layer. In one embodiment, the first semiconductor contact layer and the highly doped semiconductor contact layer contain the same dopant, and the dopant is in the highly doped semiconductor contact layer A doping concentration is greater than a doping concentration in the first semiconductor contact layer. In one embodiment, the doping concentration of the dopant in the highly doped semiconductor contact layer is greater than the doping concentration in the treatment region of the first semiconductor contact layer .

The disclosure further provides a method for manufacturing a semiconductor device, including providing a substrate, forming a semiconductor contact layer on the substrate, wherein the first semiconductor contact layer includes a first region, a second region, and A dopant, forming an active structure on the first region and the second region of the first semiconductor contact layer, removing the active structure on the second region to expose the first The first semiconductor contact layer of the second region, wherein the second region further includes a first sub-region and a second sub-region, forming a mask on the active structure and the first On the semiconductor contact layer, wherein the mask covers the second sub-region and includes an opening exposing the first sub-region, processing the first sub-region exposed by the opening to form A treatment area, and forming an electrode on the first sub-area, wherein an upper surface of the first sub-area is lower than an upper surface of the second sub-area that has not been processed.

In one embodiment, the step of treating the first sub-region exposed by the opening includes treating the first sub-region with a siloxane plasma. In one embodiment, the step of processing the first sub-region exposed by the opening has an etching rate of 0.1˜0.6 nm/sec for the first semiconductor contact layer.

Please refer to FIG. 1 , which shows a first embodiment of a semiconductor device 10 according to the present disclosure. The semiconductor element 10 is, for example, a light emitting element, comprising a substrate 100, a first semiconductor contact layer 102, an active structure 103 such as a light emitting stack, and a second semiconductor contact layer 104 sequentially formed on the substrate 100, a first electrode 105 and The first semiconductor contact layer 102 is electrically connected, and the second electrode 106 is electrically connected to the second semiconductor contact layer 104 . Specifically, the first semiconductor contact layer 102 includes a first region 102a, a second region 102b, and dopants, wherein the thickness of the first region 102a of the first semiconductor contact layer 102 is greater than the thickness of the second region 102b. The active structure 103 is located in the first area 102a and not located in the second area 102b. The second area further includes a first sub-area 102b1 and a second sub-area 102b2, the first electrode 105 is located in the first sub-area 102b1 and not in the second sub-area 102b2, and the first electrode 105 and the first sub-area 102b1 The semiconductor contact layer 102 forms a good electrical contact, such as an ohmic contact; wherein, the upper surface of the first sub-region 102b1 is lower than the upper surface of the second sub-region 102b2, for example, lower than 6-30 nm, preferably lower than 10~20nm. Wherein, the first sub-region 102b1 has a cross-sectional shape of approximately a shallow dish. In one embodiment, the second sub-region 102b2 surrounds the first sub-region 102b1. As shown in FIG. 1, the first semiconductor contact layer 102 has a treatment region 107 extending from the upper surface of the first sub-region 102b1 to the substrate at a depth in the first sub-region 102b1, wherein the depth is, for example, 0.1-50nm . The dopant of the first semiconductor contact layer 102 contains a first dopant concentration in the processing region 107, the dopant of the first semiconductor contact layer 102 contains a second dopant concentration in a region beyond the processing region 107, and the first dopant The dopant concentration is greater than the second dopant concentration. Preferably, the first doping concentration decreases gradually from the upper surface of the first sub-region 102b1 toward the substrate. In one embodiment, the first semiconductor contact layer 102 includes AlxGa1 _{- xN} , 0.3≤x≤0.7, the dopant is silicon, for example, the first doping concentration is 5*10 ¹⁹ cm ^-3 ~ 5*10 ²⁰ cm ^-3 , the second doping concentration is 10 ¹⁹ cm ^-3 to 10 ²⁰ cm ^-3 . The active structure 103 includes a first carrier blocking layer (carrier blocking layer) 103a located on the first semiconductor contact layer 102, an active layer (active layer) 103b such as a light emitting layer located on the first carrier blocking layer 103a, And a second carrier blocking layer 103c is located on the active layer 103b. Wherein, the first carrier blocking layer 103a has a first conductivity type and the second carrier blocking layer 103c has a second conductivity type opposite to the first conductivity type, wherein the first conductivity type is, for example, n-type and the second conductivity type is, for example, For p-type. The first carrier blocking layer 103a and the second carrier blocking layer 103c are used to confine carriers (electrons and holes) in the active layer 103b to prevent carriers from overflowing out of the active layer 103b to reduce luminous efficiency. The active layer 103b includes a multiple quantum well (Multiple Quantum Wells; MQW) structure, wherein the multiple quantum well structure includes a plurality of barrier layers (barrier layer) 103b1 and a plurality of quantum well layers (quantum well layer) 103b2 stacked alternately, and in Visible light or invisible light is emitted during driving, wherein the number of overlapping pairs is, for example, 3-15 pairs. The material of the quantum well layer 103b1 has an energy band gap corresponding to the wavelength of the emitted light and smaller than the energy band gap of the barrier layer 103b2. Each of the first carrier blocking layer 103a and the second carrier blocking layer 103c has an energy gap higher than that of the quantum well layer 103b1. During driving, carriers (electrons and holes) combine in the quantum well layer 103b1 to emit light of a specific wavelength, such as ultraviolet light with a peak wavelength of 190-400 nm. The first semiconductor contact layer 102 has the same first conductivity type as the first carrier blocking layer 103a and the second semiconductor contact layer 104 has the same second conductivity type as the second carrier blocking layer 103c. The first conductivity type is, for example, n-type and the second conductivity type is, for example, p-type. In one embodiment, the first semiconductor contact layer 102 includes AlxGa1 _{- xN} , 0.3≤x≤0.7, and includes an n-type dopant (such as silicon) and an n-type dopant concentration of 10 ¹⁹ cm ^-3 to 10 ²⁰ cm ^-3 ; the first carrier blocking layer 103a and/or the blocking layer 103b1 includes an n-type dopant (such as silicon) and an n-type dopant concentration, such as ^{10 18 cm - 3} ~ 10 ¹⁹ cm ^-3 , less than the doping concentration of the first semiconductor contact layer 102; the quantum well layer 103b1 contains unintentionally doped (unintentionally doped) Al _x Ga _1–xN (0.05 ≤ x ≤ 0.5) and has a The thickness is between 1~5 nm, and the barrier layer 103b2, for example, includes doped or unintentionally doped AlxGa1 _{- xN} (0.3≤x≤0.7) and has a thickness between 5~15 nm; The second carrier blocking layer 103c includes Al _x Ga _1-x N, 0.3≤x≤0.7, and includes a p-type dopant (such as magnesium) and a p-type dopant concentration, such as 10 ^{1 7} cm ^{- 3} to 10 ¹⁸ cm ^-3 , less than the doping concentration of the second semiconductor contact layer 102; the second semiconductor contact layer 104 includes GaN, and includes a p-type dopant (such as magnesium) and a p-type dopant concentration of 10 ¹⁹ cm ^-3 ～5*10 ²⁰ cm ^-3 .

Please refer to FIG. 2, which shows a second embodiment of a semiconductor device according to the present disclosure. In this embodiment, the components having the same names or labels as those in the first embodiment represent corresponding components, which have the same characteristics and properties such as structure, composition material and function, and their specific descriptions, if not specifically described in this For the embodiment, reference may be made to the content of the first embodiment, and details are not repeated here. The main difference between this embodiment and the first embodiment is that the semiconductor element 20 includes all components of the first embodiment and further includes a highly doped semiconductor contact layer 108 formed between the first semiconductor contact layer 102 and the first electrode 105, Wherein, the highly doped semiconductor contact layer 108 does not contain aluminum or contains an aluminum content smaller than that of the first semiconductor contact layer 102 . In one embodiment, the highly doped semiconductor contact layer 108 includes AlxGa1 _{- xN} (0>x≤0.3) or GaN, and includes an n-type dopant (such as silicon) and a third dopant concentration , for example, 10 ²⁰ cm ^-3 to 10 ²¹ cm ^-3 , wherein the third doping concentration is greater than the first doping concentration, preferably, the third doping concentration is greater than the first doping concentration and the second doping concentration .

Please refer to FIG. 3A-3E and FIG. 1, which shows the manufacturing method of the semiconductor device according to the first embodiment of the present disclosure, which includes the following steps (steps S1~S3 please refer to FIG. 3A, step S4 please refer to FIG. 3B, For steps S5~S6, please refer to Figure 3C, for step S7, please refer to Figure 3D, for step S8, please refer to Figure 3E, for steps S9~S10, please refer to Figure 1): S1. Please refer to Figure 3A to provide a substrate 100; S2. Forming a first semiconductor contact layer 102 on the substrate 100, wherein the first semiconductor contact layer 102 includes a first region 102a and a second region 102b; S3. Forming the active structure 103 and the second semiconductor contact layer 104 on the first region 102a and the second region 102b of the first semiconductor contact layer 102; S4. Referring to FIG. 3B, a first mask MK1 is formed on the second semiconductor contact layer 104, wherein the first mask MK1 is correspondingly formed on the first region 102a of the first semiconductor contact layer 102; S5. Please refer to FIG. 3C, etch and remove the active structure 103 and the second semiconductor contact layer 104 corresponding to the second region 102b to expose the second region 102b of the first semiconductor contact layer 102, wherein the second region 102b further includes the first sub-area 102b1 and the second sub-area 102b2; S6. Remove the first mask M1; S7. Referring to FIG. 3D, a second mask MK2 is formed on the second semiconductor contact layer 104 and the second region 102b of the first semiconductor contact layer 102, wherein the second mask MK2 covers the second sub-region 102b2 and includes an opening exposing the first sub-region 102b1; S8. Referring to Figure 3E, process the first sub-area 102b1 exposed by the opening; S9. Removing the second mask MK2; and S10. Forming the first electrode 105 on the processed first sub-region 102b1 and forming the second electrode 106 on the second semiconductor contact layer 104, so as to form the semiconductor device 10 as shown in FIG. 1 .

Please refer to FIG. 3A-3F and FIG. 2, showing the manufacturing method of the semiconductor device according to the second embodiment of the present disclosure, which includes the following steps (steps S1~S3 please refer to FIG. 3A, and step S4 please refer to FIG. 3B , Steps S5~S6, please refer to Figure 3C, Step S7, please refer to Figure 3D, Step S8, please refer to Figure 3E, Step S9, please refer to Figure 3F, Steps S10-S11, please refer to Figure 2): S1. Please refer to Figure 3A to provide a substrate 100; S2. forming a first semiconductor contact layer 102 on the substrate 100, wherein the first semiconductor contact layer 102 includes a first region 102a and a second region 102b; S3. Forming the active structure 103 and the second semiconductor contact layer 104 on the first region 102a and the second region 102b of the first semiconductor contact layer 102; S4. Referring to FIG. 3B, a first mask MK1 is formed on the second semiconductor contact layer 104, wherein the first mask MK1 is correspondingly formed on the first region 102a of the first semiconductor contact layer 102; S5. Please refer to FIG. 3C, etch and remove the active structure 103 and the second semiconductor contact layer 104 corresponding to the second region 102b to expose the second region 102b of the first semiconductor contact layer 102, wherein the second region 102b further includes the first sub-area 102b1 and the second sub-area 102b2; S6. Remove the first mask MK1; S7. Referring to FIG. 3D, a second mask MK2 is formed on the active structure 103 and the second region 102b of the first semiconductor contact layer 102, wherein the second mask MK2 covers the second sub-region 102b2 and includes an opening exposed the first sub-area 102b1; S8. Referring to Figure 3E, process the first sub-area 102b1 exposed by the opening; S9. Please refer to FIG. 3F, forming a highly doped semiconductor contact layer 108 in the processed first sub-region 102b1; S10. Removing the second mask MK2; and S11. Form the first metal electrode 105 on the highly doped semiconductor contact layer 108 and form the second metal electrode 106 on the second semiconductor contact layer 104 to form the semiconductor device 20 as shown in FIG. 2 .

In the manufacturing method described in each of the above embodiments, wherein the step of treating the first sub-region 102b1 exposed by the opening includes treating the first sub-region 102b1 with a plasma, wherein the plasma treatment of the first The etch rate of the first semiconductor contact layer 102 of the sub-region 102b1 is, for example, 0.1-0.6 nm/sec, and the processing time is, for example, 30-90 sec. The plasma treatment makes the upper surface of the first sub-region 102b1 lower than the upper surface of the second sub-region 102b2, for example, lower than 6-30 nm, preferably lower than 10-20 nm. Wherein, the first sub-region 102b1 has a cross-sectional shape of approximately a shallow dish. The plasma treatment makes the first semiconductor contact layer 102 form a treatment region 107 in the first sub-region 102b1, wherein the range of the treatment region 107 extends from the upper surface of the first sub-region 102b1 to a depth to the substrate, wherein, The said depth is, for example, 0.1-50 nm. In one embodiment, the plasma contains the same elements as the dopant of the first semiconductor contact layer 102, for example, the plasma contains silane (SiCl ₄ ) plasma and the dopant contains Silicon (Si). The plasma treatment makes the dopant of the first semiconductor contact layer 102 contain the first dopant concentration in the treatment region 107, and the dopant of the first semiconductor contact layer 102 contains the second dopant concentration in the region beyond the treatment region 107. impurity concentration, and the first doping concentration is greater than the second doping concentration. Preferably, the first doping concentration decreases gradually from the upper surface of the first sub-region 102b1 toward the substrate. In one embodiment, the first semiconductor contact layer 102 includes AlxGa1 _{- xN} , 0.3≤x≤0.7, the dopant is silicon, for example, the first doping concentration is 5*10 ¹⁹ cm ^-3 ~ 5*10 ²⁰ cm ^-3 , the second doping concentration is 10 ¹⁹ cm ^-3 to 10 ²⁰ cm ^-3 . The step of forming the highly doped semiconductor contact layer 108 on the processed first sub-region 102b1 is directly epitaxially grown on the exposed surface of the first sub-region 102b1 by, for example, metal organic chemical vapor deposition (MOCVD).

Please refer to FIG. 4, which shows a semiconductor device according to the third embodiment of the present disclosure. The semiconductor element 40 includes all the structures of the semiconductor element 10 of the first embodiment or the semiconductor element 20 of the second embodiment, and further includes an electrical insulating layer 409 covering the second semiconductor contact layer 104, the first electrode 105, and the second electrode 106 , wherein the electrical insulation layer 409 has openings that respectively expose a part of the upper surface of the first electrode 105 and the second electrode 106 so that the first electrode pad 410 and the second electrode pad 411 respectively fill the opening and are connected to the first electrode 105 and the second electrode 106. The second electrode 106 is electrically connected. In one embodiment, the electrical insulation layer 409 includes a plane, and the first electrode pad 410 and the second electrode pad 411 extend to cover the plane of the electrical insulation layer 409 . In one embodiment, the projected areas of the first electrode pad 410 and the second electrode pad 411 on the substrate 100 are substantially equal. In one embodiment, the ratio of the projected area of the first electrode 105 and the second electrode 106 on the substrate 100 to the area of the substrate 100 is about 0.6˜0.95. The first electrode pad 410 and the second electrode pad 411 are used to electrically connect to other components or external power sources.

In each of the above-mentioned embodiments, the substrate 100 is an epitaxial substrate, such as a sapphire substrate, and the first semiconductor contact layer 102, the active structure 103, the second semiconductor contact layer 104, and the highly doped semiconductor contact layer 108 are transparent For example, the epitaxy is grown on the substrate 100 by metal organic chemical vapor deposition (MOCVD). In one embodiment, the main light-emitting surface of the semiconductor element is emitted toward the back of the substrate 100, and the material of the substrate is transparent to the light emitted by the active layer 103a; in another embodiment, the main light-emitting surface of the semiconductor element is directed toward the second semiconductor The contact layer 104 emits light, and the material of the substrate 100 can be transparent or opaque to the light emitted by the active layer 103a. In one embodiment, the upper surface of the substrate 100 has a plurality of protrusions separated from each other for changing the path of the light to increase the light extraction efficiency. In one embodiment, the protrusions are formed by directly patterning the surface of the substrate 100 to a depth, and thus have the same composition material as the substrate 100 . In another embodiment, after forming a light-transmitting material layer on the upper surface of the substrate 100, the light-transmitting material layer is patterned to form the protrusions, wherein the protrusions and the substrate 100 have different The constituent materials.

In the above-mentioned embodiments, the first semiconductor contact layer 102, the first carrier blocking layer 103a, the active layer 103b, the second carrier blocking layer 103c, the second semiconductor contact layer 104, and the highly doped semiconductor contact layer 108 Contains the same series of III-V compound semiconductor materials, such as AlInGaN series. Wherein, the AlInGaN series can be expressed as (Al _x1 In _(1-x1) ) _1-x2 Ga _x2 N, where 0≦x ₁ ≦1, 0≦x ₂ ≦1. The light emitted by the semiconductor device depends on the material composition of the active layer 103b. For example, when the material of the active layer 103b includes AlGaN series, it can emit ultraviolet light with a peak wavelength of 190 nm~400 nm.

In each of the above-mentioned embodiments, the first electrode 105 and the second electrode 106 are composed of a single-layer or multi-layer metal structure, such as chromium (Cr), titanium (Ti), tungsten (W), silver (Ag), gold ( Au), aluminum (Al), indium (In), tin (Sn), nickel (Ni), platinum (Pt), or alloys of the above materials, preferably, include a light emitting element having a ratio greater than 80% to the light emitted by the active layer 103b. Reflective metals, such as silver (Ag), aluminum (Al), or platinum (Pt). The first electrode pad 410 and the second electrode pad 411 comprise at least one material selected from nickel (Ni), titanium (Ti), platinum (Pt), palladium (Pd), silver (Ag), gold (Au), aluminum ( A group consisting of Al) and copper (Cu). The first electrode pad 410 and the second electrode pad 411 are used as welding pads to connect to external circuits.

In the above-mentioned embodiments, the first mask MK1 and the second mask MK2 include dielectric materials such as tantalum oxide (TaOx), aluminum oxide ( _AlOx ), silicon dioxide ( _SiOx ), titanium oxide (TiO _x ), niobium oxide (Nb ₂ O ₅ ), silicon nitride (SiN _x ), or spin-on-glass (SOG). The electrically insulating layer 409 includes a dielectric material and may include a distributed Bragg reflector (DBR; Distributed Bragg Reflector) structure, wherein the DBR structure includes a plurality of first dielectric layers and a plurality of second dielectric layers. The layers overlap each other, and the first dielectric layer and the second dielectric layer have different refractive indices. When the light emitted by the semiconductor element is extracted through the substrate 100, the electrically insulating layer 409 includes a dielectric material The inclusion of the DBR structure helps to reflect light out towards the substrate 100 to increase the luminous efficiency of the semiconductor device.

Please refer to FIG. 5 , which shows a semiconductor light-emitting device according to the disclosure of flip-chip bonding of a semiconductor device to a carrier. The semiconductor light emitting component 50 includes a plurality of semiconductor elements 40 of the third embodiment, a carrier board 500, a first wire 501, a second wire 502, a first welding pad 503, and a second welding pad 504 located on the carrier board 500 and electrically connected A plurality of semiconductor devices 40 and a transparent protection structure 505 cover the semiconductor devices 40 and the carrier 500 . Wherein, the first wire 501 includes a plurality of first protrusions 501a facing the second wire 502, the second wire 502 includes a plurality of second protrusions 502a facing the first wire 501, and the plurality of first protrusions 501a are The plurality of second protrusions 502a correspond one-to-one. The first electrode pad 410 and the second electrode pad 411 of each semiconductor element 40 are respectively connected to a corresponding first protrusion 501a and second protrusion 502a so that a plurality of light emitting diode elements 40 are connected in parallel to each other. on the carrier board 500. The first pad 503 and the second pad 504 are respectively electrically connected to the first wire 501 and the second wire 502 for electrically connecting to other components or an external power source. The carrier 500 is, for example, a package submount or a printed circuit board (PCB); the first wire 501, the second wire 502, the first pad 503, and the second pad 504 include a single layer or multilayer structure and includes at least one material selected from nickel (Ni), titanium (Ti), platinum (Pt), palladium (Pd), silver (Ag), gold (Au), aluminum (Al) and copper (Cu) composed of groups. The transparent protective structure 505 is composed of a transparent dielectric material, for example, an organic transparent dielectric material is selected from Su8, benzocyclobutene (BCB), perfluorocyclobutane (PFCB), silicone, epoxy Resin (Epoxy), acrylic resin (Acrylic Resin), cycloolefin polymer (COC), polymethyl methacrylate (PMMA), polyethylene terephthalate (PET), polycarbonate (PC), poly A group consisting of Polyetherimide and Fluorocarbon Polymer, or inorganic transparent dielectric materials including materials selected from aluminum oxide (Al2O3), silicon nitride (SiNx), oxide A group consisting of silicon (SiOx), titanium oxide (TiOx), and magnesium fluoride (MgFx).

10,20,40: Semiconductor optical components 100: Substrate 102: the first semiconductor contact layer 102a: District 1 102b: Second District 102b1: The first sub-area 102b2: Second sub-area 103:Active structure 103a: the first carrier blocking layer 103b: active layer 103b1: Quantum well layer 103b2: Barrier layer 103c: second carrier blocking layer 104: the second semiconductor contact layer 105: the first electrode 106: second electrode 107: Processing area 108: Highly doped semiconductor contact layer 409: electrical insulating layer 410: first electrode pad 411: second electrode pad 50:Semiconductor light emitting components 500: carrier board 501: First wire 501a: first protrusion 502: second wire 502a: second protrusion 503: The first welding pad 504: Second welding pad 505: transparent protective structure MK1: First Mask MK2: Second Mask

FIG. 1 is a schematic diagram showing a first embodiment of a semiconductor device according to the present disclosure.

FIG. 2 is a schematic diagram showing a second embodiment of a semiconductor device according to the present disclosure.

3A-3F are schematic diagrams showing a method of manufacturing a semiconductor device according to the present disclosure.

FIG. 4 is a schematic diagram showing a third embodiment of a semiconductor device according to the present disclosure.

FIG. 5 is a schematic diagram showing a semiconductor device consistent with the present disclosure.

10: Semiconductor components

100: Substrate

102: the first semiconductor contact layer

102a: District 1

102b: Second District

102b1: The first sub-area

102b2: Second sub-area

103:Active structure

103a: the first carrier blocking layer

103b: active layer

103b1: Quantum well layer

103b2: Barrier layer

103c: second carrier blocking layer

104: the second semiconductor contact layer

105: the first electrode

106: second electrode

107: Processing area

Claims (10)

A semiconductor element, comprising: a substrate; a first semiconductor contact layer located on the substrate, including a first region, a second region, and a dopant; an active structure located in the first region and not located in the first region Two regions, wherein the second region further includes a first subregion and a second subregion; and an electrode is located in the first subregion; wherein the first subregion has a recess that is lower than the second sub-region, and the recessed portion is only located in the first semiconductor contact layer. The semiconductor device as claimed in item 1, wherein the active structure comprises a quantum well layer comprising AlxGa1 _{- xN} , wherein, 0.05

x

0.5. The semiconductor device according to claim 1, wherein, in a cross section of the semiconductor device, a surface of the first sub-region is 6-30 nm lower than a surface of the second sub-region. The semiconductor device as claimed in claim 1, wherein the second sub-region surrounds the first sub-region. The semiconductor element as claimed in claim 1, wherein, in a section of the semiconductor element, the first sub-region has a processing region extending from a surface of the first sub-region to the substrate, wherein, in the first semiconductor In the contact layer, a doping concentration of the dopant in the processing region is greater than a doping concentration in a region beyond the processing region. The semiconductor device as claimed in claim 1, wherein the first semiconductor contact layer comprises AlxGa1 _{- xN} , wherein, 0.3

x

0.7. The semiconductor device as claimed in claim 1, further comprising a highly doped semiconductor contact layer formed between the first semiconductor contact layer and the electrode, wherein the highly doped semiconductor contact layer does not contain aluminum or contains an aluminum content less than an aluminum content of the first semiconductor contact layer. The semiconductor device according to claim 7, wherein the first semiconductor contact layer and the highly doped semiconductor contact layer contain the same dopant, and the dopant is doped in one of the highly doped semiconductor contact layers The concentration is greater than a doping concentration in the first semiconductor contact layer. A method for manufacturing a semiconductor element, comprising: providing a substrate; forming a semiconductor contact layer on the substrate, wherein the first semiconductor contact layer includes a first region, a second region, and a dopant; forming a An active structure is on the first region and the second region of the first semiconductor contact layer; the active structure on the second region is removed to expose the first semiconductor contact layer of the second region, wherein the The second region further includes a first subregion and a second subregion; a mask is formed on the active structure and the first semiconductor contact layer, wherein the mask covers the second subregion and includes an opening to expose the the first sub-region; processing the first sub-region exposed by the opening to form a processing region; and forming an electrode on the first sub-region, wherein an upper surface of the first sub-region is lower than the untreated treating the upper surface of one of the second sub-regions. The manufacturing method as claimed in claim 9, wherein the step of treating the first sub-region exposed by the opening comprises treating the first sub-region with a silane plasma.

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