TW201929258A - Light-emitting element - Google Patents

Abstract

A light-emitting device, includes: a first semiconductor layer; a second semiconductor layer formed on the first semiconductor layer; a third semiconductor layer formed on the second semiconductor layer; an active layer formed between the second and the third semiconductor layers; an exposed region, passing through the third semiconductor layer and the active layer to expose a first surface of the first semiconductor layer and a second surface of the second semiconductor layer; and a first electrode, formed in the exposed region and contacting the first surface and the second surface; wherein the first semiconductor layer and the second semiconductor layer have different resistances.

Description

Light-emitting element

The present invention relates to a light-emitting device, and more particularly to a light-emitting element having high brightness.

A light-emitting diode (LED) is a photoelectric element composed of a P-type semiconductor and an N-type semiconductor, and emits light through a combination of PN junction uploaders, and has a small volume, low power consumption, and long life. The advantages of fast response, etc., are widely used in optical display devices, traffic signs, data storage devices, communication devices, lighting devices and medical equipment.

A light emitting device comprising: a first semiconductor layer; a second semiconductor layer on the first semiconductor layer; a third semiconductor layer on the second semiconductor layer; and an active layer on the second semiconductor layer and Between the three semiconductor layers; an exposed region, passing through the third semiconductor layer and the active layer, exposing a first surface of the first semiconductor layer and a second surface of the second semiconductor layer; and a first electrode located in the exposed region And contacting the first surface and the second surface; wherein the first semiconductor layer and the second semiconductor layer have different resistance values.

The embodiments of the application are described in detail and are drawn in the drawings, and the same or the like

Fig. 1A is a modification A of the upper view of a light-emitting element 1 disclosed in the first embodiment of the present application. Fig. 1B is a side view of the B-B' section of the modification A in Fig. 1A, and Fig. 1C is a partial enlarged view of the region R in Fig. 1B.

Referring to FIGS. 1A to 1C, the light-emitting element 1 of Modification A of the first embodiment includes a substrate 10, and a semiconductor structure 20 is disposed on the upper surface 10a of the substrate 10. The semiconductor structure 20 includes a first semiconductor layer 201, a second semiconductor layer 202, an active layer 204, and a third semiconductor layer 203 sequentially from the upper surface 10a of the substrate 10. In the semiconductor structure 20, an exposed region 28 is formed, extending downward from the upper surface 203a of the third semiconductor layer 203, passing through the third semiconductor layer 203 and the active layer 204, exposing the upper surface TS1 of the first semiconductor layer 201 and a side surface LS1, and an upper surface TS2, an upper side surface LS2, and a lower side surface LS2' of the second semiconductor layer 202, wherein the upper surface TS1 of the first semiconductor layer 201 has a width W1 as viewed from the side of the cross section; The side surface LS1 of the first semiconductor layer 201 and the lower side surface LS2' of the second semiconductor layer 202 are connected, and the upper surface TS1 of the first semiconductor layer 201 and the upper surface TS2 of the second semiconductor layer 202 are substantially parallel.

In an embodiment of the present application, the exposed region 28 may be formed by a plurality of etching processes. For example, in the first etching process, a portion of the region is selected from the upper surface 203a of the third semiconductor layer 203. The third semiconductor layer 203, the active layer 204, and the second semiconductor layer 202 underneath are removed, up to a depth of one of the second semiconductor layers 202, exposing the upper surface TS2 of the second semiconductor layer 202 and the upper side surface LS2. In one embodiment, the etch depth is between 0.8 and 1.5 μm from the upper surface 203a. Next, in the second etching process, a portion of the region from the upper surface TS2 of the second semiconductor layer 202 is selected, and the second semiconductor layer 202 and the first semiconductor layer 201 below it are removed downward until the first semiconductor One of the layers 201 is deep to expose the upper surface TS1 and the side surface LS1 of the first semiconductor layer 201, and the lower side surface LS2' of the second semiconductor layer 202. In one embodiment, the etch depth is between 0.2 and 1 μm from the upper surface TS2 of the second semiconductor layer 202. In the present embodiment, the upper surface TS1 of the first semiconductor layer 201 is closer to the substrate 10 than the interface between the first semiconductor layer 201 and the second semiconductor layer 202.

In an embodiment of the present application, the substrate 10 includes an insulating substrate or a conductive substrate. When the substrate 10 is a conductive substrate, a germanium insulating region may exist between the substrate 10 and the semiconductor structure 20 thereon to avoid Leakage current is generated. The insulating substrate comprises a sapphire (Al ₂ O ₃ ) wafer for growing indium gallium nitride (InGaN); the conductive substrate comprises a gallium arsenide (GaAs) wafer for growing aluminum gallium indium phosphide (AlGaInP), or A gallium nitride (GaN) wafer, a bismuth (Si) wafer, or a tantalum carbide (SiC) wafer in which an indium gallium nitride (InGaN) is grown. The surface 10a on the substrate 10 to be formed on the semiconductor structure 20 may include a patterned structure 101, thereby improving the epitaxial quality of the semiconductor structure 20 or improving the light extraction efficiency of the light-emitting element 1.

In an embodiment of the present application, another semiconductor layer may be further included between the substrate 10 and the first semiconductor layer 201, for example, including a buffer structure (not shown). The buffer structure can slow the mismatch of the lattice constant between the substrate 10 and the semiconductor structure 20, or help stress release to improve the epitaxial quality.

Forming Semiconductor Structure 20 on Substrate 10 The method of including a buffer structure includes a deposition process. The deposition includes epitaxial (Epitaxy) and physical vapor deposition (PVD). Epitaxial crystals include molecular beam epitaxy (MBE), organometallic vapor epitaxy (MOVPE), vapor phase epitaxial growth (VPE) or liquid phase epitaxial growth (LPE); physical vapor deposition includes evaporation (evaporator) or sputter.

In the present application, the first semiconductor layer 201, the second semiconductor layer 202, the active layer 204, or the third semiconductor layer 203 in the semiconductor structure 20 may be a single layer or include a plurality of sub-layers. The material of the semiconductor structure 20 comprises a III-V semiconductor material, such as Al _x In _y Ga _(1-xy) N or Al _x In _y Ga _(1-xy) P, where 0 ≦ x, y ≦ 1; (x+ y) ≦1. According to the material of the active layer 204, when the material of the semiconductor structure 20 is AlInGaP series material, red light with a wavelength between 610 nm and 650 nm and green light with a wavelength between 530 nm and 570 nm can be emitted as a semiconductor. When the structure 10 material is InGaN series material, blue light with wavelength between 450 nm and 490 nm can be emitted, or when the semiconductor structure 20 material is AlN, AlGaN, AlGaInN series materials, the wavelength can be emitted at 400 nm and 250 Blue-violet or invisible ultraviolet light between nm. The choice of III-V semiconductor materials is not limited to this, and materials other than the above may be selected to generate non-visible light in other wavelength bands, such as infrared light or far infrared light. The active layer 204 may be a single heterostructure (SH), a double heterostructure (DH), a double-side double heterostructure (DDH), or a multi-quantum well structure. MQW). The active layer material may be a semiconductor that is not doped with a dopant, doped with a p-type dopant, or doped with an n-type dopant.

The first and second semiconductor layers 201 and 202 have the same conductivity, electrical properties, polarity or dopant, and the third semiconductor layer 203 and the first and second semiconductor layers 201, 202 have different electrical conductivity and electrical properties. , polarity or dopant. Taking the embodiment as an example, the third semiconductor layer 203 can provide a hole for the p-type, and the first and second semiconductor layers 201 and 202 can provide electrons for the n-type, so that the electrons and the holes can be combined in the active layer 204. Produce light. In one embodiment, the thickness of the second semiconductor layer 202 is less than the thickness of the first semiconductor layer 201, for example, the thickness of the second semiconductor layer 202 is less than 1 μm. The first and second semiconductor layers 201 and 202 have different resistance values, and the materials and implementations thereof will be described in detail later.

The resistance of the first semiconductor layer 201 may be higher or lower than the second semiconductor layer 202. In one embodiment, the first and second semiconductor layers 201 and 202 comprise the same conductive dopant of the same material and different doping concentrations; here, the same material means that the composition of the material other than the dopant in the semiconductor is the same . For example, the first semiconductor layer 201 and the second semiconductor layer 202 are respectively n-type GaN having different germanium doping concentrations. In one embodiment, the resistance of the first semiconductor layer 201 is smaller than that of the second semiconductor layer 202, the first semiconductor layer 201 is n-type GaN with a germanium doping concentration of 2×10 ¹⁹ cm ⁻³ , and the second semiconductor layer 202 is germanium. The doping concentration is 1.3×10 ¹⁹ cm ⁻³ of n-type GaN; in another embodiment, the first semiconductor layer 201 has a resistance greater than the second semiconductor layer 202 , and the first semiconductor layer 201 has a germanium doping concentration of 8×10. ¹⁸ cm ^-3 of n-type GaN, and the second semiconductor layer 202 is n-type GaN having a germanium doping concentration of 1.3 × 10 ¹⁹ cm ^-3 .

In another embodiment, the first and second semiconductor layers 201 and 202 comprise different materials, for example, the first semiconductor layer 201 is n-type AlGaN, and the second semiconductor layer 202 is n-type GaN; or the first and second The semiconductor layers 201 and 202 are respectively n-type AlGaNs having different aluminum contents, wherein the first semiconductor layer 201 has a higher aluminum content than the second semiconductor layer 201. In one embodiment, the resistance of the first semiconductor layer 201 is smaller than that of the second semiconductor layer 202. For example, the first semiconductor layer 201 is an n-type Al _x Ga _1-x N having a germanium doping concentration of a×10 ¹⁹ cm ⁻³ . The second semiconductor layer 202 is an n-type Al _y Ga _1-y N having an erbium doping concentration of b × 10 ¹⁹ cm ^-3 , where a > b, 10 > a > 0.5, and x > y. In addition, the first and second semiconductor layers 201 and 202 may have the same conductive dopant of different or the same doping concentration. In one embodiment, the resistance of the first semiconductor layer 201 is smaller than that of the second semiconductor layer 202. For example, the first semiconductor layer 201 is an n-type AlGaN with a germanium doping concentration of 2×10 ¹⁹ cm ⁻³ , and the second semiconductor layer 202 . It is an n-type GaN having a doping concentration of 5 × 10 ¹⁸ cm ^-3 to 7 × 10 ¹⁸ cm ^-3 .

In another embodiment, the first semiconductor layer 201 may include a superlattice structure, such as a superlattice structure of two sub-layers of AlGaN/GaN, or a semiconductor formed by modulation doping in a single semiconductor material. Floor.

A first electrode 30 is located in the exposed region 28 while contacting the first semiconductor layer 201 and the second semiconductor layer 202 having different resistance values. As shown in FIGS. 1B and 1C, the first electrode 30 contacts the upper surface TS1 and the side surface LS1 of the first semiconductor layer 201, and the upper surface TS2 and the lower side surface LS2' of the second semiconductor layer 202, and the first electrode 30 There is a gap between the upper side surface LS2 and the upper side surface LS2. In the present embodiment, the first electrode 30 is a first wire bonding pad having a width W _N in a top view, and the upper surface TS1 has a similar pattern shape as the first electrode 30. The upper surface TS1 includes a first contact region C _{1 in} contact with the first electrode 30, and the upper surface TS2 includes a second contact region C _{2 in} contact with the first electrode 30. The area of the first contact area C ₁ is not equal to the area of the second contact area C ₂ . In the variation A of the first embodiment, the width W _{N of the} first electrode 30 is larger than the width W ₁ of the upper surface TS1, the area of the first contact area C ₁ is equal to the area of the upper surface TS1, and the area of the first contact area C ₁ is larger than Second contact area C ₂ area. In one embodiment, the resistance of the first semiconductor layer 201 is larger than the second semiconductor layer 202, first contact regions C ₁ and the second area is greater than or equal to the area of the contact region C _2. In one embodiment, the resistance of the first semiconductor layer 201 is smaller than the second semiconductor layer 202, a first area of the contact regions C ₁ and C ₂ is larger than the area of the second contact region.

In another embodiment of the present application, the area of the first contact area C ₁ is smaller than the area of the second contact area C ₂ . In one embodiment, the resistance of the first semiconductor layer 201 is larger than the second semiconductor layer 202, a first area of the contact regions C ₁ and C ₂ is smaller than the area of the second contact region. In one embodiment, the resistance of the first semiconductor layer 201 is smaller than the second semiconductor layer 202, first contact regions C ₁ and the second area is less than or equal to the area of the contact region C _2.

The upper surface 203a of the third semiconductor layer 203 has a current blocking layer 60. In one embodiment, the current blocking layer 60 includes an opening 60a exposing a portion of the upper surface 203a. The current blocking layer 60 may comprise a single layer of dielectric material or a dielectric material laminated by a complex group of dielectric materials having different refractive indices are stacked one composition, which material may include, but are not limited to silicon oxide _(X-of SiO), silicon nitride (Si ₃ N ₄ ), alumina (Al ₂ O ₃ ), titanium oxide (Ti _X O _Y ), tantalum pentoxide (Ta ₂ O ₅ ), niobium oxide (Nb ₂ O ₅ ), zirconium oxide (ZrO _{2 )} ) or a combination of the foregoing materials. The current blocking layer 60 is transparent to the light emitted by the active layer 204.

A transparent conductive layer 18 covers the upper surface 203a of the third semiconductor layer 203, is in electrical contact with the third semiconductor layer 203, and simultaneously covers the current blocking layer 60. The transparent conductive layer 18 may be a metal or a transparent conductive material, wherein the metal may be selected from a light-transmissive thin metal layer transparent to the light emitted by the active layer 204, including indium tin oxide (ITO), Materials such as aluminum zinc oxide (AZO), gallium zinc oxide (GZO), or indium zinc oxide (IZO). The transparent conductive layer 18 has an opening 18a corresponding to the opening 60a of the current blocking layer 60. In one embodiment, the transparent conductive layer 18 covers only the upper surface 203a of the third semiconductor layer 203, is in electrical contact with the third semiconductor layer 203, but does not cover the current blocking layer 60, and the transparent conductive layer 18 and the current blocking layer. There is a gap between 60.

A second electrode 40 is disposed on the current blocking portion 60, the transparent conductive layer 18, and the third semiconductor layer 203, and is electrically connected to the transparent conductive layer 18 and the third semiconductor layer 203. The second electrode 40 includes a second wire pad 401 and a second extension electrode 402 extending from the second wire pad 401. Compared with the second extension electrode 402, the first wire pad of the first electrode 30 and the second wire pad 401 of the second electrode 40 have a wide width, and can be used for wire bonding and external power or external electronics in subsequent processes. The components are electrically connected. The second electrode 40 is located at a corresponding position of the current blocking portion 60, and the outer contour of the second electrode 40 may be equal to or slightly smaller than the outer contour of the current blocking portion 60. In the present embodiment, the position of the second bonding pad 401 corresponds to the opening 60a of the current blocking layer 60 and the opening 18a of the transparent conductive layer 18, and passes through the openings to be in contact with the third semiconductor layer 203. The material of the first electrode 30 and the second electrode 40 includes a metal such as chromium (Cr), titanium (Ti), gold (Au), aluminum (Al), copper (Cu), tin (Sn), nickel (Ni), A metal such as rhodium (Rh) or platinum (Pt) or an alloy or laminate of the above materials. A metal material having a higher reflectivity may be selected on the surface of the first electrode 30 and the second electrode 40 adjacent to the semiconductor structure 20 to form a mirror to enhance light output, where the higher reflectivity refers to the active layer. The wavelength of the light emitted by 204 has a reflectivity of 80% or more. The higher reflectivity metal material includes, for example, aluminum (Al) or silver (Ag).

In another embodiment of the present application, the light-emitting element 1 does not have the current blocking layer 60, and the second wire pad 401 is in contact with the third semiconductor layer 203 via the opening 18a of the transparent conductive layer 18.

In another embodiment of the present application, the current blocking layer 60 does not have an opening 60a. The transparent conductive layer 18 covers a portion of the upper surface and the sidewall of the current blocking layer 18. The opening 18a of the transparent conductive layer 18 exposes the second bonding pad 401. Directly below the upper surface of the current blocking layer 60, the second bonding pad 401 is brought into contact with the current blocking layer 60 via the opening 18a. The second bonding pad 401 can contact the transparent conductive layer 18 on the sidewall of the opening 18a, or the second bonding pad 401 does not contact the transparent conductive layer 18 on the sidewall of the opening 18a.

In another embodiment of the present application, the current blocking layer 60 does not have an opening 60a, the transparent conductive layer 18 covers a portion of the upper surface and the sidewall of the current blocking layer 18, and the opening 18a of the transparent conductive layer 18 is exposed to the second bonding pad. The upper surface and the sidewall of the current blocking layer 60 directly below the 401 contact the second bonding pad 401 with the current blocking layer 60 but not with the transparent conductive layer 18.

In another embodiment of the present application, the current blocking layer 60 is disposed only under the second wire pad 401, and the second extending electrode 402 does not have the current blocking portion 60.

In another embodiment of the present application, the opening 18a of the transparent conductive layer 18 may be greater than, less than, or equal to the width of the second wire pad 401. When the opening 18a of the transparent conductive layer 18 is larger than the width of the second bonding pad 401, the second bonding pad 401 does not contact the transparent conductive layer 18.

In another embodiment of the present application, the opening 60a of the current blocking layer 60 may be larger than, smaller than or equal to the opening 18a of the transparent conductive layer 18.

A reflective structure (not shown) is selectively disposed on the lower surface 10b of the substrate 10 to reflect light from the semiconductor structure 20 to enhance the light extraction efficiency of the light-emitting element 1. The material of the reflective structure may be a metal material including, but not limited to, copper (Cu), aluminum (Al), tin (Sn), gold (Au), silver (Ag), lead (Pb), titanium (Ti), nickel ( Ni), platinum (Pt), tungsten (W), rhodium (Rh) or an alloy of the above materials. The reflective structure may also be a distributed Bragg reflector (DBR) comprising at least two layers of permeable material layers having different refractive indices. The Bragg reflection structure may be an insulating material or a conductive material, and the insulating material includes, but not limited to, polyammonium (PI), benzocyclobutene (BCB), perfluorocyclobutane (PFCB), magnesium oxide (MgO), Su8. , Epoxy, Acrylic Resin, Cyclic Olefin Polymer (COC), Polymethyl Methacrylate (PMMA), Polyethylene Terephthalate (PET), Polycarbonate (PC) ), polyetherimide, fluorocarbon polymer, glass, alumina (Al ₂ O ₃ ), magnesium oxide (MgO), cerium oxide (SiO _x ), titanium oxide ( TiO ₂ ), lanthanum oxide (Ta ₂ O ₅ ), tantalum nitride (SiN _x ), spin-on glass (SOG) or tetraethoxy decane (TEOS). Conductive materials include, but are not limited to, indium tin oxide (ITO), indium oxide (InO), tin oxide (SnO), cadmium tin oxide (CTO), antimony tin oxide (ATO), aluminum zinc oxide (AZO), zinc tin oxide ( ZTO), gallium zinc oxide (GZO), zinc oxide (ZnO), magnesium oxide (MgO), aluminum gallium arsenide (AlGaAs), gallium nitride (GaN), gallium phosphide (GaP) or indium zinc oxide (IZO) . The reflective structure may also be an omnidirectional reflector (ODR) formed by the permeable material layer and the metal layer.

Fig. 1D is a view showing the light-emitting element 1 of Modification B in the first embodiment. The light-emitting element 1 of the modification B in the first embodiment is similar to the modification A, except that the upper surface TS1 and the first electrode 30 have the same width and pattern shape from the upper side, and the area of the upper surface TS1 and the surface The bottom area of one electrode 30 is the same. The contact surface of the first electrode 30 and the semiconductor structure 20 includes the upper surface TS1 and the side surface LS1 of the first semiconductor layer 201, and the lower side surface LS2' of the second semiconductor layer 202 without contacting the second semiconductor layer 202. Surface TS2.

Fig. 2A is a diagram showing variations C and D of the upper view of one of the light-emitting elements 2 disclosed in the second embodiment of the present application. Fig. 2B is a side view of the BB' section of the variation C in Fig. 2A. The light-emitting element 2 in the second embodiment is similar to the light-emitting element 1, except that the upper surface TS1 of the first semiconductor layer 201 in the modification C is viewed from the upper side as an annular pattern. Increase compared to the light emitting element 1, the light emitting element 2 a first electrode 30 and the second semiconductor layer 202 in contact with the second contact region C ₂ area 201 and the first semiconductor layer in contact with the first contact area of regions C _{1 and} cut back.

The variation D is similar to the modification C, except that the upper surface TS1 of the first semiconductor layer 201 includes a plurality of regions from the top view; that is, the upper surface TS1 includes the annular pattern region TS1a, and one is in the ring shape. The intermediate area TS1b in the pattern area TS1a.

Fig. 3A is a diagram showing variations E and F of the upper view of one of the light-emitting elements 3 disclosed in the third embodiment of the present application. Fig. 3B is a side view of the B-B' section along the variation E or the modification F. The light-emitting element 3 in the third embodiment is similar to the light-emitting element 1, except that, from the top, the upper surface TS1 of the first semiconductor layer 201 in the variations E and F includes two regions TS1' separated from each other, and this The two regions TS1' are separated by a portion of the first semiconductor layer 201 and the second semiconductor layer 202. Therefore, in the upper view of the embodiment, the upper surface TS2 of the second semiconductor layer 202 is strip-shaped between the two regions TS1'. The upper surface TS2 of the strip-shaped second semiconductor layer 202 may be parallel to either edge 11 of the light-emitting element 3 as shown in Variant E, or inclined to either edge 11 of the light-emitting element 3 as shown in Variation F .

Fig. 4A is a variation G to K of the upper view of one of the light-emitting elements 4 disclosed in the fourth embodiment of the present application. The difference of the light-emitting elements 4 of the variations G to K is in the exposed region 28, the contact surface below the first electrode 30; the layers other than the exposed regions 28 have the same structure. Fig. 4B is a side view of the B-B' section of the modification G in Fig. 4A, and Fig. 4C is a side view of the section B-B' of the modification J. The light-emitting element 3 in the third embodiment is similar to the light-emitting element 1, except that, from the top view, the upper surface TS1 of the first semiconductor layer 201 in the variations G to K includes the plurality of regions TS1' separated from each other, and this The complex region TS1' is separated by the upper surface TS2 of the plurality of strip-shaped second semiconductor layers 202. The upper surface TS2 of the strip-shaped second semiconductor layer 202 can be viewed from the upper side as shown by the modification G, parallel or perpendicular to the side edges 11 of the light-emitting element 4 and in a crisscross shape.

In the variation H of the present embodiment, the upper surface TS2 of the plurality of strip-shaped second semiconductor layers 202 is viewed from above, and is crossed and inclined to the side 11 of the light-emitting element 3.

In the variation I of the embodiment, the number of the plurality of regions TS1' is larger than that of the variation H, and the upper surface TS2 of the plurality of strips of the second semiconductor layer 202 is viewed from above, in the shape of a "meter". The complex region TS1' of the surface TS1 is radially arranged.

In the variation J of the embodiment, the upper surface TS2 of the plurality of strip-shaped second semiconductor layers 202 is arranged in a horizontal strip as viewed from above, and the plurality of regions TS1' of the upper surface TS1 are also arranged in a horizontal strip. . In another variation, the plurality of regions TS1' may also be arranged in a strip shape perpendicular to each other or in a strip shape parallel to each other and inclined to the side edges 11.

In the variation K of the embodiment, the upper surface TS2 of the plurality of strips of the second semiconductor layer 202 is arranged in a grid shape from the top view so that the plurality of regions TS1 of the upper surface TS1 of each of the first semiconductor layers 201 'Arranged in an array.

The different first semiconductor layer 201 and the second semiconductor layer 202 are combined with the light-emitting elements of the above-mentioned various modified examples AK, and respectively compared with a control light-emitting element (not shown) for reference comparison, wherein the first electrode of the control light-emitting element Only a single n-type semiconductor layer was contacted, and the preferred results of each set of experiments are detailed in Table 1. In the experimental group of No. 1, the first semiconductor layer 201 is n-type GaN having a germanium doping concentration of 2 × 10 ¹⁹ cm ^-3 , and the second semiconductor layer 202 is an n - type having a germanium doping concentration of 1.3 × 10 ¹⁹ cm ^-3 . GaN, in which case the resistance of the first semiconductor layer 201 is smaller than that of the second semiconductor layer 202. With the current density of 0.5-1.5 A/mm ² in the case of the light-emitting element and the control light-emitting element of the variation example AK, the light-emitting element with the modification E has a higher photoelectric conversion efficiency than the performance of the control light-emitting element (Wall Plug Efficiency, WPE), WPE increased by 1.47%-1.69% compared with the control light-emitting components. In the experimental group No. 2, the first semiconductor layer 201 is n-type GaN having a germanium doping concentration of 8 × 10 ¹⁸ cm ^-3 , and the second semiconductor layer 202 is an n - type having a germanium doping concentration of 1.3 × 10 ¹⁹ cm ^-3 . GaN, in which case the resistance of the first semiconductor layer 201 is greater than that of the second semiconductor layer 202. The light-emitting element and the control light-emitting element of each of the variations have a higher WPE than the control light-emitting element under the current density of 0.5-1.5 A/mm ² , and the light-emitting element of the modified example A has a higher WPE than the control light-emitting element. The increase is 1.2%; and the light-emitting element with the variation K has a lower forward voltage (Vf), and Vf is reduced by 0.021-0.037V compared to the control light-emitting element. In the experimental group of No. 3, when the first semiconductor layer 201 is n-type AlGaN having a germanium doping concentration of 2 × 10 ¹⁹ cm ^-3 , the second semiconductor layer 202 is n with a germanium doping concentration of 7 × 10 ¹⁸ cm ^-3 . Type GaN, in which case the resistance of the first semiconductor layer 201 is smaller than that of the second semiconductor layer 202. The light-emitting element and the control light-emitting element of each of the modified examples have a higher WPE than the control light-emitting element under the current density of 0.5-1.5 A/mm ² , and the light-emitting element of the modified example B has a higher WPE than the control light-emitting element. The increase was 0.26%-0.41%; and the light-emitting element with variation F had a lower Vf, and Vf was reduced by 0.002-0.031V compared to the control light-emitting element. 【Table I】

Fig. 5A is a top view of a light-emitting element 5 disclosed in the fifth embodiment of the present application. Fig. 5B is a side view of the section taken along line B-B' in Fig. 5A. The light-emitting element 5 is similar in structure to the light-emitting element 1 except for the exposed region 28, and therefore will not be described again. The difference is that the exposed region 28 of the light-emitting element 5 is disposed on one short side 12 of the light-emitting element 5 and extends along a long side 13; and the exposed portion 28 is provided with a first electrode 30, including the first wire pad 301 and A first extension electrode 302 extends from the wire pad 301. As in the foregoing embodiment, in addition to forming the upper surface TS1 of the first semiconductor layer 201 in the exposed region 28 corresponding to the position of the first bonding pad 301 by an etching method, the exposed region 28 corresponding to the corresponding position of the first extending electrode 302 may be simultaneously The upper surface TS1 is also formed inside. As shown in FIGS. 5A and 5B, in the exposed region 28 in the direction of the long side 13, the upper surface TS1 of the first semiconductor layer 201 includes a plurality of divided regions TS1', and the plurality of regions TS1' are arranged along the first extending electrode 302. . The contact region of the first extension electrode 301 and the semiconductor structure 20 includes the complex region TS1' of the upper surface TS1 of the first semiconductor layer 201, the side surface LS1 of the first semiconductor layer 201, the second semiconductor layer upper surface TS2, and the lower side surface LS2. '.

The embodiment is not limited thereto, and the exposed region 28 may be disposed in any region of the semiconductor structure 20. The first electrode 30 may include one or more first extension electrodes 301, and the upper surface TS1 of the first semiconductor layer 201 may be disposed on the first Below the wire pad 301 and/or below the first extension electrode 301.

For each of the light-emitting elements in the foregoing embodiments, the first semiconductor layer 201 and the second semiconductor layer 202 are combined with the upper surfaces TS1 and TS2 of different pattern shapes to make the first electrode 30 and the different resistance values. A semiconductor layer 201 and the second semiconductor layer 202 have different contact areas and contact shapes, and the first electrode 30 has a different contact resistance from the first semiconductor layer 201 and the second semiconductor layer 202. The light-emitting element has a lower forward voltage (Vf) by adjusting the contact between the first electrode 30 and the first semiconductor layer 201 and the second semiconductor layer 202. For example, when the first electrode 30 has a large contact area with the lower resistance of the first semiconductor layer 201 and the second semiconductor layer 202, the first electrode 30 has a lower contact resistance with the overall semiconductor structure 20. .

FIG. 6 is a schematic diagram of a light-emitting device 6 disclosed in an embodiment of the present application. Any one of the light-emitting elements 1-5 in the foregoing embodiment is mounted on the first spacer 511 and the second spacer 512 of the package substrate 51. The first spacer 511 and the second spacer 512 are electrically insulated by an insulating portion 53 including an insulating material. In the flip chip mounting system, the growth substrate side opposite to the pad formation surface is set as the main light extraction surface. In order to increase the light extraction efficiency of the light-emitting device, a reflective structure 54 may be disposed around the light-emitting element 1.

Figure 7 is a schematic diagram of a light-emitting device 7 in accordance with an embodiment of the present invention. The light-emitting device 7 includes a lamp cover 602, a mirror 604, a light-emitting module 610, a lamp holder 612, a heat sink 614, a connecting portion 616, and an electrical connection member 618. The light-emitting module 610 includes a carrying portion 606, and a plurality of light-emitting units 608 are located on the carrying portion 606. The plurality of light-emitting units 608 can be any of the light-emitting elements 1-5 or the light-emitting device 6 in the foregoing embodiment.

However, the above embodiments are merely illustrative of the principles and effects of the present application, and are not intended to limit the present application. Modifications and variations of the above-described embodiments can be made without departing from the spirit and scope of the invention. Therefore, the scope of protection of the present application is as set forth in the scope of the patent application described below.

1, 2, 3, 4, 5‧‧‧Lighting elements

6, 7‧‧‧Lighting device

10‧‧‧Substrate

10a‧‧‧ upper surface

10b‧‧‧ lower surface

101‧‧‧patterned structure

11‧‧‧ side

12‧‧‧ Short side

13‧‧‧Longside

18‧‧‧Transparent conductive layer

18a‧‧‧Opening of transparent conductive layer

20‧‧‧Semiconductor structure

201‧‧‧First semiconductor layer

202‧‧‧Second semiconductor layer

203‧‧‧ third semiconductor layer

204‧‧‧Active layer

30‧‧‧First electrode

301‧‧‧First line mat

302‧‧‧First extension electrode

40‧‧‧second electrode

401‧‧‧Second line mat

402‧‧‧Second extension electrode

51‧‧‧Package substrate

511‧‧‧First gasket

512‧‧‧second gasket

53‧‧‧Insulation

54‧‧‧Reflective structure

60‧‧‧current barrier

60a‧‧‧ openings for the current blocking layer

602‧‧‧shade

604‧‧‧Mirror

606‧‧‧Loading Department

608‧‧‧Lighting unit

610‧‧‧Lighting Module

612‧‧‧ lamp holder

614‧‧‧ Heat sink

616‧‧‧Connecting Department

618‧‧‧Electrical connection elements

C ₁ ‧‧‧First contact area

C ₂ ‧‧‧Second contact area

TS1‧‧‧ surface of the first semiconductor layer

TS1’‧‧‧ plural areas

TS2‧‧‧ surface of the second semiconductor layer

LS1‧‧‧ side surface

LS2‧‧‧ upper side surface

LS2'‧‧‧ lower side surface

W ₁ ‧‧‧The width of the upper surface TS1

W _N ‧‧‧ width of the first electrode

1A to 1D are light-emitting elements 1 according to an embodiment of the present application. 2A to 2B are light-emitting elements 2 according to another embodiment of the present application. 3A to 3B are light-emitting elements 3 according to another embodiment of the present application. 4A to 4C are light-emitting elements 4 according to another embodiment of the present application. 5A to 5B are light-emitting elements 5 according to another embodiment of the present application. Fig. 6 is a light-emitting device 6 according to an embodiment of the present application. Fig. 7 is a light-emitting device 7 according to another embodiment of the present application.

Claims (11)

A light emitting device comprising: a first semiconductor layer; a second semiconductor layer on the first semiconductor layer; a third semiconductor layer on the second semiconductor layer; and an active layer on the second semiconductor layer And an exposed region passing through the third semiconductor layer and the active layer to expose a first surface of the first semiconductor layer and a second surface of the second semiconductor layer; a first electrode located in the exposed region and contacting the first surface and the second surface; wherein the first semiconductor layer and the second semiconductor layer have different resistance values. The light-emitting element of claim 1, wherein the first semiconductor layer and the second semiconductor layer have the same conductive dopant of different doping concentration. The light-emitting element of claim 2, wherein the first semiconductor layer and the second semiconductor layer comprise the same material. The light-emitting element of claim 1, wherein the first semiconductor layer and the second semiconductor layer comprise different materials. The light-emitting element of claim 1, wherein the thickness of the first semiconductor layer is greater than the thickness of the second semiconductor layer. The illuminating element of claim 1, wherein: the first surface comprises a first side surface and a first upper surface, wherein the first upper surface comprises a first contact area, and the first electrode Contacting; and the second surface includes a second side surface and a second upper surface, wherein the second upper surface includes a second contact area in contact with the first electrode. (For the convenience of defining the pattern later, the "contact area" defined here is located on the first/second upper surface) The illuminating element of claim 6, wherein the first contact area and/or the second contact area comprises a pattern from above. The illuminating element of claim 7, wherein the pattern comprises a strip, a ring, or a geometric shape. The illuminating element of claim 6, wherein the first contact area comprises a plurality of first patterns from a top view, and the plurality of first patterns are separated by the second contact area. The illuminating element of claim 6, wherein an area of the first contact area is different from an area of the second contact area. The light-emitting element according to claim 1, wherein the first electrode has a large contact area with the lower one of the first semiconductor layer and the second semiconductor layer.