TWI784192B - Three-dimensional memory devices and fabrication methods thereof - Google Patents

Abstract

The embodiment of method of forming three-dimensional memory includes following steps. First, forming initial channel holes in a stack structure of alternating first layers and second layers on a substrate. Forming shift features between lateral surfaces of each first layer and each second layer on sidewalls of the initial channel holes to form channel holes. Further forming semiconductor channels by filling the channel holes with channel forming structures. The semiconductor channel is provided with memory layer including first memory portions surrounding bottom of each second layer and second memory portions connecting adjacent first memory portions. The first memory portions and the second memory portions may stagger along a vertical direction.

Description

Three-dimensional memory and its manufacturing method

Embodiments of the present disclosure relate to three-dimensional (3D) memories and methods of manufacturing the same.

By improving manufacturing technology, circuit design, programming algorithm and manufacturing process, planar memory cells have been scaled down to smaller sizes. However, as the feature size of memory cells approaches the lower limit, planar processes and fabrication techniques become challenging and costly. As a result, the storage density of planar memory cells approaches an upper limit.

3D memory architectures can address density limitations in planar memory cells. A 3D memory architecture includes a memory array and peripheral components for controlling signals to and from the memory array.

Embodiments of a 3D memory and a manufacturing method for manufacturing the 3D memory are disclosed herein.

In one example, a method for forming a 3D memory includes the following operations. First, initial channel holes are formed in a stacked structure of a plurality of first layers and a plurality of second layers alternately arranged above the substrate. An offset is formed between the side surface of each first layer and the side surface of each second layer on the sidewall of the initial channel hole to form the channel hole. Also by filling the channel hole with a channel forming structure to form into a semiconductor channel. The semiconductor channel may have a memory layer with a first memory portion surrounding the bottom of each second layer and a second memory portion connecting adjacent first memory portions. The first memory portion and the second memory portion may be staggered along a vertical direction perpendicular to the top surface of the substrate. In addition, a plurality of conductor layers are formed based on the plurality of second layers, and a gate-to-gate dielectric layer including at least one silicon oxynitride sublayer is formed between adjacent conductor layers.

In another example, a method for forming a 3D memory includes forming an initial channel hole in a stack structure of a plurality of first layers and a plurality of second layers alternately arranged above a substrate; An offset is formed between the side surface of each of the first layers and the side surface of each of the second layers to form a channel hole; and a semiconductor channel is formed by filling the channel hole with a channel forming structure. The semiconductor channel may have a memory layer comprising a first memory portion surrounding the bottom of each second layer and a second memory portion connecting adjacent first memory portions. The first memory portion and the second memory portion may be staggered along a vertical direction perpendicular to the top surface of the substrate. The method may further include removing one of the plurality of first layers and the plurality of second layers and forming gate-to-gate dielectric structure.

In yet another example, a 3D memory includes a gate-to-gate dielectric structure over a substrate. The gate-to-gate dielectric structure may include at least one silicon oxynitride sublayer between adjacent conductor layers in a vertical direction perpendicular to the top surface of the substrate. In some embodiments, the 3D memory further includes a semiconductor channel extending from the top surface of the stack structure to the substrate. The semiconductor channel includes a memory layer having a first memory portion surrounding the bottom of each conductor layer and a second memory portion connecting adjacent first memory portions. The first memory portion and the second memory portion may be staggered along the vertical direction. The 3D memory also includes a source structure extending from the top surface of the stack structure to the substrate.

10: Base

14: Semiconductor channel

16: Doping area

17: Gate to Gate Dielectric Layer

17-1, 17-2: composite layer

18: Conductor layer

19: Dielectric core

20: base

21:Stack structure

22: Initial channel hole

24: Semiconductor channel

25: First initial slit opening

29: Dielectric core

35A, 35B: Second initial slit opening

36: Doping area

37:Gate to gate dielectric layer

37-1, 37-2: composite layer

38: conductor layer

44: Semiconductor channel

45A, 45B: second initial opening

46: Doping area

47:Gate to gate dielectric layer

47-1, 47-2: composite layer

48: conductor layer

50: base

51:Stack structure

52: Channel hole

54: Semiconductor channel

55: First initial slit opening

55A, 55B: Second initial slit opening

56: Doping area

57:Gate to gate dielectric layer

57-1, 57-2: composite layer

58: Conductor layer

59: Dielectric core

61: oxide layer

62: Horizontal depression

65A, 65B: Second initial slit opening

66: Doping area

67:Gate to gate dielectric layer

67-1,67-2: composite layer

68: conductor layer

101,102,103,104,105,106: memory

120: Insulation structure

121: source contact

124: Adhesive layer

131: barrier layer

132: Memory layer

132-1: vertical part

132-2: Lateral part

132a: first memory location

132a-1: vertical part

132a-2: Lateral part

132b: Second memory location

133: Channel layer

134: semiconductor layer

170: dielectric layer

173: air gap

200: structure

211: first floor

212: second floor

222: Channel hole

224: Offset

231: barrier layer

232: Memory layer

232-1: vertical part

232-2: Lateral part

232a: The first memory location

232a-2: Lateral part

232b: Second memory location

233: Tunneling layer

234: semiconductor layer

320A, 320B: insulation structure

321: source contact

350A, 350B: slot opening

373: air gap

420A, 420B: insulation structure

421: source contact

431: barrier layer

432: memory layer

432-1: vertical part

432-2: Lateral part

433: Tunneling layer

450A, 450B: slot opening

473: air gap

511: first floor

512: second floor

520A, 520B: insulation structure

521: source contact

531: barrier layer

531m: barrier material layer

532: memory layer

532m: memory material layer

533: Tunneling layer

533m: Tunneling material layer

534: Semiconductor layer

550A, 550B: slot opening

573: air gap

620A, 620B: insulation structure

621: source contact

624: Adhesive layer

650A, 650B: slot opening

670: Unreacted dielectric layer

900: Process

902, 904, 906, 908: Operation

920: Process

922, 924, 926, 928, 930, 932: Operation

940: Flowchart

942,944,946,948,950,952,954: Operation

960: Flowchart

962, 964, 966, 968, 970: Operation

1000: flow chart

1002, 1004, 1006, 1008: Operation

X31: barrier layer

X31a: first barrier layer

X31b: Second barrier layer

X31c: first dielectric layer

X31d: Second dielectric layer

X32: memory layer

X32a: First memory sublayer

X32b: Second memory sublayer

X33: tunneling layer

X33a: First tunneling sublayer

X33b: Second tunneling sublayer

X8-1, X8-2: composite layer

X81,X82: sublayer

X83: air gap

The accompanying drawings, which are incorporated in and form a part of this specification, illustrate embodiments of the disclosure and together with the description further serve to explain the principles of the invention and to enable those skilled in the relevant art to make and use the disclosure disclosed herein .

Figures 1A-1F each show a cross-sectional view of a portion of a 3D memory according to some embodiments of the present disclosure.

Figures 2A-2G illustrate the structure of a 3D memory at various stages in an exemplary fabrication process according to some embodiments of the present disclosure.

Figures 3A-3J illustrate the structure of a 3D memory at various stages in another exemplary fabrication process according to some embodiments of the present disclosure.

Figures 4A-4G illustrate the structure of a 3D memory at various stages in another exemplary fabrication process according to some embodiments of the present disclosure.

Figures 5A-5J illustrate the structure of a 3D memory at various stages in another exemplary fabrication process according to some embodiments of the present disclosure.

Figures 6A-6I illustrate the structure of a 3D memory at various stages in another exemplary fabrication process according to some embodiments of the present disclosure.

Figures 7A-7C all show cross-sectional views of barrier layers, memory layers, and tunneling layers according to some embodiments of the present invention.

Figures 8A-8B each illustrate a cross-sectional view of a gate-to-gate dielectric layer according to some embodiments of the present disclosure.

Figure 9A shows a flowchart of an exemplary method for forming a semiconductor channel in a stacked structure according to some embodiments of the present disclosure.

Figures 9B-9D each show a flowchart of an exemplary method for forming a 3D memory following the method of Figure 9A according to some embodiments of the present disclosure.

Figure 10 shows a diagram of an exemplary method for forming another 3D memory according to some embodiments of the present invention flow chart.

Embodiments of the present disclosure will be described with reference to the drawings.

While specific configurations and settings are discussed, it should be understood that this is done for illustration purposes only. A person skilled in the relevant art will recognize that other configurations and arrangements can be used without departing from the spirit and scope of the present disclosure. It will be apparent to those skilled in the relevant art that the present disclosure may also be used in various other applications.

It should be noted that references in the specification to "one embodiment," "an embodiment," "exemplary embodiment," "some embodiments," etc. indicate that the described embodiments may include particular features, structures, or characteristics, But each embodiment may not necessarily include that particular feature, structure or characteristic. Moreover, such terms are not necessarily referring to the same embodiment. Furthermore, when a particular feature, structure, or characteristic is described in conjunction with an embodiment, it is within the purview of those skilled in the relevant arts to implement such feature, structure, or characteristic in conjunction with other embodiments, whether or not explicitly described.

In general, a term can be understood, at least in part, from its usage in context. For example, the term "one or more" as used herein may be used to describe any feature, structure or characteristic in the singular or may be used to describe a feature, structure or combination of characteristics in the plural, depending at least in part on the context. Similarly, terms such as "a", "an" or "the" may equally be read to express singular usage or to express plural usage, depending at least in part on the context. Additionally, the term "based on" may be understood as not necessarily intended to express an exclusive set of factors, but may instead, again at least in part depending on the context, allow for the presence of other factors not necessarily expressly described.

It should be readily understood that the meanings of "on", "over" and "over" in this disclosure are to be interpreted in the broadest possible manner such that "on" Not only does it mean "directly on something", but it also includes the meaning of "on something" with intermediate features or layers in between, And "on" or "over" not only means the meaning of "on something" or "above something", but can also include "on something" without an intermediate feature or layer in between. "over" or "over something" (i.e., directly on something).

In addition, for the convenience of description, spatially relative terms such as "under", "below", "below", "above", "on" and other spatially relative terms may be used herein to describe The relationship of one element or feature to another (or more) elements or features. Spatially relative terms are intended to encompass different orientations of elements in use or operation in addition to the orientation depicted in the figures. The device may be otherwise oriented (rotated 90 degrees or at other orientations) and the spatially relative descriptors used herein interpreted accordingly.

As used herein, the term "substrate" refers to a material on which subsequent layers of material are added. The substrate itself can be patterned. Materials added on top of the substrate can be patterned or can remain unpatterned. In addition, the substrate can include various semiconductor materials, such as silicon, germanium, gallium arsenide, indium phosphide, and the like. Alternatively, the substrate can be made of a non-conductive material such as glass, plastic or sapphire wafer.

As used herein, the term "layer" refers to a portion of material that includes regions having a thickness. A layer may extend over the entire underlying or superstructure, or its extent may be less than the extent of the underlying or superstructure. Furthermore, a layer may be a region of a uniform or non-uniform continuous structure with a thickness less than that of the continuous structure. For example, a layer may be located between or at any pair of horizontal planes between the top and bottom surfaces of the continuous structure. Layers may extend laterally, vertically and/or along the tapered surface. A substrate can be a layer, a substrate can include one or more layers therein, and/or a substrate can have one or more layers thereon, above, and/or below. Layers may include multiple layers. For example, an interconnect layer may include one or more conductor and contact layers in which interconnect lines and/or via contacts are formed, and one or more dielectric layers.

As used herein, the term "nominal" refers to an expected or target value for a characteristic or parameter of a component or process operation set during the design phase of a product or process, and above and/or The range of values below the expected value. The range of values may be due to slight variations in process or tolerances. As used herein, the term "about" denotes a given quantitative value that may vary based on the particular technology node associated with the subject semiconductor device. The term "about" may mean a value of a given quantity that varies, for example, within 10-30% of that value (e.g., ±10%, ±20%, or ±30% of the value) based on a particular technology node .

As used herein, the term "3D memory" refers to a semiconductor device having vertically oriented memory cell transistor strings (referred to herein as "memory strings", such as NAND memory strings) on a laterally oriented substrate , so that the memory strings extend vertically relative to the substrate. As used herein, the term "perpendicularly" means nominally perpendicular to a lateral surface of a substrate.

As used herein, the terms "ladder", "step" and "level" are used interchangeably. As used herein, a stepped structure refers to a set of surfaces comprising at least two horizontal surfaces and at least two vertical surfaces such that each horizontal surface is connected to a first vertical surface extending upward from a first edge of the horizontal surface, and Connected to a second vertical surface extending downwardly from a second edge of the horizontal surface. "Stairway" refers to the vertical offset of a set of connected surface heights.

As used herein, the x-axis and y-axis (perpendicular to the x-z plane) extend horizontally and form a horizontal plane. The horizontal plane is substantially parallel to the top surface of the substrate. As used herein, the z-axis extends vertically, ie along a direction perpendicular to the horizontal plane. The terms "x-axis" and "y-axis" are used interchangeably with "horizontal direction", the term "x-y plane" is used interchangeably with "horizontal plane", and the term "z-axis" is used interchangeably with "vertical direction".

As 3D memory shrinks for higher storage capacity, more conductor layers serving as gate electrodes of the 3D memory are stacked on top of the substrate within a given space. The spacing between adjacent conductor layers in the vertical direction (ie, the direction perpendicular to the top surface of the substrate) is reduced, resulting in a thinner gate-to-gate dielectric layer between adjacent conductor layers. Conventionally, the gate-to-gate dielectric layer mainly consists of silicon oxide (SiO _x , such as SiO), whose insulating properties are largely affected by its thickness and film quality between adjacent conductor layers. Thinner gate-to-gate dielectrics made of silicon oxide may therefore be susceptible to gate-to-gate leakage and even breakdown due to scaling. Furthermore, the reduced spacing between adjacent conductor layers may also result in increased charge loss. For example, charge trapped in a memory cell is more likely to escape from the memory cell and travel along the memory layer (eg, along its direction of extension) due to the smaller distance between adjacent memory cells. As a result, data retention in the memory layer may be affected, and the precision of operations (eg, read, write, and/or save) on the memory cells may be reduced.

Embodiments in accordance with the present disclosure provide structures and fabrication methods for 3D memory that address the aforementioned problems associated with thinner gate-to-gate dielectric layers. Embodiments of the present disclosure provide a gate-to-gate dielectric having at least one composite layer between adjacent conductor layers. The composite layer includes at least one silicon oxynitride (SiO _x N _y , eg SiON) sublayer. As a high-k dielectric material, silicon oxynitride can provide better electrical isolation between adjacent conductor layers. Even with a smaller thickness between adjacent conductor layers, the gate-to-gate dielectric layer can reduce the susceptibility to leakage and coupling. In some embodiments, the gate-to-gate dielectric layer includes at least an air gap between adjacent conductor layers. In some embodiments, the gate-to-gate dielectric layer includes a pair of composite layers, each composite layer on a different one of the adjacent conductor layers, and an air gap between the two composite layers. In some embodiments, the gate-to-gate dielectric layer includes a composite layer that fills the space between adjacent conductor layers without any air gaps therebetween. The composite layer may include at least a silicon oxynitride sublayer. In some embodiments, the composite layer includes a plurality of sublayers having at least one silicon oxynitride sublayer, each sandwiched by a silicon oxide sublayer and/or a silicon nitride sublayer. For example, the composite layer may include a plurality of alternately arranged silicon oxynitride sub-layers and silicon oxide sub-layers.

Moreover, in order to reduce the charge loss in the 3D memory, in some embodiments, the memory layer in the semiconductor channel may have a "bend" structure or a "cut off" structure, so that adjacent memory cells (such as , Conductor layers) generate a charge barrier between them. In the "mesh" structure, the memory layer has a plurality of first memory parts and a plurality of second memory parts. Each first memory part partially surrounds the corresponding conductor layer, and each second memory part is connected to an adjacent first memory part. first note The memory portion includes a vertical portion (eg, extending vertically) and a pair of lateral portions (eg, extending laterally) connected together to partially surround the bottom of the corresponding conductor layer. The first memory portion and the second memory portion may thus extend in a vertical direction in an interleaved manner, creating a barrier for charge trapped in the memory cell (eg, the first memory portion) in the vertical direction. This structure of the memory layer can reduce the loss of charge along the vertical direction. In the "cut-off" structure, unlike the "bent" structure, the second memory parts between adjacent conductor layers are removed, so that the first memory parts are disconnected from each other. This structure of the memory layer can enhance the charge barrier between adjacent memory cells.

Figures 1A-1E show cross-sectional views of 3D memory devices according to the present disclosure, each having a gate-to-gate dielectric layer. Specifically, FIG. 1A shows a memory memory 101 having memory layers including "stop" structures and gate-to-gate dielectric layers with air gaps between adjacent conductor layers. FIG. 1B shows memory 102 having memory layers including "stop" structures and gate-to-gate dielectric layers without air gaps between adjacent conductor layers. FIG. 1C shows a memory memory 103 having a memory layer including a "meander" structure and a gate-to-gate dielectric layer with an air gap between adjacent conductor layers. FIG. 1D shows a memory memory 104 having memory layers including a "meander" structure and gate-to-gate dielectric layers without air gaps between adjacent conductor layers. FIG. 1E shows memory 105 having memory layers without "meggle" or "off" structures and gate-to-gate dielectric layers with air gaps between adjacent conductor layers. FIG. 1F shows a memory memory 106 having a memory layer comprising a "meander" structure and a gate-to-gate dielectric layer having a pair of composite layers sandwiching dielectric layers of different materials. For ease of description, the same symbols are used in the figures to label the same or similar parts in Figures 1A-1F.

Embodiments of the present disclosure provide different types of memory that are configured to reduce leakage and coupling between conductor layers and prevent trapped charges from traveling in undesired directions. For example, a memory with a semiconductor channel including a "stop" structure and a gate-to-gate dielectric layer including at least a sublayer of high-k dielectric material (eg, silicon oxynitride) and an air gap can be implemented by memory 101 . Having a semiconductor channel including a "bend" structure and at least sublayers including a high-k dielectric material (eg, silicon oxynitride) The gate-to-gate dielectric layer memory can be realized by memory 103 , 104 and 106 . Memories 101, 103 and 105 realized. Formed by a "gate-first" fabrication process and having a semiconductor channel including a "bend" structure and a gate-to-gate dielectric layer including at least a sublayer of high-k dielectric material (eg, silicon oxynitride) and an air gap The memory can be realized by the memory 103 . Memories 101 and 102 may be implemented with a semiconductor channel including a "stop" structure and a gate-to-gate dielectric layer including at least a sublayer of high-k dielectric material (eg, silicon oxynitride). The structure and manufacturing process of the memory is described in detail below.

As shown in FIG. 1A, the memory 101 includes a substrate 10, a plurality of conductive layers 18 stacked on the substrate 10, and a plurality of gate-to-gate dielectric layers between and insulating adjacent conductive layers 18. 17. The conductor layer 18, the substrate 10 and the gate-to-gate dielectric layer 17 may form a stack structure. The memory 101 may include a plurality of semiconductor channels 14 each extending vertically (eg, in a direction perpendicular to the top surface of the substrate 10 or the y-direction) into the substrate 10 through a stack structure. The memory 101 may also include a plurality of source structures extending through the stack structure and into the substrate 10 . Each source structure may include a doped region 16 in the substrate 10 , an insulating structure 120 extending through the stack structure, and a source contact 121 extending in the insulating structure 120 and contacting the doped region 16 . The source contact 121 may be electrically connected to the semiconductor channel 14 through the doped region 16 and the substrate 10 .

Substrate 10 may include silicon (eg, monocrystalline silicon), silicon germanium (SiGe), gallium arsenide (GaAs), germanium (Ge), silicon-on-insulator (SOI), and/or any other suitable material. In some embodiments, substrate 10 includes silicon.

Conductor layer 18 may comprise a conductive material including, but not limited to, tungsten (W), cobalt (Co), copper (Cu), aluminum (Al), polysilicon (polysilicon), doped silicon, silicide, or any combination thereof.

The gate-to-gate dielectric layer 17 may include one or more composite layers and at least one air gap between adjacent conductor layers 18 . In this disclosure, it is used to make a plurality of conductor layers 18 in a stacked structure (for example, The plurality of gate-to-gate dielectric layers 17 insulating all conductor layers 18) from top to bottom of the stack structure may be referred to as a gate-to-gate dielectric structure. In some embodiments, the gate-to-gate dielectric layer 17 includes a pair of composite layers 17-1 and 17-2 and an air gap 173 between the composite layers 17-1 and 17-2. In some embodiments, composite layers 17 - 1 and 17 - 2 may be formed in spaces between adjacent conductor layers 18 and may be on opposing surfaces of adjacent conductor layers 18 . In some embodiments, the thickness of the composite layer, such as 17-1 or 17-2, may be less than about 5 nm, such as less than 5 nm (e.g., 0.5 nm, 1 nm, 1.5 nm, 2 nm, 2.5 nm, 3 nm, 3.5 nm, 4 nm, 4.5 nm, the lower end of any range bounded by either of these values, or within any range bounded by any two of these values). In some embodiments, the thickness of air gap 173 may depend on the thickness of composite layers 17 - 1 and 17 - 2 and the spacing between adjacent conductor layers 18 .

The gate-to-gate dielectric layer 17 may include at least one sublayer of high-k dielectric material, such as silicon oxynitride. In some embodiments, according to the material of the conductive layer 18 , the high-k dielectric material may also include materials other than silicon oxynitride. In some embodiments, each composite layer, such as 17-1 and 17-2, may include a silicon oxynitride sublayer. The gate-to-gate dielectric layer 17 may also include sublayers of other materials. In some embodiments, each composite layer, such as 17-1 and 17-2, may include at least a silicon oxide sublayer and/or a silicon nitride sublayer. In some embodiments, each composite layer, such as 17-1 and 17-2, may include multiple sublayers having at least one silicon oxynitride sublayer, at least one silicon oxide sublayer, and at least one silicon nitride sublayer . In some embodiments, each composite layer, such as 17-1 and 17-2, may have a sublayer stack configured as O/ON/O/ON/O, where "O" stands for silicon oxide and "ON" stands for Silicon oxynitride. In some embodiments, each composite layer, such as 17-1 and 17-2, may have a sub-layer stack arranged as O/ON/O/N/O/ON/O. In some embodiments, along the vertical direction, the conductor layer 18 and the composite layer formed on the conductor layer 18 (on the upper and lower surfaces of the conductor layer 18 ) are located in the space defined between the ends of the vertical portion 132 - 1 . In some embodiments, the total thickness of the conductor layer 18 and the corresponding composite layer is less than the distance between the ends of the vertical portion 132-1. In some embodiments, the ends of the lateral portions 132 - 2 facing away from the respective vertical portions are exposed by the respective gate-to-gate dielectric layer 17 . For example, the ends may be exposed by the corresponding gate-to-gate dielectric layer 17 air gap 173 . In a In some embodiments, a composite layer similar or identical to 17-1 or 17-2 may be formed on the top surface of the substrate 10.

FIG. 8A shows an exemplary structure of the gate-to-gate dielectric layer 17 . As shown in FIG. 8A, x81 represents the silicon oxide sublayer, x82 represents the silicon oxynitride sublayer, and x83 represents the air gap. The sublayers x81 , x82 and x83 on one adjacent conductor layer 18 can form a composite layer x8 - 1 , and the sublayers x81 , x82 and x83 on another adjacent conductor layer 18 can form another composite layer x8 - 2 . Composite layers x8 - 1 , x8 - 2 and air gap x83 may form gate-to-gate dielectric layer 17 . It should be noted that the number of sub-layers in the composite layer should not be limited by the embodiment of the present case. In some embodiments, the thickness of each composite layer x8-1 and x8-2 is less than about 5 nm, such as less than 5 nm (eg, 0.5 nm, 1 nm, 1.5 nm, 2 nm, 2.5 nm, 3 nm, 3.5 nm, 4 nm, 4.5 nm, the lower end of any range bounded by either of these values, or within any range bounded by any two of these values).

The semiconductor channel 14 may include a barrier layer 131 , a memory layer 132 , a tunneling layer 133 , a semiconductor layer 134 and a dielectric core 19 disposed along a radial direction from sidewalls toward the center of the semiconductor channel 14 . The barrier layer 131 may include a plurality of barrier portions each under the bottom of the corresponding conductor layer 18 and disconnected from each other. The memory layer 132 may include a plurality of memory portions, each memory portion is below the bottom of the corresponding conductor layer 18 and partially surrounds the corresponding conductor layer 18 . Each memory section can be disconnected from each other. The memory portion may include a vertical portion 132-1 (eg, extending in a vertical or y-direction) and at least one lateral portion 132-2 (eg, extending in a lateral or x-direction) connected to the vertical portion 132-1. In some embodiments, the memory portion includes a vertical portion 132-1 and a pair of lateral portions 132-2 (eg, each connected to different ends of the vertical portion 132-1). One end of the lateral portion 132-2 may be connected to the corresponding vertical portion 132-1, and the other end of the lateral portion 132-2 may face away from the corresponding vertical portion 132-1 (eg, exposed by the air gap 172). The memory portion may be below and partially surround the corresponding blocking portion. The tunneling layer 133 exposed by the air gap 173 may be under and partially surround the corresponding memory portion.

The blocking layer 131 may reduce or prevent charge from escaping into the conductor layer 18 . The barrier layer 131 may include a single-layer structure or a multi-layer structure. For example, the barrier layer 131 may include a first barrier layer and a second barrier layer. A first barrier layer may be formed over sidewalls of the channel holes, and a second barrier layer may be formed over the first barrier layer. The first barrier layer may include a dielectric material (eg, a dielectric metal oxide). For example, the first barrier layer may comprise a dielectric metal oxide having a sufficiently high dielectric constant (eg, greater than 7.9). Examples of the first barrier layer include AlO, hafnium oxide (HfO ₂ ), lanthanum oxide (LaO ₂ ), yttrium oxide (Y ₂ O ₃ ), tantalum oxide (Ta ₂ O ₅ ), silicates thereof, nitrogen-doped compounds thereof and/or alloys thereof. The second barrier layer may include a different dielectric material than the first barrier layer. For example, the second barrier layer may include silicon oxide, silicon oxynitride and/or silicon nitride. FIG. 7A shows an exemplary barrier layer x31 that is the same as or similar to barrier layer 131 . As shown in FIG. 7A, the barrier layer x31 includes a first barrier layer x31a and a second barrier layer x31b. The first barrier layer x31a may include a high-k dielectric layer, such as AlO. The second barrier layer x31b may include a plurality of laterally stacked dielectric layers. For example, the second barrier layer x31b may include a pair of a first dielectric layer x31c and a second dielectric layer x31d, wherein the second dielectric layer x31d is sandwiched by the first dielectric layer x31c. In some embodiments, the first dielectric layer x31c includes silicon oxide, and the second dielectric layer x31d includes silicon oxynitride.

The memory layer 132 may include a charge trap material and may be formed over the blocking layer 131 . The memory layer 132 may include a single-layer structure or a multi-layer structure. For example, the memory layer 132 may include conductive materials and/or semiconductor materials, such as tungsten, molybdenum, tantalum, titanium, platinum, ruthenium, alloys thereof, nanoparticles thereof, silicides thereof, and/or polycrystalline or amorphous semiconductor materials ( For example, polysilicon and amorphous silicon). The memory layer 132 may also include one or more insulating materials, such as SiN and/or SiON. FIG. 7B shows an exemplary memory layer x32 that is the same as or similar to memory layer 132 . As shown in FIG. 7B, the memory layer x32 may include a plurality of alternately arranged first memory sub-layers x32a and second memory sub-layers x32b. In some embodiments, the first memory sublayer x32a includes silicon nitride, and the second memory sublayer x31b includes silicon oxynitride.

The tunneling layer 133 may include a dielectric material through which a tunneling phenomenon may occur under an appropriate bias voltage. The tunneling layer 133 may be formed over the memory layer 132 and may include a single-layer structure or a multi-layer structure. The tunneling layer 133 may include SiO, SiN, SiON, dielectric metal oxide, dielectric metal oxynitride, Dielectric metal silicides and/or alloys thereof. FIG. 7C shows an exemplary tunneling layer x33 that is the same as or similar to tunneling layer 133 . As shown in FIG. 7C, the tunneling layer x33 may include a plurality of first tunneling sublayers x33a and second tunneling sublayers x33b. In some embodiments, the second tunneling sublayer x33b may be sandwiched by a pair of first tunneling sublayers x33a. In some embodiments, the first tunneling sublayer x33a includes silicon oxide, and the second tunneling sublayer x33b includes multilayer silicon oxynitride.

The semiconductor layer 134 may facilitate the transport of charges and may be formed over the tunneling layer 133 . The semiconductor layer 134 may include one or more semiconductor materials, such as single element semiconductor materials, group III-V compound semiconductor materials, group II-VI compound semiconductor materials, and/or organic semiconductor materials. In some embodiments, the semiconductor layer 134 includes a polysilicon layer.

The dielectric core 19 may comprise a suitable dielectric material and be able to fill the space surrounded by the semiconductor layer 134 . In some embodiments, dielectric core 19 includes silicon oxide (eg, silicon oxide of sufficiently high purity).

A doped region 16 may be formed in the substrate 10 contacting the source contact 121 . The source contact 121 may be insulated from the conductor layer 18 by the insulating structure 120 . The source contact 121 may comprise any suitable conductive material usable as a source electrode, and the doped region 16 may comprise a suitably doped (eg, P-type or N-type) semiconductor formed in the substrate 10 and opposite in polarity to the substrate 10. Area. In some embodiments, the source contact 121 includes one or more of doped polysilicon, copper, aluminum, cobalt, doped silicon, silicide, and tungsten. In some embodiments, the doped region 16 includes doped silicon. In some embodiments, the insulating structure 120 includes silicon oxide.

Figure 1B shows a cross-sectional view of memory 102 according to some embodiments. Unlike the memory memory 101 , the gate-to-gate dielectric layer 17 has no air gap between adjacent conductor layers 18 and uses composite layers to fill the space between adjacent conductor layers 18 . In some embodiments, insulating structure 120 insulates source contact 121 from conductor layer 18 and gate-to-gate dielectric layer 17 . In some embodiments, ends of lateral portion 132 - 2 , exposed portions of barrier layer 131 , and exposed portions of tunneling layer 133 are covered by gate-to-gate dielectric layer 17 . In some embodiments, the composite layer fills the space between the substrate 10 and the conductor layer 18 proximate to the substrate 10 . Figure 8B shows an exemplary structure of a composite layer. As shown in Figure 8B, a composite layer may include multiple sublayers, At least one of the sublayers includes silicon oxynitride. In some embodiments, at least one sublayer includes silicon oxynitride, and at least one sublayer includes silicon oxide. In some embodiments, at least one sublayer includes silicon oxynitride, at least one sublayer includes silicon oxide, and at least one sublayer includes silicon nitride. In some embodiments, x81 represents silicon oxide, x82 represents silicon oxynitride, and the composite layer includes a plurality of alternately arranged silicon oxynitride and silicon oxide sublayers. In some embodiments, the number of sublayers of each material and the thickness of each sublayer may be related to, for example, the overall composite layer thickness (e.g., the spacing between adjacent conductor layers 18) and/or the manufacturing process, and should not Subject to the limitations of the embodiment of this case.

Figure 1C shows a cross-sectional view of memory 103 according to some embodiments. Different from the memory 101 , the blocking layer 131 and the memory layer 132 extend uniformly along the horizontal direction and the vertical direction. The memory layer 132 may include a first memory portion 132a and a second memory portion 132b connected to the adjacent first memory portion 132a, the first memory portion 132a is at the bottom of the corresponding conductor layer 18 and on the corresponding conductor layer 18. Composite layers below and partially surrounding them. As shown in FIG. 1C , the barrier layer 131 may be above the memory layer 132 and may correspondingly be below and partially surround the bottom of the corresponding conductor layer 18 and the composite layer on the corresponding conductor layer 18 . Lateral portions of the barrier layer 131 may laterally contact the composite layer. The first memory part 132a may include a vertical part 132a-1 and at least one lateral part 132a-2. In some embodiments, the first memory portion 132a may include a vertical portion 132a-1 and a pair of lateral portions 132a-2. In some embodiments, the second memory portion 132b extends vertically. As shown in FIG. 1C, the second memory portion 132b and the vertical portion 132a-1 of the memory layer 132 may be staggered along the vertical direction. In some embodiments, the thickness of the composite layer, such as 17-1 or 17-2, may be less than about 5 nm, such as less than 5 nm (e.g., 0.5 nm, 1 nm, 1.5 nm, 2 nm, 2.5 nm, 3 nm, 3.5 nm, 4 nm, 4.5 nm, the lower end of any range bounded by either of these values, or within any range bounded by any two of these values). For a detailed description of the gate-to-gate dielectric layer 17 and the composite layers 17-1 and 17-2, please refer to the description of the gate-to-gate dielectric layer 17 and the composite layers 17-1 and 17-2 in the memory 101 , which will not be repeated here.

FIG. 1D shows a cross-sectional view of memory 104 according to some embodiments. with memory 103 The difference is that the gate-to-gate dielectric layer 17 has no air gap between adjacent conductor layers 18 and uses a composite layer to fill the space between adjacent conductor layers 18 . In some embodiments, the composite layer fills the space between the substrate 10 and the conductor layer 18 proximate to the substrate 10 . The detailed description of the structure and materials of the gate-to-gate dielectric layer 17 and the composite layer can refer to the description of the gate-to-gate dielectric layer 17 and the composite layer 17 in the memory 102 , and will not be repeated here.

Figure 1E shows a cross-sectional view of memory 105 according to some embodiments. Different from the memories 101 and 103 , the memory 105 includes a semiconductor channel 14 , wherein the barrier layer 131 , the memory layer 132 , the tunneling layer 133 and the semiconductor layer 134 all extend continuously along the vertical direction. In some embodiments, the thickness of the composite layer, such as 17-1 or 17-2, may be less than about 5 nm, such as less than 5 nm (e.g., 0.5 nm, 1 nm, 1.5 nm, 2 nm, 2.5 nm, 3 nm, 3.5 nm, 4 nm, 4.5 nm, the lower end of any range bounded by either of these values, or within any range bounded by any two of these values). The detailed description of the gate-to-gate dielectric layer 17 can refer to the description of the memory 101 , and will not be repeated here.

Figure 1F shows a cross-sectional view of the memory 106 according to some embodiments. Unlike the memory 104, the memory 106 includes a dielectric layer 170 sandwiched by a pair of composite layers 17-1 and 17-2, wherein the dielectric layer 170 includes the same material as the composite layers 17-1 and 17-2. different materials. In some embodiments, the dielectric layer 170 includes silicon nitride. The adhesive layer 124 may optionally include titanium and/or titanium oxide, and is formed between the conductive layer 18 and the gate-to-gate dielectric layer 17 . In some embodiments, the thickness of the composite layer, such as 17-1 or 17-2, may be less than about 5 nm, such as less than 5 nm (e.g., 0.5 nm, 1 nm, 1.5 nm, 2 nm, 2.5 nm, 3 nm, 3.5 nm, 4 nm, 4.5 nm, the lower end of any range bounded by either of these values, or within any range bounded by any two of these values). The detailed description of the structure and materials of the composite layers 17 - 1 and 17 - 2 can refer to the description of the composite layers 17 - 1 and 17 - 2 in the memory 101 , and will not be repeated here.

Figures 2A-2G illustrate a method for forming a stacked structure having a semiconductor channel including a "bend" structure, according to some embodiments. The structure 200 shown in Figure 2G may be used as the base structure to form memories 101-104. Figure 9A shows the flow of the process 900 shown in Figures 2A-2G map.

Referring to FIG. 9A , the process begins by forming an initial via hole in a stack structure having a plurality of alternating first and second layers over a substrate (operation 902 ). Figures 2A and 2B show the corresponding structures.

As shown in FIG. 2A , a stacked structure 21 having a plurality of alternately arranged first layers 211 and second layers 212 is formed on the substrate 20 . The material of the substrate 20 can refer to the description of the substrate 10 , and will not be repeated here. In some embodiments, substrate 20 includes silicon (N-type silicon).

The stacked structure 21 may provide a fabrication basis for forming a 3D memory. Next, a memory string (eg, a NAND memory string) including semiconductor channels and associated structures/parts may be formed in the stack structure 21 . In some embodiments, the stack structure 21 includes a plurality of first layer 211 /second layer 212 pairs stacked vertically above the substrate 20 to form a ladder structure. Each first layer 211/second layer 212 pair may include one first layer 211 and one second layer 212, and can form a ladder/hierarchical structure. That is, the stack structure 21 may include a first layer 211 and a second layer 212 alternately stacked in a vertical direction. The number of first layer 211/second layer 212 pairs (for example, 32, 64, 96 or 128) in the stack structure 21 can set the number of memory cells in the 3D memory.

The first layers 211 may all have the same thickness or different thicknesses. Similarly, second layers 212 may all have the same thickness or have different thicknesses. The second layer 212 may comprise any suitable material different from that of the first layer 211 such that an etchant (e.g., used in a subsequent process to remove the first layer 211) can have more higher etch rate. That is, the etchant can selectively etch the first layer 211 with respect to the second layer 212 . In some embodiments, the first layer 211 can include a sacrificial material and the second layer 212 can include a conductive material. In some embodiments, the first layer 211 can include a sacrificial material and the second layer 212 can include another sacrificial material. The specific selection of materials for the first layer 211 and the second layer 212 should be determined by the process (eg, gate-first process or gate-last process) and will be explained in detail below.

For example, the stack structure 21 may be formed by repeatedly etching a dielectric stack of a plurality of first material layer/second material layer pairs in vertical and lateral directions. The etching of the first material layer/second material layer pair may include repeatedly etching/trimming an etch mask (eg, a photoresist layer) over the dielectric stack to expose the first material layer/second material layer pair to be etched. parts, and etch/remove exposed parts using an appropriate etch process. The etching of the etch mask and insulating material layer/sacrificial material layer pair may be performed using any suitable etching process, such as wet etching and/or dry etching. In some embodiments, etching includes dry etching, eg, inductively coupled plasma (ICP) etching and/or reactive ion etching (RIE).

Initial via holes 22 may be formed in the stack structure 21 . In some embodiments, the initial access hole 22 extends from the top surface of the stack structure 21 to the substrate 20 . In some embodiments, the base 20 is partially exposed at the bottom of the initial access hole 22 . Initial via hole 22 may be formed by any suitable process. For example, a patterned photoresist layer may be formed over the stack structure 21 . The patterned photoresist layer can expose the part of the stack structure 21 used to form the initial channel hole 22 . A suitable etching process may be performed to remove the portion of the stacked structure 21 until the substrate 20 is exposed. The etching process may include a dry etching process.

Referring to FIG. 9A, after the initial via hole is formed, an offset is formed between the side surface of the second layer and the side surface of the adjacent first layer by removing a portion of each first layer on the sidewall of the initial via hole. , thereby forming a channel hole (operation 904). Figure 2C shows the corresponding structure.

As shown in FIG. 2C , a portion of each first layer 211 on the sidewalls of the initial via hole 22 may be removed to form the via hole 222 . For ease of description, the surface of the first layer 211 (or the second layer 212 ) facing the initial via hole 22 or the via hole 222 is referred to as a side surface of the first layer 211 (or the second layer 212 ). In some embodiments, an offset 224 may be formed on a side surface of the first layer 211 . The dimension or thickness of the removed portion of the first layer 211 (eg, in the lateral direction or x-direction) may be any suitable value that allows an offset to be formed between the second layer 212 and the side surface of the first layer 211 . In some embodiments, the side surface of the second layer 212 forms a protrusion along the sidewall of the channel hole 222 . Any suitable selective etch process (eg, recess etch) may be performed to form offset 224 . In some embodiments, a selective etching process is performed on the first layer 211 The etch selectivity to the second layer 212 is high, causing little or no damage to the second layer 212 . Wet etching and/or dry etching may be performed as a selective etching process. In some embodiments, RIE is performed as a selective etch process.

Referring to FIG. 9A, after the via hole is formed, a channel forming structure is formed to fill the via hole and form a semiconductor channel (operation 906). Figures 2D-2F show the corresponding structures.

As shown in FIGS. 2D-2F , semiconductor channel 24 may be formed by filling via hole 222 with a channel forming structure. The channel forming structure may include a barrier layer 231 deposited along the sidewall of the channel hole 222, a memory layer 232 above the barrier layer, a tunneling layer 233 above the barrier layer, a semiconductor layer 234 above the tunneling layer, and a layer that fills the channel hole 222. Dielectric core 29. Each of these layers may be the same as or similar to the barrier layer 131 , memory layer 132 , tunneling layer 133 , semiconductor layer 134 and dielectric core 19 shown in FIG. 1A , respectively. A detailed description of the materials of these layers is therefore not repeated here.

As shown in FIG. 2D , in some embodiments, a barrier material layer, a memory material layer and a tunneling material layer are sequentially deposited in the channel hole 222 along the radial direction from the sidewall toward the center of the channel hole 222 . The materials of the barrier material layer, the memory material layer and the tunneling material layer can refer to the description of the barrier layer 131 , the memory layer 132 and the tunneling layer 133 , and will not be repeated here. The layer of barrier material may be formed by suitable deposition methods such as chemical vapor deposition (CVD), atomic layer deposition (ALD), pulsed laser deposition (PLD), low pressure CVD (LPCVD) and/or liquid source spray chemical deposition. The layer of memory material may be formed by any suitable deposition method, such as CVD, ALD, and physical vapor deposition (PVD). The layer of tunneling material may be formed by suitable deposition methods, such as CVD, ALD and/or PVD. A recess etching process, such as dry etching, may be performed to remove the barrier material layer, the memory material layer and the tunneling material layer at the bottom of the channel hole 222 to expose the substrate 20 . Then the blocking layer 231 , the memory layer 232 and the tunneling layer 233 may be formed accordingly.

As shown in FIG. 2E and FIG. 2F, a semiconductor layer 234 is deposited over the tunneling layer 233 and the substrate 20, and a dielectric core 29 is deposited over the semiconductor layer 234 to fill the remainder of the space in the via hole 222, A semiconductor channel 24 is formed. Semiconductor layer 234 may be formed by any suitable deposition method, such as LPCVD, ALD, and/or metal organic chemical vapor deposition (MOCVD). In some embodiments, dielectric core 29 includes SiO (eg, substantially high purity SiO) and may be formed by any suitable deposition method, such as CVD, LPCVD, ALD, and/or PVD.

Referring back to FIG. 9A, after forming the semiconductor channel, a first initial slot opening is formed in the stack structure (operation 908). FIG. 2G shows the corresponding structure 200 .

As shown in FIG. 2G , a first initial slot opening 25 is formed to extend through the stack structure and expose the substrate 20 . An appropriate etching process, such as a dry etching process, may be performed to form the first initial slit opening 25 .

Figures 3A-3J illustrate a "gate-first" approach to forming memories 103 and 104 based on structure 200, according to some embodiments. Specifically, Figures 3A, 3C, 3E, 3G and 3I show the process of forming memory 103 based on structure 200, Figures 3B, 3D, 3F, 3H and 3J show the process of forming memory 104 based on structure 200 Process. In the “gate first” approach, the first layer 211 includes a sacrificial material, and the second layer 212 includes a conductive material for the subsequent formation of the conductive layer 18 . In some embodiments, the second layer 212 includes polysilicon. FIG. 9B shows a flow diagram of process 920 for forming memories 103 and 104 shown in FIGS. 3A-3J.

As shown in FIG. 9B, the process begins by removing a plurality of first layers (operation 922) and forming a gate-to-gate dielectric layer between adjacent conductor layers (operation 924). A second initial slit opening is formed from the first initial slit opening. Figures 3A and 3B show the corresponding structures, respectively. In some embodiments, an isotropic etching process (eg, wet etching) is performed to remove the first layer 211 and expose the barrier layer 231 and the substrate 20 . A plurality of lateral depressions may be formed by removing the first layer 211 .

As shown in FIG. 3A, an oxidation reaction and/or a nitridation reaction may be performed to form a composite layer from a portion of the second layer 212 that reacts with the reactants. The unreacted part of the second layer 212 can form the conductive layer 38 , and the conductive layer can serve as the gate electrode of the memory 103 . The reacted portion of the second layer 212 may form a composite layer 37-1 or 37-2 (eg, similar or identical to 17-1 or 17-2) covering the conductor layer 38. Composite layers can be obtained from the second The top/upper surface of layer 212 is formed from the bottom/lower surface of second layer 212 . An air gap 373 may be formed between composite layers 37 - 1 and 37 - 2 on adjacent conductor layers 38 . In some embodiments, a pair of composite layers (eg, 37-1 and 37-2) opposite each other and on adjacent conductor layers 38 and air gap 373 therebetween may form gate-to-gate dielectric layer 37, Similar or the same as the gate-to-gate dielectric layer 17 shown in Figures 1A and 1C. In some embodiments, a composite layer (for example, 37-1 or 37-2) may also be formed on the side surface of the second layer 212 (for example, the sidewall of the first initial slit opening 25), from which the first initial slit opening 25 forms a second initial slit opening 35A.

In some embodiments, the plurality of gate-to-gate dielectric layers 37 are formed by oxidizing and/or nitridating the second layer 212 through the first initial slot opening 25 and laterally recessing the second layer 212 . In some embodiments, in order to form a plurality of gate-to-gate dielectric layers 37, the oxygen diffusion concentration and/or the nitrogen diffusion concentration are controlled so that each gate-to-gate dielectric layer 37 includes at least one silicon oxynitride Floor. In some embodiments, each composite layer (eg, 37-1 or 37-2) includes at least a silicon oxynitride sublayer. In some embodiments, the oxygen and/or nitrogen diffusion concentration is controlled such that each gate-to-gate dielectric layer 37 can have the structure described in FIG. 1A. For example, each gate-to-gate dielectric layer 37 includes a pair of composite layers (eg, 37-1 and 37-2), each including a plurality of alternating silicon oxynitride sublayers and silicon oxide sublayers. The specific structure of each composite layer should not be limited by the embodiment of this case. In some embodiments, a composite layer may be formed over substrate 20 through oxidation and/or nitridation reactions.

Unlike the process of forming gate-to-gate dielectric layer 37 from portions of second layer 212, as shown in FIG. The gate-to-gate dielectric layers 37 are formed by forming at least one silicon oxynitride sublayer in each gate-to-gate dielectric layer 37 . This process can be performed through the lateral recess and the first initial slot opening 25 . In some embodiments, a dielectric material such as silicon oxide or silicon nitride may be deposited to fill the lateral recesses by suitable deposition methods such as CVD, ALD and/or PVD. An oxidation reaction and/or a nitridation reaction may be performed on the dielectric material deposited between adjacent second layers 212 to form a gate-to-gate dielectric layer 37 comprising Composite layers having at least one silicon oxynitride sublayer. In some embodiments, each composite layer includes at least a silicon oxynitride sublayer. In some embodiments, the oxygen and/or nitrogen diffusion concentration is controlled such that each gate-to-gate dielectric layer 37 can have the structure described in FIG. 1B . For example, each gate-to-gate dielectric layer 37 includes a composite layer having a plurality of alternating silicon oxynitride and silicon oxide sublayers. No air gap is formed between adjacent second layers 212 . In some embodiments, a gate-to-gate dielectric layer 37 covers the barrier layer 231 . The specific structure of each composite layer should not be limited by the embodiment of this case. In some embodiments, second layer 212 forms conductor layer 38 . In some embodiments, an adhesion layer (not shown) may be formed on the second layer 212 prior to depositing the dielectric material. In some embodiments, a composite layer may also be formed on the side surface of the second layer 212 (eg, the sidewall of the first initial slit opening 25 ) from which the second initial slit opening 35B is formed. In some embodiments, a composite layer may be formed over substrate 20 through oxidation and/or nitridation reactions.

Referring back to FIG. 9B, after forming the gate-to-gate dielectric layer, a doped region may be formed in the substrate at the bottom of the second initial slot opening (operation 926). Figures 3C and 3D show the corresponding structures.

As shown in FIGS. 3C and 3D , a doped region 36 may be formed in the substrate 20 at the bottom of the second initial slot opening (eg, 35A in FIG. 3C and 35B in FIG. 3D ). A suitable doping process, such as ion implantation, can be performed to form the doped region 36 . In some embodiments, portions of the composite layer at the bottom of the second initial slot openings (eg, 35A and 35B) are removed to expose the substrate 20 prior to the doping process. In some embodiments, portions of the composite layer at the bottom of the second initial slit openings (eg, 35A and 35B) remain.

Referring back to FIG. 9B, after the doped regions are formed, slot openings are formed from the second initial slot openings (operation 928). Figures 3E and 3F show the corresponding structures.

As shown in Figures 3E and 3F, a slit opening (eg, 350A in Figure 3E and 350B in Figure 3D) is formed from a corresponding second initial slit opening (eg, 35A in Figure 3C and 35B in Figure 3D). 350B in Figure 3F). In some embodiments, a recess etch is performed to remove any recesses from the side surfaces of conductor layer 38. The recessed material forms slot openings 350A/350B. In some embodiments, the remaining material (eg, the material of the composite layer) above the substrate 20 at the bottom of the second initial slot opening 35A/ 35B may also be etched and removed. Sidewalls of the slot openings 350A/ 350B may expose the conductive layer 38 . In some embodiments, the sidewall of the slot opening 350A exposes the air gap 373 . In some embodiments, the sidewalls of the slot openings 350A/ 350B also expose the gate-to-gate dielectric layer 37 .

Referring back to FIG. 9B, an insulating structure is formed in the slot opening (operation 930). Figures 3G and 3H show the corresponding structures.

As shown in Figures 3G and 3H, insulating structures (eg, 320A in Figure 3G and 320B). In some embodiments, the insulating structure 320A/ 320B is formed over the sidewalls of the corresponding slot opening 350A/ 350B and the substrate 20 (eg, or the doped region 36 ) is exposed at the bottom of the corresponding slot opening 350A/ 350B. In some embodiments, the insulating structure 320A/320B includes a dielectric material, such as silicon oxide, and is deposited by a suitable deposition process, such as CVD, ALD, LPCVD and/or PVD. In some embodiments, a recess etch (eg, dry etch and/or wet etch) is performed to remove any remaining material at the bottom of the slot opening 350A/350B (eg, material deposited during formation of the insulating structure 320A/320B) to Substrate 20 (eg, or doped region 36 ) is exposed.

Referring back to FIG. 9B, after the insulating structure is formed, a source contact is formed in the insulating structure (operation 932). Figures 3I and 3J show the corresponding structures.

As shown in FIGS. 3I and 3J , a suitable conductive material may be deposited in the insulating structures 320A/ 320B to form corresponding source contacts 321 . Any suitable deposition method may be used to form source contact 321 . For example, source contact 321 may be formed by CVD, ALD and/or PVD. In some embodiments, source contact 321 includes tungsten and is deposited by CVD. In some embodiments, source contact 321A, doped region 36 and corresponding insulating structure 320A/ 320B form a source structure. A suitable planarization process (eg, recess etch and/or chemical mechanical polishing) may be performed to planarize the top surface of the stacked structure, For example, the source structure, the semiconductor channel 24 and/or the gate-to-gate dielectric layer 37 are planarized.

4A-4G illustrate a "gate-first" approach to forming memories 101 and 102 based on structure 200, according to some embodiments. Specifically, Figures 4A, 4B, 4D and 4F show the process of forming the memory 101 based on the structure 200 , and Figures 4A, 4C, 4E and 4G show the process of forming the memory 102 based on the structure 200 . In the “gate first” approach, the first layer 211 includes a sacrificial material, and the second layer 212 includes a conductive material for the subsequent formation of the conductive layer 18 . In some embodiments, the second layer 212 includes polysilicon. FIG. 9C shows a flowchart 940 of the process for forming memories 101 and 102 shown in FIGS. 4A-4G.

As shown in FIG. 9C, the process begins by removing a plurality of first layers (operation 942) and forming a memory layer with a memory portion below the bottom of each second layer (operation 944). The memory sections are disconnected from each other. Figure 4A shows the corresponding structure. In some embodiments, an isotropic etch process (eg, wet etch) is performed to remove the first layer (eg, 211 ), forming a plurality of lateral recesses that expose the barrier layer (eg, 231 ) and the substrate (eg, 20).

As shown in FIG. 4A, a barrier layer 431 is formed having a plurality of barrier portions, each of which is below the bottom of the corresponding second layer 212 and disconnected from each other. Also, a memory layer 432 is formed having a plurality of memory portions each below a corresponding blocking portion. Each memory portion may include a vertical portion 432-1 and at least one lateral portion 432-2 connected to the vertical portion 432-1. In some embodiments, each memory portion includes a pair of lateral portions 432-2 connected to different ends of respective vertical portions 432-1. Each memory part may surround a corresponding barrier part under the bottom of the corresponding second layer 212, and may be disconnected from each other along a vertical direction. The tunneling layer 433 below the memory layer 432 and partially surrounding the memory layer 432 is also formed to extend uniformly along the vertical direction. In some embodiments, the tunneling layer 433 may be exposed between adjacent second layers 212 .

A suitable etch process (eg, wet etch) may be performed on the structure 200 to remove portions of the semiconductor channel 24 from the first initial slit opening 25 and the lateral recess. In some embodiments, at least the second memory portion 232b is removed to expose the lateral portion 232a-2 of the first memory portion 232a. first memory Portion 232a may be fully or partially retained to form a memory portion. Depending on the etching process, the lateral portion 232-2 may be over-etched, and the length of the lateral portion 232a-2 may vary laterally in different applications. In some embodiments, portions of the barrier layer 231 and the tunneling layer 233 may also be removed during the etching process. Blocking portions disconnected from each other and above the memory portion may be formed. After forming the memory portion, semiconductor channel 24 may form semiconductor channel 44 .

Referring back to FIG. 9C, a gate-to-gate dielectric layer is formed between adjacent conductor layers, and a second initial slot opening is formed (operation 946). Also, a doped region is formed in the substrate at the bottom of the second initial slot opening (operation 948). Figures 4B and 4C show the corresponding structures, respectively.

Figure 4B shows a gate-to-gate dielectric layer 47 with an air gap. As shown in FIG. 4B, a gate-to-gate dielectric layer 47, a conductor layer 48, a second initial opening 45A, and a doped region 46 may be formed in a stacked structure. In some embodiments, the gate-to-gate dielectric layer 47 includes a pair of composite layers 47-1 and 47-2 and an air gap 473 between the composite layers 47-1 and 47-2. The process of forming these structures can refer to the manufacturing process of forming the gate-to-gate dielectric layer 37, the conductor layer 38, the second initial slit opening 35A and the doped region 36 shown in FIG. 3A and FIG. 3C. Recap.

FIG. 4C shows the gate-to-gate dielectric layer 47 without an air gap. As shown in FIG. 4C, a gate-to-gate dielectric layer 47, a conductor layer 48, a second initial opening 45B, and a doped region 46 may be formed in a stacked structure. In some embodiments, gate-to-gate dielectric layer 47 includes a composite layer that fills the space between adjacent conductor layers 48 . In some embodiments, the gate-to-gate dielectric layer 47 covers exposed portions of the barrier layer 431 , the memory layer 432 and the tunneling layer 433 . The manufacturing process for forming these structures can refer to the manufacturing process for forming the gate-to-gate dielectric layer 37, the conductor layer 38, the second initial slit opening 35B and the doped region 36 shown in FIG. 3B and FIG. 3D, hereby No restatement.

Returning to FIG. 9C, after forming the doped regions and the gate-to-gate dielectric layer, a slot opening is formed from the second initial slot opening (operation 950) and an insulating structure is formed in the slot opening (operation 952). Figures 4D and 4E show the corresponding structures, respectively.

As shown in FIGS. 4D and 4E , slot openings (eg, 450A in FIG. 4D and 450B in FIG. 4E ) and insulating structures (eg, 420A in FIG. 4D and 450B in FIG. 4E ) can be formed. 420B). For the manufacturing process of forming the slit opening 450A and the insulating structure 420A, refer to the process of forming the slit opening 350A and the insulating structure 320A in FIG. 3E and 3G. For the process of forming the slit opening 450B and the insulating structure 420B, refer to FIGS. 3F and 3H. The process of forming the slit opening 350B and the insulating structure 320B in the figure will not be repeated here.

Referring back to FIG. 9C, after forming the slot opening and the insulating structure, a source contact is formed in the insulating structure (operation 954). Figures 4F and 4G show the corresponding structures, respectively.

As shown in FIGS. 4F and 4G , source contacts 421 are formed in corresponding insulating structures (eg, 420A in FIG. 4F and 420B in FIG. 4G ), contacting corresponding doped regions 46 . The process for forming the source contact portion 421 can refer to the process for forming the source contact portion 321 shown in FIG. 3I and FIG. 3J . The details will not be repeated here.

Figures 5A-5D, 5E, and 5I illustrate a "gate first" approach to forming memory 105 with an air gap in the gate-to-gate dielectric layer, according to some embodiments. Figures 5A-5D, 5F, and 5J illustrate a "gate first" approach to forming memory without air gaps in the gate-to-gate dielectric layer, according to some embodiments. Figure 10 shows a flowchart 1000 of the process shown in Figures 5A-5J.

The process begins by forming a semiconductor channel in a stack structure (operation 1002). Figures 5A-5C show corresponding structures.

As shown in FIGS. 5A-5C , a semiconductor channel 54 may be formed in the stack structure 51 above the substrate 50 . As shown in FIG. 5A, the stack structure 51 may include a plurality of alternately arranged first layers 511 and second layers 512 forming a plurality of steps, wherein each first layer 511/second layer 512 forms a step/hierarchical structure. The first layer 511 may include a sacrificial material, and the second layer 512 may include a conductive material for forming a conductive layer, which in turn acts as a gate electrode of the memory. The detailed description of the materials of the substrate 50 , the materials of the stacked structure 51 and the manufacturing process can refer to the description of the substrate 20 and the stacked structure 21 in FIG. 2A , which will not be repeated here. In some embodiments, the substrate 50 includes silicon, the first layer 511 includes silicon nitride and/or silicon oxide, and the second layer 512 includes polysilicon.

As shown in FIG. 5A , the via hole 52 may be formed to extend vertically through the stack structure 51 . The process for forming via hole 52 may be similar or identical to the process for forming initial via hole 22 (eg, as shown in FIG. 2B ). Unlike forming the via hole 222 shown in FIG. 2C , no offset is formed between the side surfaces of the first layer 511 and the second layer 512 in the via hole 52 . That is, side surfaces of the first layer 511 and the second layer 512 may be coplanar in a vertical direction. A barrier material layer 531 m , a memory material layer 532 m and a tunneling material layer 533 m may be successively deposited over the sidewalls of the channel hole 52 . The materials and deposition processes for forming these material layers can refer to the materials and deposition processes of the barrier material layer, the memory material layer and the tunneling material shown in FIG. 2D, and will not be repeated here.

As shown in FIG. 5B , portions of the barrier material layer 531 m , the memory material layer 532 m and the tunneling material layer 533 m may be removed to expose the substrate 50 . An etching process similar to the etching process shown in FIG. 2D may be performed, and a barrier layer 531 , a memory layer 532 and a tunneling layer 533 may be formed.

As shown in FIG. 5C , semiconductor layer 534 and dielectric core 59 may be deposited sequentially to fill via hole 52 and form semiconductor channel 54 . The material and deposition process for forming the semiconductor layer 534 and the dielectric core can refer to the description of the materials and deposition process for forming the semiconductor layer 234 and the dielectric core 29 shown in FIG. 2E and FIG. 2F , and will not repeat them here. .

Referring back to FIG. 10, after forming the semiconductor channel, a gate-to-gate dielectric layer is formed between adjacent conductor layers, and a second initial slot opening is formed (operation 1004). Figures 5D and 5E show corresponding structures with gate-to-gate dielectric layers including air gaps. Figures 5D and 5F show corresponding structures with gate-to-gate dielectric layers without air gaps.

As shown in FIG. 5D, a first initial slit opening 55 may be formed to extend vertically through the stack structure, and the first layer 511 may be removed through the first initial slit opening 55 to form a plurality of lateral recesses. The formation of the first initial slit opening 55 can refer to the formation of the first initial slit opening 25 shown in FIG. 2G, The formation of the lateral depressions can refer to the formation of the lateral depressions shown in FIG. 3A. In some embodiments, portions of the barrier layer 531 are exposed in the lateral recesses. The details will not be repeated here.

Figure 5E shows a structure formed from the structure shown in Figure 5D. In some embodiments, as shown in FIG. 5E, a gate-to-gate dielectric layer 57 and a second initial slot opening 55A may be formed. Gate-to-gate dielectric layers 57 may be located between adjacent conductor layers 58 . The gate-to-gate dielectric layer 57 may include a pair of composite layers 57-1 and 57-2 and an air gap 573 between the composite layers 57-1 and 57-2. The materials, structures and processes for forming the gate-to-gate dielectric layer 57 and the second initial slit opening 55A can refer to the materials for forming the gate-to-gate dielectric layer 37 and the second initial slit opening 35A shown in FIG. 3A , the description of the structure and the manufacturing process will not be repeated here.

Figure 5F shows another structure formed from the structure shown in Figure 5D. In some embodiments, as shown in FIG. 5E , a gate-to-gate dielectric layer 57 and a second initial slot opening 55B may be formed. The gate-to-gate dielectric layer 57 may be located between adjacent conductor layers 58 without an air gap between adjacent conductor layers 58 . The gate-to-gate dielectric layer 57 may include a composite layer between adjacent conductor layers 58 . The material, structure and manufacturing process for forming the gate-to-gate dielectric layer 57 and the second initial slit opening 55B can refer to the materials for forming the gate-to-gate dielectric layer 37 and the second initial slit opening 35B shown in FIG. 3B , the description of the structure and manufacturing process will not be repeated here.

Referring back to FIG. 10, after forming the gate-to-gate dielectric layer and the second initial slit opening, a doped region is formed at the bottom of the second slit structure, and the slit structure is formed from the second initial slit structure (operation 1006) . Figures 5G and 5H both show corresponding structures.

As shown in FIGS. 5G and 5H , doped regions 56 are formed in respective substrates 50 and slit openings (eg, 550A in FIG. 5G and 550B in FIG. 5H ) are formed to extend through the stack structure and Substrate 50 (eg, corresponding doped regions 56 ) is exposed. The specific process of forming the doped region 56 and the slit opening 550A/ 550B should refer to the description of the process of forming the doped region 36 and the slit opening 350A/ 350B, and will not be repeated here.

Referring back to FIG. 10 , after forming the doped region and the slot opening, an insulating structure is formed in the slot structure, and a source contact is formed in the insulating structure (operation 1008 ). Both Figure 5I and Figure 5J The corresponding structures are shown.

As shown in FIGS. 5I and 5J , isolation structures (eg, 520A in FIG. 5I and 520B in FIG. 5J ) and source contacts 521 are formed in respective isolation structures 520A/520B. In some embodiments, source contacts 521 contact corresponding doped regions 36 . The description of the materials and process for forming the insulating structure 520A/520B and the source contact 521 should refer to the description of the material and the manufacturing process for forming the insulating structure 320A/320B and the source contact 521 shown in FIG. 3I and FIG. 3J , which will not be repeated here.

Figures 6A-6I illustrate a "gate-last" approach to forming a memory from structure 200 with a gate-to-gate dielectric layer between adjacent conductor layers, according to some embodiments. Specifically, Figures 6A, 6B, 6D, 6F, and 6H show the gate-to-gate dielectric process from the integral formation of each first layer, and Figures 6A, 6C, 6E, 6G, and 6I A process for forming a gate-to-gate dielectric layer from a portion of a plurality of first layers is shown. In some embodiments, Figures 6A, 6B, 6D, 6F, and 6H illustrate processes for forming memory 104 , and Figures 6A, 6C, 6E, 6G, and 6I illustrate processes for forming memory 106 . In this "gate-last" approach, the first layer 211 includes a dielectric material used to form a gate-to-gate dielectric layer and the second layer 212 includes a sacrificial material used to form a conductor layer that acts as a gate electrode. . The dielectric material may include silicon oxide and/or silicon nitride. In some embodiments, the first layer 211 includes silicon nitride. In some embodiments, the second layer 212 includes a different material than the material of the first layer 211 . In some embodiments, the second layer 212 includes polysilicon, carbon and/or organic films. Figure 9D shows a flowchart 960 of the process shown in Figures 6A-6I.

As shown in Figure 6A, the process begins by removing the plurality of second layers (operation 962). Figure 6A shows the corresponding structure.

In some embodiments, an isotropic etching process (eg, wet etching) is performed to remove the second layer 212 and expose the barrier layer 231 and the substrate 20 . The plurality of lateral recesses 62 may be formed by removing the second layer 212 through the first initial slit opening 25 . Portions of the barrier layer 231 may be exposed by the lateral recess 62 .

Referring back to FIG. 9D, after removing the second layer and forming the lateral recesses, a gate-to-gate dielectric layer is formed between adjacent lateral recesses, and a second initial slot opening is formed (operation 964). Section 6B Figures and Figure 6C both show the corresponding structures.

In some embodiments, the gate-to-gate dielectric layer 67 of FIGS. 6A and 6B is formed by oxidizing the first layer 211 through the first initial slot opening 25 and the lateral recess 62 . In some embodiments, to form multiple gate-to-gate dielectric layers 67, the oxygen diffusion concentration is controlled such that each gate-to-gate dielectric layer 37 includes a desired amount of silicon oxynitride and/or silicon oxide Floor. The specific structure of each composite layer should not be limited by the embodiment of this case. A second initial slit opening (eg, 65A in FIG. 6B and 65B in FIG. 6C ) may be formed from a corresponding first initial slit opening (eg, 25 in FIG. 6A ) by an oxidation process on the first layer 211 ). In some embodiments, oxide layer 61 may be formed over substrate 20 at the bottom of second initial slit opening 65A/ 65B from an oxidation reaction between oxygen and substrate 20 .

FIG. 6B shows a structure in which each gate-to-gate dielectric layer is formed by fully oxidizing each first layer 211 . As shown in FIG. 6B , an oxidation reaction may be performed to form gate-to-gate dielectric layer 67 from oxidation of the entire portion of each first layer 211 . Each gate-to-gate dielectric layer 67 may comprise a composite layer including at least a silicon oxynitride sublayer formed from the entire portion of the corresponding first layer 211 between subsequently formed adjacent conductor layers. In some embodiments, each composite layer includes at least a silicon oxynitride sublayer and at least a silicon oxide sublayer. In some embodiments, each composite layer includes a plurality of alternating silicon oxynitride sub-layers and silicon oxide sub-layers, such as the structure shown in FIG. 8B.

FIG. 6C shows a structure in which gate-to-gate dielectric layer 67 is formed by partially oxidizing each first layer 211 . The gate-to-gate dielectric layer 67 may include a pair of composite layers (for example, 67-1 and 67-2) formed by oxidizing an outer portion of each first layer 211 instead of the entire portion. As shown in FIG. 6C , an oxidation reaction may be performed to form a gate-to-gate dielectric layer 67 from an outer portion of each first layer 211 . Each gate-to-gate dielectric layer 67 may include a pair of composite layers (eg, 67-1 and 67-2) formed between adjacent conductor layers formed next. Each composite layer may be formed from an outer portion of the first layer 211 . In some embodiments, composite layer 67-1 is formed from the top of first layer 211 (e.g., the portion extending from the upper surface of first layer 211 to the interior of first layer 211), and composite layer 67-2 is formed from the same first layer 211. The bottom of layer 211 (for example, from A portion where the lower surface of the first layer 211 extends to the inside of the first layer 211) is formed. The unreacted portion of first layer 211 may be sandwiched or surrounded by composite layers 67-1 and 67-2 and may be referred to as unreacted dielectric layer 670 (eg, composed of silicon nitride). In some embodiments, the gate-to-gate dielectric layer 67 includes a pair of composite layers 67-1 and 67-2 and an unreacted dielectric layer 670 between the composite layers 67-1 and 67-2. The thicknesses of the composite layers 67-1 and 67-2 and the unreacted dielectric layer 670 can be determined by an oxidation process, wherein the thickness of the unreacted dielectric layer 670 is greater than zero. In some embodiments, each composite layer 67-1/67-2 may include at least a silicon oxynitride sublayer. In some embodiments, each composite layer 67-1/67-2 includes at least a silicon oxynitride sublayer and at least a silicon oxide sublayer. In some embodiments, each composite layer includes a plurality of alternating silicon oxynitride sub-layers and silicon oxide sub-layers, such as the structure shown in FIG. 8B. In some embodiments, the gate-to-gate dielectric layer 67 includes a pair of composite layers 67-1 and 67-2 and an unreacted dielectric layer 670 between the composite layers 67-1 and 67-2. That is, the gate-to-gate dielectric layer 67 includes a silicon nitride sublayer sandwiched by two alternately arranged stacks of silicon oxynitride sublayers and silicon oxide sublayers.

Referring back to FIG. 9D, after forming the gate-to-gate dielectric layer, a plurality of conductor layers and slot openings are formed (operation 966). Figures 6D and 6E both show corresponding structures.

As shown in Figures 6D and 6E, a plurality of conductor layers 68 and corresponding slot openings are formed from corresponding second initial slot openings 65A/65B (e.g., 650A in Figure 6D and 650B in Figure 6E) . In some embodiments, a layer of conductive material may be deposited into each lateral recess 62 to fill the space in the lateral recess 62 through the corresponding second initial slit opening 65A/65B, and a recess etch (e.g., dry etch) may be performed. and/or wet etching) to remove any remaining conductor material and the portion of the composite layer 67-1/67-2 on the sidewalls of the second initial slit opening 65A/65B to form a corresponding conductor layer 68 and a corresponding slit opening 650A /650B. In some embodiments, conductor layer 68 includes tungsten, copper, aluminum, cobalt, suicide, doped and/or polysilicon. In some embodiments, prior to depositing the conductive material layer, an adhesion layer 624 is deposited in the lateral recess 62 through a corresponding second initial slit opening, for example, to improve the connection between the conductive material layer and the gate-to-gate dielectric layer 67. of adhesion. In some embodiments, the adhesion layer 624 includes titanium (Ti) and/or titanium nitride (TiN). In some embodiments, both the conductive material layer and the adhesive layer 624 are deposited by suitable methods, such as one or more of CVD, ALD, LPCVD, and/or PVD.

Referring back to FIG. 9D, after forming the conductor layer, a doped region is formed in the substrate at the bottom of the slit opening, and an insulating structure is formed in the slit opening (operation 968). Figures 6F and 6G both show corresponding structures.

Correspondingly doped regions 66 may be formed in substrate 20 as shown in FIGS. 6F and 6G . Doped region 66 may include a suitably doped (eg, P-type or N-type) semiconductor region formed in substrate 10 and opposite in polarity to substrate 20 . A suitable doping process, such as ion implantation, can be performed to form the doped region 66 . In some embodiments, doped region 66 includes doped silicon.

A corresponding insulating structure (eg, 620A in Figure 6F and 620B in Figure 6G) may be formed to insulate the corresponding conductor layer 68 from a subsequently formed source contact. In some embodiments, the insulating structures 620A/ 620B both cover the sidewalls of the corresponding slit openings and expose the substrate 20 (eg, the corresponding doped regions 66 ). In some embodiments, the insulating structure 620A covers the side surfaces of the composite layer of the gate-to-gate dielectric layer 67 , the conductor layer 68 and the adhesive layer 624 . In some embodiments, the insulating structure 620B covers the composite layer of the gate-to-gate dielectric layer 67 , the unreacted dielectric layer 670 of the gate-to-gate dielectric layer 67 , the conductor layer 68 and the side surfaces of the adhesive layer 624 . To form the insulating structures 620A/620B, a suitable insulating material may be deposited to cover the sidewalls of the corresponding slot openings 650A/650B, and a suitable recess etch (eg, dry etch and/or wet etch) may be performed to remove the slot openings 650A/650B. The remainder of the insulating material on the side walls and bottom. The corresponding oxide layer 61 can also be removed by a recess etching process. Insulation structures 620A/620B may be formed in slot openings 650A/650B. In some embodiments, the insulating structure 120 includes silicon oxide and is deposited by any one of CVD, ALD, LPCVD and/or PVD. In various embodiments, the order of forming the corresponding insulating structures 620A/ 620B and the doped regions 66 may vary based on different manufacturing operations, and should not be limited by the present embodiment.

Referring back to FIG. 9D, after forming the insulating structure and the doped region, forming in the insulating structure A source contact is formed (operation 970). Figures 6H and 6I both show corresponding structures.

As shown in FIGS. 6H and 6I , source contacts 621 are formed in respective insulating structures 620A/ 620B. The source contact 621 may contact the corresponding doped region 66 and form an electrical connection with the semiconductor channel 24 through the doped region 66 and the substrate 20 . The source contact 621 may include one or more of tungsten, cobalt, copper, aluminum, silicide, and/or doped polysilicon, and may be deposited by one or more of CVD, PVD, and/or ALD. Appropriate CMP and/or recess etching may be performed to remove the remaining material of the insulating structures 620A/ 620B and the source contacts 621 .

In some embodiments, a "gate-last" approach is also used to form memories having semiconductor channels that do not include lateral portions, eg, the lateral portions extend uniformly in a vertical direction. For example, to form a memory, a semiconductor channel similar to or identical to semiconductor channel 54 (eg, shown in FIG. 5C ) may be formed in a stacked structure. Unlike the stack structure 51, the stack structure may have a plurality of alternating first layers of dielectric material layers and second layers of sacrificial material layers, similar or identical to the stack structure shown in FIGS. 6A-6I. In some embodiments, the first layer includes silicon nitride, and the second layer includes a different material than the first layer, such as polysilicon, carbon, and/or an organic film. The second layer can be removed to form a plurality of lateral recesses, similar to the fabrication operation shown in Figure 6A. The first layer may then be oxidized using an oxidation reaction similar to the oxidation process shown in FIGS. 6B and 6C to form a plurality of gate-to-gate dielectric layers. The stacked structure can also be processed using the fabrication process shown in FIGS. 6D-6I to form other parts, such as source contacts, insulating structures, and conductor layers. The detailed description of the materials and processes for forming the memory can refer to the descriptions in FIGS. 5A-5J and FIGS. 6A-6I , and will not be repeated here.

In various embodiments, the gate-to-gate dielectric layer may comprise different materials than those presented in this disclosure based on the material of the first layer and/or the second layer. By using the methods of the present disclosure, the first layer and/or the second layer can undergo appropriate reactions (eg, oxidation and/or nitridation reactions) to form at least a high-k Sublayers of dielectric material. For example, x81 may include hafnium oxide (HfO _x ), and x82 may include hafnium oxynitride (HfO _x N _y , such as HfON). In some embodiments, the lateral recess (formed by removing the first layer 211 ) can be filled by depositing hafnium oxide, and an oxidation and/or nitridation process is performed on the hafnium oxide between the conductor layers 18 to form the gate to At least a sub-layer of hafnium oxynitride is formed in the gate dielectric layer 17 to form the gate-to-gate dielectric layer 17 of the memories 102 and 104 . In some embodiments, in a "gate-first" approach, second layer 212 includes hafnium, and the gates of memories 101, 103, 105, and 106 (eg, all formed by a "gate-first" approach) to The gate dielectric layer 17 includes at least a hafnium oxynitride sublayer. In some embodiments, in a "gate-last" approach, first layer 211 includes hafnium, and the gate-to-gate dielectric of memories 104 and 106 (eg, both formed by a "gate-last" approach) Layer 17 comprises at least a hafnium oxynitride sublayer. The specific material of the gate-to-gate dielectric layer should not be limited by this embodiment.

In some embodiments, a method for forming a 3D memory includes the following operations. First, initial channel holes are formed in a stacked structure of a plurality of first layers and a plurality of second layers alternately arranged above the substrate. An offset is formed between the side surface of each first layer and the side surface of each second layer on the sidewall of the initial channel hole to form the channel hole. A semiconductor channel is also formed by filling the channel hole with a channel forming structure. The semiconductor channel may have a memory layer comprising a first memory portion surrounding the bottom of each second layer and a second memory portion connecting adjacent first memory portions. The first memory portion and the second memory portion may be staggered along a vertical direction perpendicular to the top surface of the substrate. Additionally, a plurality of conductor layers are formed based on the plurality of second layers and a gate-to-gate dielectric layer including at least one silicon oxynitride sublayer is formed between adjacent conductor layers.

In some embodiments, the plurality of first layers and the plurality of second layers are formed by alternately depositing a plurality of layers of sacrificial material and a plurality of layers of conductive material on the substrate to An initial stacked structure is formed above. The plurality of sacrificial material layers may have a different etch selectivity than the plurality of conductive material layers. In some embodiments, the plurality of first layers and the plurality of second layers are further formed by repeatedly etching the plurality of sacrificial material layers and the plurality of conductive material layers along the vertical direction To form the stacked structure, the stacked structure has the plurality of first layers and the plurality of second layers arranged in a stepped structure.

In some embodiments, forming the gate-to-gate dielectric layer includes: forming a first initial slit opening extending in the stack structure and exposing the substrate; and performing an etching process to remove the plurality of first slit openings. One layer, thereby forming a plurality of lateral depressions.

In some embodiments, the plurality of second layers includes polysilicon and forming the gate-to-gate dielectric layer further includes: forming a composite layer from a portion of each of the plurality of second layers, corresponding to the first The remaining part of the second layer forms a corresponding conductor layer, a pair of composite layers facing each other on adjacent conductor layers forms the gate-to-gate dielectric layer, and the opening of the first initial slit forms a second initial slit opening, the composite layer has at least one silicon oxynitride sublayer.

In some embodiments, forming the composite layer and the plurality of conductor layers includes: performing one or more oxidation reactions on the plurality of second layers through the first initial slit opening and the plurality of lateral recesses and nitriding reaction, the reacted portion of each second layer forms a corresponding composite layer. The unreacted portion of each second layer forms the respective conductor layer.

In some embodiments, the composite layer is formed from the top and bottom of each respective second layer.

In some embodiments, forming the gate-to-gate dielectric structure further includes forming an air gap between the pair of composite layers.

In some embodiments, forming the composite layer includes controlling oxygen diffusion concentration such that the composite layer includes the at least one silicon oxynitride sublayer.

In some embodiments, forming the composite layer further includes controlling oxygen diffusion concentration, so that the composite layer includes at least one silicon oxynitride sublayer and at least one silicon oxide sublayer.

In some embodiments, forming the composite layer further includes forming a plurality of alternately disposed silicon oxynitride sub-layers and silicon oxide sub-layers.

In some embodiments, forming the gate-to-gate dielectric structure includes filling each of the lateral recesses with a gate-to-gate dielectric layer. The plurality of second layers may form the plurality of conductor layers, and the gate-to-gate dielectric layer may include at least one silicon oxynitride sublayer.

In some embodiments, the gate-to-gate dielectric layer is formed by depositing a silicon nitride layer to fill each of the lateral recesses; and oxidizing the nitride by controlling the oxygen diffusion concentration. a silicon layer such that the gate-to-gate dielectric layer includes the at least one silicon oxynitride sublayer.

In some embodiments, forming the gate-to-gate dielectric layer further includes controlling the oxygen diffusion concentration such that the gate-to-gate dielectric layer includes at least one silicon oxynitride layer between adjacent second layers. layer and at least one silicon oxide sublayer.

In some embodiments, forming the gate-to-gate dielectric layer further includes controlling the oxygen diffusion concentration, so that the gate-to-gate dielectric layer includes a plurality of oxynitride layers alternately arranged between adjacent second layers. Silicon sublayer and silicon oxide sublayer.

In some embodiments, the plurality of first layers and the plurality of second layers are formed by alternately depositing a plurality of insulating material layers and a plurality of sacrificial material layers on the substrate, so that An initial stack structure is formed above the substrate. The plurality of insulating material layers may have a different etch selectivity from the plurality of second material layers. In some embodiments, the plurality of first layers and the plurality of second layers are further formed by repeatedly etching the plurality of insulating material layers and the plurality of sacrificial material layers along the vertical direction To form the stacked structure, the stacked structure has the plurality of first layers and the plurality of second layers.

In some embodiments, forming the gate-to-gate dielectric structure includes: forming a first initial slit opening extending in the stack structure and exposing the substrate; and performing an etching process to remove the plurality of first slit openings. The second layer, thereby forming a plurality of lateral depressions.

In some embodiments, the plurality of first layers includes silicon nitride and forming the gate-to-gate dielectric structure includes forming a gate-to-gate dielectric structure from each of the plurality of first layers. Floor. The gate-to-gate dielectric layer may have at least one silicon oxynitride sublayer. Forming the gate-to-gate dielectric structure may further include forming a second initial slot opening from the first initial slot opening.

In some embodiments, forming the gate-to-gate dielectric structure includes The initial slit opening and the plurality of lateral recesses perform an oxidation reaction on the plurality of first layers to at least partially oxidize the plurality of first layers. The reacted portion of each first layer may form a composite layer having at least one silicon oxynitride sublayer.

In some embodiments, forming the gate-to-gate dielectric layer further includes forming at least one silicon oxynitride sublayer and at least one silicon oxide sublayer.

In some embodiments, forming the gate-to-gate dielectric layer further includes forming a plurality of alternately disposed silicon oxynitride sub-layers and silicon oxide sub-layers.

In some embodiments, the method further includes forming a plurality of conductor layers to fill the plurality of lateral recesses. Adjacent conductor layers may be insulated by respective gate-to-gate dielectric layers therebetween.

In some embodiments, the method further includes forming an adhesive layer in the plurality of lateral recesses prior to forming the plurality of conductor layers.

In some embodiments, forming the offset includes removing a portion of the side surface of each first layer on the sidewall of the initial via hole.

In some embodiments, removing the portion of the side surface of each first layer includes performing a recess etch process that selectively etches the plurality of first layers relative to the plurality of second layers. layer.

In some embodiments, filling the channel hole with the channel forming structure includes: forming a barrier layer above the sidewall of the channel hole, forming the memory layer above the barrier layer, and forming a tunneling layer above the memory layer. layer, forming a semiconductor layer over the tunneling layer, and forming a dielectric core over the semiconductor layer to fill the channel hole.

In some embodiments, the method further includes: forming a doped region in the substrate at the bottom of the second initial slit opening; exposing the doped region on the sidewall of the slit opening by removing part of the composite layer a plurality of second layers and exposing the substrate at the bottom of the slit opening, the slit opening is formed from the second initial slit opening; an insulating structure is formed in the slit opening, the insulating a structure over the exposed portions of the plurality of second layers on sidewalls of the slit opening and exposing the substrate at the bottom of the slit opening; and forming a contact to the doped region in the insulating structure of the source contact.

In some embodiments, forming the insulating structure in the slit opening includes depositing a layer of silicon oxide, and the silicon oxide layer covers the exposed portions of the plurality of second layers and the layers between adjacent second layers. a gate-to-gate dielectric layer; and forming the source contact includes depositing at least one of tungsten, cobalt, copper, aluminum, polysilicon, doped silicon, or silicide in the insulating structure.

In some embodiments, a method for forming a 3D memory includes: forming an initial channel hole in a stack structure of a plurality of first layers and a plurality of second layers alternately arranged above a substrate; forming an offset between the side surface of each first layer and the side surface of each second layer on the sidewall to form a via hole; and forming a semiconductor channel by filling the via hole with a channel forming structure . The semiconductor channel may have a memory layer comprising a first memory portion surrounding the bottom of each second layer and a second memory portion connecting adjacent first memory portions. The first memory portion and the second memory portion may be staggered along a vertical direction perpendicular to the top surface of the substrate. The method may further include removing one of the plurality of first layers and the plurality of second layers; and according to the remaining one of the plurality of first layers and the plurality of second layers A gate-to-gate dielectric structure is formed.

In some embodiments, the plurality of first layers and the plurality of second layers are formed by alternately depositing a plurality of layers of sacrificial material and a plurality of layers of conductive material on the substrate to An initial stacked structure is formed above. The plurality of sacrificial material layers may have a different etch selectivity than the plurality of conductive material layers. In some embodiments, the plurality of first layers and the plurality of second layers are further formed by repeatedly etching the plurality of sacrificial material layers and the plurality of conductive material layers to form the stacked structure , the stacked structure has the plurality of first layers and the plurality of second layers arranged in a stepped structure.

In some embodiments, forming the gate-to-gate dielectric structure includes: forming a first initial slit opening extending in the stack structure and exposing the substrate; and removing the plurality of first layers and the One of the plurality of second layers includes removing the plurality of first layers to form a plurality of lateral recesses.

In some embodiments, the plurality of second layers comprises polysilicon and forming the gate-to-gate dielectric structure includes forming a composite layer from a portion of each second layer, the remaining portion of the corresponding second layer forming corresponding conductor layers, a pair of composite layers facing each other on adjacent conductor layers form the gate-to-gate dielectric layer, the first initial slit opening forms a second initial slit opening, and the composite The layer has at least one silicon oxynitride sublayer.

In some embodiments, forming the composite layer and the plurality of conductor layers includes performing one or more oxidation reactions on the plurality of second layers through the first initial slit opening and the plurality of lateral recesses and Nitriding reaction. The reacted portion of each second layer may form the respective composite layer, and the unreacted portion of each second layer may form the respective conductor layer.

In some embodiments, the composite layer is formed from the top and bottom of each respective second layer.

In some embodiments, forming the gate-to-gate dielectric structure further includes forming an air gap between the pair of composite layers.

In some embodiments, forming the composite layer includes controlling oxygen diffusion concentration such that the composite layer includes the silicon oxynitride sublayer on the corresponding conductor layer.

In some embodiments, forming the composite layer further includes controlling oxygen diffusion concentration, so that the composite layer includes at least one silicon oxynitride sublayer and at least one silicon oxide sublayer.

In some embodiments, forming the composite layer further includes controlling the oxygen diffusion concentration, so that the composite layer includes a plurality of silicon oxynitride sub-layers and silicon oxide sub-layers arranged alternately.

In some embodiments, forming the gate-to-gate dielectric structure includes using a gate-to-gate A very dielectric layer fills each of the lateral recesses. The plurality of second layers may form the plurality of conductor layers, and the gate-to-gate dielectric layer may include at least one silicon oxynitride sublayer.

In some embodiments, the gate-to-gate dielectric layer is formed by depositing a silicon nitride layer to fill each of the lateral recesses; and oxidizing the nitride by controlling the oxygen diffusion concentration. a silicon layer such that the gate-to-gate dielectric layer includes the at least one silicon oxynitride sublayer.

In some embodiments, forming the gate-to-gate dielectric layer further includes controlling the oxygen diffusion concentration such that the gate-to-gate dielectric layer includes at least one silicon oxynitride layer between adjacent second layers. layer and at least one silicon oxide sublayer.

In some embodiments, forming the gate-to-gate dielectric layer further includes controlling the oxygen diffusion concentration, so that the gate-to-gate dielectric layer includes a plurality of oxynitride layers alternately arranged between adjacent second layers. Silicon sublayer and silicon oxide sublayer.

In some embodiments, the plurality of first layers and the plurality of second layers are formed by alternately depositing a plurality of insulating material layers and a plurality of sacrificial material layers on the substrate to An initial stacked structure is formed above. The plurality of insulating material layers may have a different etch selectivity from the plurality of second material layers. In some embodiments, the plurality of first layers and the plurality of second layers are formed by repeatedly etching the plurality of insulating material layers and the plurality of sacrificial material layers to form the stacked structure, The stack structure has the plurality of first layers and the plurality of second layers in a stepped structure.

In some embodiments, forming the gate-to-gate dielectric structure includes: forming a first initial slit opening extending in the stack structure and exposing the substrate; and removing the plurality of first layers and the One of the plurality of second layers includes removing the plurality of second layers to form a plurality of lateral recesses.

In some embodiments, the plurality of first layers includes silicon nitride and forming the gate-to-gate dielectric structure includes forming a gate-to-gate dielectric layer from each of the first layers. The gate-to-gate The dielectric layer may have at least one silicon oxynitride sublayer. In some embodiments, forming a gate-to-gate dielectric structure includes forming a second initial slot opening from the first initial slot opening.

In some embodiments, forming the gate-to-gate dielectric structure includes performing an oxidation reaction on the plurality of first layers through the first initial slot opening and the plurality of lateral recesses to at least partially oxidize The plurality of first layers. The reacted portion of each first layer may form a composite layer having at least one silicon oxynitride sublayer.

In some embodiments, forming the gate-to-gate dielectric layer further includes forming at least one silicon oxynitride sublayer and at least one silicon oxide sublayer.

In some embodiments, forming the gate-to-gate dielectric layer further includes forming a plurality of alternately disposed silicon oxynitride sub-layers and silicon oxide sub-layers.

In some embodiments, the method further includes forming a plurality of conductor layers to fill the plurality of lateral recesses. Adjacent conductor layers may be insulated by respective gate-to-gate dielectric layers therebetween.

In some embodiments, the method further includes forming an adhesive layer in the plurality of lateral recesses prior to forming the plurality of conductor layers.

In some embodiments, forming the offset includes removing a portion of the side surface of each first layer on the sidewall of the initial via hole.

In some embodiments, removing the portion of the side surface of each first layer includes performing a recess etch process that selectively etches the plurality of first layers relative to the plurality of second layers. layer.

In some embodiments, filling the channel hole with the channel forming structure includes: forming a barrier layer above the sidewall of the channel hole, forming the memory layer above the barrier layer, and forming a tunneling layer above the memory layer. layer, forming a semiconductor layer over the tunneling layer, and forming a dielectric core over the semiconductor layer to fill the channel hole.

In some embodiments, the method further includes: in the substrate in the second initial forming a doped region at the bottom of the slit opening; by removing a portion of the composite layer to expose the plurality of second layers on sidewalls of the slit opening and exposing the substrate at the bottom of the slit opening, from the second An initial slot opening forms the slot opening; an insulating structure is formed in the slot opening. The insulating structure may overlie the exposed portions of the plurality of second layers on sidewalls of the slot opening and expose the substrate at the bottom of the slot opening. The method also includes forming a source contact in the insulating structure in contact with the doped region.

In some embodiments, forming the insulating structure in the slit opening includes depositing a layer of silicon oxide, and the silicon oxide layer covers the exposed portions of the plurality of second layers and the layers between adjacent second layers. a gate-to-gate dielectric layer; and forming the source contact includes depositing at least one of tungsten, cobalt, copper, aluminum, polysilicon, doped silicon, or silicide in the insulating structure.

In some embodiments, a 3D memory includes a gate-to-gate dielectric structure over a substrate. The gate-to-gate dielectric structure may include at least one silicon oxynitride sublayer between adjacent conductor layers in a vertical direction perpendicular to the top surface of the substrate. In some embodiments, the 3D memory further includes a semiconductor channel extending from the top surface of the stack structure to the substrate. The semiconductor channel includes a memory layer having a first memory portion surrounding the bottom of each conductor layer and a second memory portion connecting adjacent first memory portions. The first memory portion and the second memory portion may be staggered along the vertical direction. The 3D memory also includes a source structure extending from the top surface of the stack structure to the substrate.

In some embodiments, the gate-to-gate structure includes a gate-to-gate dielectric layer between adjacent conductor layers. The gate-to-gate dielectric layer may include at least a silicon oxynitride sublayer.

In some embodiments, the gate-to-gate dielectric layer includes at least a silicon oxide sublayer and a silicon oxynitride sublayer between the adjacent conductive layers.

In some embodiments, the gate-to-gate dielectric layer includes a plurality of alternately disposed silicon oxide sublayers and silicon oxynitride sublayers.

In some embodiments, the gate-to-gate dielectric layer includes a pair of composite layers and an air gap between the pair of composite layers, the pair of composite layers are respectively located on the adjacent conductor layers and facing each other. Each pair of composite layers may include at least a silicon oxynitride sublayer.

In some embodiments, each composite layer is located between ends of a corresponding first memory portion.

In some embodiments, the composite layer includes at least a silicon oxide sublayer and a silicon oxynitride sublayer.

In some embodiments, the composite layer includes a plurality of alternately disposed silicon oxide sub-layers and silicon oxynitride sub-layers.

In some embodiments, the gate-to-gate dielectric layer fills the space between adjacent conductor layers.

In some embodiments, along the radial direction from the sidewall of the semiconductor channel to the center of the semiconductor channel, the semiconductor channel includes a barrier layer, the memory layer above the barrier layer, the memory layer A tunneling layer above, a semiconductor layer above the tunneling layer, and a dielectric core above the semiconductor layer.

In some embodiments, the barrier layer includes at least one of a first barrier layer and a second barrier layer, the first barrier layer comprising aluminum oxide (AlO), hafnium oxide (HfO ₂ ), lanthanum oxide (LaO ₂ ), oxide At least one of yttrium (Y ₂ O ₃ ), tantalum oxide (Ta ₂ O ₅ ), its silicates, its nitrogen-doped compounds, or alloys thereof, the second barrier layer includes silicon oxide, silicon oxynitride, and nitride One or more materials in silicon. In some embodiments, the memory layer includes charge trapping materials including tungsten, molybdenum, tantalum, titanium, platinum, ruthenium, alloys thereof, nanoparticles thereof, silicides thereof, polysilicon, amorphous silicon, SiN or at least one material in SiON. In some embodiments, the tunneling layer includes at least one material of SiO, SiN, SiON, dielectric metal oxide, dielectric metal oxynitride, dielectric metal silicide or alloys thereof. In some embodiments, the semiconductor layer may include at least one of a single-element semiconductor material, a III-V compound semiconductor material, a II-VI compound semiconductor material, or an organic semiconductor material. In some embodiments, the dielectric core includes SiO.

In some embodiments, the plurality of conductor layers each include a layer structure composed of one or more of W, Co, Al, doped silicon, silicide, and combinations thereof, and the source structures each include an insulating structure and are connected to the insulating structure in the insulating structure. The source contact of the base conductive contact. The insulating structure may include silicon oxide, and the source contact may include one or more materials selected from W, Co, Al, doped silicon, silicide, and combinations thereof.

The foregoing descriptions of specific embodiments are intended to demonstrate the general nature of the disclosure of the present case so that others can readily interpret such specific embodiments by applying knowledge within the skill of the art without undue experimentation and without departing from the general concepts of the present case. Modifications and/or adjustments may be made for various applications of the examples. Therefore, such adaptations and modifications are intended to be within the meaning and range of equivalents of the disclosed embodiments, based on the teaching and guidance presented herein. It should be understood that the terms or terms herein are for the purpose of illustration rather than limitation, so the terms or terms in this specification will be interpreted by skilled persons according to the teaching and guidance.

Embodiments of the present application have been described above with the aid of functional blocks illustrating the implementation of specified functions and relationships thereof. The boundaries of these functional blocks have been arbitrarily defined herein for the convenience of the description. Other boundaries can be defined so long as their specified functions and relationships are appropriately performed.

The Summary and Abstract sections may set forth, without limitation, one or more exemplary embodiments of the inventor's contemplation of the present case. Accordingly, it is not intended to limit the scope of this case and the appended patent application by any means.

The above descriptions are only preferred embodiments of the present invention, and all equivalent changes and modifications made according to the scope of the patent application of the present invention shall fall within the scope of the present invention.

10: Base

14: Semiconductor channel

16: Doping area

17: Gate to Gate Dielectric Layer

17-1, 17-2: composite layer

18: Conductor layer

19: Dielectric core

103: memory

120: Insulation structure

121: source contact

131: barrier layer

132: Memory layer

132a: the first memory part

132a-1: vertical part

132a-2: Lateral part

132b: the second memory part

133: Channel layer

134: semiconductor layer

173: air gap

Claims (16)

A method for forming a three-dimensional (3D) memory, comprising: forming an initial channel hole in a stack structure of a plurality of first layers and a plurality of second layers alternately arranged above a substrate; An offset is formed between a side surface of each of the first layers and a side surface of each of the second layers to form a via hole; a semiconductor channel is formed by filling the via hole with a channel forming structure, the The semiconductor channel has a memory layer comprising a first memory portion surrounding the bottom of each of the second layers and a second memory portion connecting adjacent first memory portions, the first The memory portion and the second memory portion are staggered along a vertical direction perpendicular to the top surface of the substrate; a plurality of conductor layers are formed from the plurality of second layers; and a plurality of conductor layers comprising a gate-to-gate dielectric layer of at least one silicon oxynitride sub-layer, wherein forming the gate-to-gate dielectric layer includes: forming a first initial gap opening extending in the stack structure and exposing the substrate ; performing an etching process to remove the plurality of first layers, thereby forming a plurality of lateral recesses; depositing a silicon nitride layer to fill each of the lateral recesses; and oxidizing the silicon nitride layer by controlling the oxygen diffusion concentration , such that the gate-to-gate dielectric layer includes the at least one silicon oxynitride sublayer. According to the method for forming a three-dimensional (3D) memory described in claim 1, wherein the plurality of second layers include polysilicon, and forming the gate-to-gate dielectric layer further includes: from each A part of each second layer forms a composite layer, the remaining part of the corresponding second layer forms a corresponding conductor layer, and a pair of composite layers facing each other on the adjacent conductor layers form the gate-to-gate a dielectric layer, the first initial slot opening forms a second initial slot opening, and the composite layer has at least a silicon oxynitride sublayer. According to the method for forming a three-dimensional (3D) memory according to claim 2 of the patent application, wherein forming the composite layer and the plurality of conductor layers includes: passing through the first initial slit opening and the plurality of The lateral recesses perform one or more oxidation reactions and nitridation reactions on the plurality of second layers, the reacted portion of each of the second layers forms a corresponding said composite layer, and the unreacted portion of each of the second layers The reacting portions form the respective conductor layers. The method for forming a three-dimensional (3D) memory according to claim 3, wherein forming the composite layer includes controlling oxygen diffusion concentration so that the composite layer includes the at least one silicon oxynitride sublayer. According to the method for forming a three-dimensional (3D) memory according to claim 1, wherein the plurality of first layers and the plurality of second layers are formed by: above the substrate Alternately depositing a plurality of insulating material layers and a plurality of sacrificial material layers to form an initial stack structure above the substrate, the plurality of insulating material layers having an etching selectivity different from that of the plurality of second material layers; and The plurality of insulating material layers and the plurality of sacrificial material layers are repeatedly etched along the vertical direction to form the stacked structure, the stacked structure has the plurality of first layers and the plurality of second layers. According to the method for forming a three-dimensional (3D) memory according to claim 5, wherein forming the gate-to-gate dielectric layer includes: forming a layer extending in the stack structure and exposing the substrate opening a first initial slit; and performing an etching process to remove the plurality of second layers, thereby forming a plurality of lateral recesses. The method for forming a three-dimensional (3D) memory according to claim 6, wherein the plurality of first layers comprise silicon nitride and forming the gate-to-gate dielectric layer comprises: from each The first layer forms the gate-to-gate dielectric layer having at least one silicon oxynitride sublayer; and a second initial slit opening from the first initial Slit opening. According to the method for forming a three-dimensional (3D) memory according to claim 1 of the patent application, wherein forming the gate-to-gate dielectric layer includes: opening through the first initial gap and the plurality of lateral An oxidation reaction is performed on the plurality of first layers to at least partially oxidize the plurality of first layers, the reacted portion of each of the first layers forming a composite layer having at least one silicon oxynitride sublayer. A method for forming a three-dimensional (3D) memory, comprising: forming initial via holes in a stacked structure of a plurality of first layers and a plurality of second layers alternately arranged over a substrate, wherein the material of the second layers includes polysilicon; forming an offset between the side surface of each of the first layer and the side surface of each of the second layer on the sidewall of the initial via hole to form a via hole; filling by utilizing the via formation structure The via hole is used to form a semiconductor channel, and the semiconductor channel has a memory layer, and the memory layer includes a first memory part surrounding the bottom of each second layer and a first memory part connecting adjacent first memory parts. Two memory portions, the first memory portion and the second memory portion are interleaved along a vertical direction perpendicular to the top surface of the substrate; the plurality of first layers are removed; and the plurality of first layers are removed; The second layer undergoes an oxidation reaction or a nitriding reaction such that a portion of each of said second layers forms Forming a gate-to-gate dielectric structure, the corresponding remaining portion of said second layer forms a corresponding conductor layer. The method for forming a three-dimensional (3D) memory according to claim 9, wherein forming the gate-to-gate dielectric structure includes: forming a composite layer from a portion of each of the second layers, A pair of the composite layers facing each other on adjacent conductive layers form the gate-to-gate dielectric structure, and the composite layers have at least one silicon oxynitride sublayer. The method for forming a three-dimensional (3D) memory according to claim 10, wherein forming the gate-to-gate dielectric structure further includes forming an air gap between the pair of composite layers. The method for forming a three-dimensional (3D) memory according to claim 9, wherein forming the gate-to-gate dielectric structure includes filling each lateral recess with a gate-to-gate dielectric layer, The gate-to-gate dielectric layer includes at least one silicon oxynitride sublayer. The method for forming a three-dimensional (3D) memory according to claim 9, wherein forming the gate-to-gate dielectric structure includes: forming a gate extending in the stack structure and exposing the substrate A first initial slit opening; and removing one of the plurality of first layers and the plurality of second layers includes removing the plurality of second layers to form a plurality of lateral recesses. The method for forming a three-dimensional (3D) memory according to claim 13, wherein the plurality of first layers comprise silicon nitride, and forming the gate-to-gate dielectric structure comprises: from Each of said first layers forms a gate-to-gate dielectric layer having to one less silicon oxynitride sublayer; and forming a second initial slot opening from the first initial slot opening. A three-dimensional (3D) memory comprising: a stack structure including a plurality of conductor layers insulated over a substrate by a gate-to-gate dielectric structure, wherein the gate-to-gate dielectric structure is along A vertical direction perpendicular to the top surface of the substrate includes a pair of composite layers and an air gap between the pair of composite layers between adjacent conductor layers, wherein the pair of composite layers are respectively located in adjacent and facing each other, the air gap extends between the entire composite layer; a semiconductor channel extending from the top surface of the stack structure to the substrate, wherein the semiconductor channel includes A memory layer, the memory layer includes a first memory portion surrounding the bottom of each conductor layer and a second memory portion connecting adjacent first memory portions, the first memory portion and the a second memory portion staggered along the vertical direction; and a source structure extending from the top surface of the stack structure to the base. According to the three-dimensional (3D) memory according to claim 15, wherein each pair of composite layers includes at least a silicon oxynitride sublayer, and each of the composite layers is located at the end of the corresponding first memory part between departments.

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