TWI782575B - Memory device and method of manufacturing the same - Google Patents

Abstract

Provided is a memory device including a stack structure, a plurality of channel layers, a source line, a bit line, a switching layer, and a dielectric pillar. The stack structure has a plurality of dielectric layers and a plurality of conductive layers stacked alternately. The channel layers are respectively embedded in the conductive layer. The source line penetrates through the stack structure to be electrically connected to the channel layers at first sides of the channel layers. The bit line penetrates through the stack structure to be coupled to the channel layers at second sides of the channel layers. The switching layer wraps the bit line to contact the channel layers at the second sides of the channel layers. The dielectric pillar penetrates through the channel layers to divide each channel layer into a doughnut shape. A method of manufacturing a memory device is also provided.

Description

Memory element and manufacturing method thereof

The invention relates to a memory element and a manufacturing method thereof.

With the advancement of semiconductor technology, all kinds of electronic products are developing towards high speed, high performance, and thin, light and compact. Under this trend, the demand for memory with higher storage capacity is also increasing. Therefore, the design of memory has also been developed towards a three-dimensional memory structure with high integration and high density.

The invention provides a memory element and a manufacturing method. The gates at the same level surround multiple memory cells, so that the multiple memory cells share the same gate voltage, thereby simplifying the gate wiring layout.

The invention provides a memory element and a manufacturing method, which can increase the current of the memory cell by increasing the thickness of the channel layer in the vertical direction. In this case, the present invention can effectively utilize the area of the wafer in the horizontal direction to increase the integration of memory elements, thereby facilitating the miniaturization of the wafer.

The invention provides a memory element including: a stack structure, multiple channel layers, source lines, bit lines, switching layers and dielectric pillars. The stack structure has a plurality of dielectric layers and a plurality of conductor layers stacked alternately. A plurality of channel layers are respectively embedded in the plurality of conductor layers. The source line runs through the stack structure to be electrically connected to the plurality of channel layers at the first side of the plurality of channel layers. The bit line runs through the stack structure to be coupled with the plurality of channel layers at the second side of the plurality of channel layers. A switching layer covers the bit lines to contact the plurality of channel layers at the second side of the plurality of channel layers. A dielectric post runs through the plurality of channel layers to segment each channel layer into a donut shape.

The present invention provides a method for manufacturing a memory element, comprising: forming a stack structure having a plurality of dielectric layers and a plurality of conductor layers alternately stacked; forming a first opening in the stack structure to penetrate through the stack structure; etching the plurality of conductive layers exposed to the first openings to form a plurality of first recesses; forming a gate dielectric layer on sidewalls of the plurality of conductive layers exposed to the plurality of first recesses; A plurality of channel layers are respectively formed in the plurality of first recesses; a dielectric column is formed in the first opening to contact the plurality of channel layers; formed at a first side of the plurality of channel layers A source line penetrating through the stack structure; a bit line penetrating the stack structure is formed at a second side of the plurality of channel layers; and a switching layer is formed covering the bit line.

1, 2: memory components

10, 12, 14, 16, 18, 20, 22, 24: opening

11, 17, 19, 21: Depression

24s: inner surface

102:Stack structure

104: Dielectric layer

104s, 104s1, 104s2, 106s, 117s, 119s, 120s, 121s: side wall

106: conductor layer

108: gate dielectric layer

110: channel material layer

111: Dielectric column

112, 112a, 112b, 114, 114a, 114b: isolation structures

117: first contact layer

119: second contact layer

120: Channel layer

120t: Thickness

121: electrode layer

122: source line

124: switch layer

126: bit line

MC: memory cell

S1: first side

S2: second side

1A to 1S are schematic plan views of a manufacturing process of a memory device according to a first embodiment of the present invention.

2A to 2S are schematic cross-sectional views of a manufacturing process of a memory device according to the first embodiment of the present invention.

FIG. 3 is a schematic perspective view of the memory cell in FIG. 1S .

4 is a schematic cross-sectional view of a memory device according to a second embodiment of the present invention.

The present invention will be described more fully with reference to the drawings of this embodiment. However, the present invention can also be embodied in various forms and should not be limited to the embodiments described herein. The thicknesses of layers and regions in the drawings may be exaggerated for clarity. The same or similar symbols indicate the same or similar elements, and the following paragraphs will not repeat them one by one.

1A to 1S are schematic plan views of a manufacturing process of a memory device according to a first embodiment of the present invention. 2A to 2S are schematic cross-sectional views of a manufacturing process of a memory device according to the first embodiment of the present invention. In the following embodiments, FIG. 1A to FIG. 1S are schematic plan views taken along line I-I of FIG. 2A to FIG. 2S . For the sake of brevity, only the line I-I is shown in FIG. 2A , and is omitted in FIG. 2B to FIG. 2S .

First, referring to FIG. 1A and FIG. 2A , a stacked structure 102 having a plurality of dielectric layers 104 and a plurality of conductive layers 106 stacked alternately is formed. In some embodiments, the material of the dielectric layer 104 includes a dielectric material, such as silicon oxide, silicon nitride, oxynitride Silicon or combinations thereof. The material of the conductive layer 106 includes doped polysilicon, undoped polysilicon or a combination thereof. In this embodiment, the dielectric layer 104 may be a silicon oxide layer, and the conductive layer 106 may be a heavily doped P-type (P+) polysilicon layer. Although FIG. 2A only shows three dielectric layers 104 and two conductive layers 106 , the present invention is not limited thereto. In other embodiments, the numbers of the dielectric layers 104 and the conductive layers 106 can be adjusted according to requirements.

Referring to FIG. 1B and FIG. 2B , a plurality of openings 10 are formed in the stack structure 102 to penetrate the stack structure 102 .

Referring to FIG. 1C and FIG. 2C , a first etching process is performed to laterally etch back the conductive layer 106 exposed in the opening 10 (ie, the first opening), thereby forming a plurality of depressions 11 (ie, the first depression). In some embodiments, the first etching process includes a wet etching process using a suitable etchant to selectively etch the conductor layer 106 . For example, when the dielectric layer 104 is a silicon oxide layer and the conductive layer 106 is a P-type polysilicon layer, an etchant containing chlorine can be used. In this case, the sidewall 106s of the conductor layer 106 is recessed from the sidewall 104s of the dielectric layer 104 such that the recess 11 is formed between adjacent dielectric layers 104 .

Referring to FIG. 1D and FIG. 2D , a thermal oxidation process is performed to form a gate dielectric layer 108 on the sidewall 106 s of the conductive layer 106 exposed in the recess 11 . In this case, as shown in FIG. 1D , the gate dielectric layer 108 laterally surrounds the composite opening formed by the recess 11 and the opening 10 . In some embodiments, the gate dielectric layer 108 may be a silicon oxide layer.

Referring to FIG. 1E and FIG. 2E , a channel material layer 110 is formed to fill in the recess 11 and the opening 10 . In some embodiments, the channel material layer 110 includes polysilicon, epitaxial silicon, indium gallium zinc oxide (IGZO) or a combination thereof. In this example, the channel The material layer 110 may be lightly doped P-type (P−) polysilicon, whose doping concentration is lower than that of the conductive layer 106 (P+ polysilicon layer). That is to say, the channel material layer 110 and the conductor layer 106 may have the same conductivity type.

Referring to FIG. 1F and FIG. 2F , the excess channel material layer 110 on the sidewall 104 s of the dielectric layer 104 is removed to form a plurality of channel layers 120 in the recesses 11 . In this case, as shown in FIG. 2F , the sidewalls 120 s of the channel layer 120 may be aligned with the sidewalls 104 s of the dielectric layer 104 . However, the present invention is not limited thereto. In other embodiments, the sidewall 120s of the channel layer 120 may also be slightly recessed from the sidewall 104s of the dielectric layer 104 .

Referring to FIG. 1G and FIG. 2G , a dielectric column 111 is formed in the opening 10 to contact the donut-shaped channel layer 120 , so that the dielectric column 111 is surrounded by the channel layer 120 and the dielectric layer 104 . The dielectric pillar 111 may have the same or different dielectric material from the dielectric layer 104 .

Referring to FIG. 1H and FIG. 2H , an opening 12 penetrating through the stack structure 102 is formed at the first side S1 of the channel layer 120 , and an opening 14 penetrating through the stack structure 102 is formed at the second side S2 of the channel layer 120 . The first side S1 of the channel layer 120 is opposite to the second side S2 of the channel layer 120 . Specifically, the gate dielectric layer 108 can be regarded as a stop layer for forming the openings 12 , 14 . Accordingly, the first side S1 of the channel layer 120 may protrude and extend into the opening 12 , and the second side S2 of the channel layer 120 may protrude and extend into the opening 14 .

Referring to FIG. 1I and FIG. 2I, the isolation material is filled into the opening 12 and the opening 14 respectively to form the isolation structure 112 at the first side S1 of the channel layer 120 and to form the isolation structure at the second side S2 of the channel layer 120. 114. In this case, the isolation structures 112 and 114 respectively penetrate through the stack structure 102 to be in contact with the channel layer 120 . exist In this embodiment, the isolation structures 112 and 114 are used to electrically isolate the channel layer 120 at the same level. In some embodiments, the isolation material includes a dielectric material such as silicon oxide, silicon nitride, silicon oxynitride or a combination thereof.

1J and FIG. 2J, an opening 16 (that is, a second opening) penetrating the isolation structure 112 is formed at the first side S1 of the channel layer 120, and an opening 16 penetrating the isolation structure 114 is formed at the second side S2 of the channel layer 120. Opening 18 (ie the third opening). Specifically, part of the gate dielectric layer 108 at the first side S1 of the channel layer 120 may be further removed, so that the opening 16 contacts the first side S1 of the channel layer 120 . On the other hand, part of the gate dielectric layer 108 at the second side S2 of the channel layer 120 may be further removed so that the opening 18 contacts the second side S2 of the channel layer 120 . In addition, each of the openings 16 and 18 is surrounded by the isolation structures 112a, 114a and the channel layer 120, and after the openings 16, 18 are formed, each of the isolation structures 112a and each of the isolation structures 114a becomes an "I" shape.

1K and FIG. 2K, a second etching process is performed to laterally etch back a part of the first side S1 of the channel layer 120 exposed to the opening 16, thereby forming a plurality of depressions 17 communicating with the opening 16 (ie, the second depressions), and laterally etch back a portion of the second side S2 of the channel layer 120 exposed to the openings 18, thereby forming a plurality of depressions 19 (ie, third depressions) communicating with the openings 18 . In some embodiments, the second etching process includes a wet etching process using a suitable etchant to selectively etch the channel layer 120 . For example, when the dielectric layer 104 and the isolation structures 112 a and 114 a are silicon oxide layers and the channel layer 120 is a P-polysilicon layer, an etchant containing chlorine may be used.

Please refer to FIG. 1L and FIG. 2L, a plurality of first contacts are respectively formed in the recesses 17. contact layer 117, and form a plurality of second contact layers 119 in the recesses 19, respectively. In some embodiments, the first contact layer 117 and the second contact layer 119 can be formed by forming a contact material layer to fill the recesses 17, 19 and cover the sidewall 104s of the dielectric layer 104, and then remove the sidewall 104s of the dielectric layer 104. The excess contact material layer on the top is formed. In this embodiment, the contact material layer may be a heavily doped N-type (N+) polysilicon layer. That is to say, the first contact layer 117 has the same conductivity type as the second contact layer 119 , but has a different conductivity type from the channel layer 120 (or the conductor layer 106 ). After forming the first contact layer 117 and the second contact layer 119, as shown in FIG. The sidewall 104s2 of the dielectric layer 104 . But the present invention is not limited thereto. In other embodiments, the sidewall 117s of the first contact layer 117 can be slightly recessed in the sidewall 104s1 of the dielectric layer 104, and the sidewall 119s of the second contact layer 119 can also be slightly recessed in the intermediate layer. The sidewall 104s2 of the electrical layer 104 . In this embodiment, the first contact layer 117 and the second contact layer 119 can be formed in the same step.

Referring to FIG. 1M and FIG. 2M, the isolation materials are respectively filled into the openings 16 and 18, so that each first contact layer 117 and each second contact layer 119 are covered by the dielectric layer 104, the channel layer 120 and the isolation structure 112a. , 114a surrounded by one. In some embodiments, the isolation material includes a dielectric material such as silicon oxide, silicon nitride, silicon oxynitride or a combination thereof. In this embodiment, the isolation material can have the same material as the isolation structures 112a, 114a and the gate dielectric layer 108, so they are shown as the same film layer in FIG. 1M and FIG. 2M.

Please refer to FIG. 1N and FIG. 2N, on the outside (sidewall) of the second contact layer 119 An opening 20 (ie, a fourth opening) passing through the isolation structure 114b (or 112b) is formed at 119s. In this case, as shown in FIG. 2N, the opening 20 exposes the outer side 119s of the second contact layer 119, and the opening 20 is surrounded by the isolation structure 114b (or 112b), wherein after the opening 20 is formed, the isolation structure 114b (or 112b ) becomes a "U" shape.

Referring to FIG. 1O and FIG. 2O , a third etching process is performed to laterally etch back the portion of the second contact layer 119 exposed to the opening 20 , thereby forming a plurality of depressions 21 (ie, fourth depressions) communicating with the opening 20 . In some embodiments, the third etching process includes a wet etching process using a suitable etchant to selectively etch the second contact layer 119 . For example, when the dielectric layer 104 and the isolation structures 112 b and 114 b are silicon oxide layers and the second contact layer 119 is an N+ polysilicon layer, an etchant containing chlorine may be used.

Referring to FIG. 1P and FIG. 2P , a plurality of electrode layers 121 are respectively formed in the recesses 21 . In some embodiments, the electrode layer 121 can be formed by using, for example, chemical vapor deposition (CVD) to form an electrode material layer (such as a TiN layer) to fill the recess 21 and cover the sidewall 104s2 of the dielectric layer 104, and then removed. The excess electrode material layer on the sidewall 104s2 of the dielectric layer 104 is formed. In this case, as shown in FIG. 2P , the sidewall 121s of the electrode layer 121 can be aligned with the sidewall 104s2 of the dielectric layer 104 . However, the present invention is not limited thereto. In other embodiments, the sidewall 121s of the electrode layer 121 may also be slightly recessed from the sidewall 104s2 of the dielectric layer 104 .

1Q and FIG. 2Q, the isolation material is filled into the opening 20, so that the electrode layer 121 is surrounded by the dielectric layer 104, the second contact layer 119 and the isolation structures 112b, 114b. In some embodiments, the isolation material includes a dielectric material such as silicon oxide, silicon nitride, silicon oxynitride or a combination thereof. In this embodiment, the isolation material can be It has the same material as the isolation structures 112b and 114b, so it is shown as the same film layer in FIG. 1Q and FIG. 2Q.

Referring to FIG. 1R and FIG. 2R , an opening 22 (ie, a fifth opening) penetrating the isolation structure 112 b (or 114 b ) is formed at the outer side (sidewall) 117 s of the first contact layer 117 . Next, a source line material (such as W with a TiN liner layer) is filled in the opening 22 to form a source line 122 contacting the first contact layer 117 .

Referring to FIG. 1S and FIG. 2S , an opening 24 (ie, a sixth opening) penetrating through the isolation structure 114 b (or 112 b ) is formed at the outer side (sidewall) 121 s of the electrode layer 121 . Next, the switching layer 124 is formed on the inner surface 24 s of the opening 24 to contact the electrode layer 121 . Then, a bit line material (for example, a suitable conductive material such as Ti) is filled in the opening 24 to form a bit line 126 covered by the switching layer 124 , thereby completing the memory element 1 .

Referring to FIG. 1S and FIG. 2S , the present disclosure provides a memory device 1 comprising: a stack structure 102 , a plurality of channel layers 120 , source lines 122 , bit lines 126 , switching layers 124 and dielectric pillars 111 . The stack structure 102 has a plurality of dielectric layers 104 and a plurality of conductive layers 106 stacked alternately. The channel layers 120 are respectively embedded in the conductor layers 106 . The source line 122 runs through the stack structure 102 to be electrically connected to the channel layer 120 at the first side S1 of the channel layer 120 . The bit line 126 runs through the stack structure 102 to be coupled to the channel layer 120 at the second side S2 of the channel layer 120 . The switching layer 124 covers the bit line 126 to be in contact with the channel layer 120 at the second side S2 of the channel layer 120 . The dielectric pillars 111 penetrate through the channel layers 120 to divide each channel layer 120 into a donut shape.

In some embodiments, switching layer 124 may include one or more than one layer. Bitline 126 may include one layer or more than one layer.

In some embodiments, the material of the switching layer 124 includes a variable resistance material, a phase change material, a ferroelectric material, a capacitive material or a combination thereof. That is, depending on the material of the switching layer 124, the memory element 1 can be a resistive random access memory (resistive random access memory, RRAM), a phase change random access memory (phase change random access memory, PCRAM), Ferroelectric random access memory (FeRAM), dynamic random access memory (dynamic random access memory, DRAM) or a combination thereof. Specifically, the memory cell MC may include a portion of the source line 122 and a portion of the bit line 126 coupled to the channel layer 120 . When the memory element 1 is an RRAM, the memory cell MC may include a 1-transistor-1-resistor (1T1R) configuration. As shown in FIG. 1S, a 1-transistor (1T) includes: a first contact layer 117 used as a source, a second contact layer 119 used as a drain, and a gate or a word line Conductor layer 106. 1 resistor (1R) includes: a switching layer 124 used as a variable resistance layer, which can change the resistance value of the resistor by changing the applied bias voltage, so that the element is in a high resistance state ( High resistance state) or low resistance state (Low resistance state), and thus judge 0 or 1 of the digital signal. The switching layer 124 may include sub-layers for regulating the movement of charged species (eg, ions, electrons, holes), and the sub-layers support the actual resistance change structure, such as a filament. In some embodiments, the bit line 126 may include a sub-layer in contact with the switching layer 124, and the sub-layer serves as a reservoir for charged species. In other embodiments, the entire bit line 126 may be considered a repository. In some embodiments, as shown in FIG. 1S, the source line 122 of a memory cell MC is connected to The bit lines 126 of adjacent memory cells MC are configured in the same isolation structure 112b or isolation structure 114b. In other words, the isolation structures 112 and 114 can be used to electrically isolate the memory cells MC at the same level to prevent sneak current or other memory cell interference phenomena.

FIG. 3 is a schematic perspective view of the memory cell in FIG. 1S .

As shown in FIG. 3 , the embodiment of the present invention can increase the current of the memory cell MC by increasing the thickness 120 t of the channel layer 120 in the vertical direction. That is to say, when the thickness 120t of the channel layer 120 is thicker, the current of the memory cell MC also increases accordingly. In this case, the embodiment of the present invention can effectively utilize the area of the wafer in the horizontal direction to increase the density of the memory element 1 , thereby facilitating the miniaturization of the wafer. In addition, the electrode layer 121 may not be buried in the second contact layer 119 , but disposed between the switching layer 124 and the channel layer 120 and between the switching layer 124 and the second contact layer 119 , as shown in FIG. 3 .

4 is a schematic cross-sectional view of a memory device according to a second embodiment of the present invention.

As shown in FIG. 4 , the conductive layer 106 (ie gate or word line) of the memory device 2 in the second embodiment surrounds multiple memory cells MC horizontally, so that multiple memory cells MC share the same gate voltage. In this case, the wiring layout of the gate electrodes at the same level can be simplified to reduce the manufacturing steps and manufacturing cost of the memory element.

1: memory element

24: opening

24s: inner surface

106: conductor layer

108: gate dielectric layer

111: Dielectric column

112b, 114b: isolation structure

117: first contact layer

119: second contact layer

120: Channel layer

121: electrode layer

122: source line

124: switch layer

126: bit line

MC: memory cell

S1: first side

S2: second side

Claims (12)

A memory element, comprising: a stack structure, with a plurality of dielectric layers and a plurality of conductor layers stacked alternately; a plurality of channel layers, respectively embedded in the plurality of conductor layers; a source line running through the stack structure, to be electrically connected to the plurality of channel layers on the first side of the plurality of channel layers; the bit line runs through the stack structure to be connected to the plurality of channel layers on the second side of the plurality of channel layers The channel layer is coupled; the switching layer wraps the bit line to be in contact with the plurality of channel layers on the second side of the plurality of channel layers, wherein the switching layer is configured on the bit line wires and the plurality of channel layers to structurally separate the bit lines from the plurality of channel layers; and dielectric pillars penetrating the plurality of channel layers to divide each channel layer into donut shape. The memory element according to claim 1, further comprising: a gate dielectric layer disposed between the plurality of conductor layers and the plurality of channel layers; a plurality of first contact layers respectively embedded in the plurality of within the first side of each channel layer to be in contact with the source line; a plurality of second contact layers are respectively embedded in the second side of the plurality of channel layers to be in contact with the switch a layer contact; and a plurality of electrode layers respectively embedded in the plurality of second contact layers to be in contact with the switching layer. The memory element according to claim 2, wherein the plurality of first contact layers and the plurality of second contact layers have the same conductivity type, and the plurality of channel layers have the same conductivity type as the plurality of first contact layers different conductivity types. The memory element according to claim 1, wherein the multiple channel layers have the same conductivity type as the multiple conductor layers, and the doping concentration of the multiple channel layers is less than the doping concentration of the multiple conductor layers concentration. The memory element according to claim 1, wherein a part of the source line and a part of the bit line coupled to one of the plurality of channel layers constitute a memory cell, and the plurality of conductor layers One of the memory cells horizontally surrounds the plurality of memory cells, so that the plurality of memory cells share the same gate voltage. A method for manufacturing a memory element, comprising: forming a stack structure having a plurality of dielectric layers and a plurality of conductor layers alternately stacked; forming a first opening in the stack structure to penetrate through the stack structure; The plurality of conductor layers of the first opening to form a plurality of first recesses; forming a gate dielectric layer on the sidewalls of the plurality of conductor layers exposed to the plurality of first recesses; A plurality of channel layers are respectively formed in the plurality of first depressions; a dielectric column is formed in the first opening to contact the plurality of channel layers; A source line of a stack structure; forming a bit through the stack structure at the second side of the plurality of channel layers line; and forming a switching layer enclosing the bit line. The manufacturing method of the memory element according to claim 6, wherein before forming the source line, the manufacturing method further includes: forming a penetrating stack structure at the first side of the plurality of channel layers second openings of the plurality of channel layers; forming a third opening through the stacked structure at the second side of the plurality of channel layers; laterally recessing the plurality of channel layers exposed to the second openings to form a plurality of second depressions; laterally recessing the plurality of channel layers exposed to the third opening to form a plurality of third depressions; forming a plurality of first contact layers in the plurality of second depressions; and forming a plurality of second contact layers in the plurality of third recesses, respectively. The method for manufacturing a memory element as claimed in claim 7, wherein the plurality of first contact layers and the plurality of second contact layers are formed in the same step. The manufacturing method of the memory element according to claim 7, wherein after forming the plurality of first contact layers and the plurality of second contact layers, the manufacturing method further includes: A fourth opening through the stack structure is formed at the outer side of the layer; the plurality of second contact layers exposed to the fourth opening are etched laterally to form forming a plurality of fourth recesses; and forming a plurality of electrode layers in the plurality of fourth recesses, respectively. The manufacturing method of the memory element according to claim 9, wherein after forming the plurality of electrode layers, the manufacturing method further includes: forming a hole penetrating through the stacked structure at the outer sides of the plurality of first contact layers a fifth opening; and filling the fifth opening with a source line material to form the source line contacting the plurality of first contact layers. The method for manufacturing a memory element according to claim 10, wherein after forming the source line, the manufacturing method further includes: forming a sixth opening through the stacked structure at the outer side of the plurality of electrode layers ; forming the switching layer on the sidewall of the sixth opening to contact the plurality of electrode layers; and filling bit line material in the sixth opening, so that the switching layer covers the bit line. The manufacturing method of the memory element according to claim 6, wherein after forming the dielectric pillar, the manufacturing method further includes: separating the first side and the second side of the plurality of channel layers An isolation structure is formed through the stack structure, wherein the source line and the bit line are disposed in the isolation structure.

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