TWI780760B - Image display and driving circuit thereof - Google Patents

Abstract

An image display includes a display panel and a driving circuit coupled to the display panel. Under a normal mode, the driving circuit updates an active region of the display panel. Under an ultra-wide mode, the driving circuit alternatively updates the active region and at least one non-active region of the display panel.

Description

Image display and its driving circuit

The invention relates to an image display and its drive circuit.

Image displays, such as liquid crystal displays, have the advantages of low radiation and low power consumption, so they have become the mainstream of the market.

Using GOA technology (Gate on Array), the gate driver ICs on the left and right sides of the panel are designed and fabricated on the glass substrate, which can greatly reduce the number of panel driver ICs used and achieve ultra-narrow bezel design.

In addition, in terms of currently used operating modes, it has been proposed that the video display has a mode switch, and the mode switch can be switched between the normal mode and the ultra-wide mode.

In the normal mode, the entire display screen is an active area, while in the ultra-wide mode, the display screen is divided into an active area and an inactive area (also called a black area).

However, the current technical problem is how to reduce the leakage current to keep the black screen in the non-active area; Start scanning below.

In addition, with the demands of different operating modes, increasing the frequency to match different resolutions is also one of the industry's efforts. Therefore, how to achieve switching in accordance with the operating mode, resolution and operating frequency without increasing the circuit cost is also one of the efforts of the industry.

According to an example of the present case, an image display is proposed, including: a display panel; and, a driving circuit coupled to the display panel, wherein, when in a normal mode, the driving circuit updates an active area of the display panel, and When in an ultra-wide mode, the driving circuit alternately updates the active area and at least one non-active area of the display panel.

According to another example of this case, a driving circuit for an image display is proposed, including: a plurality of driving units, each of which driving units includes a pull-up control circuit, a pull-up circuit, a pull-down control circuit and a pull-down circuit, the pull-up The control circuit is coupled to the pull-up circuit to control the pull-up of the output signal of the first stage by the pull-up circuit; the pull-down control circuit is coupled to the pull-down circuit to control the pull-down of the output signal of the current stage by the pull-down circuit , wherein the pull-up control circuit includes a first transistor and a second transistor, the first transistor receives a start trigger signal or a previous stage start signal; the second transistor is coupled to the first stage start signal.

In order to have a better understanding of the above-mentioned and other aspects of the present invention, the following specific examples are given in detail with the accompanying drawings as follows:

10: Image display

50: display panel

60: Drive circuit

100: drive unit

110: pull-up control circuit

120: pull-up circuit

130: pull-down control circuit

140: Pull-down circuit

130_1, 103_2: pull-down control sub-circuit

140_1~140_3: pull-down sub-circuit

C: Capacitance

T11~T12, T11-1, T11-2, T21, T32~T33, T41~T44, T51~T54, T61~T64: Transistor

G1, G256, G541, G1081, G1621, G1906, GM: drive unit

500: drive unit

510: pull-up control circuit

520: pull-up circuit

530: pull-down control circuit

540: pull-down circuit

550: Auxiliary pull-down control circuit

560: auxiliary pull-down circuit

570: Auxiliary pull-up circuit

T57, T58, T67, T68, T45, Txon, Txa, Txb: Transistor

B1~B6: display sub-area

Figure 1A shows a functional block diagram of the image display according to the first embodiment of the present application, Figure 1B shows a functional block diagram of the driving circuit of the image display according to the first embodiment of the present application, and Figure 1C shows the first embodiment of the image display according to the present application The circuit diagram of the drive circuit of the example video display.

FIG. 2A shows a circuit diagram of the pull-up control circuit of the first embodiment of the present invention. FIG. 2B shows another circuit diagram of the pull-down sub-circuit of the first embodiment of the present application.

3A to 3C show several exemplary operations and signal waveform diagrams according to the first embodiment of the present invention.

FIG. 4A to FIG. 4C show other update modes of the first embodiment of the present application.

FIG. 5 shows a functional block diagram of the driving unit of the driving circuit of the video display according to the second embodiment of the present application.

FIG. 6A to FIG. 6D show the circuit structure diagrams of the auxiliary pull-down control circuit, the auxiliary pull-down circuit and the auxiliary pull-up circuit according to the second embodiment of the present invention.

FIG. 7 shows a schematic diagram of partitions of the display panel according to the second embodiment of the present invention.

8A to 8E show signal waveform diagrams of the scan start signal, the scan end signal and the conduction signal used in various operation modes according to the second embodiment of the present invention.

FIG. 9A to FIG. 9E show the signal waveform diagrams of the scan start signal, the scan end signal and the conduction signal used in various operation modes according to the second embodiment of the present invention.

Figures 10A to 10E show the signals of the scan start signal, the scan end signal and the conduction signal used in various operation modes according to the second embodiment of the present invention. Waveform diagram.

The technical terms in this specification refer to the customary terms in this technical field. If some terms are explained or defined in this specification, the explanations or definitions of these terms shall prevail. Each embodiment of the disclosure has one or more technical features. On the premise of possible implementation, those skilled in the art may selectively implement some or all of the technical features in any embodiment, or selectively combine some or all of the technical features in these embodiments.

first embodiment

Figure 1A shows a functional block diagram of the image display according to the first embodiment of the present application, Figure 1B shows a functional block diagram of the driving circuit of the image display according to the first embodiment of the present application, and Figure 1C shows the first embodiment of the image display according to the present application The circuit diagram of the drive circuit of the example video display. The image display 10 includes a display panel 50 and a driving circuit 60 coupled to the display panel 50 . Here, for example but not limited to, the display panel 50 may be a liquid crystal display panel (LCD panel), and the drive circuit 100 may be a gate circuit (Gate circuit), such as but not limited to, a GOA technology (gate substrate Array, Gate on Array). The driving circuit 60 includes a plurality of driving units 100 , such as but not limited to, gate driving units.

The driving unit 100 includes: a pull-up control circuit 110 , a pull-up circuit 120 , a pull-down control circuit 130 and a pull-down circuit 140 .

The pull-up control circuit 110 is coupled to the pull-up circuit 120 to control the pull-up of the output signal G(n) of the current stage by the pull-up circuit 120 .

The pull-down control circuit 130 is coupled to the pull-down circuit 140 to control the pull-down of the output signal G(n) of the current stage by the pull-down circuit 140 .

As shown in FIG. 1C , the pull-up control circuit 110 includes: transistors T11 - T12 , and a capacitor C. The pull-up circuit 120 includes: a transistor T21.

The pull-down control circuit 130 includes: pull-down control sub-circuits 130_1 and 103_2.

The pull-down control sub-circuit 130_1 includes: transistors T51-T54. The pull-down control sub-circuit 103_2 includes transistors T61-T64.

The pull-down circuit 140 includes: pull-down sub-circuits 140_1~140_3.

The pull-down sub-circuit 140_1 includes: a transistor T41.

The pull-down sub-circuit 140_2 includes: transistors T32 and T42.

The pull-down sub-circuit 140_3 includes: transistors T33 and T43.

In Figure 1C, Q(n), K(n) and P(n) are internal nodes. LC1 and LC2 are low frequency signals.

FIG. 2A shows a circuit diagram of the pull-up control circuit 110 of the first embodiment of the present invention. FIG. 2B shows another circuit diagram of the pull-down sub-circuit 140_1 of the first embodiment of the present invention.

As shown in FIG. 2A, the pull-up control circuit 110 includes: a first transistor T11-1, a second transistor T12 and a third transistor T11-2, wherein the third transistor T11-2 is a selective element, Can be used to reduce leakage current.

The three terminals of the first transistor T11-1 are respectively coupled to the operating voltage VGHD, the start trigger signal ST_T or the previous stage start signal ST(n-8), and the internal Node Q(n). The three terminals of the second transistor T12 are respectively coupled to the internal node HC(n), the internal node Q(n) and the stage start signal ST(n). The three terminals of the third transistor T11-2 are respectively coupled to the operating voltage VGHD, the ground voltage VSS or the start trigger signal ST_T, and the internal node Q(n).

In more detail, the display panel 50 has a resolution of 3840 (horizontal)*2160 (vertical) as an example for illustration. Currently, this display panel has 5 operation modes, as shown in Table 1 below.

In terms of the gate coupling relationship between the first transistor T11-1 and the third transistor T11-2, in the embodiment of this case, in the first-level drive unit, the gate coupling of the first transistor T11-1 Connected to the start trigger signal ST_T, the third transistor T11-2 The gate of the first transistor T11-1 is coupled to the ground voltage VSS; in the 256th, 541st, 1081st, 1621st, and 1906th drive units, the gate of the first transistor T11-1 is coupled to the start signal ST(n-8), the gate of the third transistor T11-2 is coupled to the start trigger signal ST_T; and, in other level drive units, the gate of the first transistor T11-1 is coupled to The previous start signal ST(n-8), the gate of the third transistor T11-2 is coupled to the ground voltage VSS.

Different from FIG. 1C, as shown in FIG. 2B, in another possible embodiment of this application, the pull-down sub-circuit 140_1 includes: a fourth transistor T41 and a fifth transistor T44.

The three terminals of the fourth transistor T41 are respectively coupled to the subsequent start signal ST(n+8), the ground voltage VSS and the internal node Q(n).

Three terminals of the fifth transistor T44 are respectively coupled to the internal node Q(n), the start reset signal ST_R and the ground voltage VSS.

In the embodiment of this case, for the 255th, 540, 1080, 1620, 1905 and 2160th level drive units, (A) in operation mode 1, the fourth transistor T41 is responsible for the pull-down, and after the 2160th level drive unit operates , the fifth transistor T44 will be reset; (B) in the other four operating modes, the fifth transistor T44 is responsible for the pull-down, and after the last drive unit in the active or non-active region operates, the fifth The transistor T44 is reset, and the fourth transistor T41 is turned off. For other drive units, (A) in operation mode 1, the fourth transistor T41 is responsible for pulling down, and after the 2160-level drive unit operates, the fifth transistor T44 will be reset; (B) in other Four operation modes, by the fourth transistor T41 It is responsible for pull-down, and the fifth transistor T44 will be reset after the last-level drive unit in the active area or the non-active area operates.

3A to 3C show several exemplary operations and signal waveform diagrams according to the first embodiment of the present invention. Figure 3A applies to the case of operation mode 1 (normal mode, active area: 1-2160, no non-active area). FIG. 3B and FIG. 3C are applicable to operation modes 2-5 (ultra-wide mode). In Figure 3A to Figure 3C, G1 represents the first-level drive unit, G256 represents the 256th-level drive unit, and the rest can be deduced by analogy. GM represents the M-level drive unit (M is a positive integer), and D represents display data. Take all 2160 grades as an example, M is between 1 and 2160, but M≠1, 256, 541, 1081, 1621, 1906.

As shown in Figure 3A, in the first-level drive unit G1, the start trigger signal ST_T(L/S) transmitted from the shift register will be pulled high, and the start trigger signal ST_T(L/S) The start trigger signal ST_T( 1 ) coupled to the gate of the first transistor T11 - 1 will be triggered, which is transmitted to the first-level driving unit G1 but not to other level driving units. Other start trigger signals ST_T(2)~ST_T(6) are kept at low level. The start-reset signal ST_R is activated after the 2160th driving unit ends.

Please refer to FIG. 3B , and use the operation mode 2 (ultra-wide mode, active area: 256-1905, non-active area: 1-255, 1906-2160) as an example for illustration.

In the driving units G1, G256 and G1906, the start trigger signal ST_T(L/S) transmitted from the shift register is pulled high. The start trigger signal ST_T(L/S) is individually transmitted to become the start trigger signal ST_T(1), ST_T(2) and ST_T(6), while the start trigger signal ST_T(3)~ST_T(5) is kept at low level bit. rise The reset signal ST_R is activated after the drive units G255, G1905 and 2160 are finished.

In Figure 3B, in the operation mode 2 of the ultra-wide mode, when updating, first update the 1-255 level of the non-active area, and then update the 256-1905 level of the active area, and then update the non-active area Classes 1906-2160. That is, within a frame, both the active area and the non-active area can be scanned and updated.

3B can also be applied to the operation mode 3 to the operation mode 5 of the ultra-wide mode, and the details thereof will not be repeated here.

Please refer to FIG. 3C , and use the operation mode 2 (ultra-wide mode, active area: 256-1905, non-active area: 1-255, 1906-2160) as an example for illustration.

In the driving units G1, G256 and G1906, the start trigger signal ST_T(L/S) transmitted from the shift register is pulled high. The start trigger signal ST_T(L/S) is individually transmitted to become the start trigger signal ST_T(1), ST_T(2) and ST_T(6), while the start trigger signal ST_T(3)~ST_T(5) is kept at low level bit. The start reset signal ST_R is activated after the drive units G255, G1905 and 2160 are finished.

In Figure 3C, in the operation mode 2 of the ultra-wide mode, when updating, first update the levels 1-255 of the non-active area and levels 1906-2160 of the non-active area at the same time, and then update the active area Classes 256-1905 of.

3C can also be applied to the operation mode 3 to the operation mode 5 of the ultra-wide mode, and the details thereof will not be repeated here.

The update method of Fig. 3B and Fig. 3C can also be called interlaced update mode. active zone and non-active zone.

FIG. 4A to FIG. 4C show other update modes of the first embodiment of the present application.

In Figure 4A, in the operation mode 2 of the ultra-wide mode, when updating every 6 frames (144Hz), the update sequence is non-active area 1-255 (1440Hz) (update once), active zone (150Hz) (update 6 times) and non-active zone 1906-2160 (1440Hz) (update 1 time). In Fig. 4A, in operation mode 2 of ultra-wide mode, or in every 6 frames (144Hz), when updating, the update sequence is active zone (150Hz) (update 6 times) and non-active zone Zone (720Hz) (update once, update non-active zone 1-255 and non-active zone 1906-2160 synchronously).

The same as FIG. 4A can be applied to the operation mode 4 of the ultra-wide mode, and the details thereof will not be repeated here.

In FIG. 4B , in operation mode 3 and operation mode 5 of the ultra-wide mode, when updating is performed within each frame, the update sequence is the non-active area (720 Hz) and the active area (360 Hz).

In every 6 picture frames (240Hz), when updating, the updating sequence is the active area (360Hz) (updating 6 times) and the non-active area (120Hz) (updating once).

In the first embodiment of the present application, through the above-mentioned method, the traditional electric leakage problem that the non-active area cannot be maintained can be solved, and the scanning can be started in the middle section of the display panel.

second embodiment

Fig. 5 shows the drive of the video display according to the second embodiment of the present case A functional block diagram of the driving unit 500 of the driving circuit. The driving circuit may be a gate circuit, such as but not limited to, a GOA. The driving circuit includes a plurality of driving units 500 .

The driving unit 500 includes: a pull-up control circuit 510 , a pull-up circuit 520 , a pull-down control circuit 530 , a pull-down circuit 540 , an auxiliary pull-down control circuit 550 , an auxiliary pull-down circuit 560 and an auxiliary pull-up circuit 570 . The pull-up control circuit 510, the pull-up circuit 520, the pull-down control circuit 530, and the pull-down circuit 540 may be the same or similar to the pull-up control circuit 110, the pull-up circuit 120, the pull-down control circuit 130, and the pull-down circuit 140 in Fig. 1, so it The details are not repeated here.

The auxiliary pull-down circuit 560 is coupled to the pull-down circuit 540 for pulling down the internal nodes. The auxiliary pull-down control circuit 550 is coupled to the pull-down control circuit 530 for controlling the pull-down of internal nodes.

The auxiliary pull-up circuit 570 is used to control the pull-up of the output signal G(n) of the current stage.

6A to 6D show the circuit structure diagrams of the auxiliary pull-down control circuit 550 , the auxiliary pull-down circuit 560 and the auxiliary pull-up circuit 570 according to the second embodiment of the present invention.

As shown in FIG. 6A, the auxiliary pull-down control circuit 550 includes transistors T57, T58, T67 and T68. The gates of the transistors T57, T58, T67 and T68 all receive one of the conduction signals Xon1˜6. One terminals of the transistors T57, T58, T67 and T68 are respectively coupled to internal nodes A(n), P(n), B(n) and K(n). The other terminals of the transistors T57, T58, T67 and T68 are all coupled to the ground voltage VSS.

As shown in FIG. 6B, the auxiliary pull-down circuit 560 includes: a transistor T45. The three terminals of the transistor T45 are respectively coupled to the internal node Q(n), one of the start signals ST7-ST12, and the ground voltage VSS.

As shown in FIG. 6C , the auxiliary pull-up circuit 570 includes: a transistor Txon. The three terminals of the transistor Txon are respectively coupled to the output signal G(n) of the current stage and one of the conduction signals Xon1˜6.

As shown in FIG. 6D , the auxiliary pull-up circuit 570 includes: a transistor Txa and a transistor Txb. The three terminals of the transistor Txa are respectively coupled to the output signal G(n) of the current stage, one terminal of the transistor Txb and one of the conduction signals Xon1˜6. The three terminals of the transistor Txb are respectively coupled to one terminal of the transistor Txa and one of the conduction signals Xon1˜6.

FIG. 7 shows a schematic diagram of partitions of the display panel according to the second embodiment of the present invention. In the second embodiment of the present case, the display panel is virtually partitioned into a plurality of display sub-regions. For example, taking the display panel with 2160 scanning lines in the vertical direction as an example, the display panel can be virtually partitioned into six display sub-regions B1-B6. Among them, the display sub-areas B1~B6 are respectively driven by the driving units G1~G255, G256~G540, G541~G1080, G1081~G1620, G1621~G1905, G1906~G2160. In FIG. 7, #1~#5 represent operation mode 1 to operation mode 5, respectively. Taking the operation mode 2 as an example, in the operation mode 2, the display sub-areas B1 and B6 are used to display the non-active area, the display sub-areas B2-B5 are used to display the active area, and so on.

Taking the display sub-area B1 as an example for illustration, in the driving units G1~G255, when the scan is started, it receives the scan start signal (ST_on) ST1, and when the scan ends, it receives the scan end signal (ST_off) ST7; The gate of the transistor Txon receives the turn-on signal Xon1. The rest can be deduced by analogy.

Table 2 below shows the scan start signal, scan end signal and conduction signal used in various operation modes in the second embodiment of the present invention.

8A to 8E show signal waveform diagrams of the scan start signal, the scan end signal and the conduction signal used in various operation modes according to the second embodiment of the present invention.

It can be seen from FIG. 8A to FIG. 8E that in the second embodiment of the present case, different timings are used to control different display sub-regions, wherein the scan start signal, scan end signal and conduction signal are independently controlled by different signals.

In the second embodiment of the present application, some scan start signals may be the same as the scan end signals, and some turn-on signals may be the same.

The following table 3 shows that in the second embodiment of the present case, in various operating modes Another scan start signal, scan end signal and conduction signal used below.

9A to 9E show signal waveforms of another scan start signal, scan end signal and conduction signal used in various operation modes according to the second embodiment of the present application.

It can be seen from Fig. 9A to Fig. 9E that in the second embodiment of the present case, different display sub-regions are controlled with different timings, wherein the scan start signal, scan end signal and conduction signal can be reduced by sharing each other. The number of signals required by the system.

Table 4 below shows another scan start signal, scan end signal and conduction signal used in various operation modes in the second embodiment of the present invention.

10A to 10E show signal waveform diagrams of yet another scan start signal, scan end signal and conduction signal used in various operation modes according to the second embodiment of the present application.

It can be seen from FIG. 10A to FIG. 10E that in the second embodiment of the present case, different timing sequences are used to control different display sub-regions, wherein the scan start signal, scan end signal and conduction signal are independently controlled by different signals.

In the second embodiment of this case, in five different operation modes, it is divided into multiple display sub-areas, which are controlled by different drive units respectively, with different scan start signals (ST1~6) and different scan end signals (ST7~12 ) to control the on and off of the driving units of different display sub-areas. In addition, in different operation modes, for the non-active area, the auxiliary pull-up circuit 570, the conduction signal (Xon1~6) and the auxiliary pull-down control circuit are used to write a black picture in the non-active area to maintain the inactive area.

In the embodiment of this case, G1, G256, G541, G1081, G1621 and G1906 are referred to as candidate scan start levels, because in different modes, these levels may be selected as scan start levels; and G255, G540 , G1080, G1620, G1905 and G2160 are called candidate scan end levels, because these levels may be selected as scan end levels in different modes.

It can be known from the above embodiments that in this embodiment, the black screen of the non-active area is maintained by switching the scanning/updating sequence of the active area and the non-active area under different operation modes.

It can be known from the above embodiments that in this embodiment, by virtually dividing the display screen into a plurality of display sub-areas, in different operation modes, an appropriate candidate scan start level can be selected as the scan start level, so that the operation can be increased. convenience.

What's more, in the embodiment of this case, by increasing the leakage current balance The crystal (transistor T11-2) is used in the pull-up control circuit of the driving unit, which can improve the problem of leakage current.

To sum up, although the present invention has been disclosed by the above embodiments, it is not intended to limit the present invention. Those skilled in the art of the present invention can make various changes and modifications without departing from the spirit and scope of the present invention. Therefore, the scope of protection of the present invention should be defined by the scope of the appended patent application.

G1, G256, G541, G1081, G1621, G1906, GM: drive unit

T11-1~T11-2: Transistor

Claims (12)

An image display, comprising: a display panel; and, a driving circuit coupled to the display panel, wherein, when in a normal mode, the driving circuit updates an active area of the display panel, and when in an ultra-wide mode , the driving circuit alternately updates the active area and at least one non-active area of the display panel, wherein, in the normal mode, a display frame of the display panel is the active area, and, in the ultra-wide mode, The display screen of the display panel is divided into the active area and the at least one non-active area, and the at least one non-active area displays a black picture. The video display according to claim 1, wherein, when in the ultra-wide mode, within a picture frame, the driving circuit sequentially updates a first non-active area, the active area and a second inactive zone. The video display as described in claim 1, wherein, when in the ultra-wide mode, within a picture frame, the driving circuit synchronously updates a first inactive area and a second inactive area of the display panel, and then , the driving circuit updates the active area of the display panel. The image display as described in claim 1, wherein, when in the ultra-wide mode, In a plurality of picture frames, the drive circuit updates the active area of the display panel multiple times, and then, the drive circuit updates the at least one non-active area of the display panel; or in a plurality of picture frames, the drive circuit updates A first non-active area of the display panel, the driving circuit updates the active area of the display panel multiple times, and the driving circuit updates a second non-active area of the display panel. A driving circuit for an image display, comprising: a plurality of driving units, each of which comprises a pull-up control circuit, a pull-up circuit, a pull-up control circuit and a pull-down circuit, the pull-up control circuit is coupled to the upper The pull-up circuit is used to control the pull-up of the output signal of the first stage by the pull-up circuit; the pull-down control circuit is coupled to the pull-down circuit to control the pull-down of the output signal of the current stage by the pull-down circuit, wherein the pull-up control The circuit includes a first transistor and a second transistor, the first transistor receives a start trigger signal or a previous stage start signal; the second transistor is coupled to the stage start signal; when in a In normal mode, the driving circuit updates an active area of a display panel; and when in an ultra-wide mode, the driving circuit alternately updates the active area and at least one non-active area of the display panel, wherein, in the normal mode, A display screen of the display panel is the active area, and, in the ultra-wide mode, the display screen of the display panel is divided into For the active area and the at least one non-active area, the at least one non-active area displays a black picture. The driving circuit according to claim 5, wherein the pull-up control circuit further includes a third transistor, and the third transistor receives a ground voltage or the initial trigger signal. The driving circuit as described in claim 6, wherein, in one of the first-stage driving units of the driving units, the first transistor receives the initial trigger signal, and the third transistor receives the ground voltage; In at least one candidate scan start drive unit of some drive units, the first transistor receives the previous start signal, and the third transistor receives the start trigger signal; and in other drive units, the first The gate of the transistor receives the start signal of the previous stage, and the third transistor receives the ground voltage. The driving circuit as described in claim 5, wherein the pull-down circuit includes: a fourth transistor and a fifth transistor, the fourth transistor is coupled to a subsequent start signal, the ground voltage and an internal node , the fifth transistor is respectively coupled to the internal node, an initial reset signal and the ground voltage, wherein, for at least one candidate end-of-scan driver unit of the drive units, the fourth transistor pulls down one level internal node, the fifth transistor enters the Row reset, or, the fifth transistor pulls down the internal node of the current level and resets, the fourth transistor is turned off, for the other level drive units of these drive units, when in the normal mode, by the The fourth transistor pulls down the internal node of the current stage, and after the at least one candidate scanning end driving unit operates, the fifth transistor is reset, or, when in the ultra-wide mode, the fourth transistor pulls down the The internal node of the current stage, and after the last stage driving unit in the active area or the at least one inactive area operates, the fifth transistor is reset. The driving circuit as described in claim 5, wherein each of the driving units further includes an auxiliary pull-down control circuit, an auxiliary pull-down circuit and an auxiliary pull-up circuit, and the auxiliary pull-down circuit is coupled to the pull-down circuit to connect an internal node pull-down, the auxiliary pull-down control circuit is coupled to the pull-down control circuit, and controls the pull-down of the internal node, and the auxiliary pull-up circuit controls the pull-up of the output signal of the current stage. The drive circuit as described in Claim 9, wherein the auxiliary pull-down control circuit includes: a plurality of sixth transistors, the sixth transistors receive a conduction signal, are respectively coupled to a plurality of internal nodes, and are coupled to to a ground voltage; and the auxiliary pull-down circuit includes: a seventh transistor coupled to one of the internal nodes and receiving a start signal. The driving circuit according to claim 10, wherein the auxiliary pull-up circuit includes: an eighth transistor, the eighth transistor is coupled to the output signal of the current stage and the conduction signal. The drive circuit according to claim 10, wherein the auxiliary pull-up circuit includes: a ninth transistor and a tenth transistor, the ninth transistor is coupled to the output signal of the current stage, the tenth transistor and the conduction signal, the tenth transistor is coupled to the ninth transistor and the conduction signal.

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