TWI780555B - semiconductor memory device - Google Patents

Abstract

The embodiment provides a semiconductor memory device capable of suppressing a decrease in yield. A semiconductor memory device according to one embodiment is provided with: a layered first conductor arranged above the substrate; a plurality of second conductors arranged above the first conductor and mutually connected in the first direction. separate and laminated; a plurality of pillars, which extend toward the first direction, pass through a plurality of second conductors, and include layered semiconductors electrically connected to the first conductors; and first metal plugs, which surround The first conductor is arranged on the outer periphery, and electrically connects the first conductor to the substrate.

Description

semiconductor memory device

Embodiments relate to semiconductor memory devices. [Related Application] This application claims the priority of the basic application based on Japanese Patent Application No. 2020-49267 (filing date: March 19, 2020). This application incorporates the entire content of the basic application by referring to this basic application.

A NAND type flash memory is known as a semiconductor memory device.

Embodiments provide a semiconductor memory device capable of suppressing a decrease in yield. The semiconductor memory device of the present embodiment is provided with: a layered first conductor disposed above the substrate; a plurality of second conductors disposed above the first conductor and connected to each other in the first direction. separate and stacked; a plurality of pillars, which extend toward the first direction, pass through a plurality of second conductors, and include layered semiconductors electrically connected to the first conductors; and a first metal plug, which surrounds the first conductor The first conductor is arranged on the outer periphery, and the first conductor is electrically connected to the substrate.

Hereinafter, embodiments will be described with reference to the drawings. Each embodiment shows a device or a method that embodies the technical idea of the invention. The drawings are schematic or conceptual representations, and the dimensions, ratios, etc. of each drawing may not necessarily be the same as the actual ones. The technical idea of the present invention is not limited by the shape, structure, arrangement, etc. of the constituent elements. In addition, in the following description, the same code|symbol is attached|subjected to what has substantially the same function and a component. The numerals following the characters constituting the reference symbols are used to distinguish elements that are referred to by the reference symbols including the same characters and have the same composition. When it is not necessary to distinguish elements represented by reference symbols containing the same characters, those elements are referred to by reference symbols containing only characters. 1. First Embodiment Hereinafter, a semiconductor memory device according to a first embodiment will be described. The following description will be made for the case where the semiconductor memory device is, for example, a NAND flash memory that can store data in a non-volatile manner. 1.1 Configuration of Semiconductor Memory Device 1 1.1.1 Overall Configuration of Semiconductor Memory Device 1 The overall configuration of the semiconductor memory device 1 will be described with reference to FIG. 1 . FIG. 1 shows a configuration example of a semiconductor memory device 1 according to the first embodiment. As shown in FIG. 1 , the semiconductor memory device 1 is controlled, for example, by an external memory controller 2 . The semiconductor memory device 1 includes, for example, a memory cell array (memory cell array) 10, an instruction register 11, an address register 12, a sequencer 13, a driver module 14, a row decoder module 15, and a sense amplifier module. Group 16. The memory grid array 10 includes a plurality of blocks BLK0 ˜BLKn (n is an integer greater than 1). A plurality of bit lines and a plurality of word lines are arranged in the memory cell array 10 . The block BLK is a collection of non-volatile memory cells, for example, used as a data erasing unit. Each memory frame is associated with one bit line and one word line. The detailed structure of the grid array 10 will be described later. The command register 11 stores the command CMD received by the semiconductor memory device 1 from the memory controller 2 . The command CMD includes, for example, a command for causing the sequencer 13 to execute a read operation, a write operation, an erase operation, and the like. The address register 12 holds the address information ADD received by the semiconductor memory device 1 from the memory controller 2 . The address information ADD includes, for example, a block address BAd, a page address PAd, and a column address CAd. The block address BAd, the page address PAd, and the column address CAd are used to select the block BLK, the word line, and the bit line, respectively. The sequencer 13 controls the overall operation of the semiconductor memory device 1 . For example, the sequencer 13 controls the driver module 14, the row decoder module 15, and the sense amplifier module 16 according to the instruction CMD held by the instruction temporary memory 11, so as to perform a read operation, a write operation, and an erase operation. action etc. The driver module 14 generates voltages used in read operations, write operations, and erase operations. The driver module 14 respectively applies the generated voltages to, for example, the signal lines corresponding to the selected word lines and the signal lines corresponding to the non-selected word lines according to the page address PAd held by the address register 12 . The row decoder module 15 selects a block BLK according to the block address BAd held in the address register 12 . The row decoder module 15, for example, transmits the voltages applied to the signal lines corresponding to the selected word lines and the signal lines corresponding to the non-selected word lines to the selected word lines and non-selected word lines in the selected block BLK, respectively. Select Character Lines. In the write operation, the sense amplifier module 16 applies a voltage to each bit line corresponding to the write data DAT received from the memory controller 2 . In addition, during the read operation, the sense amplifier module 16 judges the data stored in the memory cell according to the voltage of the bit line, and sends the judgment result to the memory controller 2 as the read data DAT. A single semiconductor device may be configured by combining the semiconductor memory device 1 and the memory controller 2 described above. Examples of such semiconductor devices include memory cards such as SD ^™ cards, SSDs (solid state drives), and the like. 1.1.2 Circuit Configuration of Lattice Array 10 Next, an example of the circuit configuration of the Lattice Array 10 will be described using FIG. 2 . 2 is an example of the circuit configuration of the memory cell array 10 included in the semiconductor memory device 1 according to the first embodiment, and shows one block BLK among the plurality of blocks BLK included in the memory cell array 10 extracted. As shown in FIG. 2 , the block BLK includes, for example, four string units SU0 - SU3 . In addition, the number of string units SU included in each block BLK can be designed to be any number. Each string unit SU includes a plurality of NAND strings NS associated with bit lines BL0 to BLm (m is an integer equal to or greater than 1). The NAND string NS includes, for example, four memory cell transistors MT0 - MT3 and select transistors ST1 and ST2 . In addition, the numbers of memory cell transistors MT and selection transistors ST1 and ST2 included in each NAND string NS can be designed as arbitrary numbers. The memory cell transistor MT includes a control gate and a charge storage layer, and maintains data in a non-volatile manner. Selection transistors ST1 and ST2 are respectively used for selection of string units SU in various operations. In each NAND string NS, memory cell transistors MT0 ˜ MT3 are connected in series between the source of the selection transistor ST1 and the drain of the selection transistor ST2 . The control gates of the memory cell transistors MT0 - MT3 in the same block BLK are respectively connected to the word lines WL0 - WL3 . The gates of the selection transistors ST1 included in the string units SU0 - SU3 in the same block BLK are respectively connected to the selection gate lines SGD0 - SGD3 . The drains of the select transistors ST1 corresponding to the same column among the multiple blocks BLK are commonly connected to the corresponding bit lines BL. The gates of the select transistors ST2 in the same block BLK are commonly connected to the select gate line SGS. The sources of the select transistors ST2 in each block BLK are commonly connected to the source line SL among a plurality of blocks BLK. A plurality of memory cell transistors MT connected to a common word line WL in one string unit SU is called, for example, a cell unit CU. The memory capacity of each grid unit CU varies with the number of bits of data stored by the memory grid transistor MT. For example, when each memory grid transistor MT stores 1-bit data, one grid unit CU can store 1 page of data, and when each memory grid transistor MT stores 2-bit data, one grid unit CU can store 2-bit data. page profile. As mentioned above, "one page of data" is defined as the total amount of data stored in a grid unit CU composed of a memory transistor MT for storing 1-bit data, for example. 1.1.3 Structure of the memory cell array 10 Next, an example of the structure of the memory cell array 10 included in the semiconductor memory device 1 according to the first embodiment will be described. In the drawings referred to below, the X direction corresponds to the extending direction of the word line WL, the Y direction corresponds to the extending direction of the bit line BL, and the Z direction corresponds to the p-type semiconductor substrate used to form the semiconductor memory device 1 (hereinafter simply labeled "semiconductor substrate") in the direction perpendicular to the surface. In order to make the drawing easier to see, each component is appropriately hatched in a plan view. The hatching added to the plan view does not necessarily relate to the material or performance of the constituent elements of which the hatching is added. Component elements such as an insulating layer (interlayer insulating film), wiring, contact plugs, etc. are appropriately omitted in the cross-sectional view. FIG. 3 shows an example of the planar layout of the memory cell array 10 in the first embodiment, and shows a structure corresponding to the block BLK0 extracted from a plurality of blocks BLK. In addition, the bit line BL and the interlayer insulating film are omitted. As shown in FIG. 3 , for example, the structures corresponding to the string units SU0 ˜ SU3 of the block BLK0 are respectively extended in the X direction and arranged in the Y direction. In addition, the structures respectively corresponding to the string units SU0 - SU3 are separated by, for example, a gap SLT. That is, the string unit SU extending in the X direction is provided between adjacent gaps SLT in the Y direction. In other words, the plurality of gaps SLT extending in the X direction are arranged in the Y direction. The structures divided by the adjacent gaps SLT in the Y direction correspond to one string unit SU. For example, the structural system corresponding to the string unit SU is divided into two structural bodies via a C4 region described later. A conductor corresponding to the source line SL is provided in a layer below the structural body corresponding to the string unit SU. The metal plug 22 is provided so as to contact the side surface of the conductor corresponding to the source line SL and to surround the outer periphery of the conductor corresponding to the source line SL. The memory grid array 10 includes an array area, a step area, a C4 area, and an embolism area. First, the detailed structure in the array area will be described. The array area is an area that substantially holds data. A plurality of memory pillars MP are provided in the array area. Each memory column MP functions as, for example, one NAND string NS. In addition, the number of memory pillars MP shown in FIG. 3 is schematic, and the number of memory pillars MP is not limited to the number shown. A plurality of memory columns MP may be arranged in a staggered manner. Next, the detailed structure in the step region will be described. The stepped area is an area for electrically connecting the word line WL connected to the memory pillar MP disposed in the array area, the selection gate lines SGD, SGS and the row decoder module 15 . In the step region, a plurality of conductors respectively corresponding to the selection gate line SGS, the word lines WL0 to WL3 , and the selection gate line SGD are provided in steps from the lower layer, for example. In addition, a plurality of contact plugs CC are provided in the stepped region corresponding to, for example, the selection gate line SGS, the word lines WL0 ˜ WL3 , and the selection gate line SGD, respectively. A plurality of conductors respectively corresponding to the selection gate line SGS, the word lines WL0 ˜ WL3 , and the selection gate line SGD are electrically connected to the row decoder module 15 via respective corresponding contact plugs CC. In addition, a plurality of dummy column parts HR are provided in the step region, and the plurality of dummy column parts HR penetrate at least one of the conductors 23 - 28 , and the bottom surface reaches the conductor corresponding to the source line SL. Arrangement of the virtual column HR may be arbitrary. The dummy post HR is not electrically connected to other wiring. The dummy pillar HR functions as a pillar supporting the interlayer insulating film when forming a void in the manufacturing process. Next, a detailed structure in the C4 region will be described. The C4 area is an area for connecting the electrodes (wiring lines) provided above the cell array 10 and the circuit part provided below. A plurality of contact plugs C4 are disposed in the area C4, and the electrodes disposed above the memory cell array 10 are connected to the circuit part disposed below by the plurality of contact plugs C4. In the region C4, an opening region OR through which the contact plug C4 passes through the conductor is provided on the conductor corresponding to the source line SL. Since the contact plug C4 passes through the opening region OR, it is not electrically connected to the conductor corresponding to the source line SL. In the opening region OR, a metal plug 22 is provided between the conductor corresponding to the source line SL and the contact plug C4 so as to contact the side surface of the conductor corresponding to the source line SL. In addition, the number of contact plugs C4 shown in FIG. 3 is schematic, and the number of contact plugs C4 is not limited to the number shown. Next, a detailed structure in the embolized region will be described. The plug region is a region where the metal plug 22 is provided so as to contact the side surface of the conductor corresponding to the source line SL and surround the outer periphery of the conductor corresponding to the source line SL. In the plug region, the conductor corresponding to the source line SL is electrically connected to the impurity diffusion layer region provided on the semiconductor substrate. FIG. 4 is a cross-sectional view taken along line A1-A2 in FIG. 3, showing an example of the cross-sectional structure of the memory cell array 10 in the first embodiment. In addition, a part of the insulating layer is omitted. As shown in FIG. 4 , the memory grid array 10 includes, for example, a conductor 21 , conductors 23 - 28 , and a plurality of memory pillars MP in the array area. A conductor 21 is provided on the semiconductor substrate 20 via an insulating layer (not shown). The conductor 21 is formed, for example, in a plate shape extending along the XY plane. Conductor 21 functions as source line SL. The conductor 21 is, for example, polysilicon (poly-Si). In addition, circuits such as the row decoder module 15 or the sense amplifier module 16 are provided in the area between the semiconductor substrate 20 and the conductor 21, and these circuits include a plurality of control transistors and the like. The control transistor, for example, controls the memory grid array 10 disposed above. In FIG. 4, only two N-channel MOS transistors Tr are shown as an example of control transistors. For example, a P-type well region (P well) and an element isolation region STI are provided on the upper surface (near the surface) of the semiconductor substrate 20 . Each of the P-type well region and the device isolation region STI is in contact with the upper surface of the semiconductor substrate 20 . The device isolation region STI is used for, for example, electrically separating the N-type well region (N well) and the P-type well region. For the device isolation region STI, for example, silicon oxide is used. The N-channel MOS transistor Tr includes two N ⁺ impurity diffusion layer regions, an insulating layer OX, a gate electrode GC, and an insulating layer SW. The two N ⁺ impurity diffusion layer regions are formed on the upper surface (near the surface) of the P-type well region, and are doped with phosphorus (P), for example. One N ⁺ impurity diffusion layer region and the other N ⁺ impurity diffusion layer region are separated and arranged in the X direction. The two N ⁺ impurity diffusion layer regions function as the source (source diffusion layer) and drain (drain diffusion layer) of the N-channel MOS transistor Tr. The insulating layer OX is provided on the P-type well region between the two N ⁺ impurity diffusion layer regions, and functions as a gate insulating film of the N-channel MOS transistor Tr. The insulating layer OX is formed using an insulating material, and the insulating material includes, for example, a stacked structure of silicon oxide and silicon nitride. The gate electrode GC is provided on the insulating layer OX. The insulating layer SW is provided on the side surface of the gate electrode GC of the N-channel MOS transistor Tr, and functions as a side wall. Contact plugs C1 and CS, and a wiring layer D1 are provided above the N-channel MOS transistor Tr. The contact plug C1 is a conductor provided between the gate electrode GC of the N-channel MOS transistor Tr and the wiring layer D1. The contact plug CS is an electrical conductor disposed between the source or drain of the N-channel MOS transistor Tr and the wiring layer D1. Each of the two N ⁺ impurity diffusion layer regions is electrically connected to the wiring layer D1 through the contact plug CS. The gate electrode GC is electrically connected to the wiring layer D1 through the contact plug C1. Conductors 23 to 28 are arranged sequentially from the lower layer over the conductor 21 via an insulating layer not shown, that is, in the Z direction. The conductors 23 to 28 are formed in a plate shape extending in the X direction, for example. The conductors 23-28 are respectively used as the select gate line SGS, the word lines WL0-WL3, and the select gate line SGD. Conductors 23 to 28 include tungsten (W), for example. The memory column MP is formed in a columnar shape extending in the Z direction. The memory post MP penetrates through the conductors 23 - 28 , for example, and the bottom surface reaches the inside of the conductor 21 . In other words, the memory pillar MP does not penetrate the conductor 21 . In addition, the memory pillar MP includes, for example, a core member 29 , a semiconductor 30 , insulating layers 31 to 33 , and a conductor 34 . The core member 29 is formed in a columnar shape extending in the Z direction at the center of the memory column MP. The lower end of the core member 29 is included in the conductor 21, for example. The core member 29 is, for example, silicon dioxide (SiO ₂ ). The side surfaces and the lower surface of the core member 29 are covered with the semiconductor 30 . A part of the side surface of the semiconductor 30 is in contact with the conductor 21 to be electrically connected with the conductor 21 . The semiconductor 30 functions as respective channels of the memory cell transistor MT and the select transistors ST1 and ST2. The semiconductor 30 is, for example, polysilicon (poly-Si). A part of the side surface and the lower surface of the semiconductor 30 are covered with a laminated film of the insulating layers 31 to 33 . The insulating layer 31 is in contact with the semiconductor 30 and surrounds the side surface and the bottom surface of the semiconductor 30 . The insulating layer 31 functions as a tunnel insulating film of the memory cell transistor MT. The insulating layer 31 is, for example, SiO ₂ . The insulating layer 32 is in contact with the insulating layer 31 and surrounds the side surface and the bottom surface of the insulating layer 31 . The insulating layer 32 functions as a charge storage layer of the memory cell transistor MT. The insulating layer 32 is, for example, silicon nitride (SiN). The insulating layer 33 is in contact with the insulating layer 32 and surrounds the side surface and the bottom surface of the insulating layer 32 . In addition, the laminated film of the insulating layers 31 to 33 is not provided in the region where the semiconductor 30 is in contact with the conductor 21 . The insulating layer 33 functions as a bulk insulating film of the memory cell transistor MT. The insulating layer 33 is, for example, SiO ₂ . A conductor 34 is formed on the core member 29 and the semiconductor 30 . The conductor 34 is electrically connected to the semiconductor 30 . The side surface of the conductor 34 is covered with, for example, a laminated film of the insulating layers 31 to 33 . The conductor 34 is poly-Si, for example, and can be integrally formed with the semiconductor 30 . In the configuration of the memory pillar MP described above, for example, the portion where the memory pillar MP intersects the conductor 23 functions as the selection transistor ST2. The parts where the memory post MP intersects with the conductors 24 - 27 respectively function as memory cell transistors MT0 - MT3 . The portion where the memory pillar MP intersects the conductor 28 functions as a selection transistor ST1. In addition, the memory pillar MP may be a structure in which a plurality of pillars are connected in the Z direction. For example, the memory post MP may be a structure connected by a lower post passing through the conductors 23 - 25 and an upper post passing through the conductors 26 - 28 . In the stepped area, the memory cell array 10 includes, for example, conductors 21 , 23 - 28 , and a plurality of contact plugs CC. For example, the respective ends of the conductors 23, 24-27, and 28 corresponding to the select gate line SGS, the word lines WL0-WL3, and the select gate line SGD are arranged as steps as described above. shape. However, it is not limited thereto. In the step region, the respective ends of the conductors 23-28 only need to have at least a portion that does not overlap with the conductors 24-28 disposed on the upper layer, that is, have a region connected to the contact plug CC. That's it. Each contact plug CC is formed in a columnar shape extending in the Z direction, and includes, for example, a conductor 35 . The conductor 35 is formed in a columnar shape extending from the upper surface to the lower surface of the contact plug CC. Conductor 35 includes, for example, tungsten (W). The lower surfaces of the contact plugs CC are respectively connected to the conductors 23-28. In the area C4, the memory grid array 10 includes, for example, a conductor 21, a metal plug 22, and a plurality of contact plugs C4. In the opening region OR of the conductor 21 , a metal plug 22 is provided in contact with the side surface of the conductor 21 . The metal plug 22 contains, for example, tungsten (W). Each contact plug C4 is formed in a columnar shape extending in the Z direction, and includes, for example, a conductor 36 and a spacer 37 . The conductor 36 is formed in a columnar shape extending from the upper surface to the lower surface of the contact plug C4. The spacer 37 is formed on the side surface of the conductor 36 and is formed, for example, in a cylindrical shape. In other words, the side surface of the conductor 36 is covered by the spacer 37 . Conductor 36 includes, for example, tungsten (W). The spacer 37 is, for example, SiN. The lower surface of the contact plug C4 is connected to the wiring layer D2 disposed below the memory grid array 10 . The embolized area is the peripheral area of the memory cell array 10 above which no conductors 23 - 28 are disposed. In the plug area, the memory cell array 10 includes, for example, a conductor 21 and a metal plug 22 . In addition, a wiring layer D2 electrically connected to the conductor 21 , a contact plug C2 , a wiring layer D1 , and a contact plug C1 are disposed under the memory cell array 10 in the plug area. In addition, the wiring layer D2 , the contact plug C2 , the wiring layer D1 , and the contact plug C1 electrically connected to the conductor 21 are not electrically connected to other transistors or the like. Metal plug 22 is provided so as to contact the side surface of conductor 21 . The metal plug 22 contains, for example, tungsten (W). The lower end of the metal plug 22 is connected to the wiring layer D2 disposed below the memory cell array 10 . The wiring layer D2 is connected to the wiring layer D1 via the contact plug C2. In addition, the wiring direction of the wiring layer D2 may be the extending direction of the word line WL or the extending direction of the bit line BL. The wiring layer D1 is connected to the N ⁺ diffusion layer region provided on the semiconductor substrate 20 via the contact plug C1 . In addition, the number of wiring layers and the number of contact plugs disposed under the memory grid array 10 can be designed to be arbitrary. The metal plug 22 only needs to be electrically connected to the N ⁺ diffusion layer region of the semiconductor substrate 20 . For example, two P-type well regions are provided on the upper surface (near the surface) of the semiconductor substrate 20 . One P-type well region and the other P-type well region are separated and arranged in the X direction. The N ⁺ diffusion layer region is provided between the two P-type well regions. Each of the two P-type well regions forms a PN junction between the metal plug 22 and the N ⁺ diffusion layer region provided at the connection portion of the semiconductor substrate 20, and electrically connects the metal plug 22 and other elements on the surface of the semiconductor substrate 20. separate. Thereby, other elements on the surface of the semiconductor substrate 20 are not affected by the potential or charge of the source line SL when the memory operates. In the structure of the memory cell array 10 described above, the conductors 24-27 are designed according to the number of word lines WL. A plurality of conductors 23 provided in a plurality of layers may be allocated to the select gate line SGS. When the selection gate line SGS is provided in a plurality of layers, a conductor different from the conductor 23 can be used. A plurality of conductors 28 provided in a plurality of layers may be assigned to the select gate line SGD. FIG. 5 shows an example of the three-dimensional structure of the conductor 21 and the metal plug 22 in the first embodiment, and the structure corresponding to the block BLK0 is extracted and shown. In addition, in the example of FIG. 5 , the opening region OR is omitted for convenience of description. The metal plug 22 includes a ring portion and a plug portion. The ring portion is in contact with the side surface of the source line SL (conductor 21 ), and is provided so as to surround the outer periphery of the source line SL. The plug portion electrically connects the ring portion to the wiring layer D2 provided below. In the example of FIG. 5, the plug portion is provided on the wiring layer D2 extending in the Y direction. The upper surface of the plug part is connected with the lower surface of the ring part. In addition, no plug portion is provided on the lower surface of the ring portion of the metal plug 22 extending in the X direction. 1.2 Method of Manufacturing Semiconductor Memory Device 1 FIGS. 6 and 7 are flowcharts showing an example of a method of manufacturing the semiconductor memory device 1 according to the first embodiment. 8 to 31 each show an example of the cross-sectional structure of the structure in the region R1 of FIG. 4 in the manufacturing process of the semiconductor memory device 1 according to the first embodiment. Referring to FIG. 6 and FIG. 7 , and any one of FIG. 8 to FIG. 31 , for an example of the manufacturing method of the semiconductor memory device 1, the replacement components from the formation of the interlayer insulating film to the conductors 23 to 28 are extracted. A series of processes up to the alternate lamination of insulating layers will be explained. First, as shown in FIG. 8 , on the interlayer insulating film 50 on which the contact plug C2 and the wiring layer D2 are formed, the conductor 51 and the insulating layer 52 used as a part of the source line SL are laminated (refer to the step in FIG. 6 ). S10). Specifically, after the wiring layer D2 is formed, the interlayer insulating film 50 is formed so as to cover the upper surface of the wiring layer D2. Conductors 51 are formed on the interlayer insulating film 50 . Next, an insulating layer 52 is formed on the conductor 51 . Conductor 51 is, for example, poly-Si. The insulating layer 52 is, for example, SiN. In addition, the wiring layer D2 is electrically connected to the N ⁺ diffusion layer region of the semiconductor substrate 20 through the contact plug C2 . Next, as shown in FIG. 9 , a mask 53 is formed on the insulating layer 52 by photolithography or the like, and the mask 53 is used to form a region corresponding to the source line SL (step S11 in FIG. 6 ). Next, as shown in FIG. 10 , after processing the insulating layer 52 and the conductor 51 by anisotropic etching such as RIE (Reactive Ion Etching), the mask 53 is removed (step S12 in FIG. 6 ). Next, as shown in FIG. 11, an insulating layer 54 is formed on the interlayer insulating film 50 and the insulating layer 52 (step S13 in FIG. 6). The insulating layer 54 is, for example, SiO ₂ . Next, as shown in FIG. 12, an insulating layer 55 is formed on the insulating layer 54 (step S14 in FIG. 6). The insulating layer 55 is, for example, NSG (non-silicate glass). Next, as shown in FIG. 13 , the surface is planarized by, for example, CMP (Chemical Mechanical Polishing) (step S15 in FIG. 6 ). At this time, the insulating layer 52 functions as a CMP barrier layer and is exposed on the surface after CMP. Next, as shown in FIG. 14, the insulating layer 52 is removed (step S16 in FIG. 6). At this time, for example, the insulating layer 54 and a part of the insulating layer 55 are removed together with the insulating layer 52 by etching back (etch back) using an etching condition with low material selectivity. Next, as shown in FIG. 15, an insulating layer 56 is formed (step S17 in FIG. 6). The insulating layer 56 is, for example, SiO ₂ . Next, as shown in FIG. 16, a sacrificial member 57 is formed on the insulating layer 56 (step S18 in FIG. 6). The sacrificial member 57 is removed when forming the connection between the source line SL and the memory pillar MP. The sacrificial member 57 is, for example, SiN. Next, as shown in FIG. 17 , a mask 58 is formed on the sacrificial member 57 by photolithography or the like (step S19 in FIG. 6 ). At this time, the mask area of the resist mask 58 is set to be smaller than the area of the conductor 51 in consideration of misalignment in position and the like. Next, as shown in FIG. 18 , after the sacrificial member 57 is processed by anisotropic etching such as RIE, the mask 58 is removed (step S20 in FIG. 6 ). Next, as shown in FIG. 19, an insulating layer 59 is formed (step S21 in FIG. 6). The insulating layer 59 is, for example, SiO ₂ . Next, as shown in FIG. 20 , the conductor 67 used as a part of the source line SL is formed on the insulating layer 59 (step S22 in FIG. 6 ). Conductor 67 is, for example, poly-Si. Next, as shown in FIG. 21, the insulating layer 60 is formed on the conductor 67 (step S23 in FIG. 6). The insulating layer 60 is, for example, SiN. Next, as shown in FIG. 22 , a mask 61 is formed by NIL (nanoimprint lithography) (step S24 in FIG. 7 ). The mask 61 is provided with an opening in a region corresponding to the plugging portion of the metal plug 22 . In addition, the height of the mask differs between the region of the mask 61 corresponding to the source line SL and the region outside the source line SL (including the region where the plug portion of the metal plug 22 is not provided). More specifically, the height of the mask 61 in the region corresponding to the source line SL is higher than in the region outside the source line SL. Next, as shown in FIG. 23 , a groove pattern corresponding to the metal plug 22 is formed by anisotropic etching such as RIE. Thereafter, the mask 61 is removed (step S25 in FIG. 7). Specifically, for example, a groove pattern whose bottom surface reaches the wiring layer D2 is formed in a region corresponding to the plug portion of the metal plug 22 . In a region corresponding to the source line SL, the insulating layer 60 is not etched. In the region outside the source line SL, the insulating layer 60 and the conductor 67 are removed. In the region of the plug portion where the metal plug 22 is not provided, the insulating layer 60 and the conductor 67 are removed. Therefore, in the region where the metal plug 22 is not provided, corners are formed by the side surfaces of the insulating layer 60 and the conductor 67 and the upper surface of the insulating layer 59 in the region corresponding to the source line SL. In addition, the insulating layer 56, the sacrificial member 57, and the insulating layer 59 in the region corresponding to the source line SL are removed when forming the connection region between the semiconductor 30 and the conductor 21 in the manufacturing process of the memory pillar MP. The void formed by removing the insulating layer 56, the sacrificial member 57, and the insulating layer 59 is filled with a conductive material. The conductor 21 , that is, the source line SL includes the conductive material, the conductor 51 and the conductor 67 . Next, as shown in FIG. 24, a conductor used for the metal plug 22 is formed, and a trench pattern is filled (step S26 in FIG. 7). At this time, the conductor used for the metal plug 22 is also formed on the insulating layer 59 and the insulating layer 60 . Next, as shown in FIG. 25, a metal plug 22 is formed (step S27 in FIG. 7). Specifically, it is a conductor used to remove the metal plug 22 on the insulating layer 59 and the insulating layer 60 by etching back, for example. The metal plug 22 is buried in the groove pattern in the region corresponding to the plug portion, contacts the side surfaces of the conductor 67 and the conductor 51 , and is processed into a shape vertically from the conductor 67 to the insulating layer 55 . In addition, the metal plug 22 remains in the corner formed by the side surface of the conductor 67 and the upper surface of the insulating layer 59 in the region corresponding to the source line SL in the region where no plug portion is provided. That is, the metal plug 22 is formed to surround a region corresponding to the source line SL. Next, as shown in FIG. 26, an insulating layer 62 is formed (step S28 in FIG. 7). The insulating layer 62 is NSG, for example. Next, as shown in FIG. 27 , the surface is planarized by, for example, CMP (step S29 in FIG. 7 ). At this time, a part of the surface of the insulating layer 60 is exposed. Next, as shown in FIG. 28 , a part of insulating layer 62 is processed such that the surface of insulating layer 60 is exposed in a region corresponding to source line SL by etching back (step S30 in FIG. 7 ). Next, as shown in FIG. 29 , the insulating layer 60 is removed by, for example, anisotropic etching such as RIE (step S31 in FIG. 7 ). Next, as shown in FIG. 30, an insulating layer 63 is formed (step S32 in FIG. 7). The insulating layer 63 is, for example, SiO ₂ . Next, as shown in FIG. 31 , six layers of replacement members 64 corresponding to conductors 23 to 28 and six layers of insulating layers 63 are alternately stacked (step S33 in FIG. 7 ). The six-layer replacement member 64 is replaced with the conductors 23-28 in the subsequent manufacturing process. More specifically, structures corresponding to the conductors 23 - 28 are respectively formed by using, for example, six layers of replacement members 64 in subsequent manufacturing processes. The conductors 23 to 28 can be formed by embedding a conductive material into the voids formed by removing the replacement members 64 . The replacement member 64 is, for example, SiN. 1.3 Effects of the present embodiment According to the semiconductor memory device 1 of the first embodiment described above, it is possible to suppress the decrease in the yield rate of the semiconductor memory device 1 . Hereinafter, this effect will be described in detail. In a structure in which a circuit such as a row decoder module or a sense amplifier module is provided on a semiconductor substrate, and a memory grid array is provided thereon, the source line may not be connected to the semiconductor substrate. In this case, for example, when a hole corresponding to a memory column is processed by RIE, positive charges are accumulated in a conductor corresponding to a source line, and arcing (abnormal discharge) may occur. When arcing occurs, pattern abnormalities will occur and product yield will decrease. In contrast, in the semiconductor memory device 1 of the present embodiment, the metal plug 22 can be formed. The metal plug 22 contacts the side surface of the outer periphery of the source line SL, and is connected to the upper surface of the wiring layer D2 disposed below. The wiring layer D2 is electrically connected to the N ⁺ diffusion layer region of the semiconductor substrate 20 through the underlying wiring. According to this structure, the positive charge accumulated in the source line SL during the processing of the memory pillar MP can be released to the semiconductor substrate 20 through the metal plug 22, the wiring layer D2, and the lower layer wiring. Therefore, the static elimination effect of the source line SL can be improved. Thereby, the decrease in the yield of the semiconductor memory device 1 caused by the arc can be suppressed. In addition, according to the configuration of the present embodiment, the metal plug 22 is in contact with the entire outer periphery of the conductor 21 corresponding to the source line SL. According to this structure, the contact area between the conductor 21 and the metal plug 22 increases. The static elimination effect of the semiconductor memory device 1 can be improved. In addition, according to the configuration of this embodiment, the metal plug 22 is electrically connected to the N ⁺ diffusion layer region of the p-type semiconductor substrate. Therefore, when a voltage is applied to the source line SL during a write operation or the like, current does not easily flow into the semiconductor substrate side. In addition, according to the manufacturing method of the semiconductor memory device 1 of the present embodiment, by forming the mask 61 when processing the groove pattern of the metal plug 22 using NIL, the increase in the number of manufacturing steps due to the addition of the metal plug 22 can be suppressed. 2. Second Embodiment Next, a semiconductor memory device 1 according to a second embodiment will be described. In the second embodiment, a part of the manufacturing process of the semiconductor memory device 1 described in the first embodiment is modified. The following description will focus on points different from the first embodiment. 2.1 Method of Manufacturing Semiconductor Memory Device 1 FIG. 32 is a flowchart showing an example of a method of manufacturing the semiconductor memory device 1 according to the second embodiment. 33 to 35 each show an example of the cross-sectional structure of the structure in the region R1 of FIG. 4 in the manufacturing process of the semiconductor memory device 1 according to the second embodiment. The flow chart in Fig. 32 shows the flow of step S23 following the flow chart in Fig. 6 of the first embodiment. Hereinafter, with reference to any one of FIGS. 32, 33 to 35, an example of the manufacturing method of the semiconductor memory device 1 will be extracted and described in terms of steps different from those of the first embodiment. First, steps S10 to S23 in FIG. 6 are implemented in the same manner as in the first embodiment. After the insulating layer 60 is formed in step S23 of FIG. 6 , as shown in FIG. 33 , a mask 65 is formed on the insulating layer 60 by photolithography or the like. Those who open the mouth (step S34 of Fig. 32). Next, as shown in FIG. 34 , after processing the insulating layer 60 , the conductor 67 , and the insulating layers 59 and 56 by, for example, RIE, the mask 65 is removed (step S35 in FIG. 32 ). Next, as shown in FIG. 35 , a mask 66 is formed by photolithography, etc., and the mask 66 is provided with openings in the area corresponding to the plugging portion of the metal plug 22 and the outer area of the polar line SL ( FIG. 32 . Step S36). Next, a groove pattern corresponding to the metal plug 22 is formed in the same manner as in FIG. 23 of the first embodiment. Thereafter, the mask 66 is removed (step S37 of FIG. 32). The following flow is the same as steps S26-S33 of the first embodiment. 2.2 Effects of the present embodiment According to the semiconductor memory device 1 of the second embodiment described above, the same effects as those of the first embodiment can be obtained. 3. Variations etc. As mentioned above, the semiconductor memory device of the embodiment includes: a layered first conductor (SL) arranged above the substrate (20); A plurality of second conductors (23~28) stacked apart from each other in the first direction (Z direction); extending in the first direction (Z direction), passing through a plurality of second conductors, and including the first conductor A plurality of electrically connected layered semiconductor pillars; and a first metal plug (22) arranged to surround the outer periphery of the first electrical conductor and electrically connect the first electrical conductor to the substrate. In addition, embodiment is not limited to the form demonstrated above, Various deformation|transformation is possible. In the above-mentioned embodiment, an example in which a part of the side surface of the semiconductor 30 of the memory pillar MP is in contact with the conductor 21 corresponding to the source line SL has been described, but the present invention is not limited thereto. In addition, as shown in FIG. 36, in the opening region OR of the source line SL provided in the C4 region, the metal plug 22 provided so as to be in contact with the side surface of the conductor 21 has a plug portion and is connected to the The lower wiring layer D2 may be electrically connected to the semiconductor substrate 20 via the wiring layer D2 and the lower wiring. In this case, since the current path between the conductor 21 and the semiconductor substrate 20 can be further increased, the static elimination effect of the source line SL can be further enhanced. "Connected" in this specification means to be electrically connected, and does not exclude, for example, interposing another element therebetween. Several embodiments of the present invention will be described, but these embodiments are merely illustrative examples and are not intended to limit the scope of the invention. These embodiments can be implemented in other various forms, and various omissions, substitutions, and changes can be made without departing from the gist of the invention. These embodiments and modifications thereof are included in the scope or gist of the invention, and are also included in the inventions described in the claims and their equivalents.

1: Semiconductor memory device 2: Memory controller 10: memory cell array 11: Instruction register 12: Address register 13: Sequencer 14: Driver module 15: Line decoder module 16: Sense Amplifier Module 20: Semiconductor substrate 21: Conductor 22: Metal plug 23~28: Conductor 29: core member 30: Semiconductor 31~33: insulating layer 34~36: Conductor 37: spacer 50: interlayer insulating film 51: Conductor 52: Insulation layer 53: mask 54~56: insulating layer 57: Sacrificial components 58: mask 59,60: insulating layer 61: mask 62,63: insulating layer 64: Replace components 65,66: mask 67: Conductor

[ Fig. 1] Fig. 1 is a block diagram showing a configuration example of a semiconductor memory device according to a first embodiment. [ Fig. 2] Fig. 2 is a circuit diagram showing an example of a circuit configuration of a memory cell array included in the semiconductor memory device according to the first embodiment. [ Fig. 3] Fig. 3 is a plan view showing an example of a planar layout of a cell array included in the semiconductor memory device according to the first embodiment. [FIG. 4] A cross-sectional view showing an example of a cross-sectional structure of a cell array along line A1-A2 in FIG. 3. [FIG. [ Fig. 5] Fig. 5 is a schematic perspective view showing an example of a three-dimensional structure of source lines in a cell array included in the semiconductor memory device according to the first embodiment. 6 and 7 are flowcharts showing an example of the method of manufacturing the semiconductor memory device according to the first embodiment. [ FIGS. 8 to 31 ] are cross-sectional views showing a part of a cell array as an example of the manufacturing process of the semiconductor memory device according to the first embodiment. [ Fig. 32 ] A flowchart showing an example of a method of manufacturing a semiconductor memory device according to the second embodiment. 33 to 35 are cross-sectional views showing a part of a cell array as an example of the manufacturing process of the semiconductor memory device according to the second embodiment. [FIG. 36] A cross-sectional view showing a modified example of the cross-sectional structure of the cell array along line A1-A2 in FIG. 3. [FIG.

20: Semiconductor substrate

21: Conductor

22: Metal plug

23~28: Conductor

29: core member

30: Semiconductor

31~33: insulating layer

34~36: Conductor

37: spacer

MP: memory column

CC: contact embolism

SL: source line

WL0~WL3: character line

SGD, SGS: select gate line

C4: contact plug

OX, SW: insulating layer

GC: gate electrode

STI: component separation area

P well: P-type well area

C1: contact embolism

C2: contact embolism

CS: contact embolism

D1: wiring layer

D2: wiring layer

Tr: Transistor

R1: Region

Claims (6)

A semiconductor memory device, comprising: a layered first conductor disposed above a substrate; a plurality of second conductors disposed above the first conductor and separated from each other in a first direction Stack; a plurality of pillars, which extend toward the first direction, pass through the plurality of second conductors, and include layered semiconductors electrically connected to the first conductors; first metal plugs, which contact the first conductors 1. The outer peripheral surface of the conductor, and electrically connect the first conductor to the substrate; the first plug, which passes through the first conductor and the plurality of second conductors, and the side surface is not connected to the first conductor. A conductor is in contact with the plurality of second conductors; and a second metal plug is in contact with a side surface of an opening region through which the first plug passes. The semiconductor memory device according to claim 1, further comprising: a first wiring layer disposed between the substrate and the first conductor; the first metal plug includes: a first portion surrounding the first conductor the aforementioned outer periphery, and contact the side surface of the aforementioned first conductor; and a second portion, which electrically connects the aforementioned first portion and the aforementioned first wiring layer; and the aforementioned first wiring layer is electrically connected to the aforementioned substrate. The semiconductor memory device according to claim 2, wherein the first wiring layer is arranged parallel to the substrate and facing A second direction intersecting the first direction extends, and the second portion is provided on the first wiring layer. The semiconductor memory device as claimed in claim 1, further comprising: a second wiring layer disposed between the aforementioned substrate and the aforementioned first conductor; the aforementioned second metal plug includes a third part that connects the aforementioned first The conductor is electrically connected to the second wiring layer; the second wiring layer is connected to the substrate. The semiconductor memory device according to claim 1, wherein each of the plurality of pillars comprises: the aforementioned semiconductor, a part of a side surface thereof is electrically connected to the aforementioned first electrical conductor; and a charge storage layer. The semiconductor memory device according to any one of claims 1 to 5, wherein the first metal plug contains at least tungsten.

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