TWI779799B - Chip package and method of manufacturing the same - Google Patents

Abstract

A chip package includes a redistribution layer, a chip, and an encapsulation member. The redistribution layer includes an insulation part, a plurality of first pads and a plurality of second pads, where the insulation part has a first surface, a second surface opposite to the first surface, and a side surface between the first surface and the second surface. The first pads and the second pads are located at the first surface and the second surface respectively. The chip is disposed on the first surface and electrically connected to the first pads. The encapsulation member wraps the chip and the redistribution layer, and covers the first surface and the side surface, where the encapsulation member exposes the second pads, and the encapsulation member is not flush with the first surface and the side surface.

Description

Chip package and manufacturing method thereof

The present invention relates to a chip package and a manufacturing method thereof, and in particular to a chip package including a redistribution layer (Redistribution Layer, RDL) and a manufacturing method thereof.

After the existing chip package is manufactured, a series of reliability tests will be performed to ensure the quality of the chip package. The current reliability test includes a thermal cycle test (Thermal Cycling Test, TCT). During thermal cycling testing, chip packages are exposed to extreme temperature variations. For example, the chip package can be set to be tested in an environment with a temperature varying from -55°C to 125°C. Therefore, the manufactured chip package needs to have a structure with sufficient strength to pass the thermal cycle test to ensure the quality of the chip package in terms of reliability.

At least one embodiment of the present invention provides a chip package, which utilizes a sealing member covering the chip and the redistribution layer to improve reliability.

At least one embodiment of the present invention provides a manufacturing of a chip package method to manufacture the above-mentioned chip package.

A chip package provided by at least one embodiment of the present invention includes a redistribution layer, a chip, and a sealing member. The redistribution layer includes an insulating part, a plurality of first pads and a plurality of second pads, wherein the insulating part has a first surface, a second surface opposite to the first surface, and a side between the first surface and the second surface. surface. The first pads and the second pads are respectively located on the first surface and the second surface. The chip is configured on the first surface and electrically connected to the first pads. The sealing member wraps the chip and the redistribution layer, and covers the first surface and the side surface, wherein the sealing member exposes the second pads, and the sealing member is not aligned with the first surface and the side surface.

In at least one embodiment of the present invention, the redistribution layer includes a first outer insulating layer and a second outer insulating layer. The first outer insulating layer has a first surface, and the second outer insulating layer has a second surface, wherein the first outer insulating layer is located between the chip and the second outer insulating layer.

In at least one embodiment of the present invention, the first outer insulating layer includes an insulating material and a plurality of fillers. These fillers are distributed in the insulating material.

In at least one embodiment of the present invention, the second outer insulating layer includes an insulating material and a plurality of fillers. These fillers are distributed in the insulating material.

In at least one embodiment of the present invention, the redistribution layer further includes at least one inner insulating layer. The inner insulating layer is located between the first outer insulating layer and the second outer insulating layer, wherein each of the first outer insulating layer, the second outer insulating layer and the inner insulating layer includes an insulating material and a plurality of fillers. These fillers are distributed in the insulating material.

In at least one embodiment of the present invention, the fillers are a plurality of filler particles or a plurality of filler fibers.

In at least one embodiment of the present invention, the sealing member does not cover the second surface.

In at least one embodiment of the present invention, the sealing member further covers the second surface.

In at least one embodiment of the present invention, a part of the sealing member fills up a gap between the chip and the redistribution layer.

In at least one embodiment of the present invention, the above-mentioned chip package further includes a plurality of solder bumps, wherein the solder bumps are respectively connected to the second pads.

In at least one embodiment of the present invention, the above-mentioned second surface is aligned with the outer surface of each second pad.

In at least one embodiment of the present invention, the length and width of the sealing member are respectively greater than the length and width of the redistribution layer.

A method for manufacturing a chip package provided by at least one embodiment of the present invention includes the following steps. First, an initial redistribution layer is formed on the carrier substrate. Afterwards, a plurality of chips are mounted on the initial redistribution layer. Afterwards, the initial redistribution layer is cut to form a plurality of redistribution layers separated from each other, wherein a plurality of trenches are formed between the redistribution layers. Afterwards, a sealing member is formed, wherein the sealing member wraps the wafer and the redistribution layer, and fills up the trenches. Remove the carrier substrate. Afterwards, along these grooves, seals are cut.

In at least one embodiment of the present invention, each redistribution layer has a first surface, a second surface opposite to the first surface, and a side surface between the first surface and the second surface. The step of forming a seal includes forming a first mold seal Materials are placed on the carrier substrate, wherein the first molding material covers the chips, the first surfaces and the side surfaces, but does not cover the second surfaces, and the first molding material fills up the grooves. The carrier substrate is removed after forming the first molding material.

In at least one embodiment of the present invention, the step of forming the sealing member further includes forming a second molding material on the second surfaces after removing the carrier substrate, wherein the second molding material is connected to the first molding material.

In at least one embodiment of the present invention, the manufacturing method of the chip package further includes forming a plurality of solder bumps on the redistribution layers after removing the carrier substrate and before cutting the sealing member, wherein each redistribution layer is located on one of the wafers and between multiple solder bumps.

Based on the above, since the sealing member wraps the chip and the redistribution layer, and covers the first surface and the side surface of the redistribution layer, the sealing member can strengthen the structure of the chip package to improve the reliability of the chip package, so that the chip The package can have a structure of sufficient strength to pass the thermal cycle test.

20: Carrier substrate

41m: insulating material

41p, 51f: filler

100, 300, 400a, 400b, 500: chip package

110, 410a, 410b, 510: redistribution layers

110L, 130L: Length

110W, 130W: Width

111, 411a, 411b, 511: insulating part

120: chip

121: side

129: Alignment

130, 330: seals

131: The first molding material

132: Second molding material

D11, D41, D51: the first outer insulating layer

D12, D42, D52: second outer insulating layer

D13, D43, D53: inner insulating layer

F11a: first surface

F11b: second surface

F11c: side surface

G1: Gap

P11a, P11b: conductive connection structure

S11, S12: Solder bumps

T2: Groove

W11: The first outer circuit layer

W11p: First pad

W12: The second outer circuit layer

W12p: Second pad

W12s: External surface

W13: inner circuit layer

FIG. 1A is a schematic top view of a chip package according to at least one embodiment of the invention.

FIG. 1B is a schematic cross-sectional view drawn along line 1B-1B in FIG. 1A .

2A to 2G are schematic flowcharts of the manufacturing method of the chip package in FIG. 1B .

3A to 3B are schematic flowcharts of a method for manufacturing a chip package according to another embodiment of the present invention.

4A is a schematic cross-sectional view of a chip package according to another embodiment of the present invention.

4B is a schematic cross-sectional view of a chip package according to another embodiment of the present invention.

FIG. 5 is a schematic cross-sectional view of a chip package according to another embodiment of the present invention.

In the following text, in order to clearly present the technical features of this application, the dimensions (such as length, width, thickness, and depth) of elements (such as layers, films, substrates, and regions) in the drawings will be enlarged in a non-proportional manner . Therefore, the description and explanation of the following embodiments are not limited to the size and shape of the elements in the drawings, but should cover the deviations in size, shape and both caused by actual manufacturing process and/or tolerances. For example, a planar surface shown in the drawings may have rough and/or non-linear features, while acute angles shown in the drawings may be rounded. Therefore, the components shown in the drawings of this case are mainly for illustration, and are not intended to accurately depict the actual shape of the components, nor are they used to limit the scope of the patent application of this case.

Secondly, words such as "about", "approximately" or "substantially" appearing in the content of this case not only cover the clearly stated values and numerical ranges, but also cover The allowable deviation range, which can be determined by the error generated during measurement, and this error is caused, for example, by the measurement system or process conditions Limitations of both. Additionally, "about" can mean within one or more standard deviations of the above-recited values, eg, within ±30%, ±20%, ±10%, or ±5%. Words such as "about", "approximately" or "substantially" appearing in this text can choose the acceptable deviation range or standard deviation according to optical properties, etching properties, mechanical properties or other properties, not a single The standard deviation is used to apply all properties such as the above optical properties, etching properties, mechanical properties and other properties.

FIG. 1A is a schematic top view of a chip package according to at least one embodiment of the present invention, and FIG. 1B is a schematic cross-sectional view drawn along line 1B-1B in FIG. 1A . Referring to FIG. 1A and FIG. 1B , the chip package 100 includes a redistribution layer 110 . The redistribution layer 110 includes an insulating portion 111 having a first surface F11a, a second surface F11b opposite to the first surface F11a, and a side surface F11c between the first surface F11a and the second surface F11b.

In this embodiment, the first surface F11a and the second surface F11b can be the upper surface and the lower surface of the insulating part 111 respectively, and the shape of the side surface F11c can be annular, and along the first surface F11a and the second surface F11b The edges of both are extended. In addition, the side surface F11c may be the outer edge of the redistribution layer 110 , and in the embodiment shown in FIG. 1A , the side surface F11c may surround a rectangle with four sides (not shown). The length 110L of the redistribution layer 110 is the distance between two opposite sides, and the width 110W of the redistribution layer 110 is the distance between the other two opposite sides.

The insulating part 111 may have a multi-layer structure. For example, the insulating part 111 may include a first outer insulating layer D11, a second outer insulating layer D12 and a multilayer Inner insulating layer D13. These inner insulating layers D13 are located between the first outer insulating layer D11 and the second outer insulating layer D12, and the first outer insulating layer D11, the second outer insulating layer D12 and these inner insulating layers D13 are stacked on each other, wherein the first outer insulating layer D11, the second outer insulating layer D12 and these inner insulating layers D13 An outer insulating layer D11 has a first surface F11a, and a second outer insulating layer D12 has a second surface F11b.

Materials of the first outer insulating layer D11, the second outer insulating layer D12, and the inner insulating layer D13 may be the same as each other. In this embodiment, the first outer insulating layer D11, the second outer insulating layer D12 and the inner insulating layer D13 can be made of photosensitive dielectric (Photoimageable Dielectric, PID) material or other insulating materials, such as ABF (Ajinomoto Build-up Film) resin or polypropylene (Polypropylene, PP). In addition, in other embodiments, materials of at least two of the first outer insulating layer D11 , the second outer insulating layer D12 and the inner insulating layer D13 may be different from each other.

The redistribution layer 110 may also include a first outer circuit layer W11, a second outer circuit layer W12 and a multi-layer inner circuit layer W13, wherein the inner circuit layer W13 is located between the first outer circuit layer W11 and the second outer circuit layer W12. between. Each of the first outer circuit layer W11 and the second outer circuit layer W12 includes a plurality of pads. Taking FIG. 1B as an example, the first outer circuit layer W11 includes a plurality of first pads W11p, and the second outer circuit layer W12 includes a plurality of second pads W12p.

At least one of the first outer circuit layer W11 and the second outer circuit layer W12 may further include wires. For example, in the embodiment shown in FIG. 1B, the second outer layer wiring layer W12 may further include a plurality of wires 129, while the first outer layer The circuit layer W11 only includes the first pads W11p without any wires. However, in other embodiments, the first outer wiring layer W11 may also include a plurality of wires, while the second outer wiring layer W12 may not include any wires. Therefore, FIG. 1B does not limit whether each of the first outer wiring layer W11 and the second outer wiring layer W12 includes wires. In addition, in this embodiment, each inner circuit layer W13 may include a plurality of wires and a plurality of pads (not shown).

Each inner circuit layer W13 is located between the first outer insulating layer D11 , the second outer insulating layer D12 and adjacent two of these inner insulating layers D13 . In FIG. 1B, the upper inner layer wiring layer W13 may be located between the adjacent first outer insulating layer D11 and the inner layer insulating layer D13, while the lower inner layer wiring layer W13 may be located between the adjacent first outer insulating layer D11 and the inner insulating layer D13. between the second outer insulating layer D12 and the inner insulating layer D13. The middle inner wiring layer W13 may be located between two adjacent inner insulating layers D13.

The first outer wiring layers W11 are located on the first outer insulating layer D11 , and the second outer wiring layers W12 are located on the second outer insulating layer D12 . It should be noted that the first outer circuit layer W11 located on the first outer insulating layer D11 means that the first outer circuit layer W11 in FIG. 1B can be located on (on) or above (above) the first outer insulating layer D11, or The first outer wiring layer W11 may be located in (in) the first outer insulating layer D11 . Similarly, the second outer circuit layer W12 located on the second outer insulating layer D12 means that the second outer circuit layer W12 in FIG. 1B can be located under (on) or below the second outer insulating layer D12, or the second outer layer The wiring layer W12 may be located in (in) the second outer insulating layer D12 .

In the embodiment of Figure 1B, the first outer layer W11 is a bit On the first surface F11a of the first outer insulating layer D11, the second outer wiring layer W12 is located in the second outer insulating layer D12 and does not substantially protrude from the second surface F11b, wherein the second outer wiring layer The outer surface of W12 is coplanar with the second surface F11b. Therefore, the first pads W11p located on the first surface F11a can be located on the first surface F11a and protrude from the first surface F11a, and the second pads W12p located on the second surface F11b can be located on the second surface F11a. In the surface F11b, the second surface F11b can be aligned with the outer surface W12s of each second pad W12p, as shown in FIG. 1B , and the outer surface W12s is also the outer surface of the aforementioned second outer circuit layer W12.

In addition, the redistribution layer 110 may further include a plurality of conductive connection structures P11a and P11b, wherein the conductive connection structures P11a and P11b are located in the insulating portion 111 . Taking FIG. 1B as an example, the conductive connection structures P11a can be located in the first outer insulating layer D11, and the conductive connecting structures P11b can be located in the second outer insulating layer D12 and the inner insulating layer D13. In addition, since the first outer insulating layer D11, the second outer insulating layer D12, and the inner insulating layer D13 can be made of photosensitive dielectric (PID) materials, the methods for forming these conductive connection structures P11a and P11b can be Including laser ablation or lithography.

The conductive connection structures P11 a and P11 b are electrically connected to the first outer circuit layer W11 , the second outer circuit layer W12 and the inner circuit layer W13 . Specifically, each conductive connection structure P11a is connected to the first pad W11p of the first outer circuit layer W11 and to the first outer circuit layer W11 is adjacent to the inner circuit layer W13, and each conductive connection structure P11b is connected to the second pad W12p of the second outer circuit layer W12 and adjacent two of these inner circuit layers W13. In this way, current can be transmitted between the first outer circuit layer W11 , the second outer circuit layer W12 and the inner circuit layer W13 through the conductive connection structures P11a and P11b.

In the embodiment shown in FIG. 1B , both the conductive connection structures P11a and P11b are conductive pillars, wherein the conductive connection structure P11a can be a solid conductive pillar, and the conductive connection structure P11b can be a hollow conductive pillar. However, in other embodiments, the conductive connection structure P11a can also be a hollow conductive column, and the conductive connection structure P11b can also be a solid conductive column. Alternatively, the conductive connection structures P11a and P11b can both be solid conductive pillars or hollow conductive pillars. Therefore, the conductive connection structures P11a and P11b are not limited to FIG. 1B .

It is worth mentioning that, in this embodiment, the redistribution layer 110 may include more than three circuit layers (namely, the first outer circuit layer W11, the second outer circuit layer W12, and the inner circuit layer W13) and more than three layers. The insulating layers (ie, the first outer insulating layer D11, the second outer insulating layer D12 and the inner insulating layer D13). However, in other embodiments, the redistribution layer 110 may only include two wiring layers (eg, the first outer wiring layer W11 and the second outer wiring layer W12 ) and an insulating layer between the two wiring layers.

Therefore, in a single redistribution layer 110, the number of wiring layers (such as including the first outer wiring layer W11, the second outer wiring layer W12 and the inner wiring layer W13) can be two layers, and the insulating layer (such as including the second outer wiring layer W13) can be two layers. The number of the first outer layer wiring layer W11, the second outer layer wiring layer W12 and the inner layer wiring layer W13) can be only one layer, so the wiring layer in the redistribution layer 110 The number of each of the insulating layers is not limited to that shown in FIG. 1B . For example, in other embodiments, the redistribution layer 110 may include only one inner insulating layer D13.

The chip package 100 further includes a chip 120, wherein the chip 120 is disposed on the first surface F11a of the first outer insulating layer D11, so the first outer insulating layer D11 is located between the chip 120 and the second outer insulating layer D12. The chip 120 may be an unpackaged die or a packaged chip. The chip 120 may be mounted on the first surface F11a and electrically connected to the first pads W11p. In addition, the chip package 100 can be a fan-out package structure (fan-out packaged structure), wherein the size of the chip 120 is smaller than the size of the redistribution layer 110, and the redistribution layer 110 can protrude from the side 121 of the chip 120, such as Figure 1A and Figure 1B.

In the embodiment shown in FIG. 1B , the chip 120 can be electrically connected to the first pads W11p in a flip chip manner, so the chip 120 can be electrically connected to the first pads W11p through a plurality of solder bumps S11 . In other embodiments, the chip 120 may also be electrically connected to the first pad W11p by wire bonding, so the flip-chip electrical connection between the chip 120 and the first pad W11p is not limited.

The chip package 100 further includes a sealing member 130 , wherein the sealing member 130 covers the chip 120 and the redistribution layer 110 . The sealing member 130 will cover the first surface F11a, the second surface F11b and the side surface F11c of the wafer 120 and the redistribution layer 110, and will not be aligned with the first surface F11a and the side surface F11c. In other words, the length 130L of the seal 130 is the same as the width 130W is respectively larger than the length 110L and the width 110W of the redistribution layer 110 , so that both the chip 120 and the redistribution layer 110 can be located in the sealing member 130 .

The sealing member 130 can expose the second pads W12p and not completely cover the first pads W11p, so that the solder bumps S11 can connect the first pads W11p. In this embodiment, the chip package 100 may further include a plurality of solder bumps S12. Since the sealing member 130 can expose the second pads W12p, the outer surfaces W12s of the second pads W12p are exposed, so that the solder bumps S12 can be respectively connected to the second pads W12p. In this way, the second pads W12p can be electrically connected to the solder bumps S12, so that the chip package 100 can be electrically connected to a circuit substrate, such as a printed circuit board or an electronic carrier board, through the solder bumps S12.

The seal 130 may include a first molding material 131 and a second molding material 132, wherein the first molding material 131 is connected to the second molding material 132, and the first molding material 131 and the second molding material 132 are connected to each other. The materials may be the same as or different from each other. The first molding material 131 covers the chip 120 and the redistribution layer 110 , wherein the first molding material 131 covers the first surface F11 a and the side surface F11 c of the redistribution layer 110 , but does not cover the second surface F11 b. The second molding material 132 covers the second surface F11b, so the second molding material 132 also covers the traces 129 . The second molding material 132 exposes the second pad W12p so that the solder bump S12 can be connected to the second pad W12p.

In addition, after the chip 120 is mounted on the first surface F11a, a gap G1 may be formed between the chip 120 and the redistribution layer 110, and the first molding material 131 will fill the gap G1. In other words, one of the seals 130 Partially fill the gap G1 between the wafer 120 and the redistribution layer 110, and the sealing member 130 will cover the upper surface, the lower surface and the side surface 121 of the wafer 120, thereby wrapping the entire wafer 120, as shown in FIG. 1A and FIG. 1B .

Since the sealing member 130 covers the chip 120 and the redistribution layer 110, and covers the first surface F11a and the side surface F11c of the redistribution layer 110, the sealing member 130 can strengthen the structure of the chip package 100 and reduce the occurrence of the redistribution layer 110. The fracture probability is improved to improve the reliability of the chip package 100, so that the chip package 100 can have a structure with sufficient strength to pass the thermal cycle test.

2A to 2G are schematic flowcharts of the manufacturing method of the chip package in FIG. 1B . Referring to FIG. 2A , in the manufacturing method of the chip package 100 , first, an initial redistribution layer 110i is formed on the carrier substrate 20 , wherein the initial redistribution layer 110i can be formed by a build-up method or a lamination method. The carrier substrate 20 is used to support the initial redistribution layer 110i, and may be a rigid substrate, such as a ceramic board or a glass board. It should be particularly noted that the second outer wiring layer W12 of the initial redistribution layer 110 i is in direct contact with the carrier substrate 20 .

In the subsequent process, the initial redistribution layer 110 i can be cut into multiple redistribution layers 110 , so the initial redistribution layer 110 i can include multiple redistribution layers 110 . In other words, both the initial redistribution layer 110i and the redistribution layer 110 include the same film layers and components, that is, the first outer insulating layer D11, the second outer insulating layer D12, the inner insulating layer D13, the first outer circuit layer W11, the second outer circuit layer W12, the inner circuit layer W13, and the conductive connection structures P11a and P11b. where the second outer insulating layer D12, the second outer circuit layer W12, and the carrier substrate 20 form a coplanar plane (not shown), and the coplanar plane is located between the second outer layer insulating layer D12 and the carrier substrate 20, and between the second outer layer circuit layer W12 and the carrier substrate 20. between.

Please refer to FIG. 2B , after that, a plurality of chips 120 are mounted on the initial redistribution layer 110i. In this embodiment, these chips 120 may be mounted on the initial redistribution layer 110i by flip-chip. That is to say, the chips 120 can be electrically connected to the first pads W11p through the plurality of solder bumps S11. After these chips 120 are mounted on the initial redistribution layer 110i, a gap G1 may be formed between each chip 120 and the initial redistribution layer 110i. In other embodiments, the chips 120 can also be installed on the initial redistribution layer 110i by wire bonding, so the arrangement between the chips 120 and the initial redistribution layer 110i is not limited to flip chip.

Please refer to FIG. 2C and FIG. 2D , wherein FIG. 2D is a schematic top view of FIG. 2C , and FIG. 2C may be drawn along the line 2C-2C in FIG. 2D . Afterwards, the initial redistribution layer 110i is cut to form a plurality of redistribution layers 110 separated from each other. After the initial redistribution layer 110i is cut, a plurality of trenches T2 are formed between the redistribution layers 110 , wherein the wafers 120 can be arranged in an array, and the trenches T2 can be arranged in a network, as shown in FIG. 2D . In addition, since the first outer insulating layer D11, the second outer insulating layer D12, and the inner insulating layer D13 can be made of photosensitive dielectric (PID) materials, the method of cutting the initial redistribution layer 110i can be lightning. ablation or lithography.

See Figure 2E and Figure 2F, after that, start to form the seal 130. In this embodiment, forming the sealing member 130 includes the following steps. Referring to FIG. 2E , first, a first molding material 131 is formed on the carrier substrate 20, wherein the first molding material 131 fills the trenches T2 and the gaps G1, and covers the wafers 120 and the redistribution layers 110. The first surface F11a and the side surface F11c do not cover the second surface F11b of these redistribution layers 110 .

Referring to FIG. 2F , after the first molding material 131 is formed, the carrier substrate 20 is removed, so that the second surfaces F11b of the redistribution layers 110 can be exposed. Afterwards, a second molding material 132 is formed on the second surfaces F11b of the redistribution layers 110, wherein the second molding material 132 exposes the second pads W12p. So far, the sealing member 130 is formed. In addition, after forming the second molding material 132 , a plurality of solder bumps S12 may be formed on the redistribution layers 110 , wherein each redistribution layer 110 is located between one of the wafers 120 and the plurality of solder bumps S12 .

Referring to FIG. 2F and FIG. 2G , afterward, the sealing member 130 is cut along the trenches T2 to form a plurality of chip packages 100 separated from each other. Since the sealing member 130 has filled these trenches T2 before cutting the sealing member 130, the sealing member 130 in the same chip package 100 can cover the redistribution layer 110 after cutting the sealing member 130 along these trenches T2. The first surface F11a, the side surface F11c and the second surface F11b. In this way, the sealing member 130 of each chip package 100 can cover the chip 120 and the redistribution layer 110 to improve reliability.

3A to 3B are schematic flowcharts of a method for manufacturing a chip package according to another embodiment of the present invention. Please refer to Figure 3A and Figure 3B, this implementation The manufacturing method of the chip package 300 of the example is similar to the manufacturing method of the aforementioned chip package 100 . The following text and drawings mainly disclose the differences between the chip packages 100 and 300 , and the same features of the chip packages 100 and 300 will not be repeated.

Please refer to FIG. 3B first. Compared with the chip package 100 in the foregoing embodiments, the chip package 300 includes a sealing member 330, wherein the sealing member 130 covers the chip 120 and the redistribution layer 110, and covers the chip 120 and the first surface. F11a and the side surface F11c, but not covering the second surface F11b. Therefore, the sealing member 330 does not cover the second pads W12p. In addition, the sealing member 330 may be the first molding material 131 in the foregoing embodiments.

Referring to FIG. 3A, after forming the sealing member 330 (which may be the first molding material 131) on the carrier substrate 20 (please refer to FIG. 2E), the carrier substrate 20 is removed, wherein the sealing member 330 fills up the trenches T2 . Next, a plurality of solder bumps S12 are respectively formed on the second pads W12p. Afterwards, the sealing member 330 is cut along the trenches T2 to form a plurality of chip packages 300 separated from each other. It can be seen that, compared with the manufacturing method of the chip package 100 , the manufacturing method of the chip package 300 substantially omits the step of forming the second molding material 132 .

4A is a schematic cross-sectional view of a chip package according to another embodiment of the present invention. Referring to FIG. 4A , the chip package 400a of this embodiment is similar to the chip package 100 of the previous embodiment. For example, the chip package 400a includes a redistribution layer 410a including an insulating portion 411a, wherein the insulating portion 411a may include a first outer insulating layer D41, a second outer insulating layer D42, and a multi-layer inner insulating layer D13. However, unlike chip packages 100. The first outer insulating layer D41 and the second outer insulating layer D42 are different from the first outer insulating layer D11 and the second outer insulating layer D12.

Specifically, at least one of the first outer insulating layer D41 and the second outer insulating layer D42 includes an insulating material 41m and a plurality of fillers 41p, wherein the fillers 41p are distributed in the insulating material 41m. The insulating material 41m can be a polymer material, such as epoxy resin (Epoxy), polyimide (Polyimide, PI), polybenzoxazole (Polybenzoxazole, PBO), benzocyclobutene (Benzocyclobutene, BCB) or other material, or any combination of these materials and other materials, and these fillers 41p can be a plurality of filler particles, which can be made of silicon dioxide. With these fillers 41p, at least one of the first outer insulating layer D41 and the second outer insulating layer D42 can also strengthen the structure of the chip package 400a, reduce the probability of breakage of the redistribution layer 410a, and improve reliability.

It is worth mentioning that, in the embodiment shown in FIG. 4A , each of the first outer insulating layer D41 and the second outer insulating layer D42 includes an insulating material 41m and the fillers 41p. However, in other embodiments, only one of the first outer insulating layer D41 and the second outer insulating layer D42 may include the insulating material 41m and the fillers 41p. Therefore, in FIG. 4A , the filler 41 p in one of the first outer insulating layer D41 and the second outer insulating layer D42 may be omitted. Alternatively, one of the first outer insulating layer D41 and the second outer insulating layer D42 can be replaced by an insulating layer made of a photosensitive dielectric material, such as the first outer insulating layer D11 or the second outer insulating layer D12 .

4B is a schematic cross-sectional view of a chip package according to another embodiment of the present invention. Referring to FIG. 4B , the chip package 400b includes a redistribution layer 410b including an insulating portion 411b , wherein the insulating portion 411b may include a first outer insulating layer D41 , a second outer insulating layer D42 and a multilayer inner insulating layer D43 . The chip package 400b is similar to the chip package 400a, and the only difference between the chip package 400a and 400b is that in the chip package 400b, the first outer insulating layer D41, the second outer insulating layer D42 are insulated from these inner layers. Layers D43 each comprise insulating material 41m and these fillers 41p. Therefore, the entire insulating portion 411b can also strengthen the structure of the chip package 400b, and can reduce the probability of breakage of the redistribution layer 410b, thereby improving reliability.

It should be noted that, in the embodiment shown in FIG. 4B , each inner insulating layer D43 includes an insulating material 41m and these fillers 41p. However, in other embodiments, at least one of the inner insulating layers D43 includes the insulating material 41m and the fillers 41p. Therefore, in FIG. 4B, the filler 41p in one of the interlayer insulating layers D43 can be omitted. Alternatively, one of the inner insulating layers D43 can be replaced with an insulating layer made of photosensitive dielectric material, that is, the inner insulating layer D13. In addition, only one of the first outer insulating layer D41 and the second outer insulating layer D42 in FIG. 4B may include the insulating material 41m and the fillers 41p.

FIG. 5 is a schematic cross-sectional view of a chip package according to another embodiment of the present invention. Referring to FIG. 5, the chip package 500 of this embodiment includes a redistribution layer 510, which includes an insulating portion 511, wherein the insulating portion 511 may include a first outer insulating layer D51, a second outer insulating layer D52, and a multilayer inner layer. Insulation layer D53. Each of the first outer insulating layer D51 , the second outer insulating layer D52 and the inner insulating layers D53 includes an insulating material 41 m and a plurality of fillers 51 f, wherein the fillers 51 f are distributed on the insulating material 41 m.

The chip package 500 is similar to the chip package 400b, and the only difference between the chip package 500 and 400b is that the fillers 51f can be a plurality of filling fibers, such as glass fibers. With these fillers 51f, the entire insulating portion 511 can also strengthen the structure of the chip package 500, and can reduce the probability of breakage of the redistribution layer 510, thereby improving reliability.

It is worth mentioning that, in the embodiment shown in FIG. 5 , each of the first outer insulating layer D51 , the second outer insulating layer D52 and the inner insulating layers D53 includes the insulating material 41m and the fillers 51f. However, in other embodiments, at least one of the first outer insulating layer D51 , the second outer insulating layer D52 and the inner insulating layers D53 may include the insulating material 41m and the fillers 51f.

In other words, in FIG. 5 , the filler 51 f in at least one of the first outer insulating layer D51 , the second outer insulating layer D52 and the inner insulating layers D53 can be omitted. Alternatively, at least one of the first outer insulating layer D51, the second outer insulating layer D52, and the inner insulating layers D53 can be replaced with an insulating layer made of a photosensitive dielectric material, that is, the first outer insulating layer D11, the second outer insulating layer Two outer insulating layers D12 or inner insulating layers D13.

In addition, part of the filler 51f shown in FIG. 5 can be replaced with a filler 41p, so that the insulating part 511 can include two kinds of fillers 41p and 51f, wherein the first outer insulating layer D51, the second outer insulating layer D52 and these inner insulating layers The filler 51f in at least one layer of the insulating layer D53 may be replaced with the filler 41p. In addition, in the chip packages 400 a , 400 b and 500 shown in FIGS. 4A , 4B and 5 , the sealing member 130 can be replaced with the sealing member 330 shown in FIG. 3B . In other words, the chip package 300 of FIG. 3B may also include at least one of the fillers 41p and 51f.

In summary, since the seals disclosed in the above embodiments all cover the chip and the redistribution layer, and cover the first surface and the side surface of the redistribution layer, the seal can strengthen the structure of the chip package to lift the chip. The reliability of the package, so that the chip package can have a structure with sufficient strength to pass the thermal cycle test.

Although the present invention has been disclosed above with the embodiments, it is not intended to limit the present invention. Those with ordinary knowledge in the technical field of the present invention can make some changes and modifications without departing from the spirit and scope of the present invention. Therefore, this The protection scope of the invention shall be defined by the scope of the appended patent application.

100: chip package

110:Rewiring layer

111: insulation part

120: chip

121: side

129: Alignment

130: seal

131: The first molding material

132: Second molding material

D11: The first outer insulating layer

D12: Second outer insulating layer

D13: Inner insulating layer

F11a: first surface

F11b: second surface

F11c: side surface

G1: Gap

P11a, P11b: conductive connection structure

S11, S12: Solder bumps

W11: The first outer circuit layer

W11p: First pad

W12: The second outer circuit layer

W12p: Second pad

W12s: External surface

W13: inner circuit layer

Claims (17)

A chip package, comprising: a rewiring layer, comprising: an insulating portion having a first surface, a second surface opposite to the first surface, and a side surface located between the first surface and the second surface ; an outer circuit layer, located on the insulating layer, and the outer surface of the outer circuit layer is coplanar with the second surface; a plurality of first pads, located on the first surface; a plurality of second pads, located in The second surface; a chip configured on the first surface and electrically connected to the first pads; and a sealing member covering the chip and the rewiring layer, and covering the first surface and the first pad The side surface, wherein the seal exposes the second pads, and the seal is not flush with the first surface and the side surface. The chip package as claimed in claim 1, wherein the redistribution layer comprises: a first outer insulating layer having the first surface; and a second outer insulating layer having the second surface, wherein the first outer layer The insulating layer is located between the wafer and the second outer insulating layer. The chip package as claimed in item 2, wherein the first outer insulating layer comprises: an insulating material; and a plurality of fillers distributed in the insulating material. The chip package as claimed in claim 2, wherein the second outer insulating layer comprises: an insulating material; and a plurality of fillers distributed in the insulating material. The chip package according to claim 1, wherein the redistribution layer comprises: a first outer insulating layer having the first surface; a second outer insulating layer having the second surface, wherein the first outer insulating layer located between the wafer and the second outer insulating layer; and at least one inner insulating layer located between the first outer insulating layer and the second outer insulating layer, wherein the first outer insulating layer, the second outer insulating layer Each of the two outer insulating layers and the at least one inner insulating layer includes: an insulating material; and a plurality of fillers distributed in the insulating material. The chip package as claimed in claim 3, 4 or 5, wherein the fillers are a plurality of filler particles or a plurality of filler fibers. The chip package as claimed in claim 1, wherein the sealing member does not cover the second surface. The chip package as claimed in claim 1, wherein the sealing member further covers the second surface. The chip package as claimed in claim 1, wherein a part of the sealing member fills up a gap between the chip and the redistribution layer. The chip package as claimed in claim 1 further comprises a plurality of solder bumps, wherein the solder bumps are respectively connected to the second pads. The chip package as claimed in claim 1, wherein the second surface is aligned with an outer surface of each of the second pads. The chip package as claimed in claim 1, wherein a length and a width of the sealing member are respectively greater than a length and a width of the redistribution layer. A method for manufacturing a chip package, comprising: forming an initial redistribution layer on a carrier substrate, wherein the initial redistribution layer has an outer circuit layer, and the outer circuit layer is in direct contact with the carrier substrate; installed on the initial redistribution layer; cutting the initial redistribution layer to form a plurality of redistribution layers separated from each other, wherein a plurality of grooves are formed between the redistribution layers; forming a sealing member, wherein the sealing parts encapsulating the die and the rewiring layer, and fill the grooves; remove the carrier substrate; and cut the sealing member along the grooves. The method for manufacturing a chip package according to claim 13, wherein forming the initial redistribution layer further includes forming an outer insulating layer, wherein the outer insulating layer, the outer wiring layer, and the carrier substrate form a common plane, and the common The plane is located between the outer insulating layer and the carrier substrate, and between the outer circuit layer and the carrier substrate. The method for manufacturing a chip package as claimed in claim 13, wherein each of the redistribution layers has a first surface, a second surface opposite to the first surface, and a layer between the first surface and the second surface. The side surface of the sealing member, and the step of forming the sealing member includes: forming a first molding material on the carrier substrate, wherein the first molding material covers the chips, the first surfaces and the side surfaces, but The second surfaces are not covered, and the first molding material fills the grooves, wherein the carrier substrate is removed after forming the first molding material. The method for manufacturing a chip package as claimed in claim 15, wherein the step of forming the sealing member further includes: after removing the carrier substrate, forming a second molding material on the second surfaces, wherein the second The molding material is connected to the first molding material. The method for manufacturing a chip package according to claim 13, further comprising: after removing the carrier substrate and before cutting the sealing member, forming a plurality of solder bumps on the rewiring layers, wherein each rewiring layer Located between one of the chips and a plurality of the solder bumps.

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