TWI779627B - Semiconductor structure and method of fabricating the same - Google Patents

Abstract

A semiconductor structure includes a substrate with an isolation area and an active area, and a word-line structure. The word-line structure includes a first section formed in and surrounded by the isolation area of the substrate, and a second section formed in the active area of the substrate. A width of the second section is larger than a width of the first section.

Description

Semiconductor structures and methods of forming them

This disclosure relates to semiconductor structures and methods of forming them, especially word line structures for DRAMs.

With the advancement of technology, dynamic random access memory (DRAM) has become more highly integrated, and the performance of DRAM has been improved by shortening the pitch between semiconductor structures in DRAM. Due to the shrinking of the size, in addition to increasing the difficulty of the manufacturing process, the components in the semiconductor structure are also prone to leakage due to too close distances.

Therefore, how to reduce the leakage phenomenon to improve the process yield of the semiconductor structure has become an important issue.

According to some embodiments of the present disclosure, a semiconductor structure includes a substrate having isolation regions and active regions, and a word line structure. The word line structure includes a first part and a second part. The first portion is formed in the isolation area of the substrate, wherein the isolation area surrounds the first portion. The second portion is formed in the active area of the substrate, wherein the width of the second portion is greater than that of the first portion.

In some embodiments, the width of the second portion of the semiconductor structure is about 1 nm to about 3 nm wider than the width of the first portion.

According to some embodiments of the present disclosure, a semiconductor structure includes a substrate having an isolation region and an active region, and a plurality of wordline structures, wherein each wordline structure extends through the isolation region and the active region. The lateral distance between adjacent word line structures located in the isolation area is a first length, and the lateral distance between adjacent word line structures located in the active area is a second length, wherein the first length is greater than the first length Two lengths.

In some embodiments, the first length of the semiconductor structure is greater than the second length by about 1 nm to about 3 nm.

According to some embodiments of the present disclosure, a method of forming a semiconductor structure includes receiving a substrate, forming isolation regions and active regions in the substrate, forming trenches in the substrate, wherein the trenches are linear in shape and extend through the substrate the isolation region and the active region of the substrate. The trench includes a first partial trench located in the isolation area and a second partial trench located in the active area. The method of forming the semiconductor structure also includes increasing the width of the second portion of the trench after forming the trench. The method of forming a semiconductor structure also includes forming a dielectric layer on the inner surface of the trench, forming a conductive layer in the trench and the dielectric layer covers the conductive layer, and forming a capping layer in the trench and stacked on the conductive layer superior.

In some embodiments, the method of forming the semiconductor structure increases the width of the second portion of the trench by about 1 nm to about 3 nm.

The present disclosure relates to semiconductor structures and methods of forming them. Various parts in each word line structure have different widths according to their positions. Part of the word line structure located in the isolation region has a smaller width, so as to increase the distance between the word line structure and adjacent elements, so that the isolation region can provide better electrical isolation and reduce leakage of the semiconductor structure. At the same time, part of the word line structure located in the active region has a larger width to provide sufficient channel area and maintain the performance of the semiconductor structure.

When an element is referred to as being "on", it can generally mean that the element is directly on other elements, or there may be other elements present in between. Conversely, when an element is said to be "directly on" another element, it cannot have other elements in between. As used herein, the word "and/or" includes any combination of one or more of the associated listed items.

In the present disclosure, terms such as first, second and third are used to describe various elements, components, regions, layers and/or blocks to be understood. But these elements, components, regions, layers and/or blocks should not be limited by these terms. These terms are limited to identifying a single element, component, region, layer and/or block. Therefore, a first element, component, region, layer and/or block hereinafter may also be referred to as a second element, component, region, layer and/or block without departing from the original meaning of the present disclosure.

As used in this disclosure, "about" generally means within about 20 percent, preferably within about 10 percent, and more preferably about 5 percent, of the error or range of the value of the index within. If there is no explicit statement in the text, the values mentioned are regarded as approximate values, that is, the error or range indicated by "approximately".

Please refer to FIG. 1 , which illustrates a configuration diagram of a semiconductor structure 100 according to some embodiments of the present disclosure. The semiconductor structure 100 may include a plurality of word line structures 110 extending along the first direction D1, and adjacent word line structures 110 are arranged at equal distances and separated from each other along the second direction D2. A plurality of bit line structures 120 extend along the second direction D2 and are arranged on the word line structures 110 to intersect with the word line structures 110 . Likewise, adjacent bit line structures 120 are equidistant apart along the first direction D1 and parallel to each other.

The semiconductor structure 100 includes an active area 130 and an isolation area 140 , wherein the active area 130 has a short axis and a long axis. In some embodiments, the long axis of the active region 130 extends along a third direction D3, wherein the third direction forms an angle θ with the second direction D2. The area outside the active area 130 is the isolation area 140 .

The bit line structure 120 can be connected to the active area 130 through a direct contact 150 . Each active area 130 is electrically connected to a direct contact 150 . In addition, a plurality of contacts 160 are formed at both ends of the long axis of the active region 130 and between two adjacent word line structures 110 . In some embodiments, the contacts 160 are spaced apart from each other along the first direction D1. The contact 160 can electrically connect the lower electrode of the storage node/capacitor (not shown) to the corresponding active region 130 . In the embodiment shown in FIG. 1 , a single active region 130 can electrically connect two contacts 160 .

According to some embodiments of the present disclosure, each word line structure 110 of the semiconductor structure 100 has a linear shape extending along the first direction D1 and passes through the isolation region 140 and the active region 130 . Therefore, each word line structure 110 may include two parts, the first part 110A is the word line structure 110 formed in the isolation region 140 , and the second part 110B is the word line structure 110 formed in the active region 130 . In the embodiment shown in FIG. 1, the first part 110A and the second part 110B in each word line structure 110 can have different widths respectively, and the width depends on where each part in the word line structure 110 is located. area.

In detail, the word line structure 110 formed in the isolation region 140 (ie, the first portion 110A of the word line structure 110 ) has a first width W1, and the word line structure 110 formed in the active region 130 (ie, The second portion 110B) of the word line structure 110 has a second width W2, wherein the first width W1 is different from the second width W2. In some embodiments, the second width W2 is greater than the first width W1, and the second width W2 is wider than the first width W1 by about 1.0 nm to about 3.0 nm, such as 1.0, 1.5, 2.0, 2.5 or 3.0 nm. In some embodiments, the second width W2 may be wider than the first width W1 by about 2.0 nm.

From another point of view, when the various parts in each word line structure 110 have different widths, the length of each part in the word line structure 110 from the adjacent element (for example, another word line structure 110) There are also differences. As shown in FIG. 1, the lateral distance (eg, the distance along the second direction D2) between adjacent first portions 110A (ie, two adjacent word line structures 110 located in the isolation region 140) is The first length L1, the lateral distance between adjacent second portions 110B in the same active region 130 (ie, two adjacent word line structures 110 in the same active region 130 ) is the second length L2. The first length L1 is different from the second length L2 due to the different widths of parts in each word line structure 110 . In some embodiments, the first length L1 is greater than the second length L2, and the first length L1 is greater than the second length L2 by about 1.0 nm to about 3.0 nm, such as 1.0, 1.5, 2.0, 2.5 or 3.0 nm. In some embodiments, the first length L1 may be greater than the second length L2 by about 2.0 nm.

Likewise, as shown in FIG. 1 , between the first part 110A (that is, the word line structure 110 located in the isolation region 140 ) and the second part 110B (that is, the word line structure 110 located in the active region 130 ) The lateral distance (for example, the distance along the second direction D2) is the third length L3, and the adjacent second parts 110B in different active regions 130 (that is, two adjacent characters located in different active regions 130 The lateral distance between the wire structures 110) is a fourth length L4, wherein the fourth length L4 is substantially equal to the second length L2. The third length L3 is greater than the fourth length L4 due to the different widths of the portions in each word line structure 110 , and the third length L3 is greater than the fourth length L4 by about 0.5 nm to about 1.5 nm. In some embodiments, the third length L3 may be wider than the fourth length L4 by about 1.0 nm. In summary, in the embodiment shown in the first figure, the first length L1>the third length L3>the second length L2=the fourth length L4.

The first portion 110A and the second portion 110B of the word line structure 110 may have different widths respectively, so that the lengths of the first portion 110A and the second portion 110B in the word line structure 110 from the surrounding elements are also different, which may further affect The electrical isolation effect between the word line structure 110 and surrounding components. This is because when the isolation region 140 includes a dielectric material, the distance between the word line structure 110 and the surrounding elements can be positively correlated with the thickness of the isolation region 140 between the word line structure 110 and the surrounding elements, thereby affecting the character The electrical barrier effect between the wire structure 110 and surrounding elements. Therefore, for the first part 110A (that is, the word line structure 110 located in the isolation region 140), the first part 110A with a smaller width produces a larger separation length with the surrounding elements, and improves the distance between the first part 110A and the surrounding elements. 110A and the thickness of the isolation region 140 of the surrounding components, thereby improving the electrical isolation of the isolation region.

Please refer to FIG. 2 . FIG. 2 shows a cross-sectional view of the semiconductor structure 100 along line A-A in FIG. 1 according to some embodiments of the present disclosure. In detail, the section line A-A is parallel to the third direction D3. The semiconductor structure 100 includes a substrate 200 , wherein the substrate 200 has an active region 130 and a plurality of isolation regions 140 separating the active region 130 . The substrate 200 can be further subjected to an ion implantation process to dope N-type or P-type dopants into the substrate 200 . In some embodiments, the source/drain regions 132 can be formed by doping N-type or P-type dopants into the active region 130 of the substrate 200 .

As shown in FIG. 2 , several word line structures 110 of the semiconductor structure 100 are formed in the substrate 200 , wherein the word line structures 110 have a dielectric layer 112 , a conductive layer 114 and a capping layer 116 .

In the cross-sectional view shown in FIG. 2, three word line structures 110 are shown, one word line structure 110 is in the first part 110A of the isolation region 140, and the other two word line structures 110 are in the active The second portion 110B of the region 130 . As shown in FIG. 2, the first portion 110A has a third width W3, and the second portion 110B has a fourth width W4, wherein the third width W3 is substantially similar to the first width W1 and the fourth width W4 is substantially similar to the second width W4. Width W2. To further illustrate, the first width W1/second width W2 (along the second direction D2) is the third width W3/fourth width W4 (along the third direction D3) multiplied by cosθ. Therefore, the original relationship between the first width W1 and the second width W2 can be applied to the third width W3 and the fourth width W4. For example, in the embodiment where the second width W2 is greater than the first width W1, the third width W3 can maintain a relationship greater than the fourth width W4, and the width increase can be converted by the aforementioned cosθ.

It should be understood that the number (three) of the word line structures 110 shown in FIG. 2 is only an example and not a limitation. Actually, the number of word line structures 110 can be adjusted based on product design and process conditions.

Continuing to refer to FIG. 2 , a first interlayer dielectric layer 220 and a second interlayer dielectric layer 240 may be sequentially disposed on the substrate 200 . In some embodiments, the bit line structure 120 is disposed in the second interlayer dielectric layer 240, and the direct contact 150 is disposed in the first interlayer dielectric layer 220, and the bit line structure 120 is electrically connected to the direct contact. 150. Therefore, the bit line structure 120 can be electrically connected to the active region 130 of the substrate 200 through the direct contact 150 .

The contact 160 of the semiconductor structure 100 may include a first contact plug 162 and a second contact plug 164 , wherein the second contact plug 164 is located above the first contact plug 162 and electrically connected to each other. The second contact plug 164 can electrically connect the lower electrode of the storage node/capacitor (not shown) to the corresponding active region 130 through the first contact plug 162 . In some embodiments, the first contact plug 162 is a buried contact. In some embodiments, the second contact plug 164 is a landing pad.

In FIG. 2 , the distance S is between the first portion 110A and the first contact plug 162 . Since the first portion 110A has a smaller third width W3, the thickness of the material of the isolation region 140 between the first portion 110A and the first contact plug 162 (substantially equal to the distance S) can provide sufficient electrical barrier , so as to avoid electric leakage between the first portion 110A and the first contact plug 162 . In addition, the first portion 110A with the smaller third width W3 can also provide more room for error tolerance in subsequent processes, such as the alignment error of forming the first contact plug 162 . In some embodiments, the distance S between the first portion 110A and the first contact plug 162 is at least greater than about 2 nm.

Figures 1 and 2 are for illustrative purposes only, and the structures, shapes, or configurations presented in the figures should not limit the present disclosure.

3, 4B, 5, 6B, 7B, and 8-10 illustrate cross-sectional views of various process stages of forming a semiconductor structure 100 according to some embodiments of the present disclosure, And Figures 4A, 6A, and 7A depict configurations of various process stages for forming semiconductor structure 100 according to some embodiments of the present disclosure.

It should be noted that when Fig. 3, Fig. 4A, Fig. 4B, Fig. 5, Fig. 6A, Fig. 6B, Fig. 7A, Fig. 7B, and Fig. 8 to Fig. 10 depict or describe When forming a sequence of operations or events, the order in which these operations or events are described should not be restricted. For example, some operations or events may be undertaken in a different order than in the present disclosure, some operations or events may occur concurrently, some operations or events may not be required, and/or some operations or events may be repeated. Moreover, the actual process may require additional steps before, during, or after forming the semiconductor structure 100 to completely form the semiconductor structure 100 . Therefore, this disclosure may briefly illustrate some of these additional operational steps. Furthermore, unless otherwise stated, Figures 3, 4A, 4B, 5, 6A, 6B, 7A, 7B, and 8-10 refer to The same instructions for , can be directly applied to other pictures.

Please refer to FIG. 3 , which illustrates a cross-sectional view of one of the process stages of forming the semiconductor structure 100 according to some embodiments of the present disclosure. First, a substrate 200 is received. The substrate 200 is a semiconductor material, which may include silicon, such as crystalline silicon, polycrystalline silicon, or amorphous silicon. Substrate 200 may include an elemental semiconductor, such as germanium (Ge). The substrate 200 may include alloy semiconductors such as silicon germanium (SiGe), silicon carbide phosphide (SiPC), gallium arsenide phosphide (GaAsP), aluminum indium arsenide (AlInAs), aluminum gallium arsenide (AlGaAs), gallium arsenide Indium gallium (GaInAs), gallium indium phosphide (GaInP), gallium indium phosphide (GaInAsP), or other suitable materials. The substrate 200 may include compound semiconductors such as silicon carbide (SiC), silicon phosphide (SiP), gallium arsenide (GaAs), gallium phosphide (GaP), indium phosphide (InP), indium arsenide (InAs), Indium antimonide (InSb), zinc oxide (ZnO), zinc selenide (ZnSe), zinc sulfide (ZnS), zinc telluride (ZnTe), cadmium selenide (CdSe), cadmium sulfide (CdS), cadmium telluride ( CdTe), or other suitable materials.

In addition, the substrate 200 may be a semiconductor-on-insulator (semiconductor-on-insulator) substrate, such as a silicon-on-insulator (SOI) substrate or germanium-on-insulator (germanium-on-insulator, GeOI) substrate. The semiconductor-on-insulator substrate can be made by separation by implantation of oxygen technology, wafer bonding technology, other suitable technologies, or a combination of the above.

Please refer to FIG. 4A and FIG. 4B. FIG. 4A shows a configuration diagram of one of the process stages of forming semiconductor structure 100 according to some embodiments of the present disclosure, and FIG. A cross-sectional view of the semiconductor structure 100 along line A-A in FIG. 4A at one of the process stages. As shown in FIGS. 4A and 4B , an isolation region 140 is formed within the substrate 200 . The material of the isolation region 140 may include at least one of silicon oxide, silicon nitride, and silicon oxynitride. The isolation region 140 may be a single-layer or multi-layer structure. For example, the isolation region 140 may include silicon oxide and silicon nitride. In some embodiments, the isolation region 140 may be formed by a shallow trench isolation (STI) process. After the isolation region 140 is formed, the semiconductor material located around the isolation region 140 and extending from the substrate 200 can serve as the active region 130 , wherein the isolation region 140 separates the active region 130 .

Please refer to FIG. 5 , which illustrates a cross-sectional view of one of the process stages of forming the semiconductor structure 100 according to some embodiments of the present disclosure. An ion implantation process may be further performed on the substrate 200 to dope N-type or P-type dopants into the substrate 200 . In some embodiments, source/drain regions 132 can be formed in the active region 130 by doping N-type or P-type dopants into the substrate 200 . N-type dopants may include phosphorus or arsenic. The P-type dopant may include boron or boron fluoride.

Please refer to FIG. 6A and FIG. 6B. FIG. 6A shows a configuration diagram of one of the process stages of forming semiconductor structure 100 according to some embodiments of the present disclosure, and FIG. A cross-sectional view of the line A-A in FIG. 6A of one of the process stages of the semiconductor structure 100 . As shown in FIGS. 6A and 6B , trenches 600 are formed in the substrate 200 . The trench 600 has a linear shape and extends through the isolation region 140 and the active region 130 . Therefore, each trench 600 may include a first partial trench 600A and a second partial trench 600B: the first partial trench 600A is the trench 600 located in the isolation region 140, and the second partial trench 600B is located in the active region 130 grooves 600 .

In some embodiments, the first part of the trench 600A and the second part of the trench 600B are substantially the same, and the only difference lies in the regions where they are located (the isolation region 140 and the active region 130 ). Therefore, the first partial trench 600A and the second partial trench 600B may have the same width, eg, the first width W1. In other words, the trench 600 shown in FIG. 6A and FIG. 6B may have a uniform first width W1.

In the embodiment shown in FIG. 6B, the formation of the trench 600 includes forming a patterned mask 620 (not shown in FIG. 6A) on the substrate 200, followed by an appropriate etching process, such as a dry etching process or The wet etching process is used to etch the substrate 200 to form the trench 600, wherein the formed trench 600 has a first width W1. In some embodiments, the patterned mask 620 may include silicon oxide, silicon nitride, silicon oxynitride, other suitable materials, or combinations thereof.

The trench 600 with the first width W1 can define the width of the word line structure 110 (ie, the first portion 110A) located in the isolation region 140 in subsequent processes. As mentioned above, when the first portion 110A has a smaller width, the distance between the word line structure 110 and adjacent devices can be increased, so that the isolation region 140 can provide better electrical isolation. Therefore, the first width W1 can be determined according to product design and process conditions.

FIG. 6B and the following FIG. 7B and FIG. 8 to FIG. 10 depict three trenches 600, wherein one trench 600 is the first part trench 600A in the isolation region 140, and the other two trenches 600 are In the second portion of the trench 600B of the active region 130 . Because the cross-sectional view is a single cut plane, when reading the cross-sectional views of Figures 6B, 7B, and 8 to 10, it should be noted that in fact, each groove 600 can have the first part of the groove 600A and the second part at the same time. The groove 600B is shown in FIG. 6A and FIG. 7A.

Please refer to FIG. 7A and FIG. 7B. FIG. 7A shows a configuration diagram of one of the process stages of forming semiconductor structure 100 according to some embodiments of the present disclosure, and FIG. A cross-sectional view of the semiconductor structure 100 along the line A-A in FIG. 7A at one of the process stages. As shown in FIGS. 7A and 7B , after forming the trench 600 , the width of the second portion of the trench 600B (ie, the trench 600 located in the active region 130 ) is increased. In some embodiments, the first part of the trench 600A can maintain the first width W1, and the second part of the trench 600B can have the second width W2.

In some embodiments, the second partial trench 600B increases from the first width W1 to the second width W2, wherein the second width W2 is wider than the first width W1 by about 1.0 nm to about 3.0 nm, such as 1.0, 1.5, 2.0, 2.5 or 3.0 nm. In other words, the increase of the width of the second portion of the trench 600B is about 1.0 nm to about 3.0 nm, such as 1.0, 1.5, 2.0, 2.5 or 3.0 nm. In some embodiments, the increase in width of the second portion of the trench 600B is about 2.0 nm.

By selectively increasing the width of the second portion of the trench 600B, the word line structure 110 located in the active region 130 can have a larger width. The second part of the trench 600B having the second width W2 can define the word line structure 110 in the active region 130 (ie, the second part 110B) in subsequent processes without affecting the word line structure in the isolation region 140 110 (ie, the first portion 110A) has a first width W1. Accordingly, the semiconductor structure 100 can still provide sufficient channel area to maintain the performance of the semiconductor structure 100 .

Increasing the width of the second portion of the trench 600B includes using an etching process. In an embodiment using an etching process, the etching process may remove material from the active region 130 at a rate greater than that from the isolation region 140 by performing selective etching. In some embodiments, during the selective etching process, the etching selectivity ratio of the material of the active region 130 to the material of the isolation region 140 is at least greater than about 5. In one embodiment, the etching process is isotropic etching.

When the material of the active region 130 includes silicon and the material of the isolation region 140 includes silicon oxide, the etching process may use gases, wherein the gases may include nitrogen-containing gases, fluorine-containing gases, other suitable gases, and combinations thereof. The nitrogen-containing gas may include ammonia or nitrogen trifluoride, but the disclosure is not limited thereto. The fluorine-containing gas may include hydrogen fluoride or nitrogen trifluoride, but the disclosure is not limited thereto.

The etching process can be combined with the use of plasma. By adjusting the operating parameters of the plasma, the plasma interacts with the gas used in the etching process to generate an etchant in a radical state. In some embodiments, the plasma generates hydrogen radicals as an etchant. In some embodiments, the plasma generates fluorine radicals as an etchant. Next, the plasma is separated from the etchant in a free radical state. In some embodiments, a charged grating (not shown) may be used to block the movement of charged ions from the plasma and allow uncharged particles (eg, etchant in a free radical state) to pass through the charged grating. For example, a charged grating can prevent the passage of charged ions (eg, positively charged ions or negatively charged ions) by repelling or attracting charged ions. Any etchant that can separate the plasmonic and radical states of a device is suitable for use in the present disclosure.

Next, the etchant in the free radical state can diffuse into the second partial trench 600B and react with the material of the active region 130 . Using the etchant in the free radical state, the etching selectivity of the material of the active region 130 to the material of the isolation region 140 during the etching process can be improved, so as to reduce the loss of the material of the isolation region 140 during the etching process. In some embodiments, the thickness loss of the material of the isolation region 140 during the etching process is less than about 0.2 nm. In addition, the etching process using the etchant in the free radical state is isotropic etching.

In some embodiments, after the width of the second partial trench 600B is increased, a portion 700 of the patterned mask 620 may overhang the opening of the second partial trench 600B, as shown in FIG. 7B . The length 700L of the portion 700 of the patterned mask 620 overhanging the opening of the second partial trench 600B may depend on an increase in the width of the second partial trench 600B. In some embodiments, length 700L may range between about 0.5 nanometers and about 1.5 nanometers. In some embodiments, length 700L may be about 1.0 nanometers. In other embodiments, the patterned mask 620 may be removed from the substrate 200 before the width of the second portion of the trench 600B is increased.

Please refer to FIG. 8 , which illustrates a cross-sectional view of one of the process stages of forming the semiconductor structure 100 of FIG. 2 according to some embodiments of the present disclosure. As shown in FIG. 8 , a dielectric layer 112 is formed on the inner surface 600S of the trench 600 (including the first partial trench 600A and the second partial trench 600B). In some embodiments, the dielectric layer 112 may conformally cover the inner surface 600S of the trench 600 . The dielectric layer 112 is formed of any suitable dielectric material, and the dielectric material may include silicon oxide, silicon nitride, silicon oxynitride, high dielectric constant materials (eg, hafnium oxide (HfO ₂ ), zirconium oxide (ZrO ₂ ) , or at least one of tantalum pentoxide (Ta ₂ O ₅ )). The dielectric layer 112 can be a single layer or a multi-layer structure. For example, the dielectric layer 112 having a double-layer structure may include silicon oxide and silicon nitride, but the disclosure is not limited thereto. The method of forming the dielectric layer 112 on the inner surface 600S of the trench 600 may include using CVD process, ALD process, oxygen plasma oxidation (oxygen plasma oxidation) process, thermal oxidation (thermal oxidation) process, other suitable techniques, or combination of the above.

Please refer to FIG. 9, which illustrates a cross-sectional view of one of the process stages of forming the semiconductor structure 100 according to some embodiments of the present disclosure. As shown in FIG. 9 , a conductive layer 114 is formed in the trench 600 , wherein the dielectric layer 112 covers the conductive layer 114 . The location of the conductive layer 114 at least partially overlaps with the source/drain region 132 . In other words, the source/drain regions 132 are disposed on opposite sides of the conductive layer 114 . The conductive layer 114 may be semiconductor, metal, metal nitride, metal silicide, other suitable conductive materials, or a combination thereof. For example, the conductive layer 114 may include doped polysilicon, titanium (Ti), tungsten (W), tantalum (Ta), titanium nitride (TiN), tungsten nitride (WN), tantalum nitride (TaN), Titanium silicon nitride (TiSiN), tantalum silicon nitride (TaSiN), tungsten silicon nitride (WSiN), other suitable conductive materials, or combinations thereof.

Please refer to FIG. 10 , which illustrates a cross-sectional view of one of the process stages of forming a semiconductor structure 100 according to some embodiments of the present disclosure. As shown in FIG. 10 , a capping layer 116 is formed within the trench 600 and stacked on the conductive layer 114 . The material of the capping layer 116 may include silicon oxide, silicon nitride, silicon oxynitride. In some embodiments, the material of the capping layer 116 includes silicon nitride.

After FIG. 10 , the word line structure 110 of the semiconductor structure 100 is completed. The word line structure 110 includes a first portion 110A located in the isolation region 140 and a second portion 110B located in the active region 130 . The semiconductor structure 100 shown in FIG. 2 can then be formed by performing conventional manufacturing techniques.

The present disclosure relates to semiconductor structures and methods of forming them. Each part of each word line structure has different widths according to its location, and the different widths of each part of the word line structure can provide different functions, thereby improving the process yield of the semiconductor structure. Part of the word line structure in the isolation region has a smaller width, thereby increasing the distance between the word line structure and adjacent devices, so that the isolation region can provide better electrical isolation and reduce the possibility of leakage in the semiconductor structure. At the same time, part of the word line structure located in the active area maintains a larger width, thereby providing sufficient channel area and maintaining the performance of the semiconductor structure.

The features of several embodiments of the present disclosure are briefly described above, so that those skilled in the art can understand the present disclosure more easily. Those skilled in the art should understand that this specification can be easily used as a basis for other structural or process changes or designs to achieve the same purpose and/or obtain the same advantages as the embodiments of the present disclosure. Anyone with ordinary knowledge in the technical field can also understand that the structure equivalent to the above does not depart from the spirit and protection scope of the disclosure, and can be modified, substituted and Revise.

100: Semiconductor Structures 110: Character line structure 110A: Part I 110B: Part Two 112: dielectric layer 114: conductive layer 116: Overlay 120: bit line structure 130: active area 132: source/drain region 140: Isolation area 150: direct contact 160: contact piece 162: first contact plug 164: second contact plug 200: Substrate 220: the first interlayer dielectric layer 240: the second interlayer dielectric layer 600: Groove 600A: first part groove 600B: Second part groove 600S: inner surface 620: Patterned mask 700: part 700L: Length A-A: line D1: the first direction D2: Second direction D3: Third direction L1: first length L2: second length L3: third length L4: fourth length W1: first width W2: second width W3: third width W4: fourth width S: Distance θ: angle

The following embodiments are read together with the accompanying drawings to clearly understand the viewpoints of the present disclosure. It should be noted that, in accordance with the standard practice in the industry, various features are not drawn to scale. In fact, the dimensions of the various features may be arbitrarily expanded or reduced for clarity of discussion. FIG. 1 illustrates a configuration diagram of a semiconductor structure according to some embodiments of the present disclosure. FIG. 2 shows a cross-sectional view of a semiconductor structure along line A-A of FIG. 1, according to some embodiments of the present disclosure. FIG. 3 illustrates a cross-sectional view of one of the process stages of forming a semiconductor structure according to some embodiments of the present disclosure. FIG. 4A illustrates a configuration diagram of one of the process stages of forming a semiconductor structure according to some embodiments of the present disclosure. 4B illustrates a cross-sectional view along line A-A of FIG. 4A during one of the process stages of forming a semiconductor structure, according to some embodiments of the present disclosure. FIG. 5 illustrates a cross-sectional view of one of the process stages of forming a semiconductor structure according to some embodiments of the present disclosure. FIG. 6A illustrates a configuration diagram of one of the process stages of forming a semiconductor structure according to some embodiments of the present disclosure. FIG. 6B illustrates a cross-sectional view along line A-A of FIG. 6A during one of the process stages of forming a semiconductor structure, according to some embodiments of the present disclosure. FIG. 7A illustrates a configuration diagram of one of the process stages of forming a semiconductor structure according to some embodiments of the present disclosure. 7B illustrates a cross-sectional view along line A-A of FIG. 7A during one of the process stages of forming a semiconductor structure, according to some embodiments of the present disclosure. FIG. 8 illustrates a cross-sectional view of one of the process stages of forming a semiconductor structure according to some embodiments of the present disclosure. FIG. 9 illustrates a cross-sectional view of one of the process stages of forming a semiconductor structure according to some embodiments of the present disclosure. FIG. 10 illustrates a cross-sectional view of one of the process stages of forming a semiconductor structure according to some embodiments of the present disclosure.

Domestic deposit information (please note in order of depositor, date, and number) none Overseas storage information (please note in order of storage country, institution, date, and number) none

100: Semiconductor Structures

110: Character line structure

110A: Part I

110B: Part Two

120: bit line structure

130: active area

150: direct contact

160: contact piece

A-A: line

D1: the first direction

D2: Second direction

D3: Third direction

L1: first length

L2: second length

L3: third length

L4: fourth length

W1: first width

W2: second width

θ: angle

Claims (6)

A method of forming a semiconductor structure, comprising: receiving a substrate; forming an isolation region and an active region in the substrate; forming a trench in the substrate, the trench being linear in shape and extending through the substrate The isolation region and the active region of the substrate, the trench includes a first part of the trench and a second part of the trench, wherein the first part of the trench is located in the isolation region and the second part of the trench is located in the active region; after forming the trench, increasing the width of the second portion of the trench by a dry etching process, wherein the dry etching process includes using a gas and a plasma, the gas and the plasma interact to generate a free radical The etchant in the state, and the plasma is separated from the etchant in the free radical state so that the etchant in the free radical state diffuses into the trench; a dielectric layer is formed on the inner surface of the trench; a A conductive layer is in the trench, wherein the dielectric layer covers the conductive layer; and a covering layer is formed in the trench and stacked on the conductive layer. The method for forming a semiconductor structure as claimed in claim 1, wherein increasing the width of the second part of the trench is 1 nm to 3 nm. The method for forming a semiconductor structure as claimed in claim 1, wherein the etchant in the free radical state etches the material of the active region more than etching The etching selectivity ratio of the material of the isolation region is at least greater than 5. The method of forming a semiconductor structure as claimed in claim 1, wherein the gas comprises ammonia. The method of forming a semiconductor structure as claimed in claim 1, wherein the gas comprises nitrogen trifluoride. The method of forming a semiconductor structure as claimed in claim 1, wherein the etchant in a free radical state includes hydrogen free radicals or fluorine free radicals.

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