TWI774346B - Integrated circuit structure and method of forming the same - Google Patents

Abstract

An integrated circuit (IC) structure includes a gate structure, a source epitaxial structure, a drain epitaxial structure, a front-side interconnection structure, a backside dielectric layer, an epitaxial regrowth layer, and a backside via. The source epitaxial structure and the drain epitaxial structure are respectively cn opposite sides of the gate structure. The front-side interconnection structure is over a front-side of the source epitaxial structure and a front-side of the drain epitaxial structure. The backside dielectric layer is over a backside of the source epitaxial structure and a backside of the drain epitaxial structure. The epitaxial regrowth layer is on the backside of a first one of the source epitaxial structure and the drain epitaxial structure. The backside via extends through the backside dielectric layer and overlaps the epitaxial regrowth layer.

Description

Integrated circuit structure and method of forming the same

The present disclosure relates to an integrated circuit structure and a method for forming the same.

The semiconductor industry moves into the nanotechnology process node in pursuit of higher component density, better performance, and lower cost. Manufacturing and design challenges have led to the development of 3D designs, such as multi-gate field effect transistors (field effect transistor, FET), including a fin field effect transistor (Fin FET) and a gate-all-around FET (GAA FET). In a Fin FET, the gate electrode is adjacent to three surfaces of the channel region, and the gate dielectric layer is interposed between the two. Because the gate structure surrounds (encloses) the fins on the three surfaces, the transistor essentially has three gates that control the current flow through the fin or channel region. Unfortunately, on the fourth side, the bottom portion of the channel is far from the gate electrode and is therefore not under adjacent gate control. In contrast, in a GAA FET, the entire surface of the channel layer is surrounded by the gate electrode, which allows the channel region to have Fuller depletion and less short channel effects due to steep sub-threshold current swing (SS) and smaller drain induced barrier lowering (DIBL).

An integrated circuit structure includes a gate structure, a source epitaxial structure, a drain epitaxial structure, a front side interconnection structure, a back side dielectric layer, an epitaxial regrowth layer and a back side through hole. The source epitaxial structure and the drain epitaxial structure are respectively located on opposite sides of the gate structure. The front side interconnect structure is located above the front side of the source epitaxial structure and the front side of the drain epitaxial structure. The backside dielectric layer is located over the backside of the source epitaxial structure and the backside of the drain epitaxial structure. The epitaxial regrowth layer is located behind the first one of the source epitaxial structure and the drain epitaxial structure. The backside vias extend through the backside dielectric layer to the epitaxial regrowth layer.

An integrated circuit structure includes a channel layer, a gate structure, a source epitaxial structure, a drain epitaxial structure, a front side interconnection structure, a back side through hole and an epitaxial regrowth layer. The channel layers are arranged one after the other in a spaced manner. A gate structure surrounds each channel layer. The source epitaxial structure and the drain epitaxial structure are respectively located on opposite end faces of the channel layer. The front side interconnection structure is located above the front side of the source epitaxial structure and the front side of the drain epitaxial structure. The backside via is located above the backside of the first one of the source epitaxial structure and the drain epitaxial structure. The epitaxial regrowth layer is located between the back side through hole and the first one of the source epitaxial structure and the drain epitaxial structure.

A method of forming an integrated circuit structure comprising: forming a transistor Above the substrate, the transistor includes a first source/drain epitaxial structure, a second source/drain epitaxial structure, and laterally located on the first source/drain epitaxial structure and the second source/ gate structure of drain epitaxial structure; removing at least a part of the substrate to expose the back side of the transistor; forming a back side dielectric layer on the exposed back side of the transistor; forming a back side via opening in in the backside dielectric layer to expose the backside of the first source/drain epitaxial structure of the transistor; forming an epitaxial regrowth layer over the exposed backside of the source/drain epitaxial structure of the transistor ; and forming a backside via in the backside via opening and above the epitaxial regrowth layer.

100, 100a, 100b, 100c: Integrated Circuit Structures

102: Groove

110: Substrate

112: Parts

119: Opening

120: Epitaxy stacking

122: epitaxial layer

124: epitaxial layer

130: Fins

140: Shallow trench isolation structure

150: virtual gate structure

152: virtual gate dielectric layer

154: virtual gate electrode layer

156,912: oxide layer

158,914: Nitride layer

160: Spacer material layer

162, 164: Spacer

170: Spacer material layer, internal spacer

180: Sacrificial epitaxial plug

190S: source epitaxial structure

190D: Drain epitaxial structure

192,194: Epitaxy layer

200: Contact etch stop layer

210: Interlayer dielectric layer

220: Gate structure

222: interface layer

224: Dielectric Layer

226: gate metal layer

230: source contact

240: drain contact

250: Multilayer Interconnect Structure

252: Front side metallization

253: first front side metal dielectric layer

254: Second Front Metal Dielectric Layer

255: Front side metal wire

256: front side metal through hole

260: Carrier substrate

270: Dielectric Layer

280, 280': epitaxial regrowth layer

290, 290': Through hole spacers

300: Rear side through hole

310: Multilayer Interconnection Multilayer Interconnection Structure

311: Bottom-most backside metallization

312: Upper backside metallization

313: Backside Intermetal Dielectric Layer

314: first back side intermetal dielectric layer

315: Metal Wire

316: Second rear intermetal dielectric layer

317: rear metal wire

318: Rear side metal through hole

320, 320': metal layer

330, 330': silicide area

600: Rear side through hole

910: Hard mask layer

D: drain region

GT1: Gate trench

M1, M2, M3, M4: Method

O1, O4, O5, O5': opening

P3: Mask

R1, R2, R3: groove

S: source region

S101,S102,S103,S104,S105,S106,S107,S108,S109,S110,S111,S201,S202,S203,S204,S301,S302,S303,S304,S305,S401,S402,S403,S404,S405: square

X-X, Y1-Y1, Y2-Y2, Y3-Y3: cutting line

Aspects of the present disclosure are best understood from the following detailed description when read in conjunction with the accompanying drawings. It should be noted that in accordance with standard practice in the industry, various features are not drawn to scale. In fact, the dimensions of the various features may be arbitrarily increased or decreased for clarity of discussion.

FIGS. 1 , 2, 3, 4A, 5A, 6A to 7A are schematic diagrams illustrating intermediate steps in manufacturing an integrated circuit structure according to one or more embodiments of the present disclosure. .

4B, 5B, 6B, 7B, 8, 9, 10A, 11A, 12, 13A, 14A, 15A, 16A Figure 17A, Figure 18A, Figure 19A, Figure 20A, Figure 21A, Figure 22A, Figure 23A, Figure 24A to Figure 25 according to one or more embodiments of the present disclosure Section along the first section of the intermediate steps in the manufacture of the integrated circuit structure Plane view along the longitudinal direction of the channel and perpendicular to the top surface of the substrate.

10B, 11B, 14B, 15B, 16B, 17B, 18B, 19B, 20B, 21B, 22B, 23B to 24B Figure is a cross-sectional view of an intermediate step of fabricating an integrated circuit structure along a second cut plane, in the source region and perpendicular to the longitudinal direction of the channel, in accordance with one or more embodiments of the present disclosure.

10C, 11C, 14C, 15C, 16C, 17C, 18C, 19C, 20C, 21C, 22C, 23C to 24C Figure is a cross-sectional view of an intermediate step of fabricating an integrated circuit structure along a third cut plane, which is in the drain region and perpendicular to the longitudinal direction of the channel, according to one or more embodiments of the present disclosure.

13B is a cross-sectional view of an intermediate step of fabricating an integrated circuit structure along a fourth cut plane, in the gate region and perpendicular to the longitudinal direction of the channel, according to one or more embodiments of the present disclosure.

FIGS. 23D-24D are top views of intermediate steps of fabricating an integrated circuit structure according to one or more embodiments of the present disclosure.

26 is a flowchart of intermediate steps in fabricating an integrated circuit structure in accordance with one or more embodiments of the present disclosure.

FIGS. 27A, 28A, 29A, 30A to 31 are cross-sectional views of intermediate steps of manufacturing an integrated circuit structure along a first cut plane according to one or more embodiments of the present disclosure, It is along the longitudinal direction of the channel.

FIGS. 27B , 28B, 29B to 30B are cross-sectional views of intermediate steps of fabricating an integrated circuit structure along a second cut plane according to one or more embodiments of the present disclosure. area and perpendicular to the longitudinal direction of the channel.

FIGS. 27C, 28C, 29C to 30C are cross-sectional views of intermediate steps of manufacturing an integrated circuit structure along a third cut plane according to one or more embodiments of the present disclosure, which is at the drain electrode area and perpendicular to the longitudinal direction of the channel.

FIG. 28D is a top view of an intermediate step of fabricating an integrated circuit structure in accordance with one or more embodiments of the present disclosure.

32 is a flowchart of intermediate steps in fabricating an integrated circuit structure in accordance with one or more embodiments of the present disclosure.

FIGS. 33A , 34A, 35A to 36 are cross-sectional views of intermediate steps of fabricating an integrated circuit structure along a first cut surface along a channel according to one or more embodiments of the present disclosure. portrait orientation.

FIGS. 33B , 34B to 35B are cross-sectional views of intermediate steps of fabricating an integrated circuit structure along a second cut plane, in the source region and vertical channel, according to one or more embodiments of the present disclosure. portrait orientation.

FIGS. 33C , 34C to 35C are cross-sectional views of intermediate steps of fabricating an integrated circuit structure along a third cut plane, in the drain region and vertical channel, according to one or more embodiments of the present disclosure. portrait orientation.

37 is a flow diagram of intermediate steps in fabricating an integrated circuit structure in accordance with one or more embodiments of the present disclosure.

Figure 38A, Figure 39A, Figure 40A to Figure 41 are based on the A cross-sectional view of an intermediate step of fabricating an integrated circuit structure along a first cut surface, along the longitudinal direction of the channel, is disclosed in one or more embodiments.

FIGS. 38B , 39B to 40B are cross-sectional views of intermediate steps of fabricating an integrated circuit structure along a second cut plane, in the source region and vertical channel, according to one or more embodiments of the present disclosure. portrait orientation.

FIGS. 38C , 39C to 40C are cross-sectional views of intermediate steps of fabricating an integrated circuit structure along a third cut plane, in the drain region and vertical channel, according to one or more embodiments of the present disclosure. portrait orientation.

42 is a flowchart of intermediate steps in fabricating an integrated circuit structure in accordance with one or more embodiments of the present disclosure.

The following disclosure provides many different embodiments or examples for implementing different features of the provided subject matter. Specific examples of components and arrangements are described below to simplify the present disclosure. Of course, these are only examples and are not intended to be limiting. For example, in the following description a first feature is formed over or over a second feature may include embodiments in which the first feature and the second feature are formed in direct contact, and may also include embodiments in which additional features may be Embodiments formed between the first feature and the second feature such that the first feature and the second feature may not be in direct contact. Additionally, the present disclosure may repeat reference numerals and/or letters in various instances. This repetition is for simplicity and clarity, and does not in itself represent a relationship between the various embodiments and/or configurations discussed.

In addition, for simplicity of description, such as Spatially relative terms "below", "below", "lower", "above", "upper" and similar terms to describe an element or feature as shown in the figures Relationship to another (additional) element or feature. These spatially relative terms are intended to encompass different orientations of elements in use or operation in addition to the orientation depicted in the figures. The device may be otherwise oriented (rotated 90 degrees or at other orientations), and the spatially relative descriptors used herein should likewise be interpreted accordingly. As used herein, "about", "about", "approximately" or "substantially" generally means within 20 percent, or within 10 percent, or within 20 percent of a given value or range of 5. Numerical quantities given herein are approximations, indicating that the use of terms such as "about," "approximately," "approximately," or "substantially" can be inferred when not explicitly stated.

The present disclosure generally relates to an integrated circuit structure and a method of forming the same, and more particularly to the fabrication of a gate-all-around (GAA) transistor having a gate-all-around (GAA) transistor having a source region and/or a drain region below the Wrap-around gate transistor with backside through hole. It should be noted that the embodiment of the present disclosure is a multi-gate transistor. Multi-gate transistors include transistors in which these gate structures are formed at least across the channel region. These multi-gate transistors may comprise p-type metal oxide semiconductor elements or n-type metal oxide semiconductor elements. Certain embodiments, based on their fin structures, may be disclosed and described herein as Fin Field Effect Transistors (FinFETs). And some embodiments disclosed herein are multi-gate transistors, known as gate-all-around (GAA) devices. GAA components include any component with a gate structure, or some components with a gate structure, in the form of Formed on four sides of the channel area (eg, around a portion of the channel area). The devices disclosed herein also include embodiments having channel regions disposed over nanosheet channel(s), nanowire channel(s), and/or other suitable channel configurations. Some device embodiments disclosed herein may have one or more channel regions (eg, nanosheets) associated with a single continuous gate structure. However, those skilled in the art will understand that the teachings of the present disclosure can be applied to a single channel (eg, a single nanosheet) or any number of channels. Those skilled in the art should note that other semiconductor device embodiments may benefit from the teachings of this disclosure.

As fin widths in fin field effect transistors (FinFETs) are shrinking, the change in channel width can cause mobility loss. GAA transistors, such as nanochip transistors, are being studied as an alternative to fin-field effect transistors. In a nanochip transistor, the gate of the transistor is fabricated to surround a channel (eg, a nanochip channel or a nanowire channel) such that the channel is surrounded or encapsulated by the gate. This enables the transistor to take advantage of the gate electrostatic control channel and reduce leakage current at the same time.

In some embodiments, backside power lines are applied, thereby creating more routing space for integrated circuit (IC) structures with a large number of GAA transistors. The backside metal vias provide electrical connection to the GAA transistor, eg, to the source epitaxial region. In some embodiments of the present disclosure, an epitaxial regrowth layer is formed on the backside of the source epitaxial structure after the wafer frontside process and the carrier wafer attach process. In this way, the epitaxial regrown layer undergoes less thermal process than the source epitaxial structure, and thus has better quality than the source epitaxial structure, which helps to reduce Contact resistance between the backside via and the epitaxial regrowth layer.

FIGS. 1 to 25 are diagrams and cross-sectional views illustrating intermediate steps of forming an integrated circuit with multiple gate devices according to various embodiments of the present disclosure. The steps presented in FIGS. 1 to 25 are also schematically reflected in the flow chart shown in FIG. 26 . As used herein, the term "multi-gate device" is used to describe a device (eg, a semiconductor transistor) that has at least some gate material disposed on multiple sides of at least one channel. In some embodiments, a multi-gate element, which may be referred to as a GAA element or nanochip element, has gate material disposed over at least four sides of at least one channel of the element. Channel regions may be referred to as "nanostructures," as used herein to include channel regions having various geometries (eg, cylinders, rods, sheets, etc.) and dimensions.

FIGS. 1, 2, 3, 4A, 5A, 6A to 7A illustrate intermediate steps of fabricating an integrated circuit structure 100 according to one or more embodiments of the present disclosure. Schematic. 4B, 5B, 6B, 7B, 8, 9, 10A, 11A, 12, 13A, 14A, 15A, 16A Figure 17A, Figure 18A, Figure 19A, Figure 20A, Figure 21A, Figure 22A, Figure 23A, Figure 24A to Figure 25 according to one or more embodiments of the present disclosure A cross-sectional view of an intermediate step in the fabrication of the integrated circuit structure 100 along a first cut plane (eg, cut plane line X-X in FIG. 4A ), which is along the longitudinal direction of the channel and perpendicular to the top surface of the substrate. Fig. 10B, Fig. 11B, Fig. 14B, Fig. 15B, Fig. 16B, Fig. 17B, Fig. 18B, Fig. 19B, Fig. 19B Figure 20B, Figure 21B, Figure 22B, Figure 23B to Figure 24B are along the second secant plane (eg, the secant plane line Y1-Y1 in Figure 4A) according to one or more embodiments of the present disclosure A cross-sectional view of an intermediate step in the fabrication of the integrated circuit structure 100, in the source region and perpendicular to the longitudinal direction of the channel. 10C, 11C, 14C, 15C, 16C, 17C, 18C, 19C, 20C, 21C, 22C, 23C to 24C 4A is a cross-sectional view of an intermediate step of fabricating the integrated circuit structure 100 along a third cut plane (eg, cut plane line Y2-Y2 in FIG. 4A ), in accordance with one or more embodiments of the present disclosure. polar region and perpendicular to the longitudinal direction of the channel. 13B is a cross-sectional view of an intermediate step of manufacturing the integrated circuit structure 100 along a fourth secant plane (eg, secant line Y3-Y3 in FIG. 4A ) according to one or more embodiments of the present disclosure, which in the gate region and perpendicular to the longitudinal direction of the channel. FIGS. 23D-24D are top views of intermediate steps of fabricating an integrated circuit structure 100 according to one or more embodiments of the present disclosure. It should be understood that additional operations may be provided before, during, and after the processes represented in FIGS. 1-25 and that some of the operations described below may be substituted or substituted in additional embodiments of the method. remove. The sequence of operations/processes can be interchanged.

As with other method embodiments and example elements discussed herein, it should be understood that portions of the integrated circuit structure 100 may be fabricated by CMOS technology process flows, and thus some of the processes are only described in general terms herein. Further, the exemplary integrated circuit structure may include various other elements and features, such as other types of elements such as additional transistors, Bipolar junction transistors, resistors, capacitors, inductors, diodes, fuses, static random access memory (SRAM) and/or other logic circuits, etc., but are simplified for better understanding Expose concept. In some embodiments, an exemplary integrated circuit structure includes a plurality of semiconductor elements (eg, transistors), including PFETs, NFETs, etc., which may be interconnected. Further, it should be noted that the process steps for fabricating the integrated circuit structure 100, including any description given according to FIG. 1 to FIG. 25, and the method and example diagrams provided in the present disclosure are for illustration only and are not intended to be limiting The content specified in the attached claim.

FIG. 1 is a schematic diagram illustrating an initial structure. The initial structure includes an epitaxial stack 120 formed over the substrate 110 . In some embodiments, the substrate 110 may include silicon (Si). Additionally, the substrate 110 may include germanium (Ge), silicon germanium (SiGe), III-V semiconductors (eg, GaAs, GaP, GaAsP, AlInAs, AlGaAs, GaInAs, InAs, GaInP, InP, InSb, and/or GaInAsP or a combination thereof) or other suitable semiconductor materials. In some embodiments, the substrate 110 may include a semiconductor-on-insulator (SOI) structure such as a buried dielectric layer. Additionally, the substrate 110 may include a buried dielectric layer, such as a buried oxide (BOX) layer, such as by utilizing a method known as separation by implantation of oxygen (SIMOX), a crystal Buried dielectric layer formed by circular connection, SEG or other suitable methods.

The epitaxial stack 120 includes an epitaxial layer 122 of a first composition intercalated by an epitaxial layer 124 of a second composition. The first component and the second component may be different. In some embodiments, epitaxial layer 122 is SiGe and epitaxial layer 124 is silicon (Si). However, other embodiments may include first and second components having different oxidation rates and/or etch selectivities. In some embodiments, the epitaxial layer 122 includes SiGe and the epitaxial layer 124 includes Si, and the oxidation rate of Si of the epitaxial layer 124 is lower than the oxidation rate of SiGe of the epitaxial layer 122 .

The epitaxial layer 124 of the multi-gate transistor, or a portion thereof, may form one or more nanochannels. As used herein, the term "nanostructure" is used to refer to any metal portion on the nanoscale, or any metal portion on the micrometer scale, and which has an elongated shape, regardless of the cross-sectional shape of the portion. Thus, this term refers to both circular and substantially circular cross-sectional areas of elongated material portions (eg, nanowires) and portions of bundles or rods of material (eg, nanosheets, nanowires) rod) which comprises, for example, a cylindrical shape or a substantially rectangular cross-sectional area. The epitaxial layer 124 is used to define a single channel or multiple channels of the device, which are discussed further below.

It should be noted that the three-layer epitaxial layers 122 and the three-layer epitaxial layers 124 are alternately arranged as shown in FIG. 1 , which are only for illustrative purposes and are not intended to limit the content specifically described in the claims. It is acceptable for any number of epitaxial layers to be formed in the epitaxial stack 120; the number of layers depends on the desired number of channel regions of the transistor. In some embodiments, the number of epitaxial layers 124 is between two and ten.

In some embodiments, each epitaxial layer 122 has a thickness ranging from about 1 nanometer (nm) to about 10 nm, although other ranges are possible within the scope of various embodiments of the present disclosure. The epitaxial layer 122 may have a substantially average thickness. In some embodiments, each epitaxial layer 124 Has a thickness in the range of about 1 nanometer (nm) to about 10 nm, although other ranges are possible within the scope of the various embodiments of the present disclosure. In some embodiments, epitaxial layer 124 may have a substantially average thickness. As described in more detail below, epitaxial layer 124 may serve as channel region(s) to substantially form a multi-gate device and its thickness is considered based on device performance. The epitaxial layer 122 can be finally removed in the channel region(s) and used to define the vertical distance between the channel region(s) to substantially form a multi-gate device, and its thickness is based on component performance is considered. Therefore, the epitaxial layer 122 may also be referred to as a sacrificial layer, and the epitaxial layer 124 may also be referred to as a channel layer.

For example, the layers of stack 120 may be epitaxially grown by a molecular beam epitaxy (MBE) process, a metalorganic chemical vapor deposition (MOCVD) process, and/or other suitable processes The epitaxial growth process is implemented. In some embodiments, an epitaxial growth layer such as epitaxial layer 124 includes the same material as substrate 110 . In some embodiments, epitaxial growth layers 122 and 124 comprise different materials than substrate 110 . As described above, in at least some embodiments, epitaxial layer 122 includes an epitaxially grown silicon germanium (SiGe) layer and epitaxial layer 124 includes an epitaxially grown silicon (Si) layer. Therefore, in some embodiments, both epitaxial layers 122 and 124 may include other materials such as germanium, semiconductor compounds such as silicon carbide, gallium arsenide, gallium phosphide, indium phosphide, indium arsenide and/or antimony Indium oxide, a semiconductor alloy such as SiGe, GaAsP, AlInAs, AlGaAs, InGaAs, GaInP, and/or GaInAsP or combinations thereof. As discussed above, the materials of epitaxial layers 122 and 124 may be selected based on providing different oxidation states and/or selective etch characteristics. In some embodiments, epitaxial layers 122 and 124 are substantially free of dopants (eg, have external dopant concentrations between about 0 cm ⁻³ to about 1×10 ¹⁸ cm ⁻³ ), for example , no intentional doping is performed during the epitaxial growth process.

FIG. 2 is a schematic diagram illustrating forming a plurality of semiconductor fins 130 extending from the substrate 110 . In various embodiments, each fin 130 includes substrate portion 112 formed from substrate 110 and a portion of each epitaxial layer in epitaxial stack 120 , including epitaxial layers 122 and 124 .

In some embodiments shown in FIGS. 1 and 2, a hard mask (HM) layer 910 is formed over the epitaxial stack 120 before the fins 130 are patterned. In some embodiments, the HM layer 910 includes an oxide layer 912 (eg, the slab oxide layer may include SiO ₂ ) and a nitride layer 914 (eg, the slab nitride layer may include Si ₃ N ₄ ) is formed over the oxide layer. The oxide layer 912 can serve as an adhesion layer between the epitaxial stack 120 and the nitride layer 914 and as an etch stop layer for etching the nitride layer 914 . In some embodiments, the HM oxide layer 912 includes thermally grown oxide, chemical vapor deposition (CVD) deposited oxide, and/or atomic layer deposition (ALD) deposited oxide. In some embodiments, the HM nitride layer 914 is deposited over the HM oxide layer 912 by CVD and/or other suitable techniques.

The fins 130 may be substantially fabricated by suitable processes, including photolithography and etching processes. The photolithography process may include forming a photoresist layer (not shown) OUT) Over the HM layer 910, the photoresist layer is exposed under the pattern, a pre-exposure bake process is performed, and the photoresist is developed to form a patterned mask including the photoresist. In some embodiments, patterning photoresist to form patterned mask elements may utilize an electron beam (e-beam) lithography process or utilize light in the extreme ultraviolet (EUV) region, having wavelengths At, eg, about 1-100 nm, an EUV lithography process is performed. A patterned mask can then be used to protect regions of the substrate 110 and form multiple layers over the regions while the etch process forms recesses 102 in the unprotected regions and through the HM layer 910, through the epitaxial Stack 120 and enter substrate 110, thereby leaving a plurality of extended fins 130. The grooves 102 may be etched using dry etching (eg, reactive ion etching), wet etching, and/or combinations thereof. Embodiments of numerous other methods of forming fins over a substrate may also be used including, for example, defining fin regions (eg, by masks or isolation regions) and epitaxially growing epitaxial layers when forming fins 130 Stack 120. The fins 130 may be fabricated using suitable processes including dual patterning or multi-patterning processes. In general, dual-patterning or multi-patterning combined with photolithography and self-alignment processes allows patterns to be created with, for example, gaps smaller than those achieved with a single, direct photolithography process. For example, in one embodiment, a sacrificial layer is formed over the substrate and patterned using a photolithography process. Spacers are formed side-by-side on the patterned sacrificial layer using a self-aligned process. The sacrificial layer is then removed, leaving spacers, or mandrels, which can then be used to pattern the fins 130 by etching the initial epitaxial stack 120 . The etching process may include dry etching, wet etching, reactive ion etching (RIE) and/or or other suitable process.

FIG. 3 is a schematic diagram of forming a shallow trench isolation (STI) structure 140 laterally surrounding the lower portion of the fin 130 . By way of example and not limitation of the present disclosure, a dielectric layer is first deposited over substrate 110, filling recess 102 with a dielectric material. In some embodiments, the dielectric layer may include silicon oxide, silicon nitride, silicon oxynitride, fluorine-doped silicate glass (FSG), low-k dielectrics, combinations thereof, and/or other suitable materials. In various examples, the dielectric layer may be formed by a CVD process, a subatmospheric CVD (SACVD) process, a flowable CVD process, an ALD process, a physical vapor deposition (PVD) process, and/or Other suitable processes are deposited. In some embodiments, the integrated circuit structure 100 may be annealed after deposition of the dielectric layer, eg, to improve the quality of the dielectric layer. In some embodiments, the dielectric layer (and substantially formed STI structure 140 ) may comprise a multi-layer structure, eg, with one or more liner layers.

In some embodiments where shallow trench (STI) features are formed, after depositing the dielectric layer, the deposited dielectric material is thinned and planarized, eg, by a chemical mechanical polishing (CMP) process . In some embodiments, the HM layer 910 (as shown in Figure 2) is used as a CMP stop layer. The STI structures 140 surrounding the fins 130 are recessed. According to the example of FIG. 3 , the STI structure 140 is recessed to provide the fins 130 extending over the STI structure 140 . In some embodiments, the recessing process may include a dry etching process, a wet etching process, and/or a combination thereof. The HM layer 910 may also be removed before, during, and/or after the STI structure 140 is recessed. The _nitride layer 914 of the HM layer 910 can be removed, for example, by wet etching with _H3PO4 or other suitable etchant. In some embodiments, oxide layer 912 of HM layer 910 may be removed by the same etchant used to recess STI structure 140 . In some embodiments, the recess depth is controlled (eg, by controlling the etch time) to ultimately obtain the desired height of the exposed upper portion of the fins 130 . In the illustrated embodiment, the desired height exposes multiple layers in each epitaxial stack 120 of fins 130 .

According to FIGS. 4A and 4B, the gate structure 150 is formed. In some embodiments, gate structure 150 is a dummy (sacrificial) gate structure, which can be substantially removed. Therefore, in some embodiments using the last gate process, the gate structure 150 is a dummy gate structure and is replaced by the final gate structure in subsequent process steps of the integrated circuit structure 100 . Specifically, the dummy gate structure 150 may be replaced by a high-k dielectric layer (HK) and a metal gate electrode (MG) in subsequent process steps, as discussed below. In some embodiments, dummy gate structures 150 are formed over substrate 110 and at least partially disposed over fins 130 . The portion of the fin 130 under the dummy gate structure may be referred to as a channel region. The dummy gate structure 150 may also define source/drain (S/D) regions of the fin 130 , eg, the regions of the fin 130 are adjacent to and on opposite sides of the channel region.

In the illustrated embodiment, dummy gate fabrication begins by forming a dummy gate dielectric layer 152 over the fins 130 . In some embodiments, the dummy gate dielectric layer 152 may include SiO ₂ , silicon nitride, high-k dielectric materials, and/or other suitable materials. In various embodiments, the dummy gate dielectric layer 152 may be formed by a CVD process, a subatmospheric CVD (SACVD) process, a flowable CVD process, an ALD process, or a physical vapor deposition (PVD) process. ) process or other suitable process is deposited. By way of example, the dummy gate dielectric layer 152 can avoid damage to the fins 130 through subsequent processes (eg, subsequent fabrication of the dummy gate structure). Subsequently, portions of other gate electrode structures 150 are formed, including a dummy gate electrode layer 154 and a hard mask, which may include multiple layers 156 and 158 (eg, oxide layer 156 and nitride layer 158). In some embodiments, the dummy gate structure 150 is formed by various process steps such as layer deposition, patterning, etching, and other suitable process steps. Exemplary layer deposition processes include CVD (including both low pressure CVD and plasma enhanced CVD), PVD, ALD, thermal oxidation, e-beam evaporation, or other suitable deposition techniques, or combinations thereof. In the example of forming the gate structure, the patterning process includes a lithography process (eg, photolithography or e-beam lithography), which may further include photoresist coating (eg, spin coating), soft bake, mask pairing calibration, exposure, pre-exposure bake, photoresist development, rinse, drying (eg, spin and/or hard bake), other suitable lithography techniques, and/or combinations thereof. In some embodiments, the etching process may include dry etching (eg, RIE etching), wet etching, and/or other etching methods. In some embodiments, the dummy gate electrode layer 154 may include polysilicon. In some embodiments, the hard mask includes an oxide layer 156, such as a slab oxide layer, which may include _SiO2 , and a nitride layer 158, such as a slab _nitride layer, which may include _Si3N4 and/or silicon oxynitride. In some embodiments, after patterning the dummy gate electrode layer 154 , the dummy gate dielectric layer 152 is removed from the S/D regions of the fins 130 . The etching process may include wet etching, dry etching, and/or combinations thereof. The etch process is selected to selectively etch dummy gate dielectric layer 152 and not substantially etch fin 130 , dummy gate electrode layer 154 , oxide layer 156 and nitride layer 158 .

FIGS. 4A and 4B illustrate the formation of gate spacers 162 over the sidewalls of the regional gate structures 150 and fin spacers 164 over the sidewalls of the semiconductor fins 130 . In some embodiments where these spacers 162 , 164 are formed, a layer of spacer material 160 is first deposited over the substrate 110 . Spacer material layer 160 may be a conformal layer that is substantially etched to form gate sidewall spacers 162 and fin sidewall spacers 164 . In the illustrated embodiment, a layer of spacer material 160 is conformally deposited over the dummy gate structures 150 and the tops and sidewalls of the fins 130 . In some embodiments, the spacer material layer 160 includes multiple layers, such as a first spacer layer and a second spacer layer formed over the first spacer layer. The spacer material layer 160 may include one or more dielectric materials, such as silicon oxide, silicon nitride, silicon carbide, silicon oxynitride, SiCN films, silicon oxycarbide, SiOCN films, and/or combinations thereof. By way of example, a dielectric material is deposited over the dummy gate structure 150 to form the spacer material layer 160 by utilizing a process such as a CVD process, a subatmospheric CVD (SACVD) process, a flowable CVD process, ALD process, physical vapor deposition (PVD) or other suitable processes. Anisotropic etching process connection This is implemented on the layer of spacer material 160 before deposition to expose portions of the fins 130 not covered by the dummy gate structures 150 (eg, in the source/drain regions of the fins 130 ). The portion of the spacer material layer 160 directly above the dummy gate structure 150 can be completely removed by this anisotropic etching process. The portion of the spacer material layer 160 located on the sidewall of the dummy gate structure 150 is reserved as the gate spacer 162, and the lower portion of the spacer material layer 160 located on the sidewall of the semiconductor fin 130 is reserved as the fin spacer Object 164.

According to FIGS. 5A and 5B, the exposed portions of the semiconductor fins 130 extend laterally over the gate spacers 162 (eg, the fins 130 in the source/drain regions) and by utilizing the dummy gate structure 150 and the gate spacer 162 are etched in an anisotropic etching process as an etching mask, and finally a groove R1 is formed in the semiconductor fin 130 and between the corresponding dummy gate structures 150 . After the anisotropic etching process, the termination surfaces of the sacrificial layer (epitaxy layer 122 ) and the channel layer (epitaxy layer 124 ) are aligned with the outermost sidewalls of the corresponding gate spacers 162 due to the effect of the anisotropic etching. In some embodiments, anisotropic etching can be performed by dry chemical etching with a plasma source and reactive gases. The plasma source can be an inductively coupled plasma (ICR) source, a transformer coupled plasma (TCP) source, an electron cyclotron resonance (ECR) source, or the like, and the reactive gas Can be, for example, fluorine based gas (eg _SF6 , _CH2F2 , _CH3F , _CHF3 or the like ₎ , chlorine based gas (eg Cl2), _hydrogen bromide gas (HBr), oxygen ( O ₂ ), the like or a combination thereof.

Next, according to FIGS. 6A and 6B , the sacrificial layer (epitaxial layer 122 ) is recessed laterally or horizontally by a suitable etching process, finally between each corresponding channel layer (epitaxial layer 124 ) The lateral grooves R2 are formed vertically. This step can be performed by a selective etching process. By way of example and not limitation of the present disclosure, the sacrificial layer (epitaxial layer 122 ) is SiGe and the channel layer (epitaxial layer 124 ) is silicon allowing selective etching of the sacrificial layer (epitaxial layer 122 ). In some embodiments, the selective wet etch includes an APM etch (eg, an ammonium hydroxide-ammonia peroxide-water mixture) that etches SiGe at a faster etch rate than etching Si. In some embodiments, the SiGe-containing oxide is selectively etched and then SiGeOx _is removed. For example, oxidation can remove SiGeOx _by providing an _O3 clean followed by an etchant such as _NH4OH , which etches _SiGeOx at a faster etch rate than etching Si. Further, since the oxidation rate of Si is much smaller (sometimes 30 times smaller) than that of SiGe, the channel layer (epitaxial layer 124 ) is substantially in the process of recessing the sacrificial layer (epitaxial layer 122 ) laterally. It is kept intact. Ultimately, the channel layer (epitaxial layer 124 ) extends laterally through the opposite terminal surface of the sacrificial layer (epitaxial layer 122 ).

Next, according to FIGS. 7A and 7B , an internal spacer material layer 170 is formed to fill the recesses left by the side etching of the sacrificial layer (epitaxial layer 122 ) discussed above with respect to FIGS. 6A and 6B R2. The inner spacer material layer 170 may be a low-k dielectric material such as SiO ₂ , SiN, SiCN or SiOCN and may be formed by a suitable deposition method such as ALD. After the deposition of the inner spacer material layer 170, an anisotropic etch process may be performed to trim the deposited inner spacer material layer 170 so that the inner spacer material layer 170 fills only through the sacrificial layer (epitaxy layer 122). A portion of the groove R2 left by the side etching remains. After the trimming process, the portion of the deposited inner spacer material layer 170 that remains is designated as inner spacer 170 for simplicity. The internal spacers 170 serve as isolation metal gates for source/drain epitaxial structures formed in subsequent processes. In the example of Figures 7A and 7B, the sidewalls of the internal spacers 170 are aligned with the sidewalls of the channel layer (epitaxial layer 124).

In some embodiments, the source regions S of the fins 130 according to FIG. 8 are further recessed, so that a sacrificial epitaxial plug can be substantially formed in the recessed source regions S, and then processed by a later stage of the subsequent process. side vias are replaced. In some embodiments of the source region recessing step, the patterned mask P3 is first formed to cover the drain region D of the fin 130 but not the source region S of the fin 130 , and then the The source region S is recessed, resulting in a source region groove R3 of the fin 130 . In some embodiments, the patterned mask P3 may be a photoresist mask formed by a suitable photolithography process. For example, a photolithography process may include spin-coating a photoresist layer over the structures as depicted in Figures 7A and 7B, performing a pre-exposure bake process, and developing the photoresist layer to form the patterned mask P3 . In some embodiments, patterning the photoresist to form the patterned mask elements may be performed using an electron beam (e-beam) lithography process or an extreme ultraviolet (EUV) lithography process.

After the patterned mask P3 is formed, the source region groove R3 may be formed in the source region S using, for example, an anisotropic etching process. In some embodiments, anisotropic etching can be performed by dry chemical etching with a plasma source and reactive gases. By way of example and not limitation of the present disclosure, the plasma source may be an inductively coupled plasma (ICR) source, a transformer coupled plasma (TCP) source, an electron cyclotron resonance (ECR) source ) source or the like, and the reactive gas may be, for example, a fluorine _- based gas (eg, _SF6 , _CH2F2 , _CH3F , CHF3, or the like), a chlorine _- based gas (eg, Cl2 ₎ , Hydrogen bromide gas (HBr), oxygen ( _O2 ), the like, or a combination thereof.

FIG. 9 shows that the sacrificial epitaxial plug 180 is formed in the source region groove R3. In some embodiments of this step, with the patterned mask P3 positioned, an epitaxial growth process is performed to grow epitaxial material in the source region recess R3 until the epitaxial material creates a sacrificial epitaxial plug 180 to fill the source Area groove R3. The epitaxial material and the substrate 110 have different compositions, thus resulting in different etch selectivities between the sacrificial epitaxial plug 180 and the substrate 110 . For example, the substrate 110 is silicon and the sacrificial epitaxial plug 180 is SiGe. In some embodiments, the sacrificial epitaxial plug 180 is SiGe without p-type dopants (eg, boron) and n-type dopants (eg, phosphorus) because the sacrificial epitaxial plugs 180 will be processed later in the process is removed from the fuse and does not serve as the source terminal of the transistor in the final IC product. After the formation of the sacrificial epitaxial plug 180 is completed, the patterned mask P3 is removed by, for example, ashing.

According to some embodiments of the present disclosure, in order to prevent SiGe from being inadvertently formed on the termination surface of the Si channel layer (the epitaxial layer 124 ), the SiGe sacrificial epitaxial plug 180 may be grown in a bottom-up manner. By way of example and not limitation of the present disclosure, the SiGe sacrificial epitaxial plug 180 may be grown by a deposition/partial etch process that repeats the deposition/partial etch process at least once. This repeated deposition/partial etch process is also referred to as a cyclic deposition-etch (CDE) process. In some embodiments, the SiGe sacrificial epitaxial plug 180 is grown by selective epitaxial growth (SEG), in which etching gas is added to lift from the bottom of the source region groove R3 having the first crystal plane Selective growth of silicon germanium rather than the selective growth of silicon germanium from the vertical termination surface of the channel layer (epitaxial layer 124 ) having a second crystal plane different from the first crystal plane. For example, the SiGe sacrificial epitaxial plug 180 is prepared using reactive gases such as HCl as an etching gas, _GeH4 as a Ge precursor gas, DSC and/or _SiH4 as a Si precursor gas, and _H2 and/or _N2 as a carrier gas. Epitaxial growth. In some embodiments, the etching gas may be other chlorine-containing gas or bromine-containing gas such as Cl ₂ , BCl ₃ , BiCl ₃ , BiBr ₃ , or the like.

The deposition state of SiGe is controlled (for example, by adjusting the flow rate ratio of Ge precursor gas, Si precursor gas and carrier gas) so that the growth rate of SiGe at the bottom of the source region groove R3 The growth rate of the vertical terminal surface of the channel layer (epitaxial layer 124 ) is faster because the bottom of the source region groove R3 and the vertical terminal surface of the channel layer (epitaxial layer 124 ) have different crystal orientation planes. Therefore, the SiGe deposition step combined with the etching step promotes bottom-up SiGe growth. For example, the growth of SiGe from the bottom of the source region groove R3 is compared with that from the channel layer (epitaxy). The vertical termination surface of layer 124) grows at a faster rate. The etching gas simultaneously etches the SiGe grown from the vertical terminal surface of the channel layer (epitaxy layer 124 ) and the SiGe grown from the bottom of the source region groove R3 at the same etching rate. However, since the growth rate of SiGe grown from the bottom of source region recess R3 is faster than that of SiGe grown from the vertical termination surface of the channel layer (epitaxial layer 124), the net effect is that SiGe will grow substantially from the bottom to the bottom. It grows from the bottom of the groove R3 in the source region. By way of example and not limitation of the present disclosure, in each deposition etch cycle of the CDE process, the etch step will stop when the terminal surface of the channel layer (epitaxial layer 124 ) is exposed, and the bottom of the groove R3 from the source region will be stopped. The grown SiGe will remain in the source region recess R3 because it is thicker than the SiGe grown from the vertical termination surface of the channel layer (epitaxial layer 124). In this way, bottom-up growth can be achieved. The CDE process discussed above is only one example to explain how to form the SiGe sacrificial epitaxial plug 180 in the source region recess R3 rather than from the vertical termination surface of the channel layer (epitaxial layer 124 ), and other suitable techniques may also be used is used to form the SiGe sacrificial epitaxial plug 180 .

10A to 10C illustrate the formation of the source/drain epitaxial structures 190S/190D. In more detail, the source epitaxial structure 190S is formed over the sacrificial epitaxial plug 180 in the recessed source region S of the fin 130 , and the drain epitaxial structure 190D is formed in the drain region of the fin 130 Above D. The source/drain epitaxial structures 190S/190D may be formed by performing epitaxial growth to provide epitaxial material over the sacrificial epitaxial plug 180 and the fin 130 . During the epitaxial growth process, the dummy gate structure 150 and gate sidewall spacers 162 confine the source/drain epitaxial structure 190S/190D is limited to source/drain region S/D. Suitable epitaxial processes include CVD deposition techniques (eg, vapor-phase epitaxy (VPE) and/or ultra-high vacuum CVD (UHV-CVD)), molecular beam epitaxy, and/or or other suitable process. The epitaxial growth process may utilize gaseous and/or liquid precursors that act in combination with the semiconductor materials of the fins 130, the sacrificial epitaxial plugs 180, and the channel layer (the epitaxial layer 124).

In some embodiments, the source/drain epitaxial structures 190S/190D may comprise Ge, Si, GaAs, AlGaAs, SiGe, GaAsP, SiP, or other suitable materials. The source/drain epitaxial structures 190S/190D may be formed by introducing dopant species during the epitaxial process including: p-type dopants such as boron or BF ₂ , n-type dopants such as phosphorus or arsenic and/or other suitable dopants, including combinations thereof, are doped in situ. If the source/drain epitaxial structures 190S/190D are not doped in-situ, an implantation process (eg, an interface implantation process) is performed to dope the source/drain epitaxial structures 190S/190D. In some exemplary embodiments, the source/drain epitaxial structures 190S/190D of the NFET devices include SiP, and the source/drain epitaxial structures 190S/190D of the PFET devices include GeSnB and/or SiGeSnB.

In some embodiments, each source/drain epitaxial structure 190S/ 190D includes a first epitaxial layer 192 and a second epitaxial layer 194 over the first epitaxial layer 192 . The first epitaxial layer 192 and the second epitaxial layer 194 may be different in at least one of germanium atomic percentage (Ge %) or phosphorus concentration (P %). In the depicted embodiment, the first epitaxial layer 192 may be In order to grow not only from the top surface of the sacrificial epitaxial plug 180 and the fin 130, but also from the terminal surface of the channel layer (the epitaxial layer 124). This is because the formation of the source/drain epitaxial structures 190S/190D does not necessarily have to have a bottom-up approach according to the sacrificial epitaxial plug 180 discussed above.

In some source/drain epitaxial structures 190S/190D with GeSnB and/or SiGeSnB to form PFETs, the first epitaxial layer 192 and the second epitaxial layer 194 differ at least in germanium atomic percent (Ge%). In certain embodiments, the first SiGe epitaxial layer 192 has a lower atomic percentage of germanium than the second SiGe epitaxial layer 194 . The lower atomic percentage of germanium in the first SiGe epitaxial layer 192 can help lower the Schottky barrier of undoped Si in the fins 130 . A high atomic percentage of germanium in the second SiGe epitaxial layer 194 can help reduce source/drain contact resistance. By way of example and not limitation of the present disclosure, the atomic percentage of germanium in the first SiGe epitaxial layer 192 is in the range of about 10% to about 20%, and the atomic percentage of germanium in the second SiGe epitaxial layer 194 is in the range of about 20% to about 20%. A range of about 60%, but other ranges without departing from the various embodiments of the present disclosure, may also be used. In some embodiments, the second SiGe epitaxial layer 194 may have a gradient of atomic percent germanium. For example, the germanium atomic percentage of the second SiGe epitaxial layer 194 increases as the distance from the first SiGe epitaxial layer 192 increases.

In some embodiments, the source/drain epitaxial structure 190S/190D includes SiP to form an NFET, and the first SiP epitaxial layer 192 and the second SiP epitaxial layer 194 differ at least in phosphorus concentration (P%). In certain embodiments, the first SiP epitaxial layer 192 has a lower phosphorus concentration than the second SiP epitaxial layer 194 . The low phosphorous concentration of the first SiP epitaxial layer 192 can help lower the Schottky barrier of undoped Si in the fins 130 . The high phosphorus concentration of the second SiGe epitaxial layer 194 can help reduce the source/drain contact resistance. By way of example and not limitation of the present disclosure, the phosphorus concentration of the first SiP epitaxial layer 192 is in the range of about 5×10 ¹⁹ cm ⁻³ to about 1×10 ²¹ cm ⁻³ , and the second SiP epitaxial layer 194 has a phosphorus concentration in the range of about 5×10 19 cm −3 to about 1×10 21 cm −3 . Phosphorus concentrations are in the range of about 1×10 ²¹ cm ⁻³ to about 3×10 ²¹ cm ⁻³ , but other ranges may be used without departing from the various embodiments of the present disclosure. In some embodiments, the second SiP epitaxial layer 194 may have a gradient phosphorous concentration. For example, the phosphorus concentration of the second SiP epitaxial layer 194 increases as the distance from the first SiP epitaxial layer 192 increases.

After the source/drain epitaxial structures 190S/190D are formed, an annealing process may be performed to activate p-type dopants or n-type dopants in the source/drain epitaxial structures 190S/190D. The annealing process may be, for example, a rapid thermal anneal (RTA), laser annealing, millisecond thermal annealing (MTA) process, or the like.

FIGS. 11A to 11C illustrate the formation of a front-side interlayer dielectric (ILD) layer 210 over the substrate 110 . The ILD layer 210 is referred to herein as the "front-side" ILD layer because it is formed on the front side of the multi-gate transistor (eg, the gate of the multi-gate transistor protrudes from the sides of the source/drain regions 190S/190D ). In some embodiments, a contact etch stop layer (CESL) 200 is also formed before forming the ILD layer 210 . in some real In an embodiment, the CESL 200 includes a silicon nitride layer, a silicon oxide layer, a silicon oxynitride layer, and/or other suitable materials having different etch selectivities than the front side ILD layer 210 . CESL 200 may be formed by a plasma-enhanced chemical vapor deposition (PECVD) process and/or other suitable deposition or oxidation processes. In some embodiments, the front side ILD layer 210 includes a material such as tetraethylorthosilicate (TEOS) oxide, undoped silicate glass, or doped silicon oxide, such as borophosphosilicate glass (borophosphosilicate glass, BPSG), fused silica glass (fused silica glass, FSG), phosphosilicate glass (phosphosilicate glass, PSG), boron doped silicon glass (boron doped silicon glass, BSG) and/or other comparable CESL 200 has suitable dielectric materials with different etch selectivities. The front side ILD layer 210 may be deposited by a PECVD process or other suitable deposition techniques. In some embodiments, the integrated circuit structure 100 may be subject to a high thermal budget process to anneal the front side ILD layer 210 prior to forming the front side ILD layer 210 .

In some embodiments, after depositing the front side ILD layer 210 , a planarization process may be performed to remove excess material of the front side ILD layer 210 . For example, the planarization process includes a chemical mechanical planarization (CMP) process that removes the portion of the front side ILD layer 210 (and CESL 200 layer, if present) over the dummy gate structure 150 and the planarization product The top surface of the bulk circuit structure 100 . In some embodiments, the CMP process also removes the hard mask layer 156, 158 (shown in FIG. 10A ) and a dummy gate electrode layer 154 .

Next, the dummy gate electrode structure 150 is removed, followed by removal of the sacrificial layer (epitaxial layer 122). The final structure is shown in Figure 12. In the illustrated embodiment, the dummy gate structure 150 is formed by utilizing a selective process (eg, selective dry etching, selective wet etching, or a combination thereof), which is superior to other materials (eg, gate The gate sidewall spacers 162 , CESL 200 and/or the front side ILD layer 210 ) have faster etch rates to etch the material in the dummy gate structure 150 , thus resulting in gate trenches GT1 between the corresponding gate sidewall spacers 162 , and the sacrificial layer (the epitaxial layer 122 ) is exposed in the gate trench GT1 . Then, the sacrificial layer (epitaxial layer 122 ) in the gate trench GT1 is etched using other selective etching processes, which is compared to etching the channel layer (epitaxial layer 124 ) when etching the sacrificial layer (epitaxial layer 122 ) It is exposed with a faster etch rate, thus forming openings O1 between adjacent channel layers (epitaxy layer 124). As a result, the channel layer (epitaxial layer 124 ) becomes the nanostructure suspended above the substrate 110 and between the source/drain epitaxial structures 190S/190D. This step is also known as the channel release process. During this interim process step, the openings 119 between the nanostructures (the epitaxial layers 124 ) can be filled in an atmospheric environment (eg, air, nitrogen, etc.). In some embodiments, the nanostructures (epitaxy layer 124) may be referred to interchangeably as nanowires, nanosheets, nanoplates, and nanorings, depending on their geometry. For example, in some other embodiments, the channel layer (epitaxial layer 124 ) may be trimmed to have a substantially rounded shape (eg, a cylinder) that utilizes a selective etch process to completely remove the sacrificial layer ( epitaxial layer 122). In this case, the resulting channel layer (epitaxial layer 124) can be referred to as a nanowire.

In some embodiments, the sacrificial layer (epitaxial layer 122 ) is removed by utilizing a selective wet etch process. In some embodiments, the sacrificial layer (epitaxial layer 122 ) is SiGe and the channel layer (epitaxial layer 124 ) is silicon, which allows for selective removal of the sacrificial layer (epitaxial layer 122 ). In some embodiments, the selective wet etch includes an APM etch (eg, a mixture of ammonium hydroxide-ammonia peroxide-water). In some embodiments, the selective removal includes SiGe oxidation followed by removal of _SiGeOx . For example, oxidation can remove SiGeOx _by providing an _O3 clean followed by an etchant such as _NH4OH , which etches _SiGeOx at a faster etch rate than etching Si. Furthermore, because the oxidation rate of silicon is much lower (sometimes up to 30 times lower) than that of SiGe, the channel layer (epitaxial layer 124) can remain substantially intact during the channel release process. In some embodiments, both the channel release step and the previous step of laterally recessing the sacrificial layer (ie, the steps shown in Figures 6A and 6B) etch SiGe with a faster etch rate compared to Si The selective etch process and thus the two steps can use the same etchant chemistry in some embodiments. In this example, the etch time/process of the channel release process is longer than the etch time/process of the previous step of laterally recessing the sacrificial layer in order to completely remove the sacrificial SiGe layer.

13A and 13B illustrate the formation of the alternate gate structure 220 . A replacement gate structure 220 is correspondingly formed in the gate trench GT1 to surround each nanostructure (epitaxial layer 124 ) suspended in the gate trench GT1 . The gate structure 220 can serve as the final gate of the GAA FET. The final gate structure can be a high-k/metal gate stack, although other combinations are possible. In some embodiments, each gate structure 220 is formed by Gates associated with multiple channels by multiple nanostructures (epitaxial layers 124). For example, the high-k/metal gate structure 220 is formed in the opening O1 provided by the release nanostructure (the epitaxial layer 124) (as shown in FIG. 12). In various embodiments, the high-k/metal gate structure 220 includes an interface layer 222 formed around the nanostructure (epitaxial layer 124 ) and a high-k gate dielectric layer 224 formed around the gate metal layer 226 and Fill the remaining gate trench GT1. The formation of the high-k/metal gate structure 220 may include one or more deposition processes to form various gate materials, followed by a CMP process to remove excess gate material, resulting in the top of the high-k/metal gate structure 220 having The surface is at the same level as the top surface of the front side ILD layer. A cross-sectional view along the longitudinal axis of the high-k/metal gate structure 220 as depicted in FIG. 13B, the high-k/metal gate structure 220 surrounds each nanostructure (epitaxial layer 124) and is therefore referred to as a GAA FET gate.

In some embodiments, the interface layer 222 is silicon oxide formed on the exposed surface of the semiconductor material of the gate trench GT1, which is formed using, for example, thermal oxidation, chemical oxidation, wet oxidation, or the like. Finally, the surface portion of the nanostructure (the epitaxial layer 124 ) exposed in the gate trench GT1 and the substrate portion 112 are oxidized to silicon oxide to form the interface layer 222 . Therefore, the remaining part of the nanostructure (epitaxial layer 124 ) in the gate trench GT1 is thinner than the other part of the nanostructure (the epitaxial layer 124 ) not in the gate trench GT1 , such as the As shown in Figure 13A.

In some embodiments, the high-k gate dielectric layer 224 includes a dielectric material with a high dielectric constant, eg, greater than that of thermal silicon oxide (~3.9). For example, the high-k gate dielectric layer 224 may include hafnium dioxide (HfO ₂ ), hafnium silicon oxide (HfSiO), hafnium silicon oxynitride (HfSiON), hafnium tantalum oxide (HfTaO), hafnium titanium oxide (HfTiO) , Hafnium zirconium oxide (HfZrO), lanthanum oxide (LaO), zirconium oxide (ZrO), titanium oxide (TiO), tantalum oxide (Ta ₂ O ₅ ), yttrium oxide (Y ₂ O ₃ ), strontium titanium oxide (SrTiO ₃ , STO), barium titanate (BaTiO ₃ , BTO), barium zirconium oxide (BaZrO), hafnium lanthanum oxide (HfLaO), lanthanum silicon oxide (LaSiO), aluminum silicon oxide (AlSiO), aluminum oxide (Al ₂ O ₃ ), silicon nitride (Si ₃ N ₄ ), oxynitride (SiON), the like or a combination thereof.

In some embodiments, gate metal layer 226 includes one or more metal layers. For example, gate metal layer 226 may include one or more work function metal layers stacked on top of each other and fill metal to fill the remainder of gate trench GT1. One or more work function metal layers in gate metal layer 226 provide a suitable work function for high-k/metal gate structure 220 . For n-type GAA FETs, gate metal layer 226 may include one or more n-type work function metal (N-metal) layers. The n-type work function metal may exemplarily include, but is not limited to, titanium aluminide (TiAl), titanium aluminum nitride (TiAlN), tantalum carbonitride (TaCN), hafnium (Hf), zirconium (Zr), titanium (Ti), tantalum (Ta), aluminum (Al), metal carbides (eg, hafnium carbide (HfC), zirconium carbide (ZrC), titanium carbide (TiC), aluminum carbide (AlC)), aluminides and/or other suitable materials. On the other hand, for p-type GAA FETs, gate metal layer 226 may include one or more p-type work function metal (P-metal) layers. The p-type work function metal may exemplarily include, but is not limited to, titanium nitride (TiN), tungsten nitride (WN), tungsten (W), ruthenium (Ru), palladium (Pd), platinum (Pt), Cobalt (Co), Nickel (Ni), conductive metal oxides and/or other suitable materials. exist In some embodiments, the filling metal of the gate metal layer 226 can exemplarily include, but is not limited to, tungsten, aluminum, copper, nickel, cobalt, titanium, tantalum, titanium nitride, tantalum nitride, nickel silicide, silicide Cobalt, TaC, TaSiC, TaCN, TiAl, TiAlN or other suitable materials.

FIGS. 14A to 14C illustrate the source contact 230 over the source epitaxial structure 190S and the drain contact 240 over the drain epitaxial structure 190D. In some embodiments, this step first exposes the source/drain epitaxial structures 190S/190D in the front side ILD layer 210 and CESL 200 by suitable photolithography and etching techniques to form source/drain contact openings. Subsequently, the step of forming the source/drain contacts will deposit one or more metallic materials (eg, tungsten, cobalt, copper, the like, or combinations thereof) by suitable deposition techniques (eg, CVD, PVD, ALD, its like or a combination thereof) to fill the source/drain contact openings, followed by a CMP process to remove excess metal material outside the source/drain contact openings while leaving the source/drain contact openings The metal material in the pole contacts serves as the source/drain contacts 230 and 240 .

FIGS. 15A-15C illustrate the formation of a front-side multilevel interconnect (MLI) structure 250 over substrate 110 . The front-side MLI structure 250 may include a plurality of front-side metallization layers 252 . The number of front-side metallization layers 252 may vary according to the design characteristics of the integrated circuit structure 100 . For simplicity, only two front side metallization layers 252 are shown in FIGS. 15A to 15C. Each front side metallization layer 252 includes a first front side intermetal dielectric (IMD) layer 253 and a second front side IMD layer 254 . The second front side IMD layer 254 is formed over the corresponding first front side IMD layer 253 . Front side metallization layer 252 includes one or more horizontally oriented interconnects, such as front side metal lines 255, respectively extending horizontally or laterally in second front side IMD layer 254 and vertically oriented interconnects, such as front side metal vias 256, respectively vertical Extends in the first front side IMD layer 253 .

In some embodiments, the bottom-most front-side metallization layer 252 has front-side metal vias 256 therein and is connected to the drain contact 240 to form an electrical connection with the drain epitaxial structure 190D. In some embodiments, the bottommost front side metallization layer 252 does not have metal vias, which are connected to the source contact 230 . Instead, the source epitaxial structure 190S will be electrically connected to the backside vias formed later.

The front side metal lines 255 and the front side metal vias 256 may be formed using, for example, a single damascene process, a dual damascene process, the like, or a combination thereof. In some embodiments, the front-side IMD layers 253, 254 may include a low-k dielectric material having a k value, eg, below about 4.0 or even 2.0, disposed between the conductive features. In some embodiments, the front side IMD layers 253, 254 may be made of, for example, phosphosilicate glass (PSG), borophosphosilicate glass (BPSG), fused silica glass (FSG) ), _SiOxCy , _spin -on glass, spin-on polymer, silicon oxide, silicon oxynitride, combinations thereof, or the like, by any suitable method, such as spin coating, chemical vapor deposition (CVD), plasma Enhanced CVD (plasma-enhanced CVD, PECVD) or the like is made. Front side metal lines 255 and front side metal vias 256 may include copper, aluminum, tungsten, combinations thereof, or the like. In some embodiments, the front side metal lines 255 and the front side metal vias 256 may further have one or more barrier/adhesion layers (not shown) to protect the corresponding front side IMD layers 253, 254 from metal diffusion (eg, copper diffusion) and metal poisoning. One or more barrier/adhesion layers may comprise titanium, titanium nitride, tantalum, tantalum nitride or the like and may be formed using physical vapor deposition (PVD), CVD, ALD or the like .

According to FIGS. 16A-16C , the carrier substrate 260 is connected to the front-side MLI structure 250 according to some embodiments of the present disclosure. The carrier substrate 260 may be silicon, doped or undoped, or may contain other semiconductor materials, such as germanium, semiconductor compounds, or combinations thereof. The carrier substrate 260 may provide structural support on the backside of the integrated circuit structure 100 for subsequent processing and, in some embodiments, may remain in the final product. In some other embodiments, the carrier substrate 260 may be removed after subsequent backside processing of the integrated circuit structure 100 is completed. In some embodiments, the carrier substrate 260 is connected to the topmost dielectric layer of the MLI structure 250 by, for example, fusion bonding. After the carrier substrate 260 is connected to the front MLI structure 250 , the integrated circuit structure 100 is turned back and forth so that the back surface of the substrate 110 faces upward, as shown in FIGS. 17A to 17C .

Next, as shown in FIGS. 18A to 18C , the substrate 110 is thinned to expose the sacrificial epitaxial plugs 180 . In some embodiments, the thinning step is accomplished by a CMP process, a polishing process, or the like. After the thinning step is complete, the substrate portion 112 is left to cover the backside of the drain epitaxial structure 190D.

Next, as shown in FIGS. 19A to 19C, the substrate portion 112 is removed. In some embodiments, the Si substrate portion 112 is removed by a selective etch process that has a faster etch rate when etching Si compared to etching the SiGe sacrificial epitaxial plug 180 . In some embodiments, the selective etching process for selectively removing Si substrates may utilize wet etching solutions such as tetramethylamine hydroxide (TMAH), potassium hydroxide (KOH), _NH4OH , and the like or a wet etching process of its combination. The wet etch process eventually results in opening O4 being formed in STI structure 140 and exposing the backside of drain epitaxial structure 190D, while sacrificial epitaxial plug 180 is left in STI structure 140 and protrudes from source epitaxial structure 190S.

FIGS. 20A-20C illustrate the formation of the backside dielectric layer 270 in the opening O4 in the STI structure 140 and which laterally surrounds the sacrificial epitaxial plug 180 . In some embodiments, the steps of FIGS. 20A-20C first deposit the dielectric material of the backside dielectric layer 270 to overfill the opening O4 in the STI structure 140 by a suitable deposition technique such as CVD. Subsequently, the deposited dielectric material is thinned by using, for example, an etch-back process, a CMP process, or the like, until the sacrificial epitaxial plug 180 is exposed. Dielectric layer 270 is referred to herein as a "rear side" dielectric layer because it is formed on the rear side of the multi-gate transistor corresponding to the front side of the multi-gate transistor, replacing gate 220 at the rear side by the source. The pole/drain regions 190S/190D protrude.

In some embodiments, the backside dielectric layer 270 includes a material such as tetraethylorthosilicate (TEOS) oxide, undoped silica glass, or doped silica such as borophosphosilicate glass glass, BPSG), fused silica glass fused silica glass (FSG), phosphosilicate glass (PSG), boron doped silicon glass (BSG) and/or other suitable dielectric materials. In some embodiments, the backside dielectric layer 270 has the same material as the frontside ILD layer 210 .

Next, as shown in FIGS. 21A to 21C , the sacrificial epitaxial plug 180 is removed to form a backside via opening O5 extending from the backside dielectric layer 270 to expose the backside of the source epitaxial structure 190S side. In some embodiments, the sacrificial epitaxial plug 180 is removed using a selective etch that has a faster etch rate in etching the SiGe sacrificial epitaxial plug 180 than etching the dielectric material of the backside dielectric layer 270 . In other words, the selective etch process utilizes an etchant that attacks both SiGe and backside dielectric layer 270 more strongly. Therefore, after the selective etching process is completed, the backside drain epitaxial structure 190D is retained where the backside dielectric layer 270 is covered. By way of example and not limitation of the present disclosure, the sacrificial epitaxial plug 180 is etched by selective wet etching such as APM (eg, a mixture of ammonium hydroxide-ammonia peroxide-water), which is compared to etching dielectrics. Material is removed at a faster etch rate when etching SiGe.

In the depicted embodiment, the backside of the source epitaxial structure 190S is recessed by selective etching of SiGe. In this case, the first epitaxial layer 192 of the source epitaxial structure 190S can be etched through the bottom of the backside via opening O5, so that the second epitaxial layer 194 (compared to the first epitaxial layer 192) with higher Ge% or P%) can be exposed at the bottom of the backside via opening O5.

FIGS. 22A-22C illustrate the formation of an epitaxial regrowth layer 280 over the backside of the source epitaxial structure 190S. The epitaxial regrowth structure 280 may be formed by performing a regrowth process to provide epitaxial material epitaxial on the backside of the source epitaxial structure 190S. During the epitaxial growth process, the internal spacers 170 , the fin spacers 164 , the backside dielectric layer 270 and/or the STI structure 140 confine the epitaxial regrowth layer 280 to the backside through the opening O5 . Suitable epitaxy processes include CVD deposition techniques (eg, vapor-phase epitaxy (VPE) and/or ultra-high vacuum CVD (UHV-CVD)), molecular beam epitaxy, and/or other suitable processes. The epitaxial growth process may utilize gaseous and/or liquid precursors that interact with compounds of the semiconductor material of the source epitaxial structure 190S. The backside of the drain epitaxial structure 190D does not have any epitaxial regrowth layer because it is covered by the backside dielectric layer 270 during the epitaxial growth process.

In some embodiments, the epitaxial regrowth layer 280 may include Ge, Si, GaAs, AlGaAs, SiGe, GaAsP, SiP, or other suitable materials. The epitaxial regrown layer 280 may include p-type dopants such as boron or BF ₂ , n-type dopants such as phosphorus or arsenic and/or other suitable dopants by introducing dopant species during the epitaxial process. Impurities including combinations thereof are doped in situ. If the epitaxial regrowth layer 280 is not doped in-situ, an implantation process (ie, an interface implantation process) is performed to dope the epitaxial regrowth layer 280 . In some exemplary embodiments, epitaxial regrowth layer 280 includes SiP in NFET devices, while GeSnB and/or SiGeSnB are included in PFET devices.

In some embodiments, the epitaxial regrowth layer 280 and the source epitaxy The crystal structure 190S is formed of the same material. For example, epitaxial regrowth layer 280 and source epitaxial structure 190S in a PFET device include GeSnB and/or SiGeSnB, while epitaxial regrowth layer 280 and source epitaxial structure 190S include SiP. In some embodiments, the epitaxial regrowth layer 280 may have a difference from the first epitaxial layer 192 and the second epitaxial layer 194 by at least one of germanium atomic percent (Ge %) or phosphorus concentration (P %) .

Taking a PFET device as an example, the epitaxial regrowth layer 280 has a higher atomic percentage of germanium than the first epitaxial layer 192, which helps to reduce the backside vias formed between the epitaxial regrowth layer 280 and the subsequent formation source contact resistance between. By way of example and not limitation of the present disclosure, the ratio of the germanium atomic percentage of the epitaxial regrowth layer 280 to the first epitaxial layer 192 is greater than 1:1. In some embodiments, the germanium atomic percentage of the epitaxial regrowth layer 280 is also greater than that of the second epitaxial layer 194 . By way of example and not limitation of the present disclosure, the germanium atomic percent of the epitaxial regrowth layer 280 is in the range of about 20% to about 70%. In some embodiments, the epitaxial regrowth layer 280 has a gradient distribution of atomic percent germanium. For example, the germanium atomic percentage of the epitaxial regrowth layer 280 increases as the distance from the source epitaxial structure 190S increases, and the maximum germanium atomic percentage of the epitaxial regrowth layer 280 is greater than that of the first epitaxial layer 192 and/or or the second epitaxial layer 194 .

On the other hand, in some embodiments of the NFET device, the epitaxial regrown layer 280 has a higher phosphorous concentration than the first epitaxial layer 192, which helps reduce side pass through the epitaxial regrown layer 280 and subsequent formation The source contact resistance of the hole. By way of example and not limitation of the present disclosure, the phosphorus concentration ratio of the epitaxial regrowth layer 280 to the first epitaxial layer 192 is greater than 1:1. In some embodiments, the phosphorus concentration of the epitaxial regrowth layer 280 is also greater than that of the second epitaxial layer 194 . By way of example and not limitation of the present disclosure, the phosphorus concentration of the epitaxial regrowth layer 280 is in the range of about 1×10 ²¹ cm ⁻³ to about 5×10 ²¹ cm ⁻³ . In some embodiments, the epitaxial regrowth layer 280 has a gradient profile of phosphorus concentration. For example, the phosphorus concentration of the epitaxial regrowth layer 280 increases as the distance from the source epitaxial structure 190S increases, and the maximum phosphorus concentration of the epitaxial regrowth layer 280 is greater than that of the first epitaxial layer 192 and/or the second epitaxial structure 190S. Two epitaxial layers 194 .

In some embodiments, the growth temperature of the epitaxial regrowth layer 280 is different from the source/drain epitaxial structures 190S/190D. For example, the growth temperature of the epitaxial regrowth layer 280 may be lower than the growth temperature of the source/drain epitaxial structures 190S/190D, so as to reduce the source/drain epitaxial structures 190S/190D caused by high temperature growth. Negative impact. By way of example and not limitation of the present disclosure, the growth temperature of the epitaxial regrowth layer 280 is lower than the source/drain epitaxial structure 190S/ 190D growth temperature.

In some embodiments, after epitaxial growth is complete, an annealing process may be performed to activate p-type dopants or n-type dopants in the epitaxial regrowth layer 280 . The annealing process may be, for example, a rapid thermal anneal (RTA), laser annealing, millisecond thermal annealing (MTA) process, or the like.

Figures 23A-23D illustrate via spacer 290 liners The side wall of the rear side through hole opening O5. In some embodiments, a layer of backside spacer material is first deposited over carrier volume 260 . The via spacer material layer may be a conformal layer that is subsequently etched to form via spacers 290 . In the illustrated embodiment, a layer of via spacer material is conformally deposited to line the bottom and sidewalls of the backside via opening O5. By way of example and not limitation of the present disclosure, the via spacer material layer may be deposited over the carrier substrate 260 by depositing a dielectric material by a CVD process, a subatmospheric CVD (SACVD) process, flowable. A CVD process, an ALD process, a physical vapor deposition (PVD) process, or other suitable processes are formed. An anisotropic etch process is then performed on the deposited via spacer material layer to remove the via spacer material layer from the backside surface of the epitaxial regrowth layer 280 and the backside surface of the backside dielectric layer 270. The horizontal part, while leaving vertical and inclined parts on the vertical and inclined side walls of the rear side through the opening O5. The remainder of these via spacer material layers in backside via opening O5 are collectively referred to as via spacer 290 . The reason for this is that the via spacer 290 is formed after the epitaxial regrowth layer 280 is formed, and the via spacer 290 is spaced apart from the source epitaxial structure 190S by the epitaxial regrowth layer 280 .

The vertical portion separating the via spacer layer 290 is defined from the cross-sectional view of FIG. 23A, and the inclined portion separating the via spacer layer 290 is defined from the cross-sectional view of FIG. 23B. For example, via O5 is square/rectangular when viewed from above the rear side (see Figure 23D), then when via spacer 290 is depicted in cross-section, the vertical portion of via spacer 290 and the sloped portion refers to the present of a single continuous via spacer 290 body.

Via spacer 290 may include one or more dielectric materials different from backside dielectric material layer 270 . For example, in some embodiments, the backside dielectric material layer 270 is a silicon oxide layer, and the via spacer 290 includes silicon nitride, silicon carbide, silicon oxynitride, SiCN, silicon oxycarbide, and/or combinations thereof . The material differences result in different etch selectivities between via spacers 290 and backside dielectric material layer 270, and thus via spacers 290 can protect backside via openings O5 from being used by, for example, etching processes for Unexpected expansion due to the subsequent silicidation process, which will be discussed in more detail later.

24A to 24D illustrate the formation of the rear through hole 300 in the rear opening O5. In some backside via-forming embodiments, one or more metal layers are first deposited by a suitable deposition process, such as CVD, PVD, ALD, the like, or a combination thereof to overfill the backside via opening O5 . Subsequently, a CMP process is performed to thin the one or more metal layers until the backside dielectric material layer 270 is exposed, while leaving portions of the one or more metal layers in the backside via opening O5 as the backside Via 300. In some embodiments, the one or more metal layers include, for example, tungsten, cobalt, copper, titanium nitride, tantalum nitride, the like, or combinations thereof.

FIG. 25 shows that the backside MLI structure 310 is formed over the backside via 600 and the backside dielectric layer 270 . The multilayer interconnect MLI structure 310 may include a bottommost backside metallization layer 311 (also referred to as a backside M0 layer) and a plurality of upper backside metallization layers 312 overlying the bottommost backside metallization layer 311 . The number of upper backside metallization layers 312 can be It varies according to the design characteristics of the integrated circuit structure 100 . For simplicity, only two backside metallization layers 312 (also referred to as backside M1 and backside M2 layers) are shown in FIG. 25 .

Bottom-most backside metallization layer 311 includes backside IMD layer 313 over backside dielectric layer 270 and one or more horizontal internal interconnects, such as backside metal lines 315 , correspondingly in backside IMD layer 313 Extend horizontally or laterally. The metal lines 315 in the bottommost backside metallization layer 311 are power lines that extend across and are connected to one or more backside vias 300 to electrically connect one or more source epitaxial structures 190S. Since the power supply lines are formed in the rear-side MLI structure 310 , more wiring space can be provided to the integrated circuit element 100 .

Each upper backside metallization layer (eg, backside M1 and M2 layers) 312 includes a first backside inter-metal dielectric (IMD) layer 314 and a second backside IMD layer 316 . The second backside IMD layers 316 are formed over the corresponding first backside IMD layers 314 . The upper backside metallization layer 312 includes one or more horizontal internal interconnects, such as backside metal lines 317, extending horizontally or laterally in the second backside IMD layer 316, respectively, and vertical internal interconnects , such as backside metal vias 318 , correspondingly extend vertically in the first backside IMD layer 314 . In some embodiments, the backside metal via 318 has a tapered profile with a decreasing width as the distance from the backside dielectric layer 270 decreases, which results from the A natural consequence of the via openings etched in the backside IMD layer 314 after flipping 100 upside down.

FIG. 26 is a flowchart illustrating a method M1 of forming an integrated circuit structure according to some embodiments of the present disclosure. Although method M1 is shown and/or described as a series of acts or activities, this method is not intended to limit the disclosure to the order or acts shown. Thus, in some embodiments, acts may be performed in a different order than shown. Further, in some embodiments, a depicted act or activity may be subdivided into multiple acts or activities, which may be performed at other times or concurrently with other acts or sub-acts. In some embodiments, some illustrated acts or activities may be omitted and other non-illustrated acts or activities may be included.

At block S101, transistors are formed over the substrate on the front side. 1 to 14C are schematic diagrams and cross-sectional views illustrating the formation of GAA transistors according to some embodiments of block S101.

At block S102, a front-side MLI structure is formed over the transistor. 15A to 15C are cross-sectional views illustrating some embodiments according to block S101.

At block S103, the carrier substrate is attached to the front-side MLI structure. 16A to 16C are cross-sectional views illustrating some embodiments according to block S103.

At block S104, the substrate is turned over so that the rear side of the substrate faces upward. 17A to 17C are cross-sectional views illustrating some embodiments according to block S104.

At block S105, the substrate is removed. FIGS. 18A to 18C and FIGS. 19A to 19C are cross-sectional views illustrating some embodiments according to block S105 .

At block S106, a backside dielectric layer is formed over the backside of the transistor. FIGS. 20A to 20C are cross-sectional views illustrating some embodiments according to block S106.

At block S107, backside via openings are formed in the backside dielectric layer and expose the backside of the source epitaxial structure of the transistor. 21A to 21C are cross-sectional views illustrating some embodiments according to block S107.

At block S108, an epitaxial regrowth layer is formed over the backside of the source epitaxial structure. 22A to 22C are cross-sectional views illustrating some embodiments according to block S108.

At block S109, via spacers are formed to line the sidewalls of the backside via openings and over the epitaxial regrowth layer. 23A to 23D are cross-sectional views illustrating some embodiments according to block S109.

At block S110, backside vias are formed in the backside via openings. 24A to 24C are cross-sectional views illustrating some embodiments according to block S110.

At block S111, backside MLI structures are formed over the backside vias. FIG. 25 is a cross-sectional view illustrating some embodiments according to block S111.

FIGS. 27A-31 are cross-sectional views illustrating stages of intermediate steps in the formation of an integrated circuit having a multi-gate device in accordance with some embodiments of the present disclosure. The steps shown in FIGS. 27A to 31 also mirror the steps shown in FIG. 32 . It should be understood that additional operations may be performed before, during, or during the fabrication of those depicted in FIGS. are then provided, and some of the operations described below may be replaced or eliminated in additional methods of some embodiments. The order of operations/makes is interchangeable.

FIGS. 27A , 28A, 29A, 30A and 31 are cross-sections taken along a first secant line (eg, secant line X-X in FIG. 4A ) at an intermediate stage of manufacturing the integrated circuit structure 100 a Figure, which is along the longitudinal direction of the channel. FIGS. 27B, 28B, 29B, and 30B are cross-sectional views taken along a second secant line (eg, secant line Y1-Y1 in FIG. 4A) in an intermediate stage of manufacturing the integrated circuit structure 100a, It is in the source region and perpendicular to the longitudinal direction of the channel. FIGS. 27C, 28C, 29C, and 30C are cross-sectional views taken along a third secant line (eg, secant line Y2-Y2 in FIG. 4A) in an intermediate stage of manufacturing the integrated circuit structure 100a, It is in the drain region and perpendicular to the longitudinal direction of the channel. 28D is a top view of an intermediate stage of fabricating the integrated circuit structure 100a in accordance with some embodiments of the present disclosure.

Figures 27A to 27C illustrate some embodiments of subsequent steps according to the steps of Figures 20A to 20C. In detail, after the backside dielectric layer 270 is formed as described above in FIGS. 20A-20C, the sacrificial epitaxial plug 180 is removed by a suitable etching process to form the backside via opening O5' . The final structure is shown in Figures 27A to 27C. The details of the formation of the backside via opening O5' are discussed above with respect to the backside via opening O5' in Figures 21A to 21C, respectively, and are therefore not repeated here for the sake of simplicity.

Next, via spacers 290' are formed to open vias on the rear side Sidewall lining of O5', as depicted in Figures 28A-28D. Because the via spacer 290' is formed prior to forming the epitaxial regrowth structure layer over the backside of the source epitaxial structure 190S, the via spacer 290' connects the backside of the source epitaxial structure 190S. Details of the material and formation of via spacer 260' are discussed above with via spacer 290 depicted in FIGS. 23A-23D, respectively, and are therefore not repeated here for simplicity.

After via spacers 290' are formed to line the sidewalls of backside via opening O5', epitaxial regrowth layer 280' is in backside via opening O5', as shown in Figures 29A-29C shown. As such, the via spacers 290' may confine the epitaxial growth layer 280' to desired areas in the backside via O5'. In some embodiments, via spacer 290' laterally surrounds epitaxial regrowth layer 280'. Details of the material and formation of the epitaxial regrown layer 280' are discussed previously in the epitaxial regrown layer 280 according to Figures 22A to 22C, respectively, and are therefore not repeated here for the sake of simplicity.

Next, the backside via 300 is formed to fill the remaining portion of the backside via opening O5', as shown in FIGS. 30A to 30C. Subsequently, a backside MLI structure 310 is formed over the backside via 300 , as shown in FIG. 31 . Details of the material and formation of the backside vias 300 and the backside MLI structures 310 are discussed above in FIGS. 24A-24C and 25, respectively, and are therefore not repeated here for simplicity.

FIG. 32 is a diagram illustrating the formation according to some embodiments of the present disclosure. The flow chart of the method M2 of the integrated circuit structure. Although method M2 is shown and/or described as a series of acts or activities, this method is not intended to limit the disclosure to the order or acts shown. Thus, in some embodiments, acts may be performed in a different order than shown and/or may be performed concurrently. Further, in some embodiments, a depicted act or activity may be subdivided into multiple acts or activities, which may be performed at other times or concurrently with other acts or sub-acts. In some embodiments, some illustrated acts or activities may be omitted and other non-illustrated acts or activities may be included.

The method M2 may branch from the previously described block S107 of the method M1, and thus the method M2 may include all of the previously described blocks of the method M1 (eg blocks S101 to S106). 27A to 27C illustrate cross-sectional views according to some embodiments of block S107.

Block S201 of method M2, via spacers are formed to line the sidewalls of the backside via openings. 28A to 28C illustrate cross-sectional views according to some embodiments of block S201.

Block S202 of method M2, an epitaxial regrowth layer is formed over the backside of the source epitaxial structure and laterally surrounded by via spacers. 29A to 29C illustrate cross-sectional views according to some embodiments of block S202.

Block S203 of method M2, backside vias are formed in backside via openings. 30A to 30C illustrate cross-sectional views according to some embodiments of block S203.

At block S204 of method M2, the backside MLI structure is formed in above the rear through hole. FIG. 31 shows a cross-sectional view according to some embodiments of block S204.

FIGS. 33A-36 are cross-sectional views illustrating stages of intermediate steps in the formation of an integrated circuit having a multi-gate device in accordance with some embodiments of the present disclosure. The steps shown in FIGS. 33A-36 also mirror the steps shown in FIG. 37 . It should be understood that additional operations may be provided before, during, or after the fabrication depicted in Figures 33A-36, and that some of the operations described below may be substituted in additional methods of some embodiments or eliminated. The order of operations/makes is interchangeable.

FIGS. 33A, 34A, 35A, and 36 are cross-sectional views taken along a first secant line (eg, secant line X-X in FIG. 4A) at an intermediate stage of manufacturing the integrated circuit structure 100b, the longitudinal direction of the channel. 33B, 34B, and 35B are cross-sectional views along a second secant line (eg, secant line Y1-Y1 in area and perpendicular to the longitudinal direction of the channel. FIGS. 33C , 34C and 35C are cross-sectional views along a third secant line (eg, secant line Y2-Y2 in FIG. 4A ) at an intermediate stage of manufacturing the integrated circuit structure 100b, which is at the drain electrode area and perpendicular to the longitudinal direction of the channel.

Figures 33A-33C illustrate some embodiments of subsequent steps to the steps shown in Figures 29A-29C. In detail, after the epitaxial regrowth layer 280' is formed at the backside via opening O5' and is laterally surrounded by the bald spacer 290', the metal layer 320 is formed by a suitable Chen-based techniques such as CVD, PVD, ALD, the like, or combinations thereof are formed over carrier substrate 260 . The metal layer 320 includes a metal capable of reacting with the semiconductor material of the bottom epitaxial regrown layer 280' to form silicide regions in the epitaxial regrown layer 280' in a subsequent process. For example, the metal layer 320 includes nickel, cobalt, titanium, tantalum, platinum, tungsten, other noble metals, other refractory metals, rare earth metals, or alloys thereof.

After depositing metal layer 320, an annealing process is performed such that metal layer 320 reacts with silicon (and germanium, if present) in epitaxial regrowth layer 280' to form a metal silicide in epitaxial regrowth layer 280' (and germanide, if germanium is present in epitaxial regrowth layer 280') region 330, and unreacted portions of metal layer 320 are removed by an etching process. The final structure is shown in Figures 34A to 34C. In some embodiments, the silicide region 330 includes, for example, titanium silicide, cobalt silicide, nickel silicide, the like, or combinations thereof. As discussed above, the via spacers 290 and the backside dielectric layer 270 have different etch selectivities, and thus the etch process that removes the unreacted metal layer 320 can utilize a slower etch through than etching the backside dielectric layer 270 An etchant for hole spacers 290 that prevents unintentional expansion of backside via openings O5 ′ when removing unreacted metal layer 320 . In other words, the via spacer 290' has a higher etch resistance to the etch process for removing the unreacted metal layer 320 than the backside dielectric layer 270.

Next, the backside via 300 is formed to fill the remaining portion of the backside via opening O5', as shown in FIGS. 35A-35C. Subsequently, the rear side MLI structure 310 is formed over the rear side via hole 300 , as shown in FIG. 36 . Between the rear side through hole 300 and the rear side MLI structure 310 Details of materials and fabrication are discussed previously in accordance with Figures 24A to 24C and 25, respectively, and are therefore not repeated here for the sake of simplicity. As shown in FIG. 36, silicide region 330 is located between epitaxial regrowth layer 280' and backside via 300, and via spacer 290' extends through backside dielectric layer 270 and laterally surrounds the silicide Object area 330.

FIG. 37 is a flowchart illustrating a method M3 of forming an integrated circuit structure according to some embodiments of the present disclosure. Although method M3 is shown and/or described as a series of acts or activities, this method is not intended to limit the disclosure to the order or acts shown. Thus, in some embodiments, acts may be performed in a different order than shown and/or may be performed concurrently. Further, in some embodiments, a depicted act or activity may be subdivided into multiple acts or activities, which may be performed at other times or concurrently with other acts or sub-acts. In some embodiments, some illustrated acts or activities may be omitted and other non-illustrated acts or activities may be included.

Method M3 may branch from block S202 of method M2 described above, and thus method M3 may include all of the blocks of method M2 previously described (eg, block S107 and block S201 of method M2). 29A to 29C illustrate cross-sectional views according to some embodiments of block S202.

At block S301 of method M3, a metal layer is formed in the epitaxial regrowth layer. 33A to 33C illustrate cross-sectional views according to some embodiments of block S301.

At block S302 of method M3, the metal layer is reacted with the epitaxial regrowth layer to form a silicide region in the epitaxial regrowth layer. At block S303 of method M3, the unreacted metal layer is removed. 34A-34C illustrate cross-sectional views according to some embodiments of blocks S302 and S303.

Block S304 of method M3, a backside via is formed in the backside via opening and over the silicide region. 35A-35C illustrate cross-sectional views according to some embodiments of block S304.

At block S305 of method M3, a backside MLI structure is formed over the backside via. FIG. 36 shows a cross-sectional view according to some embodiments of block S305.

FIGS. 38A-41 are cross-sectional views illustrating stages of intermediate steps in the formation of an integrated circuit with a multi-gate device in accordance with some embodiments of the present disclosure. The steps shown in FIGS. 38A to 41 also mirror the steps shown in FIG. 42 . It should be understood that additional operations may be provided before, during, or after the fabrication depicted in Figures 38A-41, and that some of the operations described below may be substituted in additional methods of some embodiments or eliminated. The order of operations/makes is interchangeable.

FIGS. 38A , 39A, 40A and 41 are cross-sectional views taken along a first secant line (eg, secant line X-X in FIG. 4A ) at an intermediate stage of manufacturing the integrated circuit structure 100 c . the longitudinal direction of the channel. FIGS. 38B , 39B and 40B are cross-sectional views along a second secant line (eg, secant line Y1-Y1 in FIG. 4A ) at an intermediate stage of manufacturing the integrated circuit structure 100c, which is at the source area and vertical channel direction. FIGS. 38C , 39C and 40C are cross-sectional views along a third secant line (eg, secant line Y2-Y2 in FIG. 4A ) at an intermediate stage of manufacturing the integrated circuit structure 100c, which is at the drain electrode area and perpendicular to the longitudinal direction of the channel.

Figures 38A-38C illustrate some embodiments of subsequent steps to the steps shown in Figures 23A-23C. In detail, after via spacer 290 is formed in backside via opening O5 and over epitaxial regrowth layer 280, metal layer 320' is deposited by a suitable deposition technique, such as CVD, PVD, ALD, the like Either or a combination thereof are formed over the carrier substrate 260 . The metal layer 320' includes a metal capable of reacting with the semiconductor material of the bottom epitaxial regrowth layer 280 to form silicide regions in the epitaxial regrowth layer 280 in a subsequent process. For example, the metal layer 320' includes nickel, cobalt, titanium, tantalum, platinum, tungsten, other noble metals, other refractory metals, rare earth metals, or alloys thereof.

After depositing the metal layer 320 ′, an annealing process is performed to allow the metal layer 320 ′ to react with the silicon (and germanium, if present) in the epitaxial regrowth layer 280 to form a metal silicide in the epitaxial regrowth layer 280 (and germanide, if germanium is present in epitaxial regrowth layer 280) region 330', and unreacted portions of metal layer 320' are removed by an etching process. The final structure is shown in Figures 39A to 39C. In the depicted embodiment, silicide region 330' is embedded in epitaxial regrowth layer 280. In detail, the peripheral region of the epitaxial regrowth layer 280 is not converted to silicide because the epitaxial regrowth layer 280 is covered by the via spacer 290 during the silicidation process. Instead, the epitaxial regrowth layer The peripheral region 280 laterally surrounds the silicide region 330'. In some embodiments, the silicide region 330' includes, for example, titanium silicide, cobalt silicide, nickel silicide, the like, or combinations thereof. As discussed above, the via spacers 290 and the backside dielectric layer 270 have different etch selectivities, and thus the etch process that removes the unreacted metal layer 320 can utilize a slower etch through than etching the backside dielectric layer 270 An etchant for hole spacer 290 that prevents unintentional expansion of backside via opening O5 when removing unreacted metal layer 320'.

Next, the backside via 300 is formed to fill the remaining portion of the backside via opening O5 , as shown in FIGS. 40A to 40C . Subsequently, the rear side MLI structure 310 is formed over the rear side via hole 310 as shown in FIG. 41 . Details of the material and formation of the backside vias 300 and the backside MLI structures 310 are discussed above in FIGS. 24A-24C and 25, respectively, and are therefore not repeated here for simplicity.

FIG. 42 is a flowchart illustrating a method M4 of forming an integrated circuit structure according to some embodiments of the present disclosure. Although method M4 is shown and/or described as a series of acts or activities, this method is not intended to limit the disclosure to the order or acts shown. Thus, in some embodiments, acts may be performed in a different order than shown and/or may be performed concurrently. Further, in some embodiments, a depicted act or activity may be subdivided into multiple acts or activities, which may be performed at other times or concurrently with other acts or sub-acts. In some embodiments, some illustrated acts or activities may be omitted and others not illustrated Actions can be included.

The method M4 may branch from the previously described block S109 of the method M1, and thus the method M4 may include all of the previously described blocks of the method M1 (eg, blocks S107-S108). FIGS. 23A to 23D illustrate cross-sectional and top views according to some embodiments of block S109.

At block S401 of method M4, a metal layer is formed over the epitaxial regrowth layer. 38A to 38C illustrate cross-sectional views according to some embodiments of block S401.

At block S402 of method M4, the metal layer is reacted with the epitaxial regrowth layer to form a silicide region in the epitaxial regrowth layer. At block S403 of method M4, the unreacted metal layer is removed. 39A-39C illustrate cross-sectional views according to some embodiments of blocks S402 and S403.

Block S404 of method M4, a backside via is formed in the backside via opening and over the silicide region. Figures 40A-40C illustrate cross-sectional views according to some embodiments of block S404.

At block S405 of method M4, a backside MLI structure is formed over the backside via. FIG. 41 shows a cross-sectional view according to some embodiments of block S405.

From the above discussion, it can be appreciated that the present disclosure provides the following advantages. It should be understood, however, that other embodiments may provide additional additional advantages, and that not all advantages are necessarily disclosed herein, and no particular advantage is required for all embodiments. One advantage is that backside vias and backside metal lines (eg, backside power lines) can be formed on the backside of the transistor, which allows more wiring space and thus increases wiring density. another The advantage is that the epitaxial regrowth layer formed on the back side of the source epitaxial structure undergoes less thermal process than the source epitaxial structure, so that the epitaxial regrowth layer can have better quality than the source epitaxial structure. It helps reduce the contact resistance between the backside via and the epitaxial regrowth layer.

In some embodiments, an integrated circuit (IC) structure includes a gate structure, a source epitaxial structure, a drain epitaxial structure, a front side internal interconnect structure, a back side dielectric layer, and an epitaxial regrowth layer and rear through holes. The source epitaxial structure and the drain epitaxial structure are correspondingly located on the corresponding side surfaces of the gate structure. The front-side internal interconnect structure is above the front-side source epitaxial structure and the front-side drain epitaxial structure. The backside dielectric layer is over the backside source epitaxial structure and the backside drain epitaxial structure. The epitaxial regrowth layer is over the backside of the first of the source epitaxial structure and the drain epitaxial structure. The backside vias extend through the backside dielectric layer and overlap the epitaxial regrowth layer. In some embodiments, the integrated circuit structure further includes via spacers extending through the backside dielectric layer and laterally surrounding the backside vias. In some embodiments, the via spacers are separated from the first of the source epitaxial structures and the first of the drain epitaxial structures by epitaxial regrowth layers. In some embodiments, the via spacer is connected to the backside of the first of the source epitaxial structure and the drain epitaxial structure. In some embodiments, the via spacers also laterally surround the epitaxial regrowth layer. In some embodiments, the integrated circuit structure further includes a silicide region between the epitaxial regrowth layer and the backside via. In some embodiments, the integrated circuit structure further includes via spacers extending through the backside dielectric layer and laterally surrounding the silicide region. In some embodiments, the silicide regions are embedded in the epitaxial regrowth layer. In some embodiments, the source The first of the epitaxial structure and the drain epitaxial structure is the source epitaxial structure. In some embodiments, the rear side of the second one of the source epitaxial structure and the drain epitaxial structure does not have an epitaxial regrowth layer. In some embodiments, the backside of the second one of the source epitaxial structure and the drain epitaxial structure is a drain epitaxial structure.

In some embodiments, the IC structure includes a plurality of channel layers, gate structures, source epitaxial structures, drain epitaxial structures, front side internal interconnect structures, back side vias, and epitaxial regrowth layers. A plurality of channel layers are arranged one after the other in a spaced manner. A gate structure surrounds each channel layer. The source epitaxial structure and the drain epitaxial structure are respectively located on opposite end faces of the channel layer. The front side interconnection structure is located above the front side of the source epitaxial structure and the front side of the drain epitaxial structure. The backside via is located above the backside of the first one of the source epitaxial structure and the drain epitaxial structure. The epitaxial regrowth layer is located between the backside through hole and the first one of the source epitaxial structure and the drain epitaxial structure. In some embodiments, the epitaxial regrowth layer has a maximum atomic percent germanium that is greater than the maximum atomic percent germanium of the first of the source epitaxial structure and the drain epitaxial structure. In some embodiments, the epitaxial regrowth layer has a maximum phosphorus concentration that is greater than the maximum phosphorus concentration of the first of the source epitaxial structure and the drain epitaxial structure. In some embodiments, the integrated circuit structure further includes a backside dielectric layer extending through the backside via, the backside dielectric layer and the second one of the source epitaxial structure and the drain epitaxial structure. side contact. In some embodiments, the integrated circuit structure further includes via spacers to laterally separate the backside vias and the backside dielectric layer.

In some embodiments, a method includes forming a transistor over a substrate, the transistor including a first source/drain epitaxial structure, a second source/drain epitaxial structure, and laterally positioned on the first source /drain epitaxial structure with gate structure of the second source/drain epitaxial structure; removing at least a portion of the substrate to expose the backside of the transistor; forming a backside dielectric layer on the exposed backside of the transistor; after forming Side vias are opened in the backside dielectric layer to expose the backside of the first source/drain epitaxial structure of the transistor; an epitaxial regrowth layer is formed where the source/drain epitaxial structure of the transistor is exposed and forming a backside via in the backside via opening and over the epitaxial regrowth layer. In some embodiments, the method of forming an integrated circuit structure further includes forming a via spacer lining the plurality of sidewalls of the backside via opening prior to forming the epitaxial growth layer. In some embodiments, the method of forming an integrated circuit structure further includes forming a via spacer lining the plurality of sidewalls of the backside via opening after forming the epitaxial regrowth layer and before forming the backside via. In some embodiments, the method of forming an integrated circuit structure further includes forming a via spacer lining a plurality of sidewalls of the backside via opening and after forming the via spacer, forming a silicide region in the epitaxial regrowth layer .

The foregoing has outlined features of several embodiments so that those skilled in the art may better understand aspects of the disclosure. Those skilled in the art should appreciate that they may readily use the present disclosure as a basis for designing or modifying other processes and structures for carrying out the same purposes and/or achieving the same advantages of the embodiments described herein. Those skilled in the art should also realize that such equivalent constructions do not depart from the spirit and scope of the present disclosure, and that they can make various changes, substitutions, and alterations herein without departing from the spirit and scope of the present disclosure .

100: Integrated Circuit Structure

124: Epitaxial layer, channel layer, nanostructure

162: Spacer

170: Spacer material layer, internal spacer

190S: source epitaxial structure

190D: Drain epitaxial structure

192,194: Epitaxy layer

200: Contact etch stop layer

210: Interlayer dielectric layer

220: Gate structure

222: interface layer

224: Dielectric Layer

226: gate metal layer

230: source contact

240: drain contact

250: Multilayer Interconnect Structure

253: first front side metal dielectric layer

254: Second Front Metal Dielectric Layer

255: Front side metal wire

256: front side metal through hole

260: Carrier substrate

270: Dielectric Layer

280: epitaxial regrowth layer

290: Through Hole Spacer

300: Rear side through hole

310: Multilayer Interconnection Multilayer Interconnection Structure

311: Bottom-most backside metallization

312: Upper backside metallization

313: Backside Intermetal Dielectric Layer

314: first back side intermetal dielectric layer

315: Metal Wire

316: Second rear intermetal dielectric layer

317: rear metal wire

318: Rear side metal through hole

Claims (10)

An integrated circuit structure, comprising: a gate structure; a source epitaxial structure and a drain epitaxial structure, respectively located on opposite sides of the gate structure; a front side interconnection structure, located on the source epitaxial structure a front side of the structure is above a front side of the drain epitaxial structure; a back side dielectric layer is located above a back side of the source epitaxial structure and a back side of the drain epitaxial structure; an epitaxial layer a regrowth layer located at a back side of the first one of the source epitaxial structure and the drain epitaxial structure, wherein the epitaxial regrowth layer faces the source epitaxial structure and the drain epitaxial structure The backside protrusion of the first one of them; and a backside through hole extending through the backside dielectric layer to the epitaxial regrowth layer. The integrated circuit structure of claim 1, further comprising: a via spacer extending through the backside dielectric layer and laterally surrounding the backside via. The integrated circuit structure of claim 1, further comprising: a silicide region located between the epitaxial regrowth layer and the backside via between. The integrated circuit structure of claim 1, wherein the first one of the source epitaxial structure and the drain epitaxial structure is the source epitaxial structure. An integrated circuit structure, comprising: a plurality of channel layers arranged one after another in a separated manner; a gate structure surrounding each of the channel layers; a source epitaxial structure and a drain epitaxial structure, are respectively located on opposite end faces of the channel layers; a front side interconnection structure is located above a front side of the source epitaxial structure and a front side of the drain epitaxial structure; a back side through hole is located on the source epitaxy over a backside of a first one of the crystal structure and the drain epitaxial structure; and an epitaxial regrowth layer located in the backside via and the source epitaxial structure and the drain epitaxial structure Between the first one, the bottom surface of the epitaxial regrowth layer and the bottom surface of the backside through hole are located at different heights. The integrated circuit structure of claim 5, wherein the epitaxial regrowth layer has a maximum germanium atomic percentage greater than a maximum of the first one of the source epitaxial structure and the drain epitaxial structure Atom percent of germanium. The integrated circuit structure of claim 5, wherein the epitaxial regrowth layer has a maximum phosphorus concentration that is greater than a maximum phosphorus concentration of the first one of the source epitaxial structure and the drain epitaxial structure concentration. A method of forming an integrated circuit structure, comprising: forming a transistor over a substrate, the transistor comprising a first source/drain epitaxial structure, a second source/drain epitaxial structure and side grounding a gate structure of the first source/drain epitaxial structure and the second source/drain epitaxial structure; removing at least a portion of the substrate to expose a rear portion of the transistor side; forming a backside dielectric layer on the exposed backside of the transistor; forming a backside via opening in the backside dielectric layer to expose the first source/drain of the transistor a backside of the epitaxial structure; forming an epitaxial regrowth layer over the exposed backside of the first source/drain epitaxial structure of the transistor, wherein the epitaxial regrowth layer faces the first The backside of a source/epitaxial structure protrudes; and a backside via is formed in the backside via opening and over the epitaxial regrowth layer. The method of forming an integrated circuit structure as recited in claim 8, further comprising: forming a via spacer lining a plurality of sidewalls of the backside via opening before forming the epitaxial growth layer. The method of forming an integrated circuit structure as claimed in claim 8, further comprising: after forming the epitaxial regrowth layer and before forming the backside via, forming a via spacer lining the plurality of backside via openings a side wall.

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