TWI779495B - Power converter including switch components having different safe working regions - Google Patents

Abstract

A power converter including switch components having different safe working regions is provided. A first terminal of a first hide-side switch is coupled to a common voltage. A first terminal of a first low-side switch is connected to a second terminal of the first hide-side switch. A second terminal of the first low-side switch is grounded. A first terminal of a second low-side switch is connected to a node between the second terminal of the first hide-side switch and the first terminal of the first low-side switch. A second terminal of the second low-side switch is grounded. A safe operating area of the second low-side switch is larger than a safe operating area of the first low-side switch. After the first the first low-side switch is turned off, the second low-side switch is turned off. Before the first low-side switch is turned on, the second low-side switch is turned on.

Description

Power converters with switching elements with different safe operating areas

The invention relates to a power converter, in particular to a power converter with switching elements of different safe working areas.

Power converters have been widely used in different electronic products to convert electric power for use by the electronic products. When the switching power converter is used as a charger, it is necessary to use multiple transistors as components of the driving circuit, and perform power conversion through switching actions of the transistors.

When the low bridge transistor of a conventional power converter is switched from the on state to the off state, it will experience the Miller plateau as shown in the block A shown in FIG. 7 and FIG. 8 . However, when the low bridge transistor of the conventional power converter is switched from the off state to the on state, it will experience the Miller plateau as shown in box B in FIG. 8 . When going through a period of Miller plateau, the withstand voltage of the lower bridge transistor is the weakest at this time, and it is easy to be damaged due to excessive current.

Similarly, when the upper bridge transistor is switched from the on state to the off state or from the off state to the on state, it will experience a period of Miller flat zone circled by boxes A and B as shown in Figure 9, at this time The withstand voltage of the upper bridge transistor is the weakest. However, due to the energy leakage of the inductor L, the voltage of the second node LX2 will rise to 0.7V, and the cross-voltage between the drain and the source of the high-bridge transistor will be very large, which will cause the high-bridge transistor to be damaged.

In order to be damaged due to excessive current, the transistor of the drive circuit in the power converter needs to have a large layout area to achieve a large on-resistance (Ron), so that the transistor must have a high withstand voltage and be able to withstand large currents. characteristics, but this will lead to a large power loss during the operation of the power converter.

The technical problem to be solved by the present invention is to provide a power converter with switching elements with different safe working areas in view of the deficiencies in the prior art, including a first upper bridge switch, a first lower bridge switch, a second lower bridge switch, an upper bridge drive circuit and lower bridge drive circuit. The first terminal of the first high-bridge switch is coupled to the common voltage. The first end of the first lower bridge switch is connected to the second end of the first upper bridge switch. The second end of the first lower bridge switch is grounded. The first end of the second lower bridge switch is connected to the first node between the second end of the first upper bridge switch and the first end of the first lower bridge switch. The second terminal of the second lower bridge switch is grounded. The first node is grounded through a series circuit of an inductor and a capacitor. The upper bridge drive circuit is connected to the control end of the first upper bridge switch. The high-bridge driving circuit is configured to drive the first high-bridge switch to turn on or off. The lower bridge drive circuit is connected to the control terminal of the first lower bridge switch. The lower bridge driving circuit is configured to drive the first lower bridge switch to turn on or off. The safe working area of the second lower bridge switch is larger than the safe working area of the first lower bridge switch. The first upper bridge switch is complementary to the first lower bridge switch. After the lower bridge driving circuit turns off the first lower bridge switch, the lower bridge driving circuit turns off the second lower bridge switch. Before the lower bridge driving circuit turns on the first lower bridge switch, the lower bridge driving circuit turns on the second lower bridge switch.

In one embodiment, the power converter with switching elements having different safe operating areas further includes resistors connected in parallel with capacitors. The output node between the capacitor and the inductor is the output terminal of the power converter.

In one embodiment, the lower bridge driving circuit includes a first NOR gate, a second NOR gate, a first NOR gate, a second NOR gate, a first AND gate, and a second AND gate. The first input end of the first NOR gate is connected to the control end of the first upper bridge switch. The second input end of the first NOR gate is connected to the output end of the pulse signal generator. The two input terminals of the first AND gate are respectively connected with the output terminal of the first NOR gate and the control terminal of the second lower bridge switch. The output end of the first AND gate is connected to the control end of the first lower bridge switch. The two input terminals of the second NOR gate are respectively connected to the output terminal of the first NOR gate and the control terminal of the first lower bridge switch. The output end of the second inverting OR gate is connected to the input end of the second inverting gate. The output end of the second flyback is connected to the control end of the second lower bridge switch. The input end of the first flyback is connected to the control end of the second lower bridge switch. The two input terminals of the second AND gate are respectively connected to the output terminal of the second NOR gate and the output terminal of the first NOR gate. The input end of the upper bridge driving circuit is connected to the output end of the second AND gate and the output end of the pulse signal generator.

In one embodiment, the power converter having switching elements with different safe operating areas further includes a first buffer. The first buffer is connected between the output end of the first AND gate and the control end of the first lower bridge switch.

In one embodiment, the power converter having switching elements with different safe operating areas further includes a second buffer. The second buffer is connected between the output end of the second flyback and the control end of the second lower bridge switch.

In one embodiment, the power converter having switching elements with different safe operating areas further includes a second high-side switch. The first terminal of the second high bridge switch is coupled to the common voltage. The control end of the second upper bridge switch is connected to the output end of the upper bridge drive circuit. The second end of the second upper bridge switch is connected to the first end of the second lower bridge switch. A second node between the second end of the second upper bridge switch and the first end of the second lower bridge switch is grounded through the series circuit. The safe working area of the second upper bridge switch is larger than the safe working area of the first upper bridge switch.

In one embodiment, the upper bridge driving circuit includes a third AND gate, a fourth AND gate, a third NOR gate, a third NOR gate, a fourth NAND gate and a first NAND gate. The first input end of the third AND gate is connected to the output end of the pulse signal generator. The second input end of the third AND gate is connected to the output end of the second AND gate. The first input end and the second input end of the fourth AND gate are respectively connected to the output end of the third AND gate and the control end of the second upper bridge switch. The output end of the second AND gate is connected to the control end of the first upper bridge switch. The two input terminals of the third NOR gate are respectively connected to the output terminal of the third AND gate and the control terminal of the first upper bridge switch. The output end of the third inverting OR gate is connected to the input end of the third inverting gate. The output end of the third flyback is connected to the control end of the second upper bridge switch. The input end of the fourth flyback is connected to the control end of the second lower bridge switch. The two input terminals of the first NOR gate are respectively connected to the output terminal of the third NOR gate and the output terminal of the fourth NOR gate. The output terminal of the first NOR gate is connected to the first input terminal of the first NOR gate.

In one embodiment, the power converter with switching elements having different safe operating areas further includes a delay circuit. The delay circuit is connected between the output terminal of the first NOR gate and the first input terminal of the first NOR gate.

In one embodiment, the power converter with switching elements with different safe operating areas further includes a potential conversion circuit. The potential conversion circuit is connected between the output terminal of the delay circuit and the first input terminal of the fourth AND gate.

In one embodiment, the power converter having switching elements with different safe operating areas further includes a second high-side switch. The first end of the second upper bridge switch is coupled to the common voltage, and the control end of the second upper bridge switch is connected to the output end of the upper bridge drive circuit. The second end of the second upper bridge switch is connected to the first end of the second lower bridge switch. A second node between the second end of the second upper bridge switch and the first end of the second lower bridge switch is grounded through the series circuit. The safe working area of the second upper bridge switch is larger than the safe working area of the first upper bridge switch.

In one embodiment, after the high-bridge driving circuit turns off the first high-bridge switch, the high-bridge driving circuit turns off the second high-bridge switch. Before the upper bridge driving circuit turns on the first upper bridge switch, the upper bridge driving circuit turns on the second upper bridge switch.

In one implementation, the upper bridge driving circuit includes a first AND gate, a second AND gate, a first NOR gate, a first NOR gate, a second NAND gate, and a first NAND gate. The first input end of the first AND gate is connected to the output end of the pulse signal generator. The second input end of the first AND gate is connected to the output end of the lower bridge driving circuit. The first input end of the second AND gate is connected to the output end of the first AND gate. The second input end of the second AND gate is connected to the control end of the second upper bridge switch. The output end of the second AND gate is connected to the input end of the upper bridge driving circuit. The output end of the second AND gate is connected to the control end of the first upper bridge switch. The first input end and the second input end of the first NOR gate are respectively connected to the output end of the first AND gate and the control end of the first upper bridge switch. The output end of the first inverting OR gate is connected to the input end of the first inverting gate. The output end of the first flyback is connected to the control end of the second upper bridge switch. The input end of the second flyback is connected to the control end of the second lower bridge switch. The two input terminals of the first NAND gate are respectively connected to the input terminals of the lower bridge driving circuit.

In one embodiment, the power converter with switching elements with different safe operating areas further includes a potential conversion circuit. The potential conversion circuit is connected between the output terminal of the first AND gate and the first input terminal of the second AND gate.

In one embodiment, the power converter having switching elements with different safe operating areas further includes a first buffer. The first buffer is connected between the output end of the second AND gate and the control end of the first upper bridge switch.

As mentioned above, the present invention provides a power converter with switching elements with different safe operating areas, which adopts two upper-side switching elements or two lower-side switching elements with different safe operating areas to be used in conjunction with each other to achieve a smaller layout area. Obtaining the same on-resistance value reduces the chip size of the power converter as a whole, and at the same time prevents switching elements with poor withstand voltage from being damaged due to inability to withstand excessive current or voltage.

In order to further understand the features and technical content of the present invention, please refer to the following detailed description and drawings related to the present invention. However, the provided drawings are only for reference and description, and are not intended to limit the present invention.

The implementation of the present invention is described below through specific specific examples, and those skilled in the art can understand the advantages and effects of the present invention from the content disclosed in this specification. The present invention can be implemented or applied through other different specific embodiments, and various modifications and changes can be made to the details in this specification based on different viewpoints and applications without departing from the concept of the present invention. In addition, the drawings of the present invention are only for simple illustration, and are not drawn according to the actual size, just for clarification. The following embodiments will further describe the relevant technical content of the present invention in detail, but the disclosed content is not intended to limit the protection scope of the present invention. In addition, the term "or" used herein may include any one or a combination of more of the associated listed items depending on the actual situation.

[first embodiment]

Please refer to FIG. 1 and FIG. 6, wherein FIG. 1 is a circuit layout diagram of a power converter with switching elements with different safe operating areas in the first embodiment of the present invention; FIG. 6 is a circuit layout diagram of various embodiments of the present invention with different safe operating areas Signal waveform diagram of the switching elements of a power converter.

The power converter described herein may be, for example, a buck converter, but it is only an example here, and the present invention is not limited thereto.

It should be noted that, as shown in FIG. 1 , the power converter of the embodiment of the present invention further includes a second lower switch M2 in addition to the first upper switch M3 and the first lower switch M1 . The safe operating area (Safe operating area, SOA) of the second lower bridge switch M2 is larger than the safe operating area of the first lower bridge switch M1, and is used to protect the first lower bridge switch M1.

A first terminal of the first high-bridge switch M3 is coupled to the common voltage VIN. The first end of the first lower bridge switch M1 is connected to the second end of the first upper bridge switch M3. The second end of the first lower bridge switch M1 is grounded.

A first node LX1 between the second terminal of the first high-bridge switch M3 and the first terminal of the first low-bridge switch M1 is grounded through a series circuit of the inductor L and the capacitor C. In detail, the first node LX1 is connected to the first end of the inductor L. As shown in FIG. The second end of the inductor L is connected to the first end of the capacitor C. The second end of the capacitor C is grounded. The output node between the inductor L and the capacitor C is the output terminal of the power converter and has an output voltage Vout. Capacitor C can be connected in parallel with resistor R.

The first terminal of the second lower bridge switch M2 is connected to the first node LX1 between the second terminal of the first upper bridge switch M3 and the first terminal of the first lower bridge switch M1 and the first terminal of the inductor L1 . The second end of the second lower bridge switch M2 is grounded.

In addition, the power converter of this embodiment may further include the upper bridge driving circuit 100 and the lower bridge driving circuit 200 . The high-bridge driving circuit 100 can be connected to the control terminal of the first high-bridge switch M3. The lower bridge driving circuit 200 can be connected to the control terminal of the first lower bridge switch M1.

If necessary, the power converter of the embodiment of the present invention may include a first buffer 301 for the first upper bridge switch M3, which is connected between the upper bridge drive circuit 100 and the control terminal of the first upper bridge switch M3, and may As a delay or relay element of the first up-side driving signal UG1 output from the up-side driving circuit 100 to the first up-side switch M3.

The input terminals of the high-bridge driving circuit 100 and the low-bridge driving circuit 200 can be connected to an external pulse signal generator (not shown), so as to receive the pulse width modulation signal PWM from the pulse signal generator. The high-side driving circuit 100 can output the high-level or low-level first high-side driving signal UG1 according to the pulse width modulation signal PWM to drive the first high-side switch M3 to turn on or off.

The lower bridge driving circuit 200 can output the first lower bridge driving signal LG1 and the second lower bridge driving signal LG2 according to the pulse width modulation signal PWM to drive the first lower bridge switch M1 and the second lower bridge switch M1 respectively. The bridge switch M2 is turned on or off.

For example, when the pulse width modulation signal PWM is at a high level, the low-level driving circuit 200 outputs a low-level first low-side driving signal LG1 to the first low-side switch M1 to turn off the first low-side switch M1. . Next, the low-side driving circuit 200 outputs the low-level second low-side driving signal LG2 to the second low-side switch M2 to turn off the second low-side switch M2.

On the contrary, when the pulse width modulation signal PWM is at the low level, the low-side driving circuit 200 outputs the high-level second low-side driving signal LG2 to the second low-side switch M2 to turn on the second low-side switch M2. Next, the low-side driving circuit 200 outputs the high-level first low-side driving signal LG1 to the first low-side switch M1 to turn on the first low-side switch M1 .

That is to say, after the lower-side driving circuit 200 turns off the first lower-side switch M1 with a larger safe operating area, the lower-side driving circuit 200 starts to turn off the second lower-side switch M2 with a smaller safe operating area. Before the lower-side driving circuit 200 turns on the first lower-side switch M1 with a smaller safe operating area, the lower-side driving circuit 200 first turns on the second lower-side switch M2 with a larger safe operating area.

In addition, the power converter according to the embodiment of the present invention may include a first buffer 401 for the first low-side switch M1 and a second buffer 402 for the second low-side switch M2. The first buffer 401 is connected between the output end of the lower bridge driving circuit 200 and the control end of the first lower bridge switch M1. The second buffer 402 is connected between the output terminal of the low bridge driving circuit 200 and the control terminal of the second low bridge switch M2. The first buffer 401 and the second buffer 402 can serve as the first lower bridge drive signal LG1 output to the first lower bridge switch M1 and the second lower bridge drive signal output to the second lower bridge switch M2 respectively by the bridge drive circuit 200 Delay or relay element for LG2.

The first upper bridge switch M3 and the first lower bridge switch M1 are complementary switched. Therefore, when the upper bridge driving circuit 100 intends to drive the first upper bridge switch M3 to switch from the off state to the on state, the first low bridge driving signal LG1 as shown in FIG. The circuit 200 drives the first lower bridge switch M1 to switch from the on state to the off state.

After turning off the first lower bridge switch M1 with a smaller safe working area for a period of time, the lower bridge driving circuit 200 starts to turn off the second lower bridge switch M2 with a larger safe working area. The second lower bridge switch M2 with a larger safe working area bears the rising voltage of the voltage signal LXS of the first node LX1 as shown in FIG. 6 due to the relationship of the energy of the inductance L.

When the upper bridge drive circuit 100 drives the first upper bridge switch M3 to switch from the on state to the off state, the lower bridge drive signal LG1 as shown in FIG. The lower bridge switch M2 is turned on. In this way, the voltage signal LXS of the first node LX shown in FIG. Pull down to low voltage. When the voltage of the first node LX reaches a low voltage, the lower bridge drive circuit 200 drives the first lower bridge switch M1 to turn on, so as to prevent the first lower bridge switch M1 with a smaller safe working area and a lower withstand voltage from being damaged by the first node LX. The voltage is too high and damaged.

If necessary, the power converter of the embodiment of the present invention may further include a potential conversion circuit 602 and a delay circuit 500 . The input terminal of the potential conversion circuit 602 can be connected to the control terminal of the first upper bridge switch M3. The output end of the potential conversion circuit 602 can be connected to the input end of the delay circuit 500 . The output end of the delay circuit 500 can be connected to the input end of the lower bridge driving circuit 200 .

When the first upper bridge switch M3 is turned from the on state to the off state, and the first lower bridge switch M1 is turned from the off state to the on state, the potential conversion circuit 602 can convert the first upper bridge driving signal of the first upper bridge switch M3 to UG1 switches from a high level to a low level to prevent excessive voltage from being injected into the first lower bridge switch M1. The delay circuit 500 can delay the phase of the transformed first upper bridge driving signal UG1.

The lower bridge driving circuit 200 can output the lower bridge conduction signal LGD to the upper bridge driving circuit 100 according to the first upper bridge driving signal UG1 received from the delay circuit 500 . The upper bridge driving circuit 100 can output a first upper bridge driving signal UG1 according to the lower bridge conduction signal LGD and the pulse width modulation signal PWM to control the operation of the upper bridge driving circuit 100 .

[Second embodiment]

Please refer to FIG. 2 , which is a circuit layout diagram of a power converter having switching elements with different safe operating areas according to a second embodiment of the present invention. Similarities with the first embodiment will not be repeated here.

In this embodiment, for example, the aforementioned lower bridge driving circuit 200 may include a first NOR gate 11, a first AND gate 12, a second NOR gate 13, a second NOR gate 14, a first NOR gate 15, and a second NOR gate 15. And gate 16.

The first input end of the first NOR gate 11 is connected to the control end of the first upper bridge switch M3. If necessary, a potential conversion circuit 602 and a delay circuit 500 can be provided between the control terminal of the first upper bridge switch M3 and the first input terminal of the first NOR gate 11 .

The first input terminal of the first AND gate 12 is connected to the output terminal of the first NOR gate 11 . The second input end of the first AND gate 12 is connected to the control end of the second lower bridge switch M2. The second input terminal of the first AND gate 12 can receive the second low-side driving signal LG2 of the second low-side switch M2. The output end of the first AND gate 12 can be connected to the control end of the first lower bridge switch M1. If necessary, a first buffer 401 may be provided between the output end of the first AND gate 12 and the control end of the first lower bridge switch M1.

The first input terminal of the second NOR gate 13 is connected to the output terminal of the first NOR gate 11 . The second input end of the second NOR gate 13 is connected to the control end of the first lower bridge switch M1. The second input terminal of the second NOR gate 13 can receive the first lower bridge driving signal LG1 of the first lower bridge switch M1 .

The output terminal of the second inverter gate 13 can be connected to the input terminal of the second inverter gate 14 , and the output terminal of the second inverter gate 14 can be connected to the control terminal of the second lower bridge switch M2 . If necessary, a second buffer 402 may be provided between the output end of the second flyback 14 and the control end of the second lower bridge switch M2.

The input end of the first flyback 15 is connected to the control end of the second lower bridge switch M2. The input terminal of the first flyback 15 can receive the second lower bridge driving signal LG2 of the second lower bridge switch M2. The first input terminal of the second AND gate 16 is connected to the output terminal of the second NOR gate 13 . The second input terminal of the second AND gate 16 is connected to the output terminal of the first inverter gate 15 . The output end of the second AND gate 16 is connected to the input end of the high bridge driving circuit 100 . The second AND gate 16 can output the lower bridge conduction signal LGD.

If necessary, the power converter may further include a delay circuit 700 connected between the output terminal of the second AND gate 16 and the input terminal of the high-bridge driving circuit 100 . The delay circuit 700 can be configured to delay the phase of the low-side conduction signal LGD to be output to the high-side driving circuit 100 .

[Third embodiment]

Please refer to FIG. 3 , which is a circuit layout diagram of a power converter with switching elements with different safe operating areas according to a third embodiment of the present invention. The points that are the same as those in the foregoing embodiments will not be repeated here.

It should be noted that the circuit of the power converter in this embodiment further includes a second high-side switch M4 in addition to the first high-side switch M3. The safe operating area of the second upper bridge switch M4 is larger than the safe operating area of the first upper bridge switch M3.

A first terminal of the second high-bridge switch M4 is coupled to the common voltage VIN. The control terminal of the second high-bridge switch M4 is connected to the output terminal of the high-bridge driving circuit 100 . If necessary, a second buffer 302 may be provided between the control terminal of the second high-bridge switch M4 and the output terminal of the high-bridge driving circuit 100 .

The second end of the second upper bridge switch M4 is connected to the first end of the second lower bridge switch M2. The second node LX2 between the second end of the second upper bridge switch M4 and the first end of the second lower bridge switch M2 is connected to the first node LX1 and the first end of the inductor L. The second end of the inductor L is connected to the first end of the capacitor C, and the second end of the capacitor C is grounded. Capacitor C can be connected in parallel with resistor R.

It is worth noting that when the lower bridge drive circuit 200 intends to drive the first lower bridge switch M1 from the on state to the off state, the upper bridge drive circuit 100 first drives the second upper bridge switch M4 with a larger safe working area to turn on, and then drives the safety The first upper bridge switch M3 with a small working area is turned on. Conversely, when the lower bridge drive circuit 200 drives the first lower bridge switch M1 to switch from the off state to the on state, the upper bridge drive circuit 100 first drives the first upper bridge switch M3 with a smaller safe working area to close, and then drives the first upper bridge switch M3 with a larger safe working area The second upper bridge switch M4 is turned off.

[Fourth embodiment]

Please refer to FIG. 4 , which is a circuit layout diagram of a power converter with switching elements with different safe operating areas according to a fourth embodiment of the present invention. The points that are the same as those in the foregoing embodiments will not be repeated here.

In this embodiment, for example, the aforementioned upper bridge drive circuit 100 may include a first AND gate 31, a second AND gate 32, a first NOR gate 33, a first NOR gate 34, a second NOR gate 35, and a first NAND gate. Gate 36.

The input terminal of the lower bridge driving circuit 200 and the first input terminal of the first AND gate 31 can be connected to the output terminal (not shown) of an external pulse signal generator, and the pulse width modulation signal PWM is received from the pulse signal generator. . The second input end of the first AND gate 31 is connected to the output end of the lower bridge driving circuit 200 to receive the lower bridge conduction signal LGD output by the lower bridge driving circuit 200 .

The first input end of the second AND gate 32 is connected to the output end of the first AND gate 31 . The second input end of the second AND gate 32 can be connected to the control end of the second upper bridge switch M4, and receives the second upper bridge driving signal UG2 of the second upper bridge switch M4. If necessary, a potential conversion circuit 601 may be provided between the output end of the first AND gate 31 and the first input end of the second AND gate 32 .

The output end of the second AND gate 32 can be connected to the control end of the first upper bridge switch M3. If necessary, a first buffer 301 may be provided between the output end of the second AND gate 32 and the control end of the first upper bridge switch M3.

The first input terminal of the first NOR gate 33 is connected to the output terminal of the first AND gate 31 , and the second input terminal of the first NOR gate 33 is connected to the control terminal of the first upper bridge switch M3 . The output terminal of the first inverter gate 33 is connected to the input terminal of the first inverter gate 34, and the output terminal of the first inverter gate 34 is connected to the control terminal of the second upper bridge switch M4.

The input end of the second flyback 35 is connected to the control end of the second lower bridge switch M2. The first input terminal of the first NOR gate 36 is connected to the output terminal of the first NOR gate 33 , and the second input terminal of the first NAND gate 36 is connected to the output terminal of the second NOR gate 35 .

The output end of the first NAND gate 36 can be connected to the input end of the lower bridge driving circuit 200 . If necessary, a delay circuit 500 and a potential conversion circuit 602 can be provided between the output terminal of the first NAND gate 36 and the input terminal of the lower bridge driving circuit 200 .

[Fifth Embodiment]

Please refer to FIG. 5 , which is a circuit layout diagram of a power converter with switching elements with different safe operating areas according to a fifth embodiment of the present invention.

In this embodiment, for example, the aforementioned upper bridge switch circuit 100 includes a third AND gate 17, a fourth AND gate 18, a third NOR gate 19, a third NOR gate 20, a fourth NAND gate 21, and a first NAND gate. 22, which are the same as the first AND gate 31, the second AND gate 32, the first NOR gate 33, the first NOR gate 34, the second NAND gate 35 and the first NAND gate 36 respectively. Therefore, please refer to the foregoing for the same content, and will not repeat them here.

In this embodiment, the lower bridge switch circuit 200 includes the first NOR gate 11, the second NOR gate 13, the first NOR gate 15, the second NOR gate 14, the first AND gate 12 and the second AND gate 16. For the same content, please refer to the above, and will not repeat it here.

To sum up, the present invention provides a power converter with switching elements with different safe operating areas, which uses two upper-side switching elements or two lower-side switching elements with different safe operating areas for use in conjunction with a smaller layout. The same on-resistance value is obtained in the area, while reducing the chip size of the power converter as a whole, it can still achieve the effect of preventing the switching elements with poor withstand voltage from being damaged due to the inability to withstand excessive current or voltage.

The content disclosed above is only a preferred feasible embodiment of the present invention, and does not therefore limit the scope of the patent application of the present invention. Therefore, all equivalent technical changes made by using the description and drawings of the present invention are included in the application of the present invention. within the scope of the patent.

100: Upper bridge drive circuit 200: lower bridge drive circuit 301, 401: first buffer 302, 402: second buffer 500: delay circuit 601, 602: Potential conversion circuit PWM: pulse width modulation signal LGD: lower bridge conduction signal VIN: common voltage M1: first lower bridge switch M2: second lower bridge switch M3: the first upper bridge switch LX1: first node UG1: the first upper bridge drive signal LG1: The first lower bridge drive signal LG2: second lower bridge drive signal L: inductance C: Capacitance R: Resistance Vout: output voltage 11, 33: The first reverse OR gate 12, 31: The first gate 13: The second reverse OR gate 14, 35: The second reverse brake 15, 34: The first reverse brake 16, 32: The second gate 700: delay circuit UGD: upper bridge conduction signal UG2: The second upper bridge drive signal M4: Second upper bridge switch LX2: second node 36, 22: The first reverse and gate 17: The third gate 18: Fourth and gate 19: The third reverse OR gate 20: The third reverse brake 21: The fourth reverse brake IL, IL01, IL02, IL03: Inductor current LXS, UXS, LGS01, LXS01, LGS02, LXS02, UXS0, LXS03: voltage signal A, B: box

FIG. 1 is a circuit layout diagram of a power converter with switching elements with different safe operating areas according to a first embodiment of the present invention.

FIG. 2 is a circuit layout diagram of a power converter with switching elements with different safe operating areas according to a second embodiment of the present invention.

3 is a circuit layout diagram of a power converter with switching elements with different safe operating areas according to a third embodiment of the present invention.

FIG. 4 is a circuit layout diagram of a power converter with switching elements with different safe operating areas according to a fourth embodiment of the present invention.

FIG. 5 is a circuit layout diagram of a power converter with switching elements with different safe operating areas according to a fifth embodiment of the present invention.

FIG. 6 is a signal waveform diagram of a power converter having switching elements with different safe operating areas according to various embodiments of the present invention.

FIG. 7 is a signal waveform diagram of a conventional power converter.

FIG. 8 is a signal waveform diagram of a conventional power converter.

FIG. 9 is a signal waveform diagram of a conventional power converter.

100: Upper bridge drive circuit 200: lower bridge drive circuit 301, 401: first buffer 402: Second buffer 500: delay circuit 602: Potential conversion circuit PWM: pulse width modulation signal LGD: lower bridge conduction signal VIN: common voltage M1: first lower bridge switch M2: second lower bridge switch M3: the first upper bridge switch LX1: first node UG1: the first upper bridge drive signal LG1: The first lower bridge drive signal LG2: second lower bridge drive signal L: inductance C: Capacitance R: Resistance Vout: output voltage

Claims (9)

A power converter with switching elements in different safe working areas, comprising: a first upper bridge switch, the first end of the first upper bridge switch is coupled to a common voltage; a first lower bridge switch, the first lower bridge switch The first end of the bridge switch is connected to the second end of the first upper bridge switch, and the second end of the first lower bridge switch is grounded; a second lower bridge switch, the first end of the second lower bridge switch is connected to the A first node between the second end of the first upper bridge switch and the first end of the first lower bridge switch, the second end of the second lower bridge switch is grounded, and the first node passes through an inductor and a capacitor A series circuit of the upper bridge is grounded; an upper bridge drive circuit is connected to the control terminal of the first upper bridge switch, configured to drive the first upper bridge switch to be turned on or off; and a lower bridge drive circuit is connected to the first lower bridge switch. The control terminal is configured to drive the first lower bridge switch to turn on or off; wherein the safe working area of the second lower bridge switch is larger than the safe working area of the first lower bridge switch; wherein, the first upper bridge switch and the second The lower bridge switch is switched complementary; wherein, after the lower bridge drive circuit closes the first lower bridge switch, the lower bridge drive circuit closes the second lower bridge switch; wherein, after the lower bridge drive circuit turns on the first lower switch Before the bridge switch, the lower bridge drive circuit turns on the second lower bridge switch. The power converter with switching elements with different safe operating areas as claimed in Claim 1 further includes a resistor connected in parallel with the capacitor, and an output node between the capacitor and the inductor is the output terminal of the power converter. The power converter with switching elements with different safe operating areas as described in claim 1, wherein the lower bridge drive circuit includes a first inverting OR gate, a second inverting OR gate, a first inverting gate, a second Reverse gate, a first and gate and a second gate, The first input terminal of the first NOR gate is connected to the control terminal of the first upper bridge switch, the second input terminal of the first NOR gate is connected to the output terminal of a pulse signal generator, and the first AND gate The two input terminals of the first NOR gate and the control terminal of the second lower bridge switch are respectively connected, the output terminal of the first NOR gate is connected to the control terminal of the first lower bridge switch, and the second NOR gate is connected to the control terminal of the first lower bridge switch. The two input ends of the gate are respectively connected to the output end of the first inverter and the control end of the first lower bridge switch, the output end of the second inverter is connected to the input end of the second inverter, and the second inverter The output end of the gate is connected to the control end of the second lower bridge switch, the input end of the first inverter is connected to the control end of the second lower bridge switch, and the two input ends of the second and gate are respectively connected to the second inverter The output end of the gate and the output end of the first reverse gate, the input end of the upper bridge drive circuit are connected to the output end of the second AND gate and the output end of the pulse signal generator. The power converter with switching elements with different safe operating areas as described in claim 3 further includes a first buffer connected between the output terminal of the first AND gate and the control terminal of the first lower bridge switch . The power converter with switching elements with different safe operating areas as described in claim 4 further includes a second buffer connected between the output end of the second flyback and the control end of the second lower bridge switch . The power converter with switching elements with different safe operating areas as described in claim 3 further includes a second upper bridge switch, the first end of the second upper bridge switch is coupled to the common voltage, and the second upper bridge switch The control end of the switch is connected to the output end of the upper bridge drive circuit, the second end of the second upper bridge switch is connected to the first end of the second lower bridge switch, the second end of the second upper bridge switch and the second A second node between the first terminals of the lower bridge switches is grounded through the series circuit; wherein the safe working area of the second upper bridge switch is larger than the safe working area of the first upper bridge switch. Power switch with switching elements of different safe operating areas as described in claim 6 converter, wherein the upper bridge drive circuit includes a third AND gate, a fourth AND gate, a third NOR gate, a third NOR gate, a fourth NOR gate and a first NAND gate, the first NAND gate The first input end of the three AND gate is connected to the output end of the pulse signal generator, the second input end of the third AND gate is connected to the output end of the second AND gate, and the first input end of the fourth AND gate is connected to the output end of the second AND gate. The second input end is respectively connected to the output end of the third AND gate and the control end of the second upper bridge switch, the output end of the second AND gate is connected to the control end of the first upper bridge switch, and the third NOR gate The two input ends of the third NOR gate are respectively connected to the output end of the third AND gate and the control terminal of the first upper bridge switch, the output end of the third NOR gate is connected to the input end of the third NOR gate, and the output terminal of the third NOR gate is connected to the input terminal of the third NOR gate. The output end is connected to the control end of the second upper bridge switch, the input end of the fourth inverter is connected to the control end of the second lower bridge switch, and the two input ends of the first NOR gate are respectively connected to the third NOR gate The output terminal of the first NOR gate and the output terminal of the fourth NOR gate, the output terminal of the first NOR gate is connected to the first input terminal of the first NOR gate. The power converter with switching elements with different safe operating areas as described in claim 7 further includes a delay circuit connected between the output terminal of the first NOR gate and the first input terminal of the first NOR gate . The power converter with switching elements with different safe operating areas as claimed in claim 8 further includes a potential conversion circuit connected between the output terminal of the delay circuit and the first input terminal of the first NOR gate.

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