TWI778745B - Capacitance measuring system, measuring circuit and calculation device - Google Patents

Abstract

A capacitance measuring system, which includes: an alternating power, a measuring circuit and a calculation device. The measuring circuit includes a circuit input electrically connected to the alternating power, a circuit output electrically connected to the calculation device, an operational amplifier, and a switch device electrically connected to a capacitor under test. Wherein when the switch device is turned off, the measuring circuit outputs at least a output signal, and when the switch device is turned on, the measuring circuit outputs an another output signal, and the calculation device calculates a first gain and a second gain according to the output signals, and calculates a capacitance of the capacitor under test according to the first gain and the second gain.

Description

Capacitance measurement system, measurement circuit and calculation device

The present invention relates to a measurement system, measurement circuit and calculation device, in particular to a capacitance measurement system, measurement circuit and calculation device capable of measuring capacitance value.

Before conducting electrical testing of some products (such as wafer testing), it may be necessary to measure the capacitors to be used so as not to affect the electrical testing. The current method of measuring the capacitance is to charge and discharge the capacitor to be measured by supplying a current from a power supply, and to estimate the capacitance value of the capacitor to be measured according to the charging and discharging time. However, this measurement method not only consumes a long measurement time, but also in the process of charging and discharging the capacitor, because the measurement environment (such as a measurement machine or a measurement instrument, etc.) usually generates parasitic capacitance, it is easy to cause a measurement error. measurement error. To eliminate the parasitic capacitance, the capacitance value of the parasitic capacitance must be calculated first, but the capacitance value of the parasitic capacitance must be calculated by adjusting a large number of measurement parameters, which will increase the time cost, and it is also possible to measure mistake.

In addition, the existing technology has limitations on the level of capacitance that can be accurately measured. For example, the current measuring equipment can only support the measurement of capacitance values above the nanofarad (nF) level (for example, the capacitance value is greater than or equal to 1nF). , If the capacitance value of the picofarad (pF) level is directly measured (for example, the capacitance value is less than 1.0nF), a great error will occur, so it does not meet the requirements.

In view of this, the present invention provides a capacitance measurement system, a measurement circuit and a computing device to solve the above problems.

An object of the present invention is to provide a capacitance measurement system, including an AC power supply, a measurement circuit and a computing device. The measurement circuit includes a circuit input terminal electrically connected to the AC power supply, a circuit output terminal electrically connected to the computing device, an operational amplifier and a switch, wherein the switch is electrically connected to the capacitor to be measured. Wherein, when the switch is turned off, the measurement circuit outputs at least one output signal, and when the switch is turned on, the measurement circuit outputs another output signal, and the computing device calculates the first amplification of the operational amplifier according to the output signals gain and the second amplification gain, and calculate the capacitance value of the capacitor under test according to the first amplification gain and the second amplification gain.

Another object of the present invention is to provide a measurement circuit, which is installed in the capacitance measurement system, and includes a circuit input terminal electrically connected to the AC power supply of the capacitance measurement system, and a circuit input terminal electrically connected to the computing device of the capacitance measurement system. A circuit output terminal that is electrically connected, an operational amplifier, and at least one switch electrically connected to the operational amplifier, wherein the AC power source is electrically connected to the operational amplifier through the circuit input terminal, and the at least one switch is electrically connected to the capacitor to be measured .

Yet another object of the present invention is to provide a computing device, which is installed in the aforementioned capacitance measurement system and used for electrical connection with a circuit output terminal of a measurement circuit of the capacitance measurement system.

1: Capacitance measurement system

10: Measurement circuit

IN: circuit input

OUT: circuit output

11~13 (first switch 11, second switch 12, third switch 13): switch

14: Operational Amplifier

20: Computing Devices

30: AC power

40: Capacitance to be measured

11a: The first end of the first switch

11b: The second end of the first switch

12a: The first end of the second switch

12b: Second end of second switcher

13a: First end of the third switcher

13b: Second end of third switcher

14a: The first input terminal

14b: The second input terminal

14c: output terminal

15: Rectifier

16: The first resistor

17: Second resistor

A: Node

B: Node

S31~S37: Steps

18: Fourth switcher

19: Fifth Switcher

50: Reference capacitance

Vo1: The potential of the first output signal

Vo2: The potential of the second output signal

Vo3: The potential of the third output signal

Av1: first amplification gain

Av2: second amplification gain

Xc: reactance value

Freq: frequency

C2: Measured value

C1: target value

1 is a schematic structural diagram of a capacitance measurement system according to an embodiment of the present invention; 2 is a detailed circuit diagram of the measurement circuit according to the first embodiment of the present invention; FIG. 3 is a flow chart of the operation of the computing device according to an embodiment of the present invention; FIG. 4 is a schematic diagram of experimental data results of an embodiment of the present invention; FIG. 6 is a circuit diagram of the measurement circuit of the third embodiment of the present invention; FIG. 7 is an experimental data diagram of the frequency modulation of the input signal according to an embodiment of the present invention; FIG. 8 is an experimental data diagram of the capacitance to be measured corresponding to a suitable frequency according to an embodiment of the present invention.

The following will describe the implementations and operation principles of the capacitance measurement system, measurement circuit and computing device of the present invention through a plurality of embodiments. Those with ordinary knowledge in the technical field to which the present invention pertains can understand the features and effects of the present invention through the above embodiments, and can combine, modify, replace or transfer based on the spirit of the present invention.

It should be noted that, herein, unless otherwise specified, "a" element is not limited to a single element, but may also refer to one or more of the element.

In addition, descriptions such as "when" or "when" in the present disclosure represent aspects such as "now, before, or after", and are not limited to simultaneous occurrences, which are described here first. In the present disclosure, descriptions such as "arranged on" and the like refer to the corresponding positional relationship between two elements, and do not limit whether there is contact between the two elements, unless otherwise specified, which is described in advance. Furthermore, when the disclosure describes multiple effects, if the word "or" is used between the effects, it means that the effects can exist independently, but it does not exclude that multiple effects can exist simultaneously.

Terms such as "first", "second", etc. used in this document are used to modify the request element, and they do not imply or represent that the request element has any previous ordinal numbers, nor does it represent a request The order of an element and another requested element, or the order of the manufacturing method, the use of these ordinal numbers is only used to clearly distinguish a requested element with a certain name from another requested element with the same name.

In addition, words such as "connected" or "coupled" in the description and claims refer not only to direct connection with another element, but also to indirect connection or electrical connection with another element. In addition, the electrical connection includes a direct connection, an indirect connection, or an aspect in which the two components communicate with each other by radio signals.

Furthermore, in the specification and claims, the terms "about", "approximately", "substantially" and "substantially" generally mean that the difference between a value and a given value is within 10% of the given value, or Within 5%, or within 3%, or within 2%, or within 1%, or within the range of 0.5%. The quantity given here is an approximate quantity, that is, "about", "approximately", "approximately", "approximately", "approximately", "approximately", "approximately", "approximately", "approximately", "approximately", "substantially" and "substantially" may still be implied without the specific description of "about", "approximately", "substantially", "substantially" The meaning of "substantially" and "substantially". Furthermore, the terms "range is from the first value to the second value", "range is between the first value and the second value" means that the range includes the first value, the second value and other values in between.

In addition, each element may be implemented as a single circuit or an integrated circuit in a suitable manner, and may include one or more active elements, such as transistors or logic gates, or one or more passive elements, such as resistors, capacitors , or inductance, but not limited thereto. The elements may be connected to each other in a suitable manner, eg, using one or more lines to form a series or parallel connection with the input signal and the output signal, respectively. In addition, each element may allow input and output signals to enter and exit sequentially or in parallel. The above configurations are all determined according to the actual application.

In addition, the technical features of different embodiments disclosed in the present disclosure may be combined to form another embodiment.

In addition, in this document, terms such as "system", "equipment", "device", "module", or "unit" refer to an electronic component or a digital circuit composed of a plurality of electronic components, an analog circuits, or other broader circuits, and they do not necessarily have a hierarchical or hierarchical relationship unless otherwise specified.

FIG. 1 is a schematic diagram of a basic structure of a capacitance measurement system 1 according to an embodiment of the present invention. As shown in FIG. 1 , the capacitance measurement system 1 includes a measurement circuit 10 , a computing device 20 and an AC power source 30 . The measurement circuit 10 may include a circuit input terminal IN, a circuit output terminal OUT, an operational amplifier 14 and a plurality of switches 11 to 13 (hereinafter referred to as the first switch 11 to the third switch 13 ), and wherein A switch (eg, the third switch 13 ) is electrically connected to a capacitor to be measured 40 . The circuit input terminal IN is electrically connected to the AC power source 30 . The circuit output terminal OUT is electrically connected to the computing device 20 . The calculation device 20 can perform calculation according to the output result of the circuit output terminal OUT, and can output the capacitance value of the capacitor 40 to be measured.

The AC power source 30 can provide an input signal Vin to the measurement circuit 10 . The measurement circuit 10 can output different output signals Vo to the computing device 20 at different time points through the switching of at least one of the switches 11-13, for example, when at least one of the switches 11-13 (for example, FIG. 2 When the third switch 13) is turned off, the measurement circuit 10 can output at least one output signal Vo to the computing device 20, and the computing device 20 can calculate the value of the operational amplifier 14 according to the at least one output signal Vo A first amplification gain; when at least one of the switches 11 to 13 (eg, the third switch 13 in FIG. 2 ) is turned on, the measurement circuit 10 can output another output signal to the computing device 20 , The computing device 20 can calculate a second amplification gain of the operational amplifier 14 according to the at least one output signal Vo obtained previously and the output signal Vo obtained currently gain, and then the capacitance value of the capacitor under test 40 is calculated according to the first amplification gain and the second amplification gain. In this way, the present invention can measure the capacitance value of the capacitor 40 to be measured.

Next, the details of each element will be described.

First, the details of the AC power supply 30 will be described.

The AC power source 30 can provide the input signal Vin to the circuit input terminal IN of the measurement circuit 10 . In one embodiment, the AC power source 30 can be, for example, various waveform generators (arbitrary waveform generators, AWGs), which can provide waveform signals such as sine wave, square wave, triangle wave, etc., but not limited to this; for the convenience of description, the following It is all taken as an example that the AC power source 30 provides a sine wave. In addition, in one embodiment, the frequency of the signal generated by the AC power source 30 can be modulated, but not limited to this.

Next, the details of the computing device 20 will be described.

In one embodiment, the computing device 20 may be, for example, a processor that includes a computer program product or firmware stored on a non-transitory computer-readable medium to perform specific computing functions. In one embodiment, the computing device 20 may be installed in a measuring machine (not shown in the figure), or may be installed in a computer (not shown in the figure), but is not limited thereto. In one embodiment, the computing device 20 may also be an integrated circuit with computing function, which can be loaded with special firmware or software to realize the computing function. It should be noted that the aspect of the computing device 20 is not limited to this.

Next, the details of the measurement circuit 10 will be described.

The measurement circuit 10 can output different output signals Vo to the computing device 20 through, for example, switching of the switches 11 - 13 . FIG. 2 is a detailed circuit diagram of the measurement circuit 10 according to the first embodiment of the present invention, and please refer to FIG. 1 at the same time.

As shown in FIG. 2, the measurement circuit 10 may include a circuit input terminal IN, a circuit output terminal OUT, a first switch 11, a second switch 12, a third switch 13, an operational amplifier 14, a rectifier 15, a A first resistor 16 and a second resistor 17 . The first switch 11 may include a first end 11a and a second end 11b. The second switch 12 may include a first end 12a and a second end 12b. The third switch 13 may include a first terminal 13a and a second terminal 13b, wherein the second terminal 13b of the third switch 13 may be electrically connected to the capacitor to be measured 40 . The operational amplifier 14 may include a first input terminal 14a, a second input terminal 14b and an output terminal 14c.

The first switch 11 can be disposed between the circuit input terminal IN and the circuit output terminal OUT. For example, the first terminal 11a of the first switch 11 can be electrically connected to the circuit input terminal IN, and the second switch 11 can be electrically connected to the circuit input terminal IN. The terminal 11b can be electrically connected to the anode terminal of the rectifier 15 and is electrically connected to the circuit output terminal OUT through the rectifier 15 .

The operational amplifier 14 and the second switch 12 can be disposed between the circuit input terminal IN and the circuit output terminal OUT. For example, the first input terminal 14a of the operational amplifier 14 can be electrically connected to the circuit input terminal IN, and the output terminal of the operational amplifier 14 14c can be electrically connected to the first terminal 12a of the second switch 12, and the second terminal 12b of the second switch 12 can be electrically connected to the anode terminal of the rectifier 15, and is electrically connected to the circuit output terminal OUT through the rectifier 15 . In addition, the output terminal 14c of the operational amplifier 14 can also be electrically connected to the first resistor 16 , for example, the output terminal 14c , the first terminal 12a of the second switch 12 and the first resistor 16 can be electrically connected to the measurement circuit 10 . A node A. In addition, the second input terminal 14 b of the operational amplifier 14 , the first resistor 16 , the second resistor 17 and the third switch 13 can be electrically connected to a node B of the measurement circuit 10 .

The first terminal 13a of the third switch 13 can be electrically connected to the node B with the second input terminal 14b of the operational amplifier 14, the first resistor 16 and the second resistor 17, and the second terminal 13b of the third switch 13 can be It is electrically connected to the capacitor to be measured 40 .

In one embodiment, the AC power supply 30 can be electrically connected to the first terminal 11a of the first switch 11 and the first input terminal 14a of the operational amplifier 14 through the circuit input terminal IN, respectively. Therefore, the AC power supply The input signal Vin provided by 30 can enter the signal path where the first switch 11 is located or the signal path where the operational amplifier 14 is located.

In one embodiment, the first switch 11 , the second switch 12 , and the third switch 13 may be, for example, a relay, a switch, or a multiplexer, but not limited thereto. In one embodiment, the aforementioned switches 11 , 12 , and 13 may be, for example, mechanical switches or electronic switches, but are not limited thereto. In one embodiment, the aforementioned switches 11 , 12 , and 13 may include transistors, or be transistors themselves, but are not limited thereto. In one embodiment, the first switch 11, the second switch 12 or the third switch 13 can be controlled by an external control element (such as but not limited to a timing controller or other mechanical controllers, not shown in the figure), and Present on or off, but not limited to this.

In one embodiment, the operational amplifier 14 may be, for example, a non-inverting amplifier, wherein the first input terminal 14a may be a positive input terminal, and the second input terminal 14b may be a negative input terminal, but not limited thereto.

In one embodiment, the rectifier 15 can be, for example, a diode, or an integrated circuit including a diode, wherein the anode terminal of the diode can be electrically connected to the first switch 11 and the second switch 12 respectively. , and the cathode terminal of the diode can be electrically connected to the circuit output terminal OUT, and is not limited to this.

Next, the operation of the measurement circuit 10 and the computing device 20 will be described.

In one embodiment, the first switch 11 , the second switch 12 and the third switch 13 can be turned on at different time points, so the input signal Vin can pass through different signal paths at different time points, and the circuit output terminal OUT Different output signals Vo can be output at different time points. In one embodiment, the conduction period of the first switch 11 does not overlap with the conduction periods of the other switches 12 and 13 . In one embodiment, the conduction period of the second switch 12 may partially overlap with the conduction period of the third switch 13 .

More specifically, in an embodiment, during a first period, the first switch 11 can be turned on, and the second switch 12 and the third switch 13 can be turned off. At this time, the signal path where the first switch 11 is located is the lead The signal path where the second switch 12 and the third switch 13 are located is in the non-conducting state, so the input signal Vin provided by the AC power source 30 can pass through the first switch 11 and be rectified by the rectifier 15 to form a The first output signal is then output to the computing device 20 at the circuit output terminal OUT. Since there is no operational amplifier on the signal path, the first output signal can be the same as or similar to the rectified input signal Vin, so the first output signal can be regarded as a rectified DC signal of the input signal Vin.

In one embodiment, during a second period, the second switch 12 can be turned on, and the first switch 11 and the third switch 13 can be turned off. At this time, the signal path of the second switch 12 is in a conducting state, while the paths of the first switch 11 and the third switch 13 are in a non-conducting state, so the input signal Vin can pass through the operational amplifier 14 (the signal is thus amplified ), the second switch 12 and the rectifier 15, and rectified by the rectifier 15 to form a second output signal, and then the second output signal is output to the computing device 20 at the circuit output terminal OUT. Since there is an operational amplifier 14 on the signal path, the second output signal can be regarded as a DC signal after the input signal Vin is amplified and rectified.

At this time, the computing device 20 can calculate the current gain (ie, the first amplification gain) of the operational amplifier 14 through the previously obtained first output signal and the currently obtained second output signal, wherein the first amplification gain can be expressed as Formula (1): Av1=Vo2/Vo1;... Formula (1) where Av1 is defined as the first amplification gain, Vo1 is defined as the potential of the first output signal, and Vo2 is defined as the potential of the second output signal.

In addition, according to the configuration of the operational amplifier 14, the first resistor 16 and the second resistor 17, it can be known that the first amplification gain (Av1) can also be expressed as formula (2): Av1=1+(R1/R2);  … .. Formula (2) R1 is defined as the resistance value of the first resistor 16 , and R2 is defined as the resistance value of the second resistor 17 . It should be noted that R1 and R2 are preset values, that is, the resistance values of the first resistor 16 and the second resistor 17 are preset values (ie, known parameters).

In one embodiment, during a third period, the second switch 12 and the third switch 13 can be turned on, and the first switch 11 can be turned off. At this time, the signal paths of the second switch 12 and the third switch 13 are in a conducting state, while the signal paths of the first switch 11 are in a non-conducting state, so the input signal Vin will pass through the operational amplifier 14 (the signal is thus amplified). ), the second switch 12 and the rectifier 15, and rectified by the rectifier 15 to form a third output signal, and then the third output signal is output to the computing device 20 at the circuit output terminal OUT. Since there is an operational amplifier 14 on the signal path, the third output signal can be regarded as an amplified and rectified DC signal of the input signal Vin, and since the third switch 13 is turned on, the amplification gain of the operational amplifier 14 will be affected by Due to the influence of the reactance value Xc of the capacitor 40 under test, the potentials of the third output signal and the second output signal are different.

At this time, the computing device 20 can calculate the current gain of the operational amplifier 14 (ie, the second amplification gain) based on the previously obtained first output signal and the currently obtained third output signal, wherein the second amplification gain can be expressed as a formula (3): Av2=Vo3/Vo1; ...... Formula (3) where Av2 is defined as the second amplification gain, and Vo3 is defined as the potential of the third output signal.

In addition, according to the configuration of the operational amplifier 14, the first resistor 16, the second resistor 17 and the capacitor to be measured 40, the second amplification gain can also be expressed as formula (4): Av2=1+[R1/(R2// Xc)]=1+[R1/(R2*Xc)/(R2+Xc)]=1+[(R1*R2+R1*Xc)/(R2*Xc)] =1+(R1/Xc)+(R1/R2)=(R1/Xc)+Av1;... Formula (4) where Xc is defined as the reactance value of the capacitor 40 to be measured, and R2//Xc is defined is the resistance value of the second resistor 17 and the capacitor 40 to be measured in parallel.

In addition, in one embodiment, after the calculation module 20 calculates the first amplification gain and the second amplification gain through the formula (1) and the formula (3), the calculation module 20 may calculate the first amplification gain and the second amplification gain according to the first amplification gain and the second amplification gain. The gain, the resistance value of the first resistor and the formula (4) calculate the reactance value of the capacitor 40 to be measured (eg Xc=R1/(Av2-Av1)). In addition, the reactance value of the capacitor 40 to be measured can also be expressed as formula (5): Xc=1/(2 π fC); ...... formula (5) where π is the pi, and f is the frequency of the input signal Vin (It is an adjustable value and is a known parameter), C is the capacitance value. Therefore, after the calculation module 20 calculates the reactance value of the capacitor under test 40, the capacitance value of the capacitor under test 40 can be calculated according to the formula (5).

In this way, the capacitance value of the capacitor to be measured 40 can be calculated by the calculation module 20 .

To make the description clearer, the operation process of the computing device 20 is summarized below. FIG. 3 is a flow chart of the operation of the computing device 20 according to an embodiment of the present invention, and please refer to FIG. 1 and FIG. 2 at the same time.

As shown in FIG. 3 , first step S31 is executed, and the computing device 20 obtains the first output signal output by the measurement circuit 10 . After that, step S32 is executed, and the computing device 20 obtains the second output signal output by the measurement circuit 10 . After that, step S33 is executed, and the computing device 20 calculates the first amplification gain of the operational amplifier 14 according to the first output signal and the second output signal (refer to the formula (1)), wherein the first amplification gain can be regarded as the measurement circuit 10 has not The gain of the operational amplifier 14 when the capacitor under test 40 is connected. After that, step S34 is executed, and the computing device 20 obtains the third output signal output by the measurement circuit 10 . Then step S35 is executed, and the computing device 20 calculates the second amplification of the operational amplifier 14 according to the first output signal and the third output signal Gain (refer to equation (3)), wherein the second amplification gain can be regarded as the gain of the operational amplifier 14 when the measurement circuit 10 is connected to the capacitor 40 to be measured. After that, step S36 is executed, and the computing device 20 calculates the reactance value of the capacitor to be measured 40 according to the first amplification gain and the second amplification gain (refer to the formula (4)). After step S37 is executed, the computing device 20 calculates the capacitance value of the capacitor under test 40 according to the reactance value of the capacitor under test 40 and the frequency of the input signal Vin (refer to formula (5)).

Thereby, the operation flow of the computing device 20 can be understood.

4 is a schematic diagram of experimental data results according to an embodiment of the present invention, which shows measured capacitance values obtained by measuring a plurality of capacitors 40 to be measured by the capacitance measurement system 1 of FIG. 2 (hereinafter referred to as measurement value C2), wherein the actual capacitance value (hereinafter referred to as the target value C1) of the capacitance to be measured 40 is known, and the comparison result between the target value C1 and the measured value C2 is obtained through the computing device 20, and the target value C1 can be For example, an actual capacitance value, or a standard value detected by a standard laboratory, has a high degree of accuracy and can be used as a basis for numerical comparison or reference. Among them, C1 represents the capacitance value of the target value (in picofarad, pF), C2 represents the capacitance value of the measured value (in picofarad, pF), and Vo1 represents the potential of the first output signal (in volts, V), Vo2 represents the potential of the second output signal (in volts, V), Vo3 represents the potential of the third output signal (in volts, V), Av1 represents the first amplification gain, Av2 represents the second amplification gain, and Freq represents the input signal The frequency of Vin (unit is Hertz, Hz), and Xc represents the reactance value (unit is ohm, ohm) of the capacitor 40 to be measured.

Next, the circuit structure of FIG. 2 is used with parameter setting, and the actual calculation method of the present invention is further described with reference to the data of FIG. 4 . The AC power source 30 in FIG. 2 can be set to 0.2 (V), the first resistor 16 can be set to 25000 (ohm), and the second resistor 17 can be set to 5000 (ohm).

As shown in FIG. 4 , when the target value C1 of the capacitance to be measured 40 is 33 (pF), the frequency of the input signal Vin provided by the AC power source 30 is set to 1091000 (Hz). When the first switch 11 is turned on and the other switches are turned off, the computing device 20 detects that the first output signal Vo1 is 0.194 (V). When the second switch is turned on and the other switches are turned off, the computing device 20 detects that the second output signal Vo2 is 1.19 (V). When the second switch 12 and the third switch 13 are turned on and the first switch 11 is turned off, the computing device 20 detects that the third output signal Vo3 is 2.292 (V). Afterwards, the computing device 20 calculates the first amplification gain (ie, Av1=Vo2/Vo1=1.19/0.194=6.134) according to the formula (1), and it is known from the above formula that the first amplification gain Av1 is about 6.134, and the computing device 20 according to Formula (3) calculates the second amplification gain (ie, Av2=Vo3/Vo1=2.292/0.194=11.8144). From the above formula, it is known that the second amplification gain Av2 is about 11.814. After that, the computing device 20 calculates the reactance value Xc according to the formula (4) (that is, Xc=R1/(Av2-Av1)=25000/(11.814-6.134)=4401.089), and the reactance of the capacitor 40 to be measured is known from the above formula The value Xc was 4401.089 (ohm). After that, the calculation device 20 calculates the measured value C2 according to the formula (5) (ie, C2=1/(2 π fXc)=1/(2 π.1091000.4401.088929=33.163.10 ⁻¹² ), so the capacitance to be measured 40 The measured value C2 is about 33.163 (pF). Accordingly, the error value between the target value C1 of the capacitance to be measured 40 and the measured value C2 can be calculated (ie |(C1-C2)|/C1=| (33.10 ^-12 -33.163.10 ^-12 )|/33.10 ^-12 =0.00494), it is known from the above formula that the error value between the target value C1 of the capacitor 40 to be measured and the measured value C2 is about 0.494%.

And when the target value C1 of the capacitance to be measured 40 is 305 (pF), the frequency of the input signal Vin provided by the AC power source 30 is set to 329000 (Hz). When the first switch 11 is turned on and the other switches are turned off, the computing device 20 detects that the first output signal Vo1 is 0.194 (V). When the second switch is turned on and the other switches are turned off, the computing device 20 detects that the second output signal Vo2 is 1.19 (V). When the second switch 12 and the third switch 13 are turned on and the first switch 11 is turned off, the computing device 20 detects that the third output signal Vo3 is 4.24 (V). After that, the computing device 20 calculates the first amplification gain Av1 to be about 6.134 and the second amplification gain Av2 to be about 21.856 according to the formulas (1), (3), (4) and (5), and the reactance value Xc of the capacitor 40 to be measured. about 1590.164 (ohm), and the measured value C2 of the capacitance to be measured 40 is about 304.371 (pF), wherein the error value of the target value C1 of the capacitance to be measured 40 and the measured value C2 is about 0.206%.

When the target value C1 of the capacitance under test 40 is 557 (pF), the frequency of the input signal Vin provided by the AC power source 30 is set to 228000 (Hz). When the first switch 11 is turned on and the other switches are turned off, the computing device 20 detects that the first output signal Vo1 is 0.194 (V). When the second switch is turned on and the other switches are turned off, the second output signal Vo2 is 1.19 (V). When the second switch 12 and the third switch 13 are turned on, and the first switch 11 is turned off, the third output signal Vo3 is 4.24 (V). Afterwards, the computing device 20 calculates that the first amplification gain Av1 is about 6.134 and the second amplification gain Av2 is about 26.082 according to the formulas (1), (3), (4) and (5), and the reactance value Xc of the capacitor 40 to be measured is calculated. is about 1253.23 (ohm), and the measured value C2 of the capacitance to be measured 40 is about 557.282 (pF), wherein the error value between the target value C1 of the capacitance to be measured 40 and the measured value C2 is about 0.051%.

When the target value C1 of the capacitance under test 40 is 792 (pF), the frequency of the input signal Vin provided by the AC power source 30 is set to 184000 (Hz). When the first switch 11 is turned on and the other switches are turned off, the computing device 20 detects that the first output signal Vo1 is 0.194 (V). When the second switch is turned on and the other switches are turned off, the second output signal Vo2 is 1.19 (V). When the second switch 12 and the third switch 13 are turned on, and the first switch 11 is turned off, the third output signal Vo3 is 5.63 (V). Then, the computing device 20 calculates the first amplification gain Av1 to be approximately 6.134 and the second amplification gain Av2 to be approximately 29.021 according to the equations (1), (3), (4) and (5), and the reactance value Xc of the capacitor 40 to be measured. It is about 1092.342 (ohm), and the measured value C2 of the capacitance to be measured 40 is about 792.253 (pF), wherein the error value between the target value C1 of the capacitance to be measured 40 and the measured value C2 is about 0.032%.

As shown in FIG. 4 , the error between the measured value displayed by each set of experimental data and the target value is less than 1%, which shows that the capacitance measurement system 1 of the present invention has good accuracy.

In addition, the measurement circuit 10 of the present invention may have different implementations. FIG. 5 is a circuit diagram of the measurement circuit 10 according to the second embodiment of the present invention, and FIG. 6 is a circuit diagram of the measurement circuit 10 according to the third embodiment of the present invention. Please refer to FIGS. 1 to 4 at the same time.

As shown in FIG. 2 , FIG. 5 and FIG. 6 , the measurement circuit 10 of the second embodiment ( FIG. 5 ) and the third embodiment ( FIG. 6 ) is roughly similar to the first embodiment ( FIG. 2 ), so the following is only for the Differences are explained.

First, the structure part will be described.

Regarding the structure of the second embodiment ( FIG. 5 ), compared with the first embodiment, the measurement circuit 10 of the second embodiment further includes a fourth switch 18 and a fifth switch 19 . In addition, the third switch 13 of the second embodiment is indirectly connected to the capacitor to be measured 40 . For example, one end of the fourth switch 18 can be electrically connected to the second end 13 b of the third switch 13 , and the fourth switch 18 The other end of the fifth switch 19 can be electrically connected to a reference capacitor 50, one end of the fifth switch 19 can be electrically connected to the second end 13b of the third switch 13, and the other end of the fifth switch 19 can be electrically connected to the capacitor to be measured 40 is electrically connected, so that the third switch 13 and the fourth switch 18 and the fifth switch 19 are respectively electrically connected in series. In one embodiment, the conduction of the fourth switch 18 and the fifth switch 19 can also be controlled by an external control element (not shown in the figure), but it is not limited thereto.

Regarding the structure of the third embodiment ( FIG. 6 ), compared with the first embodiment, the measurement circuit 10 of the third embodiment ( FIG. 6 ) further includes a fourth switch 18 . In the third embodiment, the second end 13 b of the third switch 13 is electrically connected to the capacitor to be measured 40 , for example, directly connected, and one end of the fourth switch 18 may be electrically connected to the first end 13 a of the third switch 13 Connected, the other end of the fourth switch 18 can be electrically connected to a reference capacitor 50 , so that the third switch 13 , the capacitor under test 40 , the fourth switch 18 and the reference capacitor 50 form a parallel circuit. The electrical connection of the capacitor under test 40 is controlled by the third switch 13, and the electrical connection of the reference capacitor 50 is controlled by the fourth switch 18, so that the circuit structure is simple and the cost of circuit manufacturing is reduced.

In an embodiment of FIG. 5 or FIG. 6 , the reference capacitor 50 and the capacitor to be measured 40 may be of the same specification (eg, have the same capacitance value level or the same capacitance value level interval, but not limited thereto). In addition, refer to The target value of the capacitor 50 (eg, the actual capacitance value) can be a known parameter, and the target value of the reference capacitor 50 is, for example, a standard value detected by a standard laboratory, and has a high degree of accuracy, so that the reference capacitor 50 can be used as a comparison or reference benchmark. Therefore, the reference capacitor 50 can be used as a reference for the measurement result of the capacitance measurement system 1 .

Accordingly, before the measurement of the capacitance to be measured 40 is performed, the measurement circuit 10 of FIG. 5 or FIG. 6 can measure the reference capacitance 50 first, and adjust the most suitable value according to the measured value of the reference capacitance 50 and the target value. The frequency of the input signal Vin, and then the measurement of the capacitance to be measured 40 is performed. Next, the details of the operation of the second embodiment and the third embodiment will be described.

In the second embodiment ( FIG. 5 ), during the first period, the first switch 11 is turned on, and the other switches 12 , 13 , 18 , and 19 are turned off. At this time, the measurement circuit 10 can output the first output signal to the calculation device 20. In the second period, the second switch 12 is turned on, and the other switches 11, 13, 18, and 19 are turned off. At this time, the measurement circuit 10 can output the first output signal to the computing device 20, and the computing device 20 can therefore calculate The first amplification gain of the operational amplifier 14 . During the third period, the second switch 12 , the third switch 13 and the fourth switch 18 are turned on, and the other switches 11 and 19 are turned off. At this time, the measurement circuit 10 can output the third output signal to the computing device 20 . The computing device 20 can thus calculate the second amplification gain of the operational amplifier 14 and further calculate a measured value of the reference capacitor 50 .

Moreover, in the third embodiment (FIG. 6), during the first period, the first switch 11 is turned on, and the other switches 12, 13, and 18 are turned off. At this time, the measurement circuit 10 can output the first output signal to the calculation device 20. In the second period, the second switch 12 is turned on, and the other switches 11 , 13 , and 18 are turned off. At this time, the measurement circuit 10 can output the first output signal to the computing device 20 , and the computing device 20 can therefore calculate the operational amplifier. 14 the first amplification gain. During the third period, the second switch 12 and the fourth switch 18 are turned on, and the other switches 11 and 13 are turned off. At this time, the measurement circuit 10 can output the third output signal to the computing device 20, and the computing device 20 can therefore calculate The second amplification gain of the operational amplifier 14 is obtained, and then a measured value of the reference capacitor 50 is calculated. The third embodiment can have fewer switches, has a simple structure, and can reduce circuit design costs.

Afterwards, the current accuracy of the capacitance measurement system 1 can be known by comparing the measured value of the reference capacitance 50 with the target value. In one embodiment, by modulating the frequency of the input signal Vin provided by the AC power source 30 , the accuracy of the capacitance measuring system 1 can be adjusted. In one embodiment, according to the difference between the measured value of the reference capacitor 50 and the target value, the frequency of the input signal Vin is continuously modulated, so as to find the frequency corresponding to the smallest difference between the measured value and the target value, wherein This frequency can be regarded as a frequency suitable for the specification of the reference capacitor 50 or the capacitor 40 to be measured. After the appropriate frequency is determined, the measurement of the capacitance to be measured 40 can be performed.

In addition, in one embodiment, the capacitance measurement system 1 can automatically perform the aforementioned steps of frequency modulation and finding a suitable frequency. For example, the capacitance measurement system 1 may include a controller (not shown in FIG. 5 and FIG. 6 ), a memory A body (not shown in FIGS. 5 and 6 ) and a processor (not shown in FIGS. 5 and 6 ), wherein the controller can be used to control the AC power source 30 to modulate the frequency of the input signal Vin within a specific period or a preset number of times , the computing device 20 can compare the difference between the measured value of each frequency and the target value, the memory can record each comparison result, and the processor can select the frequency corresponding to the minimum difference result from the comparison results as the frequency With a suitable frequency, the AC power supply 30 outputs an output signal with a suitable frequency.

In one embodiment, the capacitance measurement system 1 stores capacitance value or capacitance value interval data corresponding to the frequency of the input signal Vin. When the target value C1 of the reference capacitor 50 is a known parameter, the target value of the reference capacitor 50 is The value C1 is input into the capacitance measuring system 1, and the AC power source 30 can generate a suitable frequency corresponding to the target value of the reference capacitor 50. The setting of the suitable frequency can be as follows: First, the AC power source 30 provides any The input signal Vin of the desired frequency, when the first switch 11 is turned on and the other switches are turned off, the computing device 20 detects the first output signal Vo1, and when the second switch is turned on, the rest of the switches are turned off When the computing device 20 detects the second output signal Vo2, when the second switch 12, the third switch 13 and the fourth switch 18 are turned on, and the first switch 11 and the fifth switch 19 are turned off, The computing device 20 detects the third output signal Vo3, and then the computing device 20 calculates the first amplification gain Av1 and the second amplification gain Av2 according to the equations (1) and (3), and the computing device 20 calculates the first amplification gain Av1, The reactance value of the reference capacitor 50 (eg, Xc=R1/(Av2−Av1)) is calculated by the second amplification gain Av2 and the formulas (2) and (4).

Since the target value of the reference capacitor 50 is a known parameter, the reactance value of the reference capacitor 50 is also calculated, and the appropriate frequency f=1/(2 π C1Xc) provided by the AC power supply 30 can be derived by formula (5), The above calculation can be performed by the processor (not shown) in the capacitance measurement system 1, and then the capacitance measurement system 1 uses a suitable frequency as the input signal Vin of the AC power supply 30, and refers to the target value C1 of the capacitor 50 and the corresponding AC power supply. The appropriate frequency provided by 30 can be stored in the memory (not shown in the figure) of the capacitance measurement system 1, so that when the same capacitance value or capacitance value range is subsequently input, the controller of the capacitance measurement system 1 (not shown in the figure) ) can control the AC power supply 30 to generate an input signal Vin with a suitable frequency corresponding to the input capacitance value. The above-mentioned method of obtaining the frequency of the input signal Vin has the advantage of quickly obtaining the frequency according to the corresponding capacitance value, and the measurement error of the capacitance measurement system 1 Has a certain accuracy.

In addition, the method of obtaining the frequency of the input signal can be further matched with the method in the previous embodiment, that is, after obtaining the basic value of the frequency adjustment of the input signal Vin of the AC power source 30 by calculation, within a specific period or at a preset time The AC power source 30 is controlled to modulate the frequency of the input signal Vin under the number of times, and then the measured value of the reference capacitor 50 is obtained. The computing device 20 then compares the difference between the measured value of each frequency and the target value, and the memory can record each After the comparison results, the processor selects the frequency of the input signal Vin corresponding to the result with the smallest difference as the appropriate frequency from the comparison results. Because there may be a register in the measurement circuit 10 In order to reduce the influence of parasitic elements on the measurement circuit 10, the measurement circuit 10 is affected by the control circuit 10 within a certain period or at a preset number of times. The frequency of the input signal Vin is modulated by the power supply 30, and the frequency of the output of the AC power supply 30 suitable for the reference capacitor 50 or the capacitor to be measured 40 is further obtained by adjusting the frequency, so that the measurement error of the capacitance measurement system 1 is minimized, and the AC The frequency acquisition process of the power source 30 has the advantages of both efficiency and accuracy.

FIG. 7 is a graph of experimental data of frequency modulation of an input signal according to an embodiment of the present invention.

As shown in FIG. 7 , when the target value C1 of the reference capacitor 50 is 33 (pF), when the frequency of the input signal Vin is not adjusted to an appropriate frequency (for example, when the frequency is 1,000,000 Hz), the measured value of the reference capacitor 50 C2 is 34.847 (pF), and the error value between the measured value C2 and the target value C1 is about 5.597%. When the frequency of the input signal Vin is a suitable frequency (for example, when the frequency is 1090000 Hz), the measured value C2 of the reference capacitor 50 is 33.133 (pF), and the error value between the measured value C2 and the target value C1 is about 0.403%.

Also as shown in FIG. 7 , when the target value C1 of the reference capacitor 50 is 305 (pF), and the frequency of the input signal Vin is not adjusted to an appropriate frequency (for example, when the frequency is 300,000 Hz), the reference capacitor 50 has a The measured value C2 is 281.261 (pF), and the error value between the measured value C2 and the target value C1 is about 7.783%. And when the frequency of the input signal Vin is a suitable frequency (for example, when the frequency is 333000Hz), the measured value C2 of the reference capacitor 50 is 305.437 (pF), so the error value between the measured value C2 and the target value C1 is about is 0.143%.

As shown in FIG. 7 , when the target value C1 of the reference capacitor 50 is 557 (pF), and the frequency of the input signal Vin is not adjusted to an appropriate frequency (for example, when the frequency is 200,000 Hz), the reference capacitor 50 has a The measured value C2 is 505.614 (pF), and the error value between the measured value C2 and the target value C1 is about 9.225%. And when the frequency of the input signal Vin is a suitable frequency (for example, when the frequency is 230000Hz), the reference voltage The measured value C2 of the capacitor 50 is 557.281 (pF), so the error value between the measured value C2 and the target value C1 is about 0.05%.

Accordingly, each set of experimental data shows that when the frequency of the input signal Vin is adjusted to an appropriate frequency, the error between the measured value and the target value can be greatly reduced. It can be seen from this that modulating the frequency of the input signal Vin can indeed change the accuracy of the capacitance measuring system 1 .

By setting the appropriate frequency mechanism, the influence of parasitic capacitance in the measurement environment can be greatly reduced. In addition, through frequency modulation, the capacitance measurement system 1 can support the measurement of capacitance values with smaller capacitance (eg, pF level), thus solving the problem of capacity limitation in the prior art for measuring capacitance values.

It is verified by the above experiments that the appropriate frequency can indeed make the error value between the measured value C2 of the reference capacitor 50 and the target value C1 less than a predetermined value (eg, less than 1%). After that, the measurement of the capacitor under test 40 with the same specification as the reference capacitor 50 can be performed according to the appropriate frequency. Next, the details of measuring the capacitance to be measured 40 in the second embodiment ( FIG. 5 ) and the third embodiment ( FIG. 6 ) will be described.

In the second embodiment, after the appropriate frequency is determined, the measurement circuit 10 can output the corresponding first output signal and the second output signal. After that, the second switch 12 , the third switch 13 and the fifth switch 19 can be turned on, while the other switches 11 and 18 are turned off. At this time, the measurement circuit 10 can output the third output signal to the computing device 20 to calculate The device 20 can calculate the second amplification gain of the operational amplifier 14 and further calculate the capacitance value of the capacitor 40 to be measured.

Furthermore, in the third embodiment, after the appropriate frequency is determined, the measurement circuit 10 can output the corresponding first output signal and the second output signal. After that, the second switch 12 and the third switch 13 can be turned on, while the other switches 11 and 18 are turned off. At this time, the measurement circuit 10 can output the third output signal to the computing device 20, and the computing device 20 can calculate the operation The second amplification gain of the amplifier 14 is used to calculate the capacitance value of the capacitor 40 to be measured.

FIG. 8 is an experimental data diagram of the capacitance to be measured corresponding to a suitable frequency according to an embodiment of the present invention.

As shown in FIG. 8 , the measurement circuit 10 adopts the circuit design of the second embodiment or the third embodiment, and the capacitance to be measured 40 adopts a capacitance with a known actual capacitance value (hereinafter referred to as the target value C1 ), so as to facilitate the calculation of the target The error value between the value C1 and the measured value C2. In addition, the values of the capacitors 40 to be tested are selected as 33 (pF), 305 (pF) and 557 (pF) respectively, so as to meet the conditions of the same specifications as the reference capacitors 50 and match the target value C1 of the reference capacitors 50 in FIG. 7 . The corresponding appropriate frequency is calculated by the measurement circuit 10 to obtain the measurement value C2 of the capacitance to be measured, and the calculation device 20 obtains the error value result between the target value C1 and the measurement value C2.

Also as shown in FIG. 8 , when the target value C1 of the capacitor under test 40 is 33 (pF), according to the results in FIG. 7 , a reference capacitor 50 with the same specifications as the capacitor under test 40 is used (the target value C1 is also 33 (pF) ) to obtain a suitable frequency (eg, when the frequency is 1090000 Hz) as the input signal Vin, the measured value C2 of the capacitor 40 to be measured is 33.193 (pF), and the error value between the measured value C2 and the target value C1 is about 0.585%. By selecting a suitable frequency, the result of the measurement circuit 10 in detecting the capacitance to be measured 40 will be more accurate.

Also as shown in FIG. 8 , when the target value C1 of the capacitor under test 40 is 305 (pF), according to the results in FIG. 7 , the reference capacitor 50 with the same specifications as the capacitor under test 40 is used (the target value C1 is also 305 (pF) ) to obtain a suitable frequency (eg, when the frequency is 333000 Hz) as the input signal Vin, the measured value C2 of the capacitor 40 to be measured is 306.432 (pF), and the error value between the measured value C2 and the target value C1 is about 0.470%. By selecting a suitable frequency, the result of the measurement circuit 10 in detecting the capacitance to be measured 40 will be more accurate.

Also as shown in FIG. 8 , when the target value C1 of the capacitor under test 40 is 557 (pF), according to the result of FIG. 7 , the reference capacitor 50 with the same specifications as the capacitor under test 40 is used (the target value C1 is also 557 (pF). ) to obtain a suitable frequency (for example, when the frequency is 230000Hz) as the input signal Vin, the measured value C2 of the capacitor 40 to be measured is 560.161 (pF), and the error value between the measured value C2 and the target value C1 is about 0.568%. By selecting a suitable frequency, the result of the measurement circuit 10 in detecting the capacitance to be measured 40 will be more accurate.

Accordingly, through the above experiments, it is known that the capacitors 40 to be measured of different specifications can be connected to the measurement circuit 10 through the reference capacitor 50 of the same specification, and the input signal Vin can be modulated to obtain a suitable frequency, and then the appropriate frequency can be obtained. The input signal is applied to the capacitors 40 under test of the same specification, so that the measurement value C2 of each capacitor under test 40 detected by the measurement circuit 10 can be maintained below a predetermined error value (for example, the error value is less than 1%), and then The result of detecting the capacitance to be measured 40 by the measurement circuit 10 is more accurate.

In addition, when the accuracy of the capacitance measurement system of the present invention needs to be adjusted, the user only needs to adjust the frequency of the input signal of the AC power supply, compared to the situation in the prior art where a large number of parameters must be adjusted to adjust the accuracy , the present invention can be highly convenient in use.

Accordingly, the present invention provides a capacitance measurement system, a measurement circuit and a computing device, which can provide high-accuracy measurement results and solve the problems of the prior art.

The above-mentioned embodiments are only examples for convenience of description, and the scope of the claims claimed in the present invention should be based on the scope of the patent application, rather than being limited to the above-mentioned embodiments.

1: Capacitance measurement system

10: Measurement circuit

IN: circuit input

OUT: circuit output

11~13: Switcher (first switcher ~ third switcher)

14: Operational Amplifier

20: Computing Devices

30: AC power

40: Capacitance to be measured

Claims (20)

A capacitance measurement system, comprising: an AC power supply (30); a measurement circuit (10), comprising a circuit input end (IN), a circuit output end (OUT), an operational amplifier (14) and at least one switch a device (13), wherein the AC power supply (30) is electrically connected to the circuit input terminal (IN), the at least one switch (13) is electrically connected to a capacitor to be measured (40); and a computing device (20) ), electrically connected with the circuit output terminal (OUT); wherein, when the at least one switch (13) is disconnected, the measuring circuit (10) outputs at least one output signal (Vo1, Vo2), and the When at least one switch (13) is turned on, the measuring circuit (10) outputs another output signal (Vo3), and the calculating device (20) calculates the operational amplifier according to the output signals (Vo1, Vo2, Vo3) (14) a first amplification gain (Av1) and a second amplification gain (Av2), and the capacitance to be measured (40) is calculated according to the first amplification gain (Av1) and the second amplification gain (Av2) A capacitance value (C1) of . The capacitance measurement system according to claim 1, wherein the measurement circuit (10) comprises a first switch (11), a second switch (12) and a third switch (13), and the The third switch (13) is electrically connected to the capacitor to be measured (40), wherein the AC power supply (30) is connected to a first input terminal ( 14a) and a first terminal (11a) of the first switch (11) are electrically connected, and an output terminal (14c) of the operational amplifier (14) is respectively connected with a first terminal (11a) of the second switch (12) The terminal (12a) is electrically connected to a first terminal (13a) of the third switch (13), and a second terminal (13b) of the third switch (13) is used for connecting with the capacitor to be measured (40). ) is electrically connected, a second end (11b) of the first switch (11) and a second end (12b) of the second switch (12) are respectively electrically connected to the circuit output end (OUT) . The capacitance measurement system according to claim 2, wherein the measurement circuit (10) further comprises a first resistor (16) and a second resistor (17), and the output terminal ( 14c) is electrically connected to the second resistor (17) and the third switch (13) through the first resistor (16). The capacitance measurement system of claim 3, wherein the operational amplifier (14) further comprises a second input terminal (14b), and the second input terminal (14b), the first resistor (16), the first Two resistors (17) and the third switch (13) are electrically connected to a node (B) on the measurement circuit (10). The capacitance measurement system according to claim 2, wherein the measurement circuit (10) further comprises a rectifier (15), and the second end (11b) of the first switch (11) and the second switch The second end (12b) of the rectifier (12) is electrically connected to the circuit output end (OUT) through the rectifier (15), respectively. The capacitance measurement system according to claim 2, wherein during a first period, the first switch (11) is turned on, and the circuit output terminal (OUT) outputs a first output signal (Vo1) to the computing device ( 20), and in a second period, the second switch (12) is turned on, the circuit output terminal (OUT) outputs a second output signal (Vo2) to the computing device (20), wherein the computing device (20) ) calculates the first amplification gain (Av1) according to the first output signal (Vo1) and the second output signal (Vo2). The capacitance measurement system according to claim 6, wherein during a third period, the second switch (12) and the third switch (13) are turned on, and the circuit output terminal (OUT) outputs a third output a signal (Vo3) to the computing device (20), wherein the computing device (20) calculates the second amplification gain (Av2) according to the first output signal (Vo1) and the third output signal (Vo3), and the The calculating device (20) calculates a reactance value (Xc) of the capacitor to be measured (40) according to the first amplification gain (Av1) and the second amplification gain (Av2), and calculates according to the reactance value (Xc) The capacitance value (C1) of the capacitance to be measured (40). The capacitance measurement system according to claim 2, further comprising a fourth switch (18) electrically connected to a reference capacitor (50), and the third switch (13) and the fourth switch (18) Electrically connected in series, or the first end (13a) of the third switch (13) is electrically connected with a first end of the fourth switch (18), the fourth switch A second end of the device (18) is electrically connected to the reference capacitor (50), so that the third switch (13), the capacitor to be measured (40), the fourth switch (18) and the reference The capacitor (50) forms a parallel circuit. A measurement circuit is arranged in a capacitance measurement system (1), and comprises: a circuit input terminal (IN) electrically connected with an AC power supply (30) of the capacitance measurement system (1); a circuit an output end (OUT), electrically connected to a computing device (20) of the capacitance measurement system (1); an operational amplifier (14); and at least one switch (13) electrically connected to the operational amplifier 14 wherein the AC power supply (30) is electrically connected to the operational amplifier (14) through the circuit input terminal (IN), and the at least one switch (13) is electrically connected to a capacitor to be measured (40). The measurement circuit according to claim 9, wherein when the at least one switch (13) is disconnected, the measurement circuit (10) outputs at least one output signal (Vo1, Vo2), and the at least one switch (13) is switched off. (13) When turned on, the measuring circuit (10) outputs another output signal (Vo3), wherein the calculating device (20) calculates the output signal (Vo1, Vo2, Vo3) of the operational amplifier (14) according to the output signals (Vo1, Vo2, Vo3). A first amplification gain (Av1) and a second amplification gain (Av2), and a capacitance value of the capacitor to be measured (40) is calculated according to the first amplification gain (Av1) and the second amplification gain (Av2) (C1). The measurement circuit according to claim 10, further comprising a first switch (11), a second switch (12), and the switch (13) electrically connected to the capacitor to be measured (40) It is a third switch (13), wherein the AC power supply (30) is connected to a first input terminal (14a) of the operational amplifier (14) and the first switch ( A first end (11a) of 11) is electrically connected, an output end (14c) of the operational amplifier (14) is respectively connected with a first end (12a) of the second switch (12) and the third switch A first end (13a) of the switch (13) is electrically connected, a second end (13b) of the third switch (13) is used for electrical connection with the capacitor (40) to be measured, and the first switch A second end (11b) of the switch (11) and a second end (12b) of the second switch (12) are respectively electrically connected to the circuit output end (OUT). The measurement circuit according to claim 11, further comprising a first resistor (16) and a second resistor (17), and the output end (14c) of the operational amplifier (14) passes through the first resistor (16) ) is electrically connected to the second resistor (17) and the third switch (13). The measurement circuit as claimed in claim 12, wherein the operational amplifier (14) further comprises a second input terminal (14b), and the second input terminal (14b), the first resistor (16), the second The resistor (17) and the third switch (13) are electrically connected to a node (B) on the measurement circuit (10). The measurement circuit according to claim 11, further comprising a rectifier (15), the second end (11b) of the first switch (11) and the second end of the second switch (12) (12b) are respectively electrically connected to the circuit output terminal (OUT) through the rectifier (15). The measurement circuit of claim 11, wherein during a first period, the first switch (11) is turned on, and the circuit output terminal (OUT) outputs a first output signal (Vo1) to the computing device (20) ), and in a During the second period, the second switch (12) is turned on, and the circuit output terminal (OUT) outputs a second output signal (Vo2) to the computing device (20). The measurement circuit of claim 15, wherein during a third period, the second switch (12) and the third switch (13) are turned on, and the circuit output terminal (OUT) outputs a third output signal (Vo3) to the computing device (20), wherein the measurement circuit (10) calculates the second amplification gain (Av2) according to the first output signal (Vo1) and the third output signal (Vo3). The measurement circuit according to claim 11, further comprising a fourth switch (18) electrically connected to a reference capacitor (50), the third switch (13) and the fourth switch (18) be electrically connected in series, or the first end (13a) of the third switch (13) is electrically connected with a first end of the fourth switch (18), the fourth switch (18) ) is electrically connected to the reference capacitor (50), so that the third switch (13), the capacitor to be measured (40), the fourth switch (18) and the reference capacitor (50) ) to form a parallel circuit. A computing device, set in the capacitance measurement system (1) as claimed in claim 1, for electrically connecting with the circuit output terminal (OUT) of the measurement circuit (10) of the capacitance measurement system (1) connect. The computing device of claim 18, wherein during a first period (T1), the computing device (20) obtains a first output signal (Vo1) from the circuit output terminal (OUT), and during a second period (T2), the computing device (20) obtains a second output signal (Vo2) from the circuit output terminal (OUT), and calculates the The first amplification gain (Av1). The computing device as claimed in claim 18, wherein during a third period (T3), the computing device (20) obtains a third output signal (Vo3) from the circuit output terminal (OUT), and according to the first output The signal (Vo1) and the third output signal (Vo3) calculate the second amplification gain (Av2), and the calculating device (20) according to The first amplification gain (Av1) and the second amplification gain (Av2) calculate a reactance value (Xc) of the capacitor under test (40), and calculate the capacitor under test (40) according to the reactance value (Xc) ) of this capacitance value (C1).

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