TWI778604B - Frame display signal synchronization method, display device and information processing device - Google Patents

Abstract

A frame display signal synchronization method for enabling a plurality of display driving chips in cascade to drive a display panel to display a picture composed of at least one sub-picture, comprising the following steps: connecting the at least one sub-picture in a cascaded manner The display data of the sub-pictures are transmitted from the first display-driving chip of the display-driving chips, wherein a number is attached to the display data of each of the sub-pictures, and at least one of the display-driving chips has the same number. At least one corresponding display driver chip with a matching number reads the display data of a sub-picture according to a matching number; and each of the at least one corresponding display driver chip is matched according to it One of the numbers is delayed by a corresponding time so that the at least one corresponding display driving chip drives the display panel synchronously to display the at least one sub-picture synchronously.

Description

Frame display signal synchronization method, display device and information processing device

The present invention relates to the related field of display technology, and more particularly, to a frame display signal synchronization method applied to a display device including a plurality of display driving chips.

Light-emitting diodes (LEDs) have many advantages such as small size, light weight, long service life, and high luminous efficiency, and have been widely used in lighting devices and display devices. The LED display device is a self-luminous flat display device, which has the advantages of bright colors, wide dynamic range, high brightness, long life and high reliability. Therefore, the LED display device with large screen has been widely used in large squares, commercial advertisements, Sports venues, information dissemination, news releases, stock exchanges, as a public display medium.

FIG. 1 shows a structure diagram of a conventional LED display device with a large-size screen. As shown in FIG. 1, the conventional LED display device 1a includes: an LED display panel 11a, a column driving unit 12a, a row driving unit 13a, and a display control unit 14a, wherein the display control unit 14a is used for controlling the column driving The operation of the unit 12a and the row driving unit 13a. Electronic engineers familiar with the design and manufacture of LED displays must know that the row driving unit 13a usually includes a plurality of display driving chips (ie, row driving chips) 131a, because each display driving chip 131a has a fixed number of driving channels, so each display driving chip 131a has a fixed number of driving channels. The area of the panel that each display driver chip 131 can drive is limited.

When the LED display device 1a with a large screen is used for image display, the display control unit 14a controls all the display driver chips 131a to light up the entire display area of the LED display panel 11a at the same time, or only controls part of the display driver chips according to different image display requirements 131a to light up at least one display area of the LED display panel 11a. Therefore, in order to meet different display driving requirements, as shown in FIG. 1 , in the prior art, a plurality of the display driving chips 131a are firstly cascaded with each other, and a numbered data and a display data are packaged into a display data signal. , serially number each display driving chip 131a, and control each display driving chip 131a to perform the display driving work to which it belongs.

As shown in FIG. 1, the display control unit 14a uses a two-wire transmission protocol to send a display data signal SDI(1) and a clock signal CLK to the display driving chip 131a of number (1), wherein the display data signal SDI(1) 1) Contains number data and display data belonging to each display driver wafer 131a. After receiving the display data signal SDI(1), the display driver chip 131a numbered (1) performs number identification on the display data signal SDI(1), then receives its own display data, and then stores the display data in the Internal shift register, and according to the current display data stored in the display data register to configure the drive parameters, such as configuring the PWM signal.

After that, the display driving chip 131a with the number (1) performs a renumbering process on the display data signal SDI(1) (for example, adding 1 to the original number) to generate a new display data signal SDI(2), and then renumbers the new display data signal SDI(2). The display data signal SDI(2) and the clock signal CLK are sent to the display driving chip 131a of number (2). Continuing, the display driver chip 131a numbered (2) similarly identifies the new display data signal SDI(2) by number, then receives its own display data, and then completes the display data storage and drive parameter configuration actions . And so on, until each display driving chip 131a receives its own display data and completes the configuration of the driving parameters.

FIG. 2 shows an operation timing diagram of a plurality of frame display signals corresponding to a plurality of the display driving chips 131a. It should be noted that, after completing the configuration of the driving parameters, the display driving wafer 131a numbered (1) generates one frame of display signals. Similarly, the display driving chip 131a of number (2) also generates one frame of display signals after completing the configuration of the driving parameters. Therefore, as shown in FIG. 2, the pulse edge (rising edge or falling edge) of the start bit of the frame display signal generated by the display driving chip 131a of number (1) and the display driving chip 131a of number (2) are generated There is a delay time T between the pulse edges of the start bit of the frame display signal. By analogy, the pulse edge (rising edge or falling edge) of the start bit of the frame display signal generated by the display driver chip 131a of number (1) and the frame display signal generated by the display driver chip 131a of number (N) There is a delay time (N-1)*T between the pulse edges of the start bit.

To put it simply, the prior art utilizes the method of integrating the serial number data of the display driver chips 131a and the display data into a display data signal SDI, so as to control each display driver chip 131a to display and drive the LED display panel 11a to meet the requirements of each display driver chip 131a. display requirements of the scene. However, in this way, the frame display signals generated by the display driving chips 131a cannot be synchronized.

It can be seen from the above description that there is an urgent need in the art for a novel frame display signal synchronization method.

The main purpose of the present invention is to provide a frame display signal synchronization method, which is used in a display device including a display panel and L display driver chips cascaded with each other, so that the L display driver chips are connected between the L display driver chips. In the case where N of the display driving chips are selected to perform the display driving of the display panel, the N display driving chips can synchronously generate N frame display signals.

In order to achieve the above object, the present invention proposes an embodiment of the frame display signal synchronization method, which is realized by a display control unit and L display driving chips for driving a display panel, wherein L is a positive integer, and the first One of the display driver chips is coupled to the display control unit, and L of the display driver chips are cascaded with each other; the frame display signal synchronization method includes the following steps:

In the case where N total of the display driver chips are selected to perform the display driving of the display panel, the display driver chip receives a signal transmitted from the display control unit or a preceding display driver chip cascaded therewith. Display data signal; among them, N is a positive integer, and N≦L;

The display driving chip identifies the display data signal by a number, and then receives one of the display data from the display data signal;

The display driver chip performs a numbering process on the display data signal to generate a new display data signal, and then transmits the new display data signal to a subsequent display driver chip cascaded therewith; and

After each display driver chip completes receiving the display data, it then waits for (N-k) delay times to elapse to generate a frame of display signal; wherein, k is a sequence number to which each display driver chip belongs, which is a positive value. Integer and ≧1.

In one embodiment, the aforementioned frame display signal synchronization method of the present invention further includes the following steps: in the case of L=1 and N=1, after the display driver chip has finished receiving the display data, then Generates a frame of display signal.

In one embodiment, the renumbering process is to add 1 to the sequence number, so as to generate a new sequence number corresponding to the subsequent display driver chip.

In order to achieve the above object, the present invention further provides a frame display signal synchronization method, which is used for a plurality of display driving chips in cascade to drive a display panel to display a picture composed of at least one sub-picture, which includes the following steps :

Passing the display data of the at least one sub-picture from the first display driver chip of the display driver chips in a cascaded manner, wherein a number is attached to the display data of each of the sub-pictures , and at least one corresponding display driver chip in the display driver chips that matches at least one of the numbers reads the display data of the sub-picture according to the corresponding number; and

The at least one corresponding display driver chip is delayed by a corresponding time according to one of the corresponding numbers, so that the at least one corresponding display driver chip synchronously drives the display panel to synchronously display the at least one sub-picture.

The present invention also provides a display device, which includes a display panel, a column driving unit, a row driving unit including L display driving chips, and a display control unit, wherein N is an integer, and the first display driving chip is coupled to The display control unit is connected, and the L display driving chips are cascaded with each other; it is characterized in that, the display control unit and the L display driving chips realize a frame display signal synchronization method, and the frame display signal synchronization method includes the following steps :

In the case where N total of the display driver chips are selected to perform the display driving of the display panel, the display driver chip receives a signal transmitted from the display control unit or a preceding display driver chip cascaded therewith. Display data signal; among them, N is a positive integer, and N≦L;

The display driving chip identifies the display data signal by a number, and then receives one of the display data from the display data signal;

The display driver chip performs a numbering process on the display data signal to generate a new display data signal, and then transmits the new display data signal to a subsequent display driver chip cascaded therewith; and

After each display driver chip completes receiving the display data, it then waits for (N-k) delay times to elapse to generate a frame of display signal; wherein k is a sequence to which the selected display driver chip belongs number, and k≧1.

In an embodiment of the aforementioned display device of the present invention, the frame display signal synchronization method further includes the following steps: in the case of L=1 and N=1, the display driver chip completes the reception of the display data After that, the system then generates a frame of display signal.

In one embodiment, the renumbering process is to add 1 to the sequence number, so as to generate a new sequence number corresponding to the subsequent display driver chip.

In one embodiment, the display panel is selected from a liquid crystal display panel, a light-emitting diode display panel, a quantum dot light-emitting diode display panel, a micro-light-emitting diode display panel, and a sub-millimeter light-emitting diode display panel. , an organic light emitting diode display device, and a perovskite-based LED (Perovskite LED, PVSK LED) display panel in the group consisting of a flat display panel.

In one embodiment, the display panel has X×Y sub-pixels, the display driving chip has Y/L driving channels, and both X and Y are positive integers.

In order to achieve the above object, the present invention further provides a display device having a display panel and a plurality of display driver chips in cascade for driving the display panel, and the plurality of display driver chips in cascade are used for driving the display panel. Execute a frame display signal synchronization method to drive the display panel to display a picture composed of at least one sub-picture, and the method includes the following steps:

Passing the display data of the at least one sub-picture from the first display driver chip of the display driver chips in a cascaded manner, wherein a number is attached to the display data of each of the sub-pictures , and at least one corresponding display driver chip in the display driver chips that matches at least one of the numbers reads the display data of the sub-picture according to the corresponding number; and

The at least one corresponding display driver chip is delayed by a corresponding time according to one of the corresponding numbers, so that the at least one corresponding display driver chip synchronously drives the display panel to synchronously display the at least one sub-picture.

The present invention also provides an information processing device including the display device of the present invention as described above.

In one embodiment, the information processing device is selected from the group consisting of a video wall, a smart TV, a smart phone, a tablet computer, a notebook computer, an all-in-one computer, a desktop computer, and an industrial computer. an electronic device.

In order to enable your examiners to further understand the structure, characteristics, purpose, and advantages of the present invention, drawings and detailed descriptions of preferred embodiments are attached as follows.

The present invention mainly proposes a frame display signal synchronization method, which is used in a display device including a display panel, a display controller, and L display driving chips cascaded with each other, so that the display controller can The two-wire transmission protocol (SDI+CLK) is used to control N (N≦L) of the L display driver chips to synchronously generate N frame display signals, so as to simultaneously light up the display panel according to different image display requirements. The entire display area, or at least one display area of the display panel is simultaneously lit, so that the display device can provide high-quality image display.

FIG. 3 shows a structural diagram of a display device applying the frame display signal synchronization method of the present invention. As shown in FIG. 1 , the display device 1 includes: a display panel 11 , a column driving unit 12 , a row driving unit 13 , and a display control unit 14 , wherein the display panel 11 includes X×Y sub-pixels, and the row driving unit 11 includes X×Y sub-pixels. The unit 13 includes L display driving chips 131 , and X, Y, and L are all positive integers. In more detail, each of the row driving wafers 131 has J driving channels, and J=Y/L.

FIG. 4 shows a flow chart of a frame display signal synchronization method according to the present invention. In the case of applying the method of the present invention, each of the display driver chips 131 shown in FIG. 3 will perform the following steps:

S1: Under the condition that N total of the display driver chips 131 are selected to execute the display driving of the display panel 11, the display driver chips 131 are received and transmitted from the display control unit 14 or a preceding one cascaded therewith. A display data signal of the level display driver chip 131;

S2: The display driving chip 131 identifies the display data signal by a number, and then receives one of the display data from the display data signal; wherein, N is a positive integer, and N≦L;

S3: The display driver chip 131 performs a numbering process on the display data signal to generate a new display data signal, and then transmits the new display data signal to a subsequent display driver chip 131 cascaded therewith; and

S4: After each display driver chip 131 finishes receiving the display data, it then waits for (N-k) delay times to elapse to generate a frame of display signal; where k is a sequence number to which each display driver chip 131 belongs , which is a positive integer and ≧1.

To put it simply, the L display driving chips 131 shown in FIG. 3 basically perform four operations: (A) number recognition, (B) data reception, (C) renumbering processing, and (D) display driving. In step S1 and step S2, each of the display driving chips 131 executes the operations of number recognition and data reception. In addition, in step S3, each of the display driving chips 131 performs a numbering process on the display data signal to generate a new display data signal, and then transmits the new display data signal to a cascaded one after the display data signal. level display driver wafer 131 .

For example, in order to simultaneously light up all the display areas of the display panel 11 according to the image display requirements, the display control unit 14 selects N=L display driving chips 131 to perform the display driving work of the display panel 11 . In this application, after receiving the display data signal SDI(1) transmitted by the display control unit 14, the first display driver chip 131 performs number identification on the display data signal SDI(1), and then receives the display data signal SDI(1). The display data belongs to its own, and then the display data is stored in the internal shift register, and the drive parameter configuration is performed according to the current display data stored in the display data register, such as configuring the PWM signal. It should be understood that in this application, the sequence number of the M-th display driving chip 131 is 1 (ie, k=1).

Afterwards, the display driving chip 131 of the first (ie, number 1) renumbers the display data signal SDI(1) to generate a new display data signal SDI(2), and then renumbers the new display data signal SDI(2). (2) and the clock signal CLK is sent to the display driving chip 131 of number (2). For example, if the sequence number of the first display driver chip 131 is 1, the renumbering process performed by the second display driver chip 131 is to increment its sequence number by 1. It can be understood that after the second display driving chip 131 identifies the new display data signal SDI( 2 ) by number, it will identify the sequence number (ie, k=2) to which it belongs. Next, the display driver chip 131 of the first (ie, number 2) receives its own display data from the new display data signal SDI(2), and then completes the configuration of the display data and driving parameters. And so on, until each display driving chip 131 receives its own display data and completes the configuration of the driving parameters.

In particular, when performing step S4 (that is, performing display driving), each of the display driving chips 131 then waits for (N-k) delay times to elapse after completing the reception of the display data to generate a frame of display signal; Wherein, k is a sequential number to which each display driver chip belongs, and k≧1. For example, if the row driving unit 13 only includes two display driving chips 131 cascaded with each other (ie, N=2), in order to light up the entire display area of the display panel 11 at the same time, the first display driving chip 131 and the second display driver chip 131 are assigned sequence numbers 1 and 2, respectively. Further, after completing the driving parameter configuration according to the current display data stored in the display data register, the display driving chip 131 numbered 1 generates a frame of display signals after waiting for N-k=2-1=1 delay times to elapse. In addition, after completing the configuration of the driving parameters, the display driving wafer 131 of No. 2 generates a frame of display signals after waiting for the elapse of N-k=2-2=0 delay times. In other words, the display driver chip 131 of No. 2 pulls up the frame display signal immediately after completing the configuration of the driving parameters.

In another exemplary embodiment, if the row driving unit 13 includes three display driving chips 131 cascaded with each other (ie, L=3), in order to light up the entire display area of the display panel 11 at the same time, the first one The third display driver chip 131 and the second display driver chip 131 are assigned sequence numbers 1, 2, and 3, respectively. Afterwards, the display driver chip 131 numbered 1 completes the drive parameter configuration according to the current display data stored in the display data register, and then waits for N-k=3-1=2 delay times to elapse to generate a frame of display signals. In addition, the display driving chip 131 of No. 2 waits for the elapse of N-k=3-2=1 delay time, and then generates a display signal of one frame. Furthermore, the display driving chip 131 of No. 3 generates one frame of display signals after waiting for the elapse of N-k=3-3=0 delay times. In other words, the display driver chip 131 No. 3 pulls up the frame display signal immediately after completing the configuration of the driving parameters.

In yet another exemplary embodiment, if the row driving unit 13 only includes a single display driving chip 131 (ie, L=1), in order to simultaneously light up the entire display area of the display panel 11, the sequence of the display driving chips 131 The number is naturally 1. Afterwards, the display driver chip 131 numbered 1 completes the drive parameter configuration according to the current display data stored in the display data register, and then waits for the elapse of N-k=1-1=0 delay times to generate a frame of display signals.

Therefore, when the frame display signal synchronization method of the present invention is applied, the display control unit 14 can use the two-wire transmission protocol (SDI+CLK) to control the L display driving chips 131 to synchronously generate L frame display signals, thereby The entire display area of the display panel 11 is simultaneously illuminated according to different image display requirements, so that the display device 1 can provide high-quality image display.

FIG. 5 shows a block diagram of the L display driving chips 131 and a display panel applying the frame display signal synchronization method of the present invention. Of course, in the case of applying the frame display signal synchronization method of the present invention, the display control unit 14 can use the two-wire transmission protocol (SDI+CLK) to control N among all the L display driving chips 131 to generate synchronization Signals are displayed in N frames, so that only at least one display area of the display panel 11 is illuminated according to the image display requirement. For example, the M-th, M+1-th, or M+2-th display driving chips 131 are controlled to synchronously generate three frame display signals (ie, N=3), so as to display and drive the display panel 11 to Lights up at least one display area.

It is worth noting that, as shown in FIG. 5 , since the first to M-1 th display driver chips 131 are not selected to perform the display driving work, these display driver chips 131 will not perform number identification and display data reception. , renumbering processing, and display driving.

According to the above description, the M th display driving chip 131 receives the display data signal SDI( 1 ) from the M-1 th display driving chip 131 . After identifying the display data signal SDI( 1 ) by number, the M-th display driver chip 131 receives its own display data, and then stores the display data in the internal shift register. The current display data among them is used to configure the drive parameters, such as configuring the PWM signal. It should be understood that in this application, the sequence number of the M-th display driving chip 131 is 1.

After that, the M-th (ie, number 1) display driving chip 131 renumbers the display data signal SDI( 1 ) to generate a new display data signal SDI( 2 ), and then converts the new display data signal SDI( 2) and the clock signal CLK is sent to the M+1 th display driving chip 131 . That is, the sequence number of the M-th display driving chip 131 is 1, and the sequence number of the M+1-th display driving chip 131 is 2. Next, after the display driving chip 131 of the M+1 th (ie, number 2 ) performs number recognition on the new display data signal SDI( 2 ), it will recognize the sequence number to which it belongs, and then the new display data signal SDI( 2 ) The signal SDI(2) receives its own display data, and finally completes the display data storage and drive parameter configuration. By analogy, until the Mth, M+1th, and M+2th display driving chips 131 all receive their own display data and complete the configuration of the driving parameters.

Next, after completing the driving parameter configuration according to the current display data stored in the display data register, the display driving chip 131 numbered 1 (ie, the Mth) waits for the elapse of N-k=3-1=2 delay times, and generates a frame display signal. And, the display driving chip 131 with the number 2 (ie, the M+1 th) waits for the elapse of N-k=3-2=1 delay time, and then generates a display signal of one frame. Furthermore, the display driving chip 131 with the number 3 (ie, the M+2 th) waits for the elapse of N-k=3-3=0 delay times, and then generates one frame of display signals. In other words, the M+2 th display driving chip 131 pulls up the frame display signal immediately after completing the driving parameter configuration.

That is, the frame display signal synchronization method of the present invention can be used for a plurality of display driving chips in cascade to drive a display panel to display a picture composed of at least one sub-picture, and is characterized by comprising: in a cascaded manner The display data of the at least one sub-picture is transmitted from the first display-driving chip of the display-driving chips, wherein a number is attached to the display data of each of the sub-pictures, and the display At least one corresponding display driver chip in the driver chip that matches at least one of the numbers reads the display data of one of the sub-pictures according to the corresponding one of the numbers; and the at least one corresponding display driver The chips are each delayed by a corresponding time according to one of the corresponding numbers, so that the at least one corresponding display driving chip drives the display panel synchronously to display the at least one sub-picture synchronously.

Thus, the above has completely and clearly explained a frame display signal synchronization method of the present invention; and, through the above, it can be known that the present invention has the following advantages:

(1) The present invention discloses a frame display signal synchronization method, which is applied to a display device including a display panel and L display driver chips that are cascaded with each other, so that among the L display driver chips In the case where N are selected to perform the display driving of the display panel, the N display driving chips can synchronously generate N frame display signals. According to the design of the present invention, in the case of N≧2, after each display driver chip completes receiving the display data belonging to it, it then waits for (N-k) delay times to elapse to generate a frame of display signal; wherein, k is A sequential number to which each display driver chip belongs, which is a positive integer and ≧1.

(2) The present invention also provides a display device, which includes a display panel, a column driving unit, a row driving unit including L display driving chips, and a display control unit; it is characterized in that the display control unit and the L display The driving chip implements the frame display signal synchronization method of the present invention.

(3) The present invention also provides an information processing device having the display device of the present invention as described above. The information processing device is an electronic device selected from the group consisting of video walls, smart TVs, smart phones, tablet computers, notebook computers, all-in-one computers, desktop computers, and industrial computers. device.

It must be emphasized that the above-mentioned disclosure in this case is a preferred embodiment, and any partial changes or modifications originating from the technical ideas of this case and easily inferred by those who are familiar with the art are within the scope of the patent of this case. category of rights.

To sum up, regardless of the purpose, means and effect of this case, it shows that it is completely different from the conventional technology, and its first invention is suitable for practical use, and indeed meets the patent requirements of the invention. Society is to pray for the best.

1a: LED display device 11a: LED display panel 12a: Column driver unit 13a: Row drive unit 131a: Display driver chip 14a: Display Control Unit 1: Display device 11: Display panel 12: Column drive unit 13: Row drive unit 131: Display driver chip 14: Display control unit S1: Under the condition that a total of N of the display driver chips are selected to execute the display driving of the display panel, the display driver chip receives transmission from the display control unit or a previous display driver chip cascaded therewith A display data signal of S2: The display driver chip performs a number identification on the display data signal, and then receives one of the display data from the display data signal S3: The display driver chip performs a numbering process on the display data signal to generate a new display data signal, and then transmits the new display data signal to a subsequent display driver chip cascaded therewith S4: After each of the display driver chips has finished receiving the display data, it then waits for (N-k) delay times to elapse to generate a frame of display signal

FIG. 1 is a schematic diagram of a conventional LED display device with a large-size screen; 2 is a working timing diagram of a plurality of frame display signals corresponding to a plurality of display driving chips included in the LED display device of FIG. 1; 3 is a structural diagram of a display device applying a frame display signal synchronization method of the present invention; 4 is a flowchart of a frame display signal synchronization method according to the present invention; and 5 is a block diagram of L display driving chips and a display panel applying the frame display signal synchronization method of the present invention.

S1: Under the condition that a total of N of the display driver chips are selected to execute the display driving of the display panel, the display driver chip receives transmission from the display control unit or a previous display driver chip cascaded therewith A display data signal of

S2: The display driver chip performs a number identification on the display data signal, and then receives one of the display data from the display data signal

S3: The display driver chip performs a numbering process on the display data signal to generate a new display data signal, and then transmits the new display data signal to a subsequent display driver chip cascaded therewith

S4: After each of the display driver chips has finished receiving the display data, it then waits for (N-k) delay times to elapse to generate a frame of display signal

Claims (12)

A frame display signal synchronization method is realized by a display control unit and L display driving chips for driving a display panel, wherein L is a positive integer, and the first display driving chip is coupled to the display control unit, And the L display driving chips are cascaded with each other; the frame display signal synchronization method includes the following steps: In the case where N total of the display driver chips are selected to perform the display driving of the display panel, the display driver chip receives a signal transmitted from the display control unit or a preceding display driver chip cascaded therewith. Display data signal; among them, N is a positive integer, and N≦L; The display driving chip identifies the display data signal by a number, and then receives one of the display data from the display data signal; The display driver chip performs a numbering process on the display data signal to generate a new display data signal, and then transmits the new display data signal to a subsequent display driver chip cascaded therewith; and After each display driver chip completes receiving the display data, it then waits for (N-k) delay times to elapse to generate a frame of display signal; wherein k is a sequence to which the selected display driver chip belongs number, which is a positive integer and ≧1. The frame display signal synchronization method according to claim 1, further comprising the following steps: In the case of L=1 and N=1, the display driving chip generates a frame of display signals after receiving the display data. The frame display signal synchronization method according to claim 2, wherein the renumbering process is to add 1 to the sequence number to generate a new sequence number corresponding to the subsequent display driver chip. A frame display signal synchronization method, which is used to drive a display panel by a plurality of display driving chips in cascade to display a picture composed of at least one sub-picture, comprising the following steps: Passing the display data of the at least one sub-picture from the first display driver chip of the display driver chips in a cascaded manner, wherein a number is attached to the display data of each of the sub-pictures , and at least one corresponding display driver chip in the display driver chips that matches at least one of the numbers reads the display data of one of the sub-pictures according to the corresponding one of the numbers; and the at least one display driver chip Each of the corresponding display driving chips is delayed by a corresponding time according to the corresponding one of the numbers, so that the at least one corresponding display driving chip drives the display panel synchronously to display the at least one sub-picture synchronously. A display device comprising a display panel, a column of drive units, a row of drive units including L display drive chips, and a display control unit, wherein L is an integer, and the first display drive chip is coupled to the display control unit unit, and the L display driving chips are cascaded with each other; it is characterized in that, the display control unit and the L display driving chips implement a frame display signal synchronization method, and the frame display signal synchronization method includes the following steps: in a total of N When one of the display driver chips is selected to perform the display driving of the display panel, the display driver chip receives a display data signal transmitted from the display control unit or a preceding display driver chip cascaded therewith ; wherein, N is a positive integer, and N≦L; the display driving chip performs a number identification on the display data signal, and then receives one of the display data from the display data signal; the display driving chip displays the display data The data signals are repeatedly numbered to generate a new display data signal, and then the new display data signal is transmitted to a subsequent display driver chip cascaded therewith; and each of the display driver chips completes the display data After receiving, the system then waits for (N-k) delay times to elapse to generate a frame of display signal; wherein k is a sequence number to which the selected display driver chip belongs, k is a positive integer and k≧1. The display device according to claim 5, wherein the frame display signal synchronization method further comprises the following steps: in the case of L=1 and N=1, after the display driver chip finishes receiving the display data, The system then generates a frame of display signal. The display device according to claim 5, wherein the renumbering process is to add 1 to the sequence number to generate a new sequence number corresponding to the subsequent display driver chip. The display device according to claim 6, wherein the display panel is selected from the group consisting of a liquid crystal display panel, a light-emitting diode display panel, a quantum dot light-emitting diode display panel, a micro-light-emitting diode display panel, a sub-millimeter A flat display panel in the group consisting of a light emitting diode display panel, an organic light emitting diode display device, and a perovskite-based LED (Perovskite LED, PVSK LED) display panel. The display device of claim 6, wherein the display panel has X×Y sub-pixels, the display driving chip has Y/L driving channels, and both X and Y are positive integers. A display device, which has a display panel and a plurality of display driving chips in cascade for driving the display panel, the plurality of display driving chips in cascade are used for executing a frame display signal synchronization method to drive The display panel displays a picture composed of at least one sub-picture, and the method includes the following steps: Passing the display data of the at least one sub-picture from the first display driver chip of the display driver chips in a cascaded manner, wherein a number is attached to the display data of each of the sub-pictures , and at least one corresponding display driver chip in the display driver chips that matches at least one of the numbers reads the display data of the sub-picture according to the corresponding number; and The at least one corresponding display driver chip is delayed by a corresponding time according to one of the corresponding numbers, so that the at least one corresponding display driver chip synchronously drives the display panel to synchronously display the at least one sub-picture. An information processing device having the display device described in any one of claim 5 to claim 10. The information processing device of claim 11, wherein the information processing device is selected from the group consisting of video walls, smart TVs, smart phones, tablet computers, notebook computers, all-in-one computers, desktop computers, and An electronic device in a group of industrial computers.

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