TWI777513B - Memory device and fabricating method thereof - Google Patents

Abstract

The present disclosure, in some embodiments, relates to a memory device. In some embodiments, the memory device comprises a substrate and an interconnect structure disposed over the substrate. The interconnect structure comprises stacked interconnect metal layers disposed within stacked interlayer dielectric (ILD) layers. A memory cell is disposed between an upper interconnect metal layer and an intermediate interconnect metal layer. A selecting transistor is connected to the memory cell and disposed between the intermediate interconnect metal layer and a lower interconnect metal layer. By placing the selecting transistor within the back-end interconnect structure between two interconnect metal layers, front-end space is saved, and more integration flexibility is provided.

Description

Memory device and method of manufacturing the same

The present disclosure relates to a memory device, and more particularly, to a memory device having a back-end process transistor.

Today, many modern electronic devices contain electronic memory configured to store data. Electronic memory can be volatile memory or non-volatile memory. Volatile memory stores data when power is supplied, while non-volatile memory stores data when power is removed. Resistive random-access memory is a highly anticipated candidate for next-generation non-volatile memory technology. This is because resistive random access memory offers many advantages, including fast write times, high endurance, low power consumption, and low susceptibility to damage from radiation.

Embodiments of the present disclosure provide a memory device. The above-mentioned memory device includes a substrate and an interconnection structure disposed above the substrate. The interconnect structure includes a plurality of stacked interconnect metal layers disposed in a plurality of stacked interlayer dielectric (ILD) layers. The stacked interconnect metal layers include a lower interconnect metal layer, an intermediate interconnect metal layer, and an upper interconnect metal layer disposed one over the other. The memory cells are disposed between the upper interconnect metal layer and the middle interconnect metal layer. The selection transistor is connected to the memory cell and is disposed between the middle interconnect metal layer and the lower interconnect metal layer. The selection transistor includes a first selector source/drain region and a second selector source/drain region disposed on the selector channel layer. The first selector source/drain region and the second selector source/drain region are separated by sidewall spacers.

Embodiments of the present disclosure provide a memory device. The above-mentioned memory device includes a substrate and an interconnection structure disposed above the substrate. The interconnect structure includes a plurality of interconnect metal layers stacked one above the other and disposed in an interlayer dielectric (ILD) layer. A plurality of memory cells are arranged in an interconnect structure and arranged in an array of columns and rows. The plurality of selection transistors are correspondingly connected to the memory cells. The complex selection transistors are disposed in the interconnection structure and between the lower interconnection metal layer and the upper interconnection metal layer of the interconnection structure.

Embodiments of the present disclosure provide a method for manufacturing a memory device. The above-described fabrication method includes forming a lower interconnect metal layer over a substrate surrounded by an underlying interlayer dielectric (ILD) layer, and forming a plurality of selection transistors on the lower interconnect metal layer. The above manufacturing method further includes forming an intermediate interconnection metal layer on the complex selection transistor, and forming a plurality of memory cells on the intermediate interconnection metal layer. The above manufacturing method further includes forming an upper interconnect metal layer on the plurality of memory cells.

The following disclosure provides many different embodiments or examples for implementing various features of the present disclosure. Specific examples of the various components and arrangements of the present disclosure are described below to simplify the description. Of course, these examples are not intended to limit the present disclosure. For example, where the description has a first feature formed on or over a second feature, it may include embodiments where the first feature and the second feature are formed in direct contact, and may also include additional features formed on the first feature between the first feature and the second feature without direct contact between the first feature and the second feature. Furthermore, the present disclosure may repeat reference numerals and/or letters in various instances. This repetition is for simplicity and clarity, and does not in itself prescribe the relationship between the various embodiments and/or configurations discussed.

Further, the present disclosure may use spatially relative terms such as "below," "below," "below," "above," "above," and the like to facilitate describing one of the drawings The relationship of an element or feature to other elements or features. In addition to the orientation depicted in the drawings, spatially relative terms are intended to encompass different orientations of the device in use or operation. The device may be turned in different orientations (rotated 90 degrees or otherwise) and the spatially relative terms used herein should be interpreted accordingly.

The semiconductor industry continues to improve the bulk density of various electronic devices (eg, transistors, diodes, resistors, capacitors, etc.) by, for example, reducing minimum feature size and/or bringing electronic devices closer together , which allows more components to be integrated into a given area. As manufacturing nodes continue to shrink, front-end-of-line (FEOL) transistors have become the main bottleneck for driving high-density non-volatile memory (NVM), such as magnetoresistive Random access memory (magnetoresistive random access memory, MRAM) device. The operation of MRAM requires high write currents (eg, greater than 200 microamps (µA)/micrometer (µm)). One way to achieve this high write current is to enlarge the size of the transistors, or to use multiple transistors for a memory element. For example, some proposed concepts use two or more transistors for a memory element in order to have sufficient drive current. These methods cause a large loss of FEOL area.

In view of the foregoing, the present disclosure relates to back-end-of-line (BEOL) transistors for use as select transistors in memory devices and related fabrication methods to realize high-density non-volatile memory devices. In some embodiments, the memory device includes a substrate. A back-end interconnect structure is disposed over the substrate and includes a plurality of interconnect metal layers stacked one over the other. Memory cells are disposed between the upper interconnect metal layer and the middle interconnect metal layer. A selecting transistor is disposed between the middle interconnect metal layer and the underlying interconnect metal layer. By placing the select transistor in the back-end interconnect structure and between the two interconnect metal layers, front-end space can be freed up and greater integration flexibility is provided.

In some further embodiments, the selection transistor is a planar transistor. A selector gate electrode of the select transistor may be disposed on the lower interconnect metal layer and electrically coupled to the lower interconnect metal layer. A selector channel layer is disposed over the selector gate electrode. The selector source/drain layer is disposed on the selector channel layer. The selector source/drain layer includes a first selector source/drain region and a second selector source/drain region separated by sidewall spacers. A portion of the channel layer directly below the sidewall spacers is used as a channel region for the select transistor. Thus, the width of the sidewall spacers defines the channel length of the select transistor. In some embodiments, the channel layer includes an oxide semiconductor (OS) material. For example, the channel layer may be made of indium gallium zinc oxide (IGZO). The OS material channel region provides ultra-low leakage current (I _ON /I _OFF > 10 ¹³ ) and can be used to fabricate BEOL compatible transistors for memory devices. In some embodiments, the selector source/drain regions may have various shapes. For example, the second selector source/drain regions may be circular, square, single fin, multi-fin, oval, or other suitable shapes. The sidewall spacers surround the second selector source/drain regions, and the first selector source/drain regions surround the periphery of the sidewall spacers.

And in some embodiments, the memory cell includes a bottom electrode and a top electrode separated by a data storage structure. The select transistor may be connected to the bottom electrode of the memory cell via an intermediate interconnect metal layer. The storage structure is stacked with the top electrode over the bottom electrode. In some embodiments, the data storage structure is a magnetic tunnel junction (MTJ) or a spin-valve. In this case, the memory cells are referred to as magnetic memory cells, and memory devices made from arrays of such memory cells are referred to as MRAM devices. In some alternative embodiments, the data storage structure is a metal-insulator-metal (MIM) stack, and the memory cells may be resistive memory cells. Other structures for data storage structures and/or other memory cell types for memory cells are also acceptable.

FIG. 1 shows a cross-sectional view of some embodiments of a memory device 100 including a select transistor 118 . In some embodiments, memory device 100 includes memory cells 108 disposed within interconnect structure 104 , where interconnect structure 104 is located over substrate 102 . The interconnect structure 104 includes stacked interconnect metal layers disposed in inter-level dielectric (ILD) layers between the stacks. In some embodiments, the stacked ILD layers include a lower ILD layer 104L disposed between the memory cells 108 and the substrate 102 , and an upper ILD layer 104U surrounding the memory cells 108 . Each of the lower ILD layer 104L and the upper ILD layer 104U may include one or more dielectric layers. In some embodiments, the stacked interconnect metal layers include a lower interconnect metal layer 130 , a middle interconnect metal layer 106 stacked over the lower interconnect metal layer 130 , and an upper interconnect layer disposed above the middle interconnect metal layer 106 . The metal layer 116 is connected.

The memory cell 108 may include a bottom electrode 110 , a data storage structure 112 disposed over the bottom electrode 110 , and a top electrode 114 disposed over the data storage structure 112 . The upper interconnect metal layer 116 extends through the upper ILD layer 104U to reach the top electrode 114 . In some embodiments, the bottom electrode 110 and the top electrode 114 may include tantalum nitride, titanium nitride, tantalum, titanium, platinum, nickel, hafnium, zirconium, ruthenium, iridium, and the like. In some embodiments, the data storage structure 112 is a magnetic tunnel junction (MTJ) or a spin valve. In these cases, memory cells 108 are referred to as magnetic memory cells, and memory devices 100 made from arrays of such memory cells 108 are referred to as magnetoresistive random access memory (MRAM) device. In such embodiments, the data storage structure 112 may include a magnetic tunnel junction, a ferroelectric capacitor or junction, or the like. In some alternative embodiments, the data storage structures 112 are metal-insulator-metal (MIM) stacks, and the memory cells 108 may be resistive memory cells. In these cases, memory cells 108 are referred to as resistive memory cells, and memory devices 100 made from arrays of such memory cells 108 are referred to as RRAM devices. In these embodiments, the data storage structure 112 includes a high-k dielectric material, such as hafnium dioxide (HfO ₂ ), zirconium dioxide (ZrO ₂ ), aluminum oxide (Al ₂ O ₃ ), tantalum pentoxide (Ta ₂ O ₅ ), hafnium aluminum oxide (HfAlO), hafnium zirconium oxide (HfZrO), etc. Other structures for data storage structure 112 and/or other memory cell types for memory cells 108 are also acceptable.

In some embodiments, the select transistor 118 is electrically coupled to the bottom electrode 110 of the memory cell 108 via the intermediate interconnect metal layer 106 . In some embodiments, the source/drain layer 134 is disposed below the intermediate interconnect metal layer 106 . The source/drain layer 134 includes a first selector source/drain region 120 and a second selector source/drain region 122 separated by sidewall spacers 128 . The selector channel layer 126 is disposed below the source/drain layer 134 . The selector gate dielectric layer 132 is disposed below the selector channel layer 126 and separates the selector gate electrode 124 from the selector channel layer 126 . The selector gate electrode 124 may be disposed on the underlying interconnect metal layer 130 and surrounded by the underlying ILD layer 104L. During operation, a source-drain voltage is applied between the first selector source/drain region 120 and the second selector source/drain region 122 . A gate-source voltage is applied between the selector gate electrode 124 and the first selector source/drain region 120 . If the gate-source voltage is sufficient, the channel path in the selector channel layer 126 is turned-on, connecting the first selector source/drain region 120 and the second selector source/drain region 122. The width of the sidewall spacer 128 defines the channel length Lc of the select transistor 118 in the selector channel layer 126 directly below the sidewall spacer 128 . The perimeter of the interface between the sidewall spacer 128 and the second selector source/drain region 122 defines the channel width of the select transistor 118 .

In some embodiments, the first selector source/drain region 120 and the second selector source/drain region 122 include a doped semiconductor material (eg, p-doped or n-doped polysilicon) and /or titanium nitride (TiN), tantalum nitride (TaN), tungsten (W), copper (Cu), or other CMOS contact metals. Each of the first selector source/drain region 120 and the second selector source/drain region 122 may have a thickness in a range from about 10 nm (nanometers) to about 50 nm. In some embodiments, sidewall spacers 128 may be a single layer of non-conductive material. In some alternative embodiments, the sidewall spacers 128 may comprise multiple layers of the same or different materials that collectively isolate the second selector source/drain regions 122 from the first selector source/drain regions 120 . For example, the sidewall spacers 128 may include a dielectric material or multiple dielectric materials, such as silicon dioxide, silicon nitride, and the like. The sidewall spacers 128 may have a thickness ranging from about 5 nm to about 30 nm. In some embodiments, the selector channel layer 126 includes an oxide semiconductor (OS) material. For example, the channel layer can be made of materials such as indium gallium zinc oxide (IGZO), indium zinc oxide (IZO), indium tin oxide or indium titanium oxide (ITO), or another Made of oxide semiconductor materials. The selector channel layer 126 may have a thickness in the range from about 3 nm to about 50 nm, or in the range from about 5 nm to about 30 nm. The OS material channel region provides ultra-low leakage and can be used to fabricate BEOL compatible transistors for memory devices. In some embodiments, the selector gate dielectric layer 132 includes aluminum oxide (Al ₂ O ₃ ), hafnium oxide (HfO ₂ ), tantalum oxide (Ta ₂ O ₅ ), zirconium oxide (ZrO ₂ ), titanium oxide ( TiO ₂ ), strontium titanium oxide (SrTiO ₃ ), or other high-k dielectric materials, etc. The selector gate dielectric layer 132 may have a thickness in a range from about 1 nm to about 15 nm, or in a range from about 1 nm to about 5 nm. By placing the select transistor in the interconnect structure of the back end process, between two interconnect metal layers, the front end process can be used for novel logic functions and provide greater integration flexibility.

FIG. 2 shows a cross-sectional view of a memory device 200 including a select transistor 118 in greater detail, according to some additional embodiments. In some embodiments, logic device 202 is disposed within substrate 102 . The logic device 202 may include a transistor device (eg, a metal oxide semiconductor field effect transistor (MOSFET) device, a bipolar junction transistor (BJT), etc.). The interconnect structure 104 is disposed over the logic device 202 and the substrate 102 . The interconnect structure 104 includes a plurality of stacked ILD layers 104a, 104b, 104c, 104d, and 104e (104a-104e) laterally surrounding a plurality of interconnect metal layers configured to provide electrical connections. In some embodiments, the interconnect metal layer may include a conductive contact 204 that lands on the logic device 202 and includes an interconnect disposed over the conductive contact 204 and surrounded by a plurality of stacked ILD layers 104a-104e Connect lines 206a-206c and interconnect vias.

In some embodiments, a first interconnect 206a (also referred to as interconnect 206a) is disposed over a second ILD layer 104b (also referred to as ILD layer) over first ILD layer 104a (also referred to as ILD layer 104a) 104b). The first interconnection line 206a may be used as a word line of the memory device 200 . Select transistor 118 includes selector gate electrode 124 stacked on first interconnect 206a and configured to control current flow at first selector source/drain via selector channel layer 126 flow between region 120 and second selector source/drain region 122 . In some embodiments, the selector gate electrode 124 may comprise the same conductive material as the first interconnect line 206a, and may be seamless with the first interconnect line 206a. Alternatively, the selector gate electrode 124 may include a different conductive material than the first interconnection line 206a. A selector gate dielectric layer 132 may be disposed between the selector gate electrode 124 and the selector channel layer.

In some embodiments, the first selector source/drain region 120 and the second selector source/drain region 122 are disposed on the selector channel layer 126 and are separated from each other by sidewall spacers 128 . The sidewall spacers 128 may enclose the outer sidewalls of the second selector source/drain regions 122 . The first selector source/drain regions 120 may surround the outer sidewalls of the sidewall spacers 128 and may be surrounded by the third ILD layer 104c (also referred to as the ILD layer 104c). In some embodiments, a dielectric layer 222 is disposed on the first selector source/drain regions 120 and the third ILD layer 104c and surrounds the sidewall spacers 128 or the second selector source/drain regions 122 . In some embodiments, sidewall spacers 128 cover sidewall surfaces of the second selector source/drain regions 122 . The first selector source/drain regions 120 and the dielectric layer 222 may collectively cover the outer sidewalls of the sidewall spacers 128 . In some embodiments, the dielectric layer 222 may include a dielectric material such as silicon dioxide, silicon nitride, or the like. The thickness of the dielectric layer 222 may have a thickness in the range of about 1 nm to about 5 nm.

In some embodiments, the first selector source/drain region 120 is coupled to a source line SL. The second selector source/drain region 122 is coupled to the memory cell 108 via the second interconnect 206b (also referred to as the interconnect 206b), which is connected by the fourth ILD layer 104d (also referred to as the interconnect 206b). Surrounded by the so-called ILD layer 104d). The second interconnection line 206b may be disposed over the first selector source/drain region 120 and separated from the first selector source/drain region 120 by the dielectric layer 222 .

In some embodiments, the lower insulating structure 210 is disposed over the fourth ILD layer 104d. The lower insulating structure 210 includes sidewalls that define openings extending through the lower insulating structure 210 . In various embodiments, the underlying insulating structure 210 may include one or more of silicon nitride, silicon dioxide, silicon carbide, or the like. Bottom electrode vias 212 are disposed in the openings of the underlying insulating structure 210 and land on the second interconnection line 206b. The memory cells 108 are disposed on the bottom electrode vias 212 . In some embodiments, the memory cell 108 includes a bottom electrode 110 separated from the top electrode 114 by a data storage structure 112 . In some embodiments, a hard mask layer 216 may be disposed on top electrode 114 . Sidewall spacers 218 may be disposed on the opposing sides of the top electrode 114 and the hard mask layer 216 . In some embodiments, the hard mask layer 216 may include metals (eg, titanium, tantalum, etc.) and/or dielectrics (eg, nitrides, carbides, etc.). In some embodiments, the sidewall spacers 218 may include oxides (eg, silicon rich oxide), nitrides (eg, silicon nitride), carbides (eg, silicon carbide), and the like.

In some embodiments, the upper insulating structure 220 is disposed above the memory cell 108 and on the lower insulating structure 210 . The upper insulating structure 220 extends continuously from a first position directly above the memory cell 108 to a second position adjacent to the upper surface of the lower insulating structure 210 . The upper insulating structure 220 separates the memory cells 108 from the fifth ILD layer 104e (also referred to as the ILD layer 104e). The upper insulating structure 220 may include one or more dielectric materials, such as silicon nitride, silicon dioxide, silicon carbide, and the like. In some embodiments, the upper interconnect metal layer 116 extends through the fifth ILD layer 104e to electrically contact the top electrode 114 . The upper interconnect metal layer 116 may include a top electrode via 214 disposed through the hard mask layer 216 and the upper insulating structure 220, and a third interconnect line 206c (also referred to as an interconnect line) connected to the top electrode via 214. 206c). The third interconnection line 206c may be used as a bit line of the memory device 200 .

During operation, signals (eg, voltages and/or currents) may be selectively applied to word lines WL, source lines SL, and bit lines BL to read data from and write data to memory cells 108 memory unit 108 .

3 shows a cross-sectional view of a memory device 300 including select transistor 118, according to some additional embodiments. The memory device 300 includes a substrate 102 including a memory region 302 and a logic region 304 . Logic region 304 may include logic devices 306 disposed within substrate 102 . For example, the logic device 306 may include a transistor including a first source/drain region 306a, a second source/drain region separated from the first source/drain region 306a by a channel region 306b, and a gate structure 306c disposed above the channel region. The conductive contact 204 may land on the first source/drain region 306a or the second source/drain region 306b. Similarly, another logic device 202 may be disposed in the substrate 102 in the memory area 302 . In some alternative embodiments, the logic devices 202, 306 may be fin field effect transistor (FinFET) devices, nanowire devices, or other gate-all-arround (GAA) devices . Thus, by utilizing BEOL to select transistors, greater integration flexibility is provided.

The interconnect structure 104 is disposed over the substrate 102 and covers the logic devices 202 , 306 . The interconnect structure 104 includes a plurality of metal layers stacked one over the other, and includes stacked interconnect lines 206a-206e and metal vias 208a-208e disposed in the stacked ILD layers 104a-104f. In some embodiments, the plurality of stacked ILD layers 104a-104f may include one or more of the following materials: silica, fluorosilicate glass, silicate glass (eg, borophosphate silicate glass) borophosphate silicate glass (BSG), phosphosilicate glass (PSG), borophosphosilicate glass (BPSG), fluorosilicate glass (FSG), undoped silicon Acid glass (USG)) and so on. In some embodiments, adjacent ILD layers 104a-104f may be separated by an etch stop layer (not shown) including nitrides, carbides, and the like. A plurality of metal layers from a lower position close to the substrate to an upper position away from the substrate are referred to numerically as M0, M1, M2, M3 . . . in the industry. M0 refers to the metal layer closest to the substrate, and includes metal lines that are electrically coupled to the active region of the logic device via the conductive contacts 204 . M1 (not shown) refers to the next metal layer stacked above the metal layer M0 , and the metal lines included in the metal layer M1 are electrically coupled to the metal lines of the metal layer M0 through metal vias. Similarly, Mn+1 refers to the next metal layer stacked on the underlying metal layer Mn, and the metal lines included in the metal layer Mn+1 are electrically coupled to the metal lines of the underlying metal layer Mn through metal vias , where n is a positive integer. It should be emphasized that although some specific metal layer numbers are given below, such as M6, M7, M8, M9, M10, etc., these specific numbers are not for limiting purposes, and various metal layers can be used for different Applications.

The memory cell 108 is disposed between the upper interconnection metal layer 116 and the middle interconnection metal layer 106 , eg, between the metal layer M10 and the metal layer M8 as shown in FIG. 3 . In some embodiments, memory cell 108 is inserted into one or more interconnect metal layers between intermediate interconnect metal layer 106 and upper interconnect metal layer 116 (eg, between metal layers M8 and M10 ). (eg: metal layer M9). The memory cell 108 may include a bottom electrode 110 separated from the top electrode 114 by a data storage structure 112 . A hard mask layer 216 may be disposed on the top electrode 114 . Sidewall spacers 218 may be disposed on both sides of the top electrode 114 and the hard mask layer 216 . In some embodiments, the select transistor 118 is connected to the bottom electrode 110 of the memory cell 108 . The select transistor 118 is disposed between the middle interconnect metal layer 106 and the lower interconnect metal layer 130 , eg, between the metal layer M8 and the metal layer M6 as shown in FIG. 3 .

In some embodiments, select transistor 118 is interposed between one or more interconnect metal layers (eg, between metal layers M8 and M6) between intermediate interconnect metal layer 106 and underlying interconnect metal layer 130 (eg, between metal layers M8 and M6). in the metal layer M7). The selector gate electrode 124 of the select transistor 118 is disposed in the dielectric layer and is electrically coupled to the underlying interconnect metal layer 130 . The selector gate dielectric layer 132 and the selector channel layer 126 may be disposed on the selector gate electrode 124 and surrounding dielectric layers in the memory region 302 . The first selector source/drain region 120 and the second selector source/drain region 122 may be disposed on the selector channel layer 126 in the memory region 302 and separated from each other by sidewall spacers 128 . In some embodiments, the first selector source/drain region 120 is coupled to the source line SL. The second selector source/drain regions 122 are coupled via one or more interconnect lines 206c and one or more interconnect vias 208c (or metal vias 208c) surrounded by one or more ILD layers to memory cell 108 .

As mentioned above, the selection transistor 118 and the memory cell 108 can be flexibly placed in various metal layers. In some embodiments, select transistor 118 is located over metal layer M4 (also referred to as the fourth interconnect metal layer), and thus at least four interconnect metal layers (metal layers M1, M2, M3, M4) are disposed on between the selector gate electrode 124 and the substrate 102 . According to routing requirements, the interconnect structure 104 has denser metal lines and smaller dimensions in the lower metal layer compared to the upper metal layer. If the select transistor 118 is located in a metal layer lower than the fourth interconnect metal layer M4, precious routing area will be consumed. Above the fourth interconnect metal layer M4, the exact location of the selection transistor 118 can be determined with reference to routing requirements, thereby providing design flexibility.

Figure 4 shows a block diagram of a portion of a memory array 400 having a plurality of memory units C11-C33. The memory cells C11 - C33 are arranged in rows and/or columns in the memory array 400 . The memory array includes plural select transistors 118 , which are correspondingly connected to plural memory cells 108 . In some embodiments, the device structures disclosed in relation to FIGS. 1 , 2 and 3 may be combined into some embodiments of the individual memory cells C11 - C33 of the memory array 400 . A complex selection transistor 118 is disposed in the interconnect structure between a lower interconnect metal layer and an upper interconnect metal layer of the interconnect structure.

Although memory array 400 is shown as having 3 columns and 3 rows, memory array 400 may have any number of columns and any number of rows. Each of memory cells C11 - C33 may include memory cell 108 coupled to select transistor 118 . Select transistor 118 is configured to selectively provide access to selected memory cells 108 while inhibiting leakage current through unselected memory cells.

Memory cells C11-C33 may be controlled via bit lines BL ₁ -BL ₃ , word lines WL ₁ -WL ₃ , and source lines SL ₁ -SL ₃ . Word lines WL1 _{- WL3} may be used to operate select transistors 118 of corresponding memory cells C11-C33. When the select transistor 118 for a memory cell 108 is turned on, a voltage can be applied to that memory cell. A bit line decoder (decoder) 119 applies a read voltage or a write voltage to one of the bit lines BL ₁ -BL ₃ . The word line decoder 127 applies another voltage to one _of the word lines WL1 _- WL3, which turns on the select transistors 118 for the memory cells C11-C33 in the corresponding column. Together, these operations cause a read voltage or a write voltage to be applied to selected ones of memory cells C11-C33.

Applying a voltage to the selected memory cell 108 generates a current. During a read operation, a sense amplifier 117 determines the programming state of the selected memory cell based on the current. The sense amplifier 117 may be connected to the source lines SL ₁ -SL ₃ . Alternatively, sense amplifier 117 may be connected to bit lines BL ₁ -BL ₃ . The sense amplifier 117 can determine the program state of the memory cell 108 based on the current. In some embodiments, the sense amplifier 117 determines the program state of the memory cell 108 by comparing the current with one or more reference currents. The sense amplifier 117 can transmit the judgment of the program status to the I/O buffer, which can be coupled to the driving circuit to perform write and write verify operations. The driver circuit is configured to select a voltage to be applied to selected memory cells for read, write and write verify operations.

It should be understood that the meaning of this voltage is the absolute value of the potential difference across the memory cell 108 . For the memory array 400, applying a voltage to the selected memory cell represents operating word lines WL1 _- WL3 to turn _on the select transistor 118 corresponding to the memory cell, and using the driver circuit to enable the source of the corresponding cell _The magnitude of the absolute value _of the potential difference between the pole lines SL1 _- SL3 and the bit lines BL1 _- BL3 is equal to this voltage. In some embodiments, applying a voltage to a memory cell is accomplished by coupling the corresponding bit lines BL ₁ -BL ₃ to the voltage while maintaining the corresponding source lines SL ₁ -SL ₃ at ground potential. _In addition, the source lines SL1 _- SL3 can be kept at other potentials, and the roles _of the bit lines BL1 _{- BL3} and the source lines SL1 _- SL3 can be reversed.

FIG. 5 shows a cross-sectional view 500 of the memory array 400 of FIG. 4 along a column direction, according to some embodiments. For example, the memory units shown in FIG. 5 may be memory units C11 , C12 and C13 in FIG. 4 . In addition to the device structures disclosed in relation to Figures 1, 2, and 3, as shown in Figures 4 and 5, in some embodiments, memory units in a row (eg, memory units C11, C12, and C13) may share _a common bit line BL ₁ , which is connected to individual memory cells 108 through individual top electrode vias 214 .

FIG. 6 shows a cross-sectional view 600 of the memory array 400 of FIG. 4 along a row direction, according to some embodiments. For example, the memory units shown in FIG. 6 may be memory units C11 , C21 , and C31 in FIG. 4 . In addition to the device structures disclosed in relation to Figures 1, 2, and 3, as shown in Figures 4 and 6, in some embodiments, memory units in a row (eg, memory units C11, C21, and C31) may share a gate electrode or have individual gate electrodes, the gate electrodes are connected to a common word line WL ₁ , and the common word line WL ₁ is connected to the Individual selector transistors 118 .

FIGS. 7A-7D show top views 700a-700d of the memory array 400 of FIG. 4 corresponding to select transistors 118, according to some embodiments. As shown in FIGS. 7A to 7D , the first selector source/drain regions 120 and the second selector source/drain regions 122 may have various shapes. For example, the second selector source/drain regions 122 may be in the shape of separate islands surrounded by sidewall spacers 128 . The sidewall spacers 128 may have separate annular shapes. The first selector source/drain regions 120 surround the periphery of the sidewall spacers 128 . In these embodiments, the width of the sidewall spacers 128 defines the channel length of the select transistor 118 and the perimeter of the second selector source/drain region 122 defines the channel width of the select transistor 118 . As an example, the channel length Lc may be in the range of about 5 nm to about 30 nm. The channel width may be in the range of about 50 nm to about 500 nm. The resulting drain-source current can range from about 50µA to about 100µA.

In some embodiments, the second selector source/drain region 122 may have a center-symmetric shape, such as a circle, a square, or other orthopolygon as shown in FIG. 7A . In some alternative embodiments, the second selector source/drain regions 122 may have an axially symmetrical shape that is longer than the shared first selector source/drain regions 120 in the length direction The shared first selector source/drain region 120 is longer in the width direction, so that the second selector can be enlarged by setting the length of the second selector source/drain region 122 longer The area of the source/drain region 122 . Examples of these second selector source/drain regions 122 include an oval shape as shown in FIG. 7B or a rectangle shape as shown in FIG. 7C. In some further alternative embodiments, the second selector source/drain region 122 may include a plurality of fins to further enlarge the perimeter of the second selector source/drain region 122 , ie select transistors 118 channel width. In this way, the drain current of the select transistor can be further increased. Figure 7D shows a second selector source/drain region 122 with two rectangular fins as an example of those embodiments. Other suitable shapes not shown in the drawings (eg, square, plural circular fins, etc.) are also acceptable.

8-17 show cross-sectional views 800-1700 of some embodiments of a method of fabricating a memory device including a BEOL selection transistor. Although Figures 8 to 17 are described in relation to the method, it should be understood that the structures disclosed in Figures 8 to 17 are not limited to this method, but can instead be used independently of this method. structure.

As shown in cross-sectional view 800 of FIG. 8, a substrate 102 is provided. In various embodiments, the substrate 102 may be any type of semiconductor body (eg, silicon, silicon germanium (SiGe), silicon-on-insulator (SOI), etc.), such as a semiconductor wafer and/or one or more on-wafer A die, and any other type of semiconductor and/or epitaxial layer associated therewith. The substrate 102 includes a memory area 302 and a logic area 304 . In some embodiments, logic device 306 is formed in substrate 102 . Logic device 306 may be formed in memory area 302 or logic area 304 . The logic device 306 may include a transistor formed by depositing and patterning a gate dielectric film and a gate electrode film over the substrate 102 to form a gate dielectric and gate electrode. An implant may then be performed on the substrate 102 to form source and drain regions in the substrate 102 on both sides of the gate electrode.

In some embodiments, one or more lower interconnect metal layers may be formed in one or more lower ILD layers, where the one or more lower ILD layers are formed over logic device 306 and substrate 102 . In some embodiments, the one or more underlying interconnect metal layers may include conductive contacts 204 formed in the first ILD layer 104a, first interconnect lines 206a formed in the second ILD layer 104b, and first interconnect lines 206a formed in the second ILD layer 104b. Vias 208a (also referred to as metal vias 208a), and more interconnects and vias (not shown) stacked above them. One or more underlying interconnect metal layers may be formed by repeated formation of underlying ILD layers (eg, oxides, low-k dielectrics, ultra-low-k dielectrics) over substrate 102, selective etching The underlying ILD layer to define via holes and/or trenches in the underlying ILD layer, to form conductive materials (eg, copper, aluminum, etc.) in the via holes and/or trenches, and to perform planarization processes (eg, chemical chemical mechanical planarization process) to remove excess conductive material from above the underlying ILD layer. The conductive contacts 204, interconnect lines 206a/206b, and interconnect vias 208a shown in FIG. 8 are drawn for illustration purposes, and in different applications, the memory region 302 or logic can be adjusted Region 304 has more or fewer layers of interconnect lines, vias and underlying ILD layers.

As shown in the cross-sectional view 900 of FIG. 9, the selector gate electrode 124 is formed in the second ILD layer 104b. The selector gate electrode 124 may be formed by selectively etching the second ILD layer 104b to define trenches in the second ILD layer 104b, forming a conductive material (eg, tungsten, copper, aluminum, etc.) in the trenches , and performing a planarization process (eg, a chemical mechanical polishing process) to remove excess conductive material from above the second ILD layer 104b. In some embodiments, the conductive material forming the selector gate electrode 124 is the same as the first interconnect line 206a and the first interconnect via 208a. In some alternative embodiments, the conductive material forming the selector gate electrode 124 is different from the first interconnect line 206a and the first interconnect via 208a. In some embodiments, the selector gate electrode 124 is formed by a deposition process followed by a planarization process (eg, a chemical mechanical polishing process), and may have a thickness in the range of about 5 nm to about 20 nm .

As shown in cross-sectional view 1000 of FIG. 10, selector gate dielectric layer 132 and selector channel layer 126 are formed on selector gate electrode 124 and second ILD layer 104b. In some embodiments, the selector gate dielectric layer 132 and the selector channel layer 126 are formed by deposition techniques (eg, atomic layer deposition (ALD)), respectively. The selector gate dielectric layer 132 may have a thickness in the range of about 1 nm to about 15 nm. The selector channel layer 126 may have a thickness in the range of about 3 nm to about 50 nm. In some embodiments, the selector gate dielectric layer 132 includes aluminum oxide (Al ₂ O ₃ ), hafnium oxide (HfO ₂ ), tantalum oxide (Ta ₂ O ₅ ), zirconium oxide (ZrO ₂ ), titanium oxide ( TiO ₂ ), strontium titanium oxide (SrTiO ₃ ), or other high-k dielectric materials, etc. In some embodiments, the selector channel layer 126 includes an oxide semiconductor (OS) material. For example, the channel layer may be made of indium gallium zinc oxide (IGZO), indium zinc oxide (IZO), indium tin oxide or indium titanium oxide (ITO), or another oxide semiconductor material.

As shown in cross-sectional view 1100 of FIG. 11, a third ILD layer 104c is formed on the selector channel layer 126, and a first selector source/drain layer 120' is formed in the third ILD layer 104c. In some embodiments, the first selector source/drain layer 120' is formed as a plurality of parallel lines perpendicularly intersecting the selector gate electrodes 124 from a top view. Examples of the pattern of the selector gate electrode 124 and the first selector source/drain layer 120' can be found in FIGS. 7A-7D. In some embodiments, the first selector source/drain layer 120' is formed by a deposition process followed by a patterning process. The first selector source/drain layer 120' may have a thickness in the range of about 10 nm to about 50 nm. In some embodiments, the first selector source/drain layer 120' may be formed of titanium nitride (TiN), tantalum nitride (TaN), tungsten (W), copper (Cu), or others CMOS contact metal and/or doped semiconductor material (eg p-doped or n-doped polysilicon).

As shown in cross-sectional view 1200 of FIG. 12, the first selector source/drain layer 120' is patterned to form openings 1202 through the first selector source/drain layer 120', leaving the remainder as the first selector source/drain region 120 . The openings 1202 may be formed by a selective etch process that etches through the first selector source/drain layer 120' and ends on the selector channel layer 126.

In some embodiments, a dielectric layer 222 is formed on the first selector source/drain layer 120' and the third ILD layer 104c prior to forming the opening 1202. Dielectric layer 222 can be patterned and can be used as a hard mask for forming openings 1202 . The dielectric layer 222 may be formed by a deposition process followed by a planarization process (eg, a chemical mechanical polishing process), and may include an oxide material such as silicon dioxide. In some embodiments, the dielectric layer 222 may have a thickness in the range of about 1 nm to about 5 nm.

As shown in cross-sectional view 1300 of FIG. 13 , sidewall spacers 128 are formed along the sidewalls of opening 1202 . In some embodiments, sidewall spacers 128 are formed by depositing a conformal dielectric layer followed by an etch process to expose selector channel layer 126 . In some embodiments, the etching process may be or may include an anisotropic etching (eg, vertical dry etching) that removes the compliant dielectric layer including overlying the selector channel layer 126 part of the lateral part, while leaving the vertical part of the compliant dielectric layer on the sidewalls of the opening 1202. In some alternative embodiments, lateral portions of the compliant dielectric layer covering the selector channel layer 126 are removed, and some lateral portions of the compliant dielectric layer are retained for the final device structure. Sidewall spacers 128 may be formed of dielectric materials such as silicon dioxide, silicon nitride, and the like. In some embodiments, the sidewall spacers 128 may have a thickness in the range of about 5 nm to about 30 nm. As the thickness of the sidewall spacers 128 is further reduced, eg, in the range of less than 5 nm or 3 nm, source/drain leakage may be induced. As the thickness of the sidewall spacers 128 is further increased, eg, greater than 30 nm, the drive current may decrease, and thus the transistor performance.

As shown in cross-sectional view 1400 of FIG. 14 , second selector source/drain regions 122 are formed in openings 1202 . In some embodiments, the second selector source/drain regions 122 are formed by depositing a conductive material in the openings 1202 and then performing a planarization process to remove excess portions outside the openings 1202 . The second selector source/drain regions 122 may have top surfaces that are coplanar with the top surfaces of the sidewall spacers 128 and/or the dielectric layer 222 . In some embodiments, sidewall spacers 128 cover sidewall surfaces of the second selector source/drain regions 122 . The first selector source/drain regions 120 and the dielectric layer 222 may collectively cover the outer sidewalls of the sidewall spacers 128 . In some embodiments, the second selector source/drain regions 122 may have a thickness in the range of about 10 nm to about 50 nm. The thickness of the second selector source/drain region 122 may be equal to or greater than the thickness of the first selector source/drain region 120 . In some embodiments, the second selector source/drain region 122 may be formed of the following materials: titanium nitride (TiN), tantalum nitride (TaN), tungsten (W), copper (Cu), or other CMOS Contact metal and/or doped semiconductor material (eg p-doped or n-doped polysilicon).

As shown in the cross-sectional view 1500 of FIG. 15, the fourth ILD layer 104d is formed over the first selector source/drain region 120 and the second selector source/drain region 122, with an intermediate interconnect metal layer is formed and electrically coupled to the second selector source/drain region 122 . For example, a second interconnect via 208b (also referred to as a metal via 208b) may be formed through the fourth ILD layer 104d and onto the second selector source/drain region 122, and the second interconnect The connection lines 206b may be formed on the second interconnect vias 208b in the fourth ILD layer 104d. In some embodiments, the fourth ILD layer 104d is formed by a deposition process, followed by a patterning process to form vias and trenches for subsequent formation of the intermediate interconnect metal layer. Next, second interconnect vias 208b and second interconnect lines 206b may be deposited in the vias and trenches, followed by a planarization process (eg, a chemical mechanical polishing process).

As shown in the cross-sectional view 1600 of FIG. 16, the lower insulating structure 210 is formed over the second interconnection line 206b and the fourth ILD layer 104d. In some embodiments, the underlying insulating structure 210 includes a plurality of different stacked dielectric materials. As an example, the underlying insulating structure 210 may include silicon-rich oxide, silicon carbide, silicon nitride, or the like. In some embodiments, one or more deposition processes (eg, physical vapor deposition (PVD) process, chemical vapor deposition (CVD) process, plasma-enhanced CVD (plasma-enhanced CVD) process can be used. Enhanced CVD, PE-CVD) process, etc.) to form the lower insulating structure 210 . In some embodiments, the lower insulating structure 210 is selectively etched to define an opening that extends through the lower insulating structure 210 and exposes the upper surface of the intermediate interconnect metal layer. Bottom electrode vias 212 may be formed in the opening.

As shown in cross-sectional view 1700 of FIG. 17 , the memory device stack is formed and patterned over underlying insulating structure 210 to form memory cell 108 . Memory device stacks are formed by a number of different deposition processes, such as CVD, PE-CVD, sputtering, ALD, and the like. The memory device stack is patterned by one or more patterning processes. In some embodiments, a first patterning process is performed to define the top electrode 114 and the data storage structure 112 , as well as the corresponding hard mask layer 216 . In various embodiments, the hard mask layer 216 may include metals (eg, titanium, titanium nitride, tantalum, etc.) and/or dielectric materials (eg, silicon nitride, silicon carbide, etc.). Next, sidewall spacers 218 may be formed along the sidewalls of the data storage structure 112 , the top electrode 114 , and the hard mask layer 216 . In various embodiments, sidewall spacers 218 may include silicon nitride, silicon dioxide, silicon oxynitride, and/or similar materials. In some embodiments, sidewall spacers 218 may be formed by forming a spacer layer over substrate 102 . The sidewall spacer layer is then exposed to an etchant (eg, dry etchant) that removes the sidewall spacer layer from the horizontal surface. Removing the sidewall spacer layer from the horizontal surface leaves a portion of the sidewall spacer layer along both sidewalls of the data storage structure 112 , the top electrode 114 and the hard mask layer 216 as sidewall spacers 218 . Next, a second patterning process is performed on the bottom metal layer to define the bottom electrode 110 not covered by the hard mask layer 216 and the sidewall spacers 218 .

As shown in cross-sectional view 1800 of FIG. 18 , upper insulating structure 220 is formed over memory cell 108 . In some embodiments, the upper insulating structure 220 may be formed using one or more deposition techniques (eg, PVD, CVD, PE-CVD, ALD, sputtering, etc.). In various embodiments, the upper insulating structure 220 may include one or more of silicon carbide, tetraethyl orthosilicate (TEOS), or the like. The upper ILD layer 104U is formed over the upper insulating structure 220 as part of the interconnect structure 104 over the substrate 102 . In some embodiments, the upper ILD layer 104U may be formed by a deposition process (eg, PVD, CVD, PE-CVD, ALD, etc.). In various embodiments, the upper ILD layer 104U may include one or more of the following materials: silicon dioxide, carbon-doped silicon dioxide, silicon oxynitride, BSG, PSG, BPSG, FSG, USG, porous dielectric electrical materials, etc. Next, third interconnect vias 208c (also referred to as metal vias 208c, interconnect vias 208c) and third interconnect lines 206c are formed in the upper ILD layer 104U. In the memory region 302 , third interconnect vias 208c and third interconnect lines 206c may be formed in the upper ILD layer 104U on top of the memory cells 108 to expose the upper surface of the top electrode 114 . In the logic region 304, the third interconnect vias 208c and the third interconnect lines 206c may extend from the top surface of the upper ILD layer 104U to pass vertically through the memory cells 108, and further extend through the upper insulating structure 220 and The lower insulating structure 210 reaches the lower interconnect metal layer.

19 shows a flowchart of some embodiments of a method 1900 of forming a memory device including a BEOL select transistor.

Although method 1900 is depicted and described herein as a series of operations or events, it should be understood that the illustrated order of these operations or events should not be construed in a limiting fashion. For example, certain operations can occur in different orders and/or concurrently with other operations or events than those illustrated and/or described herein. Furthermore, all illustrated operations may not be required to implement one or more aspects or embodiments described herein. Further, one or more operations described herein may be performed in one or more separate operations and/or stages.

In operation 1902, a substrate is prepared and an underlying interconnect metal layer is formed in an underlying interlayer dielectric (ILD) layer over the substrate. In some embodiments, logic devices may be formed within the substrate in memory regions and/or logic regions prior to forming the underlying interconnect metal layer. FIG. 8 shows a cross-sectional view 800 corresponding to some embodiments of operation 1902 .

In operation 1904, a BEOL select transistor is formed over the underlying interconnect metal layer. In some embodiments, select transistors may be formed according to operations 1906-1916.

In operation 1906, selector gate electrodes are formed on the underlying interconnect metal layer. FIG. 9 shows a cross-sectional view 900 corresponding to some embodiments of operation 1906 .

In operation 1908, a selector channel layer is formed over the selector gate electrode. FIG. 10 shows a cross-sectional view 1000 corresponding to some embodiments of operation 1908 .

In operation 1910, first selector source/drain regions are formed over the selector channel layer. FIG. 11 shows a cross-sectional view 1100 corresponding to some embodiments of operation 1910 .

In operation 1912, a dummy dielectric layer is formed on the first selector source/drain regions. FIG. 12 shows a cross-sectional view 1200 corresponding to some embodiments of operation 1912 .

In operation 1914, sidewall spacers are formed along the openings of the dummy dielectric layer and the first selector source/drain regions. FIG. 13 shows a cross-sectional view 1300 corresponding to some embodiments of operation 1914 .

In operation 1916, a second selector source/drain region is formed in the opening and separated from the first selector source/drain region by sidewall spacers. FIG. 14 shows a cross-sectional view 1400 corresponding to some embodiments of operation 1916 .

In operation 1918, an intermediate interconnect metal layer is formed over the BEOL select transistor. FIG. 15 shows a cross-sectional view 1500 corresponding to some embodiments of operation 1918 .

In operation 1920, memory cells are formed over the intermediate interconnect metal layer. FIGS. 16-17 show cross-sectional views 1600 - 1700 corresponding to some embodiments of operation 1920 .

In operation 1922, an upper interconnect metal layer is formed over the memory cells. FIG. 18 shows a cross-sectional view 1800 corresponding to some embodiments of operation 1922 .

Accordingly, in some embodiments, the present disclosure relates to a memory device (eg, an MRAM or RRAM device) having a BEOL select transistor layer interposed between two BEOL interconnect metal layers.

In some embodiments, the present disclosure relates to a memory device. The above-mentioned memory device includes a substrate and an interconnection structure disposed above the substrate. The interconnect structure includes a plurality of stacked interconnect metal layers disposed in a plurality of stacked interlayer dielectric (ILD) layers. The memory cells are disposed between the upper interconnect metal layer and the middle interconnect metal layer. The selection transistor is connected to the memory cell and is disposed between the middle interconnect metal layer and the lower interconnect metal layer. The selection transistor includes a first selector source/drain region and a second selector source/drain region disposed on the selector channel layer. The first selector source/drain region and the second selector source/drain region are separated by sidewall spacers.

In one or more embodiments, sidewall spacers are disposed between the first selector source/drain region and the second selector source/drain region. In one or more embodiments, the select transistor includes a selector gate electrode and a selector gate dielectric disposed between the underlying interconnect metal layer and the selector channel layer. In one or more embodiments, the sidewall spacers have an annular shape and surround the second selector source/drain regions. In one or more embodiments, the second selector source/drain region has a circular or oval shape in a top view. In one or more embodiments, in a top view, the second selector source/drain region has a square or rectangular shape and is surrounded by the first selector source/drain region. In one or more embodiments, the second selector source/drain regions are connected to the intermediate interconnect metal layer. In one or more embodiments, the selector channel layer includes an oxide semiconductor material. In one or more embodiments, the selector channel layer is made of indium gallium zinc oxide (IGZO). In one or more embodiments, the memory cell includes a bottom electrode disposed on the intermediate interconnect metal layer, a data storage structure disposed over the bottom electrode, and a top electrode disposed over the data storage structure.

In other embodiments, the present disclosure relates to a memory device. The above-mentioned memory device includes a substrate and an interconnection structure disposed above the substrate. The interconnect structure includes a plurality of interconnect metal layers stacked one above the other and disposed in an interlayer dielectric (ILD) layer. A plurality of memory cells are arranged in an interconnect structure and arranged in an array of columns and rows. The plurality of selection transistors are correspondingly connected to the memory cells. The complex selection transistors are disposed in the interconnection structure and between the lower interconnection metal layer and the upper interconnection metal layer of the interconnection structure.

In one or more embodiments, the plurality of memory cells respectively include: a bottom electrode; a data storage structure disposed above the bottom electrode; and a top electrode disposed above the data storage structure. A column of the plurality of memory cells shares a common bit line, and the common bit line is connected to the top electrodes of the above-mentioned column of the plurality of memory cells. In one or more embodiments, the above-mentioned columns of plural select transistors share a common first selector source/drain region, and each have individual second selector source/drain regions; and individual second selectors The source/drain regions are islands surrounded by common first selector source/drain regions. In one or more embodiments, individual second selector source/drain regions are connected to corresponding bottom electrodes. In one or more embodiments, the individual second selector source/drain regions are separated from the common first selector source/drain region by sidewall spacers. In one or more embodiments, the above-described memory device further includes a selector channel layer disposed in a common first selector source/drain region, individual second selector source/drain regions, and sidewall spacers below. In one or more embodiments, a row of multiple select transistors shares a common gate electrode, or has a plurality of individual gate electrodes connected to a common word line.

In still other embodiments, the present disclosure relates to a method of fabricating a memory device. The above-described fabrication method includes forming a lower interconnect metal layer over a substrate surrounded by an underlying interlayer dielectric (ILD) layer, and forming a plurality of selection transistors on the lower interconnect metal layer. The above manufacturing method further includes forming an intermediate interconnection metal layer on the complex selection transistor, and forming a plurality of memory cells on the intermediate interconnection metal layer. The above manufacturing method further includes forming an upper interconnect metal layer on the plurality of memory cells.

In one or more embodiments, forming one of the plurality of select transistors includes: forming a selector gate electrode in an underlying interlayer dielectric layer; overlying the selector gate electrode and the underlying interlayer dielectric layer forming a selector channel layer; forming a first selector source/drain region and a second selector source/drain region on the selector channel layer; and forming a middle on the second selector source/drain region Interconnect metal layers. In one or more embodiments, the forming of the first selector source/drain region and the second selector source/drain region includes: forming the first selector source/drain on the selector channel layer layer; forming a trench through the first selector source/drain layer; forming sidewall spacers along sidewalls of the trench; and filling the trench with a second selector source/drain region.

The foregoing description summarizes the features of various embodiments or examples so that aspects of the present disclosure may be better understood by those of ordinary skill in the art. Those skilled in the art should appreciate that they can readily use the present disclosure as a basis to design or modify other processes and structures to accomplish the same purposes and/or achieve the same advantages as the embodiments or examples described herein. Those skilled in the art should also understand that these equivalent structures do not depart from the spirit and scope of the present disclosure, and various changes, substitutions and alterations may be made to the present disclosure without departing from the spirit and scope of the present disclosure. .

100: memory device 102: substrate 104: interconnect structure 104L: lower ILD layer 104U: upper ILD layer 106: middle interconnect metal layer 108: memory cell 110: bottom electrode 112: data storage structure 114: top electrode 116: upper interconnect metal layer 118: select transistor 120: first selector source/drain region 122: second selector source/drain region 124: selector gate electrode 126: selector channel layer 128: sidewall Spacer 130: Lower Interconnect Metal Layer 132: Selector Gate Dielectric Layer 134: Source/Drain Layer Lc: Channel Lengths 104a-104e: ILD Layer 202: Logic Device 204: Metal Vias 206a-206c: Interconnect Connection line 210: bottom insulating structure 212: bottom electrode via 214: top electrode via 216: hard mask layer 218: sidewall spacer 220: upper insulating structure 222: dielectric layer BL: bit line SL: source line WL: word line 104f: ILD layers 208a~208e: metal via 300: memory device 302: memory region 304: logic region 306: logic device 306a: first source/drain region 306b: second source /drain region 306c: gate structure M0: metal layer M6~M10: metal layer 400: memory array 117: sense amplifier 119: bit line decoder 127: word line decoder C11~C33: memory unit BL ₁ ~BL ₃ : Bit lines SL ₁ ~SL ₃ : Source lines WL ₁ ~WL ₃ : Word lines 500 : Cross-sectional views 600 : Cross-sectional views 700 a ~ 700 d : Top views 800 ~ 1100 : Cross-sectional views 120 ′: Section A selector source/drain layer 1200-1800: cross section 1900: method 1902-1922: operation

Aspects of the present disclosure can be better understood from the subsequent embodiments and accompanying drawings. It is emphasized that, in accordance with standard industry practice, the various features are not drawn to scale. In fact, the dimensions of the various features may be arbitrarily increased or decreased for clarity of discussion. FIG. 1 shows a cross-sectional view of some embodiments of a memory device including a back-end-of-line (BEOL) select transistor. Figure 2 shows a cross-sectional view of some additional embodiments of memory devices that include BEOL select transistors. Figure 3 shows a cross-sectional view of some additional embodiments of memory devices that include BEOL select transistors. Figure 4 shows a block diagram of some embodiments of a portion of a memory array having a plurality of memory units. 5 is a cross-sectional view of some embodiments of the memory array of FIG. 4 along a column direction, according to some embodiments. 6 is a cross-sectional view of some embodiments of the memory array of FIG. 4 along a row direction, according to some embodiments. Figures 7A-7D show top views of some embodiments of the memory array of Figure 4 illustrating corresponding select transistors. 8-18 show cross-sectional views of some embodiments of a method of forming a memory device including a BEOL select transistor. 19 shows a flowchart of some embodiments of a method of forming a memory device including a BEOL select transistor.

100: Memory device

102: Substrate

104: Interconnect Structure

104L: ILD layer below

104U: Upper ILD layer

106: Intermediate interconnect metal layer

108: Memory unit

110: Bottom electrode

112: Data storage structure

114: Top electrode

116: upper interconnect metal layer

118: select transistor

120: first selector source/drain region

122: Second selector source/drain region

124: Selector gate electrode

126: Selector channel layer

128: Sidewall Spacers

130: Bottom interconnect metal layer

132: Selector gate dielectric layer

134: source/drain layer

Lc: channel length

Claims (8)

A memory device includes: a substrate; an interconnection structure disposed above the substrate, the interconnection structure comprising a plurality of stacked interconnection metal layers disposed in a plurality of stacked interlayer dielectric layers, the stacked interconnection metal layers comprising One is disposed on a lower interconnection metal layer, a middle interconnection metal layer, and an upper interconnection metal layer above the other; a memory cell is disposed on the upper interconnection metal layer and the middle interconnection metal layer between the layers; and a selection transistor connected to the memory unit and disposed between the middle interconnection metal layer and the lower interconnection metal layer, wherein the selection transistor includes: a selector channel layer; A first selector source/drain region and a second selector source/drain region disposed on the selector channel layer; and a sidewall spacer disposed on the first selector source/drain between the first selector source/drain area and the second selector source/drain area, and separate the first selector source/drain area from the second selector source/drain area. The memory device of claim 1, wherein the sidewall spacer has an annular shape and surrounds the second selector source/drain region. The memory device of claim 1, wherein the second selector source/drain region has a circular, oval, square or rectangular shape in a plan view, and is surrounded by the first selector source/drain region surrounded by. The memory device of claim 1, wherein the memory unit comprises a A bottom electrode on the intermediate interconnection metal layer, a data storage structure disposed above the bottom electrode, and a top electrode disposed above the data storage structure. A memory device includes: a substrate; an interconnect structure disposed above the substrate, the interconnect structure including a plurality of interconnect metal layers stacked one above the other and disposed in an interlayer dielectric layer a plurality of memory cells, arranged in the above-mentioned interconnect structure, and arranged in an array of columns and rows; and a plurality of selection transistors, correspondingly connected to the above-mentioned memory cells, wherein the above-mentioned selection transistors are arranged in the above-mentioned interconnection In the structure, between a lower interconnect metal layer and an upper interconnect metal layer of the interconnect structure; wherein a row of the select transistors share a common first selector source/drain region, and each has a Individual second selector source/drain regions, and the individual second selector source/drain regions are separated from the common first selector source/drain region by a sidewall spacer. The memory device of claim 5, wherein the memory cells respectively comprise: a bottom electrode; a data storage structure disposed above the bottom electrode; and a top electrode disposed above the data storage structure; wherein the memory The columns of cells share a common bit line connected to the top electrodes of the columns of the memory cells. The memory device of claim 5, wherein said individual second selector source/drain regions are separated by said common first selector source/drain The island that the area surrounds. A manufacturing method of a memory device, the manufacturing method comprising: forming a lower interconnection metal layer surrounded by a lower interlayer dielectric layer above a substrate; forming a plurality of selective transistors on the lower interconnection metal layer; forming an intermediate interconnection metal layer on the above-mentioned selection transistor; forming a plurality of memory cells on the above-mentioned intermediate interconnection metal layer; and forming an upper interconnection metal layer on the above-mentioned memory cells; wherein one of the above-mentioned selection transistors The formation of the selection transistor includes: forming a selector gate electrode in the lower interlayer dielectric layer; forming a selector channel layer above the selector gate electrode and the lower interlayer dielectric layer; forming a selector channel layer on the selector channel A first selector source/drain area and a second selector source/drain area are formed on the layer; and the above-mentioned intermediate interconnection metal layer is formed on the above-mentioned second selector source/drain area; wherein The formation of the above-mentioned first selector source/drain region and the above-mentioned second selector source/drain region includes: forming a first selector source/drain layer on the above-mentioned selector channel layer; a trench in the first selector source/drain layer; forming a sidewall spacer along sidewalls of the trench; and filling the second selector source/drain region in the trench.

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