TWI775153B - Thin film transistor, method of manufacturing the thin film transistor, and display apparatus including the thin film transistor - Google Patents
Thin film transistor, method of manufacturing the thin film transistor, and display apparatus including the thin film transistor Download PDFInfo
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- TWI775153B TWI775153B TW109132901A TW109132901A TWI775153B TW I775153 B TWI775153 B TW I775153B TW 109132901 A TW109132901 A TW 109132901A TW 109132901 A TW109132901 A TW 109132901A TW I775153 B TWI775153 B TW I775153B
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- H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
- H01L29/68—Types of semiconductor device ; Multistep manufacturing processes therefor controllable by only the electric current supplied, or only the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched
- H01L29/76—Unipolar devices, e.g. field effect transistors
- H01L29/772—Field effect transistors
- H01L29/78—Field effect transistors with field effect produced by an insulated gate
- H01L29/786—Thin film transistors, i.e. transistors with a channel being at least partly a thin film
- H01L29/78696—Thin film transistors, i.e. transistors with a channel being at least partly a thin film characterised by the structure of the channel, e.g. multichannel, transverse or longitudinal shape, length or width, doping structure, or the overlap or alignment between the channel and the gate, the source or the drain, or the contacting structure of the channel
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- G02F1/00—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics
- G02F1/01—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics for the control of the intensity, phase, polarisation or colour
- G02F1/13—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics for the control of the intensity, phase, polarisation or colour based on liquid crystals, e.g. single liquid crystal display cells
- G02F1/133—Constructional arrangements; Operation of liquid crystal cells; Circuit arrangements
- G02F1/136—Liquid crystal cells structurally associated with a semi-conducting layer or substrate, e.g. cells forming part of an integrated circuit
- G02F1/1362—Active matrix addressed cells
- G02F1/1368—Active matrix addressed cells in which the switching element is a three-electrode device
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- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
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- H01L21/0271—Making masks on semiconductor bodies for further photolithographic processing not provided for in group H01L21/18 or H01L21/34 comprising organic layers
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- H01L27/1222—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being other than a semiconductor body, e.g. an insulating body comprising a plurality of TFTs formed on a non-semiconducting substrate, e.g. driving circuits for AMLCDs with a particular composition, shape or crystalline structure of the active layer
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- H01L27/12—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being other than a semiconductor body, e.g. an insulating body
- H01L27/1214—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being other than a semiconductor body, e.g. an insulating body comprising a plurality of TFTs formed on a non-semiconducting substrate, e.g. driving circuits for AMLCDs
- H01L27/1259—Multistep manufacturing methods
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- H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
- H01L29/68—Types of semiconductor device ; Multistep manufacturing processes therefor controllable by only the electric current supplied, or only the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched
- H01L29/76—Unipolar devices, e.g. field effect transistors
- H01L29/772—Field effect transistors
- H01L29/78—Field effect transistors with field effect produced by an insulated gate
- H01L29/786—Thin film transistors, i.e. transistors with a channel being at least partly a thin film
- H01L29/78606—Thin film transistors, i.e. transistors with a channel being at least partly a thin film with supplementary region or layer in the thin film or in the insulated bulk substrate supporting it for controlling or increasing the safety of the device
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- H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
- H01L29/68—Types of semiconductor device ; Multistep manufacturing processes therefor controllable by only the electric current supplied, or only the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched
- H01L29/76—Unipolar devices, e.g. field effect transistors
- H01L29/772—Field effect transistors
- H01L29/78—Field effect transistors with field effect produced by an insulated gate
- H01L29/786—Thin film transistors, i.e. transistors with a channel being at least partly a thin film
- H01L29/78606—Thin film transistors, i.e. transistors with a channel being at least partly a thin film with supplementary region or layer in the thin film or in the insulated bulk substrate supporting it for controlling or increasing the safety of the device
- H01L29/78618—Thin film transistors, i.e. transistors with a channel being at least partly a thin film with supplementary region or layer in the thin film or in the insulated bulk substrate supporting it for controlling or increasing the safety of the device characterised by the drain or the source properties, e.g. the doping structure, the composition, the sectional shape or the contact structure
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- H10K—ORGANIC ELECTRIC SOLID-STATE DEVICES
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- H10K—ORGANIC ELECTRIC SOLID-STATE DEVICES
- H10K59/00—Integrated devices, or assemblies of multiple devices, comprising at least one organic light-emitting element covered by group H10K50/00
- H10K59/10—OLED displays
- H10K59/12—Active-matrix OLED [AMOLED] displays
- H10K59/121—Active-matrix OLED [AMOLED] displays characterised by the geometry or disposition of pixel elements
- H10K59/1213—Active-matrix OLED [AMOLED] displays characterised by the geometry or disposition of pixel elements the pixel elements being TFTs
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Abstract
Description
本發明關於一種薄膜電晶體、薄膜電晶體的製造方法以及包含薄膜電晶體的顯示設備,特別係關於一種基於本身的偏差部而具有優異的開關特性之薄膜電晶體、這種薄膜電晶體的製造方法及包含這種薄膜電晶體的顯示設備。The present invention relates to a thin film transistor, a method for manufacturing the thin film transistor, and a display device including the thin film transistor, and in particular, to a thin film transistor with excellent switching characteristics based on its own deviation, and the production of the thin film transistor Methods and display devices including such thin film transistors.
可於玻璃基板或塑膠基板上製造薄膜電晶體(Thin-Film Transistor,TFT),因此薄膜電晶體被廣泛地作為顯示設備的開關元件或驅動元件使用,其中顯示設備例如為液晶顯示器(liquid crystal display,LCD)設備及有機發光顯示設備。Thin-Film Transistor (TFT) can be fabricated on a glass substrate or a plastic substrate, so thin-film transistors are widely used as switching elements or driving elements of display devices, such as liquid crystal displays. , LCD) equipment and organic light-emitting display equipment.
根據各個主動層的材料,可將薄膜電晶體分類成使用非晶矽(amorphous silicon,a-Si)作為主動層的非晶矽薄膜電晶體、使用多晶矽(polycrystalline silicon,poly-Si)作為主動層的多晶矽薄膜電晶體,以及使用氧化物半導體作為主動層的氧化物半導體薄膜電晶體。According to the material of each active layer, thin film transistors can be classified into amorphous silicon thin film transistors using amorphous silicon (a-Si) as the active layer, polycrystalline silicon (poly-Si) as the active layer of polysilicon thin film transistors, and oxide semiconductor thin film transistors using oxide semiconductors as active layers.
可藉由短時間持續沉積非晶矽主動層來形成主動層,因此非晶矽薄膜電晶體具有短的製造時間及低的製造成本。另一方面,因為電流的驅動效能會因為臨界電壓的低移動率(mobility)或偏移而降低,所以將非晶矽薄膜電晶體應用於主動矩陣有機發光二極體(active matrix organic light emitting diode,AMOLED)等會產生限制。The active layer can be formed by continuously depositing the amorphous silicon active layer for a short time, so the amorphous silicon thin film transistor has a short manufacturing time and low manufacturing cost. On the other hand, since the current driving performance is reduced due to the low mobility or shift of the threshold voltage, amorphous silicon thin film transistors are applied to active matrix organic light emitting diodes. , AMOLED), etc. will have limitations.
多晶矽薄膜電晶體是藉由沉積及結晶非晶矽所製造而成。多晶矽薄膜電晶體具有高的電子移動率、好的穩定度、薄的厚度以及高的能量效率,並可實現高解析度。多晶矽薄膜電晶體的示例包含低溫多晶矽(low temperature polysilicon,LTPS)薄膜電晶體及多晶矽薄膜電晶體。然,因為多晶矽薄膜電晶體的製程需要包含使非晶矽結晶的步驟且非晶矽需要在高的處理溫度下結晶,所以會增加製程的數量而使製造成本增加。因此,難以將多晶矽薄膜電晶體應用於大面積的顯示設備。並且,因為多晶體特性的緣故,難以確保多晶矽薄膜電晶體的均勻度。Polysilicon thin film transistors are fabricated by depositing and crystallizing amorphous silicon. Polysilicon thin film transistors have high electron mobility, good stability, thin thickness, and high energy efficiency, and can achieve high resolution. Examples of polysilicon thin film transistors include low temperature polysilicon (LTPS) thin film transistors and polysilicon thin film transistors. However, since the manufacturing process of the polysilicon thin film transistor needs to include a step of crystallizing the amorphous silicon and the amorphous silicon needs to be crystallized at a high processing temperature, the number of manufacturing processes is increased and the manufacturing cost is increased. Therefore, it is difficult to apply polysilicon thin film transistors to large-area display devices. Also, it is difficult to ensure the uniformity of polycrystalline silicon thin film transistors due to polycrystalline properties.
基於氧的性質,氧化物半導體薄膜電晶體具有高的移動率以及大的電阻變化,因此可輕易地獲得所需的物理特性。並且,在製造氧化物半導體薄膜電晶體的過程中,包含於主動層中的氧化物可於相對較低的溫度形成而使得製造成本為低的。就氧化物的特性而言,氧化物半導體為透明的,因而能輕易實施透明的顯示設備。然,相較於多晶矽薄膜電晶體而言,氧化物半導體薄膜電晶體具有較低的穩定度及電子移動率。Based on the properties of oxygen, oxide semiconductor thin film transistors have high mobility and large resistance change, and thus can easily obtain desired physical properties. Also, in the process of manufacturing the oxide semiconductor thin film transistor, the oxide contained in the active layer can be formed at a relatively low temperature so that the manufacturing cost is low. Oxide semiconductors are transparent in terms of properties of oxides, and thus a transparent display device can be easily implemented. Of course, oxide semiconductor thin film transistors have lower stability and electron mobility than polysilicon thin film transistors.
可將製造氧化物半導體薄膜電晶體製造成底閘極形式的背通道蝕刻(back channel etch,BCE)結構或蝕刻阻擋(etch stopper,ES)結構,或是製造成頂閘極形式的共平面結構。在具有共平面結構的氧化物半導體薄膜電晶體中,從氧化物半導體形成的導體提供區域(conductivity-providing region)之控制為非常重要的,且氧化物半導體薄膜電晶體的移動率可能會根據導體提供區域的薄片電阻(sheet resistance)而改變。因此,為了形成導體提供區域會需要控管製程條件,且需要於導體提供區域上使設置在氧化物半導體層上或下的絕緣層的影響最小化。The oxide semiconductor thin film transistor can be fabricated into a back channel etch (BCE) structure or an etch stopper (ES) structure in the form of a bottom gate, or a coplanar structure in the form of a top gate . In an oxide semiconductor thin film transistor having a coplanar structure, control of a conductor-providing region formed from an oxide semiconductor is very important, and the mobility of the oxide semiconductor thin film transistor may vary depending on the conductor The sheet resistance of the provided area varies. Therefore, it may be necessary to control the process conditions in order to form the conductor supply region, and it is necessary to minimize the influence of the insulating layer provided on or under the oxide semiconductor layer on the conductor supply region.
因此,本發明在於提供一種薄膜電晶體、薄膜電晶體的製造方法及包含薄膜電晶體的顯示設備,它們實質上解決習知技術的缺點或限制所導致的一或多個問題。Accordingly, the present invention provides a thin film transistor, a method for manufacturing the thin film transistor, and a display device including the thin film transistor, which substantially solve one or more problems caused by the shortcomings or limitations of the prior art.
本發明一方面係在於提供一種包含導體提供部的薄膜電晶體,其中導體提供部在沒有透過圖案化閘極絕緣層的情況下透過摻雜所形成。One aspect of the present invention is to provide a thin film transistor including a conductor supplying portion, wherein the conductor supplying portion is formed by doping without passing through a patterned gate insulating layer.
本發明另一方面在於提供一種薄膜電晶體,其藉由使用包含偏差部的主動層,確保通道部以及導體提供部的電性穩定度並使主動層上的絕緣層之影響最小化。Another aspect of the present invention is to provide a thin film transistor that ensures the electrical stability of the channel portion and the conductor providing portion and minimizes the influence of the insulating layer on the active layer by using the active layer including the offset portion.
本發明另一方面在於提供一種薄膜電晶體,其根據偏差部確保有效的通道寬度。Another aspect of the present invention is to provide a thin film transistor that secures an effective channel width according to a deviation portion.
本發明另一方面在於提供一種技術,其用於調整光阻圖案的尺寸以在半導體層的通道部及導體提供部之間形成偏差部。Another aspect of the present invention is to provide a technique for adjusting the size of a photoresist pattern to form an offset portion between a channel portion and a conductor providing portion of a semiconductor layer.
本發明另一方面在於提供一種包含薄膜電晶體的顯示設備。Another aspect of the present invention is to provide a display device including a thin film transistor.
本發明額外的優點及特徵將於以下的敘述中部分地闡述,且部分將基於檢驗以下敘述而對熟悉本技藝者為顯而易見的或可由實施本發明習得。本發明的目的及其他優點將可由以下敘述、請求項及附圖具體指出的結構實現及獲得。Additional advantages and features of the present invention will be set forth in part in the description that follows, and in part will be apparent to those skilled in the art upon examination of the description that follows, or may be learned by practice of the invention. The objectives and other advantages of the invention will be realized and attained by the structure particularly pointed out in the following description, claims and appended drawings.
為了根據本發明的目的達成這些及其他優點,如於此實施及廣泛地描述,提供有一種薄膜電晶體包含一主動層、一閘極電極以及一閘極絕緣層。主動層位於一基板上。閘極電極分離於主動層以至少部分地重疊於主動層。閘極絕緣層位於主動層及閘極電極之間。閘極絕緣層可覆蓋面對閘極電極的主動層的整個頂面。主動層可包含一通道部、一導體提供部以及一偏差部。通道部重疊於閘極電極。導體提供部不重疊於閘極電極。偏差部位於通道部及導體提供部之間。偏差部可不重疊於閘極電極。導體提供部可摻雜有一摻雜物。To achieve these and other advantages in accordance with the objectives of the present invention, as embodied and broadly described herein, there is provided a thin film transistor comprising an active layer, a gate electrode, and a gate insulating layer. The active layer is located on a substrate. The gate electrode is separated from the active layer to at least partially overlap the active layer. The gate insulating layer is located between the active layer and the gate electrode. The gate insulating layer may cover the entire top surface of the active layer facing the gate electrode. The active layer may include a channel portion, a conductor supply portion, and an offset portion. The channel portion overlaps the gate electrode. The conductor supply portion does not overlap the gate electrode. The offset portion is located between the channel portion and the conductor providing portion. The offset portion may not overlap with the gate electrode. The conductor supply portion may be doped with a dopant.
於本發明另一態樣中,提供有一種薄膜電晶體基板,其包含一基座基板、一第一薄膜電晶體以及一第二薄膜電晶體。第一薄膜電晶體以及第二薄膜電晶體位於基座基板上。第一薄膜電晶體可包含一第一主動層及一第一閘極電極。第一主動層位於基座基板上。第一閘極電極分離於第一主動層以至少部分地重疊於第一主動層。第二薄膜電晶體可包含一第二主動層、一閘極電極以及一閘極絕緣層。第二主動層位於基座基板上。閘極電極分離於第二主動層以至少部分地重疊於第二主動層。閘極絕緣層位於第二主動層及第二閘極電極之間。閘極絕緣層可覆蓋面對第二閘極電極的第二主動層的整個頂面。此外,第二主動層可包含一通道部、一導體提供部以及一偏差部。通道部重疊於第二閘極電極。導體提供部不重疊於第二閘極電極。偏差部位於通道部及導體提供部之間。偏差部不重疊於第二閘極電極。導體提供部摻雜有一摻雜物。第一主動層及第二主動層可設置於不同的層體上。In another aspect of the present invention, a thin film transistor substrate is provided, which includes a base substrate, a first thin film transistor, and a second thin film transistor. The first thin film transistor and the second thin film transistor are located on the base substrate. The first thin film transistor may include a first active layer and a first gate electrode. The first active layer is on the base substrate. The first gate electrode is separated from the first active layer to at least partially overlap the first active layer. The second thin film transistor may include a second active layer, a gate electrode and a gate insulating layer. The second active layer is on the base substrate. The gate electrode is separated from the second active layer to at least partially overlap the second active layer. The gate insulating layer is located between the second active layer and the second gate electrode. The gate insulating layer may cover the entire top surface of the second active layer facing the second gate electrode. In addition, the second active layer may include a channel portion, a conductor providing portion, and an offset portion. The channel portion overlaps the second gate electrode. The conductor supply portion does not overlap the second gate electrode. The offset portion is located between the channel portion and the conductor providing portion. The offset portion does not overlap the second gate electrode. The conductor supply portion is doped with a dopant. The first active layer and the second active layer can be disposed on different layers.
於本發明另一態樣中,提供有一種製造一薄膜電晶體的方法,此方法包含在一基板上形成一主動層、在主動層上形成一閘極絕緣層、在閘極絕緣層上形成一閘極電極以至少部分地重疊於主動層,以及在主動層摻雜一摻雜物。閘極絕緣層可覆蓋面對閘極電極的主動層的整個頂面。形成閘極電極的步驟可包含在閘極絕緣層上形成一閘極電極材料層、在閘極電極材料層上形成一光阻圖案、藉由使用光阻圖案作為遮罩來蝕刻閘極電極材料層。光阻圖案的面積大於閘極電極的面積。在平面視角中,閘極電極設置於由光阻圖案界定的區域中。因此,在主動層上摻雜摻雜物的步驟中可使用光阻圖案作為遮罩。In another aspect of the present invention, there is provided a method of manufacturing a thin film transistor. The method includes forming an active layer on a substrate, forming a gate insulating layer on the active layer, and forming a gate insulating layer on the gate insulating layer. A gate electrode at least partially overlaps the active layer, and the active layer is doped with a dopant. The gate insulating layer may cover the entire top surface of the active layer facing the gate electrode. The step of forming the gate electrode may include forming a gate electrode material layer on the gate insulating layer, forming a photoresist pattern on the gate electrode material layer, and etching the gate electrode material by using the photoresist pattern as a mask Floor. The area of the photoresist pattern is larger than that of the gate electrode. In a plan view, the gate electrode is disposed in the area defined by the photoresist pattern. Therefore, the photoresist pattern can be used as a mask in the step of doping the dopant on the active layer.
於本發明另一態樣中,提供有一種顯示設備,其包含一基板、一像素驅動電路以及一發光裝置。像素驅動電路位於基板上。發光裝置連接於像素驅動電路。像素驅動電路可包含一薄膜電晶體。薄膜電晶體可包含一主動層、一閘極電極以及一閘極絕緣層。主動層位於基板上。閘極電極分離於主動層以至少部分地重疊於主動層。閘極絕緣層位於主動層及閘極電極之間。閘極絕緣層可覆蓋面對閘極電極的主動層的整個頂面。主動層可包含一通道部、一導體提供部以及一偏差部。通道部重疊於閘極電極。導體提供部不重疊於閘極電極。偏差部位於通道部及導體提供部之間。偏差部可不重疊於閘極電極。導體提供部可摻雜有一摻雜物。In another aspect of the present invention, a display device is provided, which includes a substrate, a pixel driving circuit, and a light-emitting device. The pixel driving circuit is located on the substrate. The light-emitting device is connected to the pixel driving circuit. The pixel driving circuit may include a thin film transistor. The thin film transistor may include an active layer, a gate electrode and a gate insulating layer. The active layer is on the substrate. The gate electrode is separated from the active layer to at least partially overlap the active layer. The gate insulating layer is located between the active layer and the gate electrode. The gate insulating layer may cover the entire top surface of the active layer facing the gate electrode. The active layer may include a channel portion, a conductor supply portion, and an offset portion. The channel portion overlaps the gate electrode. The conductor supply portion does not overlap the gate electrode. The offset portion is located between the channel portion and the conductor providing portion. The offset portion may not overlap with the gate electrode. The conductor supply portion may be doped with a dopant.
本發明另一態樣中,提供有一種顯示設備,其包含一第一薄膜電晶體、一第一中間絕緣層、一第二薄膜電晶體以及一第二中間絕緣層。第一薄膜電晶體包含一第一主動層、一第一閘極電極、一第一閘極絕緣層、一第一源極電極及一第一汲極電極。第一主動層包含多晶矽。第一閘極電極重疊於第一主動層。第一閘極絕緣層位於第一主動層及第一閘極電極之間。第一源極電極及第一汲極電極各自連接於第一主動層。第一中間絕緣層設置於第一閘極電極上。第二薄膜電晶體包含一第二主動層、一第二閘極電極、一第二閘極絕緣層、一第二源極電極及一第二汲極電極。第二主動層包含氧化物半導體。第二閘極電極重疊於第二主動層。第二閘極絕緣層位於第二主動層及第二閘極電極之間。第二源極電極及第二汲極電極各自連接於第二主動層。第二中間絕緣層設置於第一閘極電極、第二閘極電極及第二閘極絕緣層上。第二閘極絕緣層及第二中間絕緣層包含用於摻雜第二主動層的一摻雜物。In another aspect of the present invention, a display device is provided, which includes a first thin film transistor, a first intermediate insulating layer, a second thin film transistor, and a second intermediate insulating layer. The first thin film transistor includes a first active layer, a first gate electrode, a first gate insulating layer, a first source electrode and a first drain electrode. The first active layer includes polysilicon. The first gate electrode overlaps the first active layer. The first gate insulating layer is located between the first active layer and the first gate electrode. The first source electrode and the first drain electrode are respectively connected to the first active layer. The first intermediate insulating layer is disposed on the first gate electrode. The second thin film transistor includes a second active layer, a second gate electrode, a second gate insulating layer, a second source electrode and a second drain electrode. The second active layer includes an oxide semiconductor. The second gate electrode overlaps the second active layer. The second gate insulating layer is located between the second active layer and the second gate electrode. The second source electrode and the second drain electrode are respectively connected to the second active layer. The second intermediate insulating layer is disposed on the first gate electrode, the second gate electrode and the second gate insulating layer. The second gate insulating layer and the second intermediate insulating layer include a dopant for doping the second active layer.
可以理解的是,本發明以上的概略性描述及以下的實施方式僅為示例性的並旨在提供請求項所請之發明更進一步的解釋。It is to be understood that the foregoing general description and the following embodiments of the present invention are exemplary only and are intended to provide further explanation of the claimed invention.
將透過以下的實施例及圖式闡述本發明的優點、特徵及其實施方法。然,本發明可用各種不同的方式實施且不應以於此闡述的實施例為限。反之,這些實施例僅用於使本發明更透徹及完整,並對本領域具通常知識者完整地傳達本發明的範圍。此外,本發明僅由請求項的範圍所界定。The advantages, features and implementation methods of the present invention will be illustrated by the following examples and drawings. However, the present invention may be embodied in various different forms and should not be limited by the examples set forth herein. Rather, these embodiments are only provided so that this disclosure will be thorough and complete, and will fully convey the scope of the present invention to those skilled in the art. Furthermore, the present invention is limited only by the scope of the claims.
圖式中用於描述本發明的實施例之外形、尺寸、比例、角度及數量僅為示例,因此本發明並不限於所繪示的細節。相似的標號於通篇指相似的元件。於以下的描述中,當相關的習知功能或構造會不必要地模糊本發明的重點時,將省略其詳細描述。The shapes, dimensions, proportions, angles and numbers of the embodiments used to describe the present invention in the drawings are only examples, and thus the present invention is not limited to the illustrated details. Like numbers refer to like elements throughout. In the following description, a detailed description of related conventional functions or constructions will be omitted when they would unnecessarily obscure the gist of the present invention.
本說明書中使用「包含」、「具有」及「包括」來描述時,除非使用「僅」,否則可添加另一部件。除非另有說明,否則單數形式的用語可包含複數的形式。When "comprising", "having" and "including" are used in this specification to describe, unless "only" is used, another component may be added. Terms in the singular may include the plural unless stated otherwise.
在解釋元件時,即使沒有詳細的描述此元件,仍應被解釋為包含誤差範圍。When explaining an element, even if the element is not described in detail, it should be interpreted as including a range of error.
在描述位置關係時,例如兩個部件之間的位置關係使用「上」、「之上」、「下」及「附近」描述時,除非使用「緊接」或「直接」,否則可在這兩個部件之間設置一或多個其他部件。When describing the positional relationship, for example, when the positional relationship between two components is described using "above", "above", "below" and "near", unless "immediately" or "directly" is used, it can be used here. One or more other components are placed between the two components.
空間相對用語「之下」、「以下」、「底部」、「之上」及「頂部」可於此用來簡易地描述圖式中繪示的裝置或元件之間的關係。可以理解的是,除了圖式中描繪的位向之外,這些空間相對用語還旨在涵蓋裝置的不同位向。舉例來說,若將圖式中的裝置反過來,被描述為位在其他元件的一側之下或以下的元件可位於其他元件的該側之上。示例性用語「底部」可涵蓋底部及頂部的位向。相似的,示例性用語「之上」或「頂部」可表達之上及之下的位向。The spatially relative terms "below," "below," "bottom," "above," and "top" may be used herein to simply describe the relationship between the devices or elements depicted in the figures. It will be appreciated that these spatially relative terms are intended to encompass different orientations of the device in addition to the orientations depicted in the figures. For example, if the device in the figures is reversed, elements described as being located below or below one side of other elements may be located above those sides of the other elements. The exemplary term "bottom" can encompass the orientation of bottom and top. Similarly, the exemplary terms "above" or "top" can express both an orientation of above and below.
在描述時間關係時,例如使用「之後」、「隨後」、「下一個」及「之前」時,除非使用「緊接」或「直接」,否則可包含不連續的情況。When describing temporal relationships, such as when using "after", "subsequent to", "next" and "before", unless "immediately" or "directly" is used, discontinuities may be included.
可以理解的是,雖然用語「第一」、「第二」等可於此被用來描述各種元件,但這些元件並不以這些用語為限。這些用語僅用來分辨這些元件。舉例來說,在不脫離本發明之範圍的情況下,第一元件可稱為第二元件,且相似地,第二元件可稱為第一元件。It will be understood that, although the terms "first," "second," etc. may be used herein to describe various elements, these elements are not limited by these terms. These terms are only used to identify these elements. For example, a first element could be termed a second element, and, similarly, a second element could be termed a first element, without departing from the scope of the present invention.
在描述本發明的元件時,可使用如第一、第二、A、B、(a)、(b)等用語。這種用語僅用於區別對應的元件及其他元件,且這些元件的本質、順序或優先性並不以這些用語為限。可以理解的是,當元件或層體被稱為位於另一元件或層體上或連接於另一元件或層體時,它可以直接地位於或連接於其他元件或層體上,或是可存在中間元件或層體。並且,應理解的是當元件設置於另一元件上或下時,可表示元件之間直接彼此接觸或可表示元件之間沒有直接彼此接觸。In describing elements of the invention, terms such as first, second, A, B, (a), (b), etc. may be used. Such terms are only used to distinguish corresponding elements from other elements, and the nature, order, or priority of these elements is not limited by these terms. It will be understood that when an element or layer is referred to as being on or connected to another element or layer, it can be directly on or connected to the other element or layer, or it can be There are intermediate elements or layers. Also, it should be understood that when an element is disposed on or under another element, it may mean that the elements are in direct contact with each other or may mean that the elements are not in direct contact with each other.
用語「至少一」應理解為包含一或多個相關列示元件的任何及所有組合。舉例來說,「第一元件、第二元件及第三元件其中至少一者」表示第一元件、第二元件及第三元件中的二或更多者之所有組合以及第一元件、第二元件或第三元件。The term "at least one" should be understood to include any and all combinations of one or more of the associated listed elements. For example, "at least one of the first, second, and third elements" means all combinations of two or more of the first, second, and third elements as well as the first, second, and element or third element.
本發明的各種實施例之特徵可部分或整體地彼此連接或結合,且可以熟悉本技藝者能充分理解的各種方式技術性地彼此交互運作及驅動。本發明的實施例可彼此獨立地執行或可以共同相關的關係一起執行。The features of the various embodiments of the invention may be connected or combined with each other in part or in whole, and may technically interact and actuate with each other in various ways well understood by those skilled in the art. Embodiments of the invention may be performed independently of each other or may be performed together in a commonly related relationship.
現在將詳細描述本發明的示例性實施例,其示例將於附圖中繪示。相同的標號將盡可能地於各個附圖中指相同或相似的部件。Reference will now be made in detail to exemplary embodiments of the present invention, examples of which are illustrated in the accompanying drawings. Wherever possible, the same reference numbers will be used throughout the various drawings to refer to the same or like parts.
在本發明的實施例中,為了方便描述,源極電極及汲極電極可彼此不同,且源極電極及汲極電極可具有相同的意涵。源極電極可為汲極電極,且汲極電極可為源極電極。並且,於一實施例中的源極電極可為另一實施例中的汲極電極,且於一實施例中的汲極電極可為另一實施例中的源極電極。In the embodiments of the present invention, for convenience of description, the source electrode and the drain electrode may be different from each other, and the source electrode and the drain electrode may have the same meaning. The source electrode may be a drain electrode, and the drain electrode may be a source electrode. Also, the source electrode in one embodiment can be the drain electrode in another embodiment, and the drain electrode in one embodiment can be the source electrode in another embodiment.
在本發明的某些實施例中,為了方便描述,源極區域及源極電極可彼此不同且汲極區域及汲極電極可彼此不同,但本發明的實施例並不以此為限。源極區域可為源極電極,且汲極區域可為汲極電極。並且,源極區域可為汲極電極,且汲極區域可為源極電極。In some embodiments of the present invention, for convenience of description, the source region and the source electrode may be different from each other and the drain region and the drain electrode may be different from each other, but the embodiments of the present invention are not limited thereto. The source region may be a source electrode, and the drain region may be a drain electrode. Also, the source region may be a drain electrode, and the drain region may be a source electrode.
圖1為根據本發明一實施例的薄膜電晶體100之剖面示意圖。FIG. 1 is a schematic cross-sectional view of a
根據本發明一實施例的薄膜電晶體100可包含一主動層130、一閘極電極140以及一閘極絕緣層150。主動層130位於一基板110上。閘極電極140分離於主動層130以至少部份地重疊於主動層130。閘極絕緣層150位於主動層130及閘極電極140之間。閘極絕緣層150可覆蓋面對閘極電極140的主動層130的整個頂面。The
主動層130可包含一通道部131、多個導體提供部133a、133b以及多個偏差部132a、132b。通道部131重疊於閘極電極140。導體提供部133a、133b不重疊於閘極電極140。偏差部132a、132b位於通道部131及導體提供部133a、133b之間。根據本發明一實施例,偏差部132a、132b可不重疊於閘極電極140,且導體提供部133a、133b可摻雜有摻雜物。The
以下,將參照圖1詳細說明根據本發明一實施例的薄膜電晶體100。Hereinafter, the
請參閱圖1,主動層130可設置於基板110上。Referring to FIG. 1 , the
基板110可使用玻璃或塑膠。塑膠可使用具有可撓特性的透明塑膠(如聚醯亞胺)。在使用聚醯亞胺作為基板110的情況中,可根據在基板110上執行高溫沉積製程而使用耐高溫的耐熱聚醯亞胺。The
緩衝層120可設置於基板110上。緩衝層120可包含氧化矽及氮化矽其中至少一者。緩衝層120可保護主動層130且可具有平坦化特性以將基板110的頂部平坦化。緩衝層120可被省略。The
根據本發明一實施例,主動層130可包含氧化物半導體材料。主動層130可為氧化物半導體層。According to an embodiment of the present invention, the
主動層130例如可包含至少一氧化物半導體材料,如氧化銦鋅(InZnO,IZO)、氧化銦鎵(InGaO,IGO)、氧化銦錫(InSnO,ITO)、氧化銦鎵鋅(InGaZnO,IGZO)、氧化銦鎵鋅錫(InGaZnSnO,IGZTO)、氧化銦錫鋅(InSnZnO,ITZO)、氧化銦鎵錫(InGaSnO,IGTO)、氧化鎵(GaO,GO)、氧化鎵鋅錫(GaZnSnO,GZTO)及氧化鎵鋅(GaZnO,GZO)。然,本發明的實施例並不以此為限,且主動層130可包含另一氧化物半導體材料。For example, the
主動層130可包含通道部131及導體提供部133a、133b。並且,主動層130可包含設置於通道部131及導體提供部133a、133b之間的偏差部132a、132b。The
閘極絕緣層150可設置於主動層130上。閘極絕緣層150可具有絕緣特性且可包含氧化矽、氮化矽及金屬氧化物(metal-based oxide)其中至少一者。閘極絕緣層150可具有單層結構或可具有多層結構。The
閘極絕緣層150可覆蓋主動層130的整個頂面。於圖1中,主動層130的多個表面中設置在朝向閘極電極140的方向中之表面可被稱作頂面。The
根據本發明一實施例,如圖1所示,閘極絕緣層150可無須被圖案化且可被形成以覆蓋包含主動層130的基板110的整個表面。According to an embodiment of the present invention, as shown in FIG. 1 , the
然而,本發明的實施例並不以此為限,且閘極絕緣層150中可形成有接觸孔。在閘極絕緣層150中形成有接觸孔的情況中,部分的主動層130可藉由接觸孔從閘極絕緣層150暴露。於本發明的一實施例中,閘極絕緣層150可覆蓋主動層130中除了接觸孔區域之外的整個頂面。並且,於本發明的一實施例中,閘極絕緣層150可覆蓋主動層130中除了接觸導體元件之區域之外的整個頂面。於此,導體元件可指接觸或連接於主動層130且包含導體材料的元件,且導體材料可包含線路(wiring line)、電極、墊片(pad)、終端等等。舉例來說,導體元件可包含各自連接於主動層130的一源極電極161及一汲極電極162(請參閱圖2)。However, the embodiments of the present invention are not limited thereto, and a contact hole may be formed in the
於本發明的一實施例中,閘極絕緣層150可被設置以至少覆蓋主動層130的偏差部132a、132b及通道部131的頂面。In an embodiment of the present invention, the
於本發明的一實施例中,部分的主動層130可基於使用摻雜物的摻雜製程而具有傳導性,且於此情況中,摻雜物可通過閘極絕緣層150並可被摻雜於主動層130。因此,即使沒有從閘極絕緣層150暴露,仍可對主動層130進行摻雜。因此,於本發明的一實施例中,閘極絕緣層150可無須被圖案化。In one embodiment of the present invention, a portion of the
閘極電極140可設置於閘極絕緣層150上。閘極電極140可包含如鋁或鋁合金的鋁材料(aluminum-based metal)、如銀或銀合金之銀材料(silver-based metal)、如銅或銅合金之銅材料(copper-based metal)、如鉬或鉬合金之鉬材料(molybdenum-based metal)、鉻(Cr)、鉭(Ta)、釹(Nd)及鈦(Ti)其中至少一者。閘極電極140可具有多層結構,且此多層結構包含具有不同特性的至少二導體層。The
閘極電極140可重疊於主動層130的通道部131。主動層130中重疊於閘極電極140的部分可為通道部131。The
導體提供部133a、133b可無須重疊於閘極電極140。導體提供部133a、133b其中一者可為源極區域,且導體提供部133a、133b其中另一者可為汲極區域。依據實際情況,源極區域可作為源極電極,且汲極區域可作為汲極電極。導體提供部133a、133b可各自作為線路。The
根據本發明一實施例,導體提供部133a、133b可藉由選擇性地將傳導性(conductivity)提供給主動層130而形成。舉例來說,導體提供部133a、133b可藉由使用摻雜物的摻雜製程形成。根據本發明一實施例,導體提供部133a、133b可處於摻雜有摻雜物的狀態。According to an embodiment of the present invention, the
摻雜物可包含硼(B)、磷(P)、氟(F)及氫(H)其中至少一者。硼離子、磷離子及氟離子其中至少一者可用於進行摻雜。氫離子可用於進行摻雜。The dopant may include at least one of boron (B), phosphorus (P), fluorine (F), and hydrogen (H). At least one of boron ion, phosphorus ion and fluoride ion can be used for doping. Hydrogen ions can be used for doping.
導體提供部133a、133b的摻雜濃度可高於通道部131的摻雜濃度,且導體提供部133a、133b的電阻率可低於通道部131的電阻率。導體提供部133a、133b的導電度可高於各個偏差部132a、132b的導電度,且導體提供部133a、133b的導電度可相似於導體的導電度。The doping concentration of the
根據本發明一實施例,偏差部132a、132b可設置於通道部及導體提供部133a、133b之間且可不重疊於閘極電極140。According to an embodiment of the present invention, the
雖然在製造薄膜電晶體100的過程中摻雜物沒有直接被植入到偏差部132a、132b中(請參閱圖7),但於將摻雜物植入到導體提供部133a、133b中的過程中摻雜物可能會擴散到偏差部132a、132b。因此,某些摻雜物可摻雜於偏差部132a、132b。Although dopants are not directly implanted into the offset
根據本發明一實施例,各個偏差部132a、132b的電阻率可低於通道部131的電阻率且可高於各個導體提供部133a、133b的電阻率。具有這種電阻率特性的偏差部132a、132b可於導體提供部133a、133b及通道部131之間執行緩衝功能。According to an embodiment of the present invention, the resistivity of each
在通道部131直接連接於導體提供部133a、133b的情況中,當薄膜電晶體100處於關閉狀態時,可能會產生漏電流。另一方面,當電阻率比各個導體提供部133a、133b高的偏差部132a、132b設置於導體提供部133a、133b及通道部131之間時,可在薄膜電晶體100處於關閉狀態時防止通道部131及導體提供部133a、133b之間產生漏電流。In the case where the
如上所述,當偏差部132a、132b設置於導體提供部133a、133b及通道部131之間時,可提升通道部131及導體提供部133a、133b的電性穩定度。As described above, when the
即使在薄膜電晶體100根據施加到閘極電極140的閘極電壓而開啟的時候,仍可不使偏差部132a、132b的傳導性增加,其中偏差部132a、132b不會被閘極電極140中產生的電場大幅度地影響。因此,當薄膜電晶體100開啟時,偏差部132a、132b的電阻率可高於通道部131的電阻率以及各個導體提供部133a、133b的電阻率。因此,可藉由偏差部132a、132b防止或減緩薄膜電晶體100的臨界電壓偏移。Even when the
根據本發明一實施例,各個偏差部132a、132b的寬度L2可設定於特定範圍中而能在不干擾薄膜電晶體100之驅動的情況下防止薄膜電晶體100之漏電流以及薄膜電晶體100的臨界電壓偏移。According to an embodiment of the present invention, the width L2 of each
根據本發明一實施例,第一偏差部132a的寬度可相同或相異於第二偏差部132b的寬度。於本發明的一實施例中,為了方便說明,第一偏差部132a的寬度及第二偏差部132b的寬度可彼此相同且可為寬度L2。According to an embodiment of the present invention, the width of the
根據本發明一實施例,當通道部131具有寬度L1且各個偏差部132a、132b具有寬度L2時,薄膜電晶體100可滿足以下的方程式1。According to an embodiment of the present invention, when the
[方程式1][Equation 1]
L1 x L2 x 1/η1 ≥ 1L1 x L2 x 1/η1 ≥ 1
其中η1 = 0.5平方微米where η1 = 0.5 square microns
當通道部131的寬度L1及各個偏差部132a、132b的寬度L2滿足方程式1時,偏差部132a、132b可在不干擾薄膜電晶體100之驅動的情況下防止薄膜電晶體100的漏電流以及薄膜電晶體100的臨界電壓偏移。When the width L1 of the
根據本發明另一實施例,於方程式1中,η1 = 1.5平方微米。或者,η1可滿足下列關係式:0.5平方微米 ≤ η1 ≤ 1.5平方微米。According to another embodiment of the present invention, in
根據本發明一實施例,各個偏差部132a、132b的寬度L2可為0.25微米或更大。當各個偏差部132a、132b的寬度L2小於0.3微米時,可能會不足以提供防止薄膜電晶體100的漏電流之效果以及防止薄膜電晶體100的臨界電壓偏移之效果。根據本發明另一實施例,各個偏差部132a、132b的寬度L2可為0.3微米或更大。詳細來說,各個偏差部132a、132b的寬度L2可為0.5微米或更大。According to an embodiment of the present invention, the width L2 of each
根據本發明一實施例,各個偏差部132a、132b的寬度L2可維持於2.5微米。當各個偏差部132a、132b的寬度L2大於2.5微米時,可能會降低薄膜電晶體100的驅動特性,這可能會不利於各個薄膜電晶體的微型化(miniaturize)。According to an embodiment of the present invention, the width L2 of each
根據本發明一實施例,偏差部132a、132b可設置於通道部131及導體提供部133a、133b之間,因此即使在通道部131的寬度L1較窄的時候,通道部131仍可有效地作為通道。因此,可微型化薄膜電晶體100。According to an embodiment of the present invention, the
根據本發明一實施例,通道部131的寬度L1可為2微米或更大。根據本發明一實施例,偏差部132a、132b可設置於通道部131及導體提供部133a、133b之間,因此即使當通道部131的寬度L1約為2微米時,薄膜電晶體100仍可有效地執行開關功能。舉例來說,通道部131的寬度可為2微米至20微米。或者,通道部131的寬度可為2微米至40微米。According to an embodiment of the present invention, the width L1 of the
此外,根據本發明一實施例,通道部131的寬度L1可為3微米或更大,並例如可為4微米或更大。舉例來說,通道部131的寬度可為3微米至20微米、3微米至10微米、3微米至8微米,或是4微米至6微米。In addition, according to an embodiment of the present invention, the width L1 of the
根據本發明一實施例,緩衝層120可設置於基板110及主動層130之間,且摻雜物可摻雜於緩衝層120。According to an embodiment of the present invention, the
可藉由調整於摻雜製程中施加到摻雜物的加速電壓來調整各個導體提供部133a、133b的摻雜濃度、閘極絕緣層150的摻雜濃度以及緩衝層120的摻雜濃度。The doping concentration of each
可增加施加到摻雜物的加速電壓以將摻雜物充分地摻雜於導體提供部133a、133b。於此情況中,摻雜物可通過導體提供部133a、133b且可摻雜於緩衝層120。當摻雜於緩衝層120的摻雜物之濃度增加時,緩衝層120的摻雜濃度可高於各個導體提供部133a、133b的摻雜濃度。The accelerating voltage applied to the dopant may be increased to sufficiently dope the
圖2為根據本發明另一實施例之薄膜電晶體200的剖面示意圖。FIG. 2 is a schematic cross-sectional view of a
相較於圖1中繪示的薄膜電晶體100,圖2中的薄膜電晶體200可更包含一中間絕緣層155、一源極電極161以及一汲極電極162。Compared with the
中間絕緣層155可設置於閘極電極140及閘極絕緣層150上並可包含絕緣材料。The intermediate
源極電極161及汲極電極162可設置於中間絕緣層155上。源極電極161及汲極電極162可彼此分離且可連接於主動層130。The
請參閱圖2,源極電極161可透過接觸孔H1連接於第一導體提供部133a,且汲極電極162可透過接觸孔H2連接於第二導體提供部133b。連接於源極電極161的第一導體提供部133a可稱為源極連接部,且連接於汲極電極162的第二導體提供部133b可稱為汲極連接部。Referring to FIG. 2 , the
請參閱圖2,接觸孔H1、H2可通過中間絕緣層155及閘極絕緣層150。部分的主動層130可藉由接觸孔H1、H2從閘極絕緣層150暴露。舉例來說,部分的第一導體提供部133a及部分的第二導體提供部133b可藉由接觸孔H1、H2從閘極絕緣層150暴露。Referring to FIG. 2 , the contact holes H1 and H2 can pass through the intermediate insulating
圖3為根據本發明另一實施例之薄膜電晶體300的剖面示意圖。FIG. 3 is a schematic cross-sectional view of a
請參閱圖3,根據本發明另一實施例之薄膜電晶體300可包含一遮光層121,遮光層121設置於基板110上。遮光層121可被設置以重疊於主動層130且可遮擋入射在基板110上的光,進而保護主動層130。舉例來說,遮光層121可被設置以重疊於主動層130的通道部131。Referring to FIG. 3 , a
圖4為根據本發明另一實施例的薄膜電晶體400之剖面示意圖。FIG. 4 is a schematic cross-sectional view of a
請參閱圖4,主動層130可具有多層結構。根據圖4中的實施例之薄膜電晶體400的主動層130可包含一第一氧化物半導體層130a以及一第二氧化物半導體層130b,其中第一氧化物半導體層130a位於基板110上且第二氧化物半導體層130b位於第一氧化物半導體層130a上。各個第一氧化物半導體層130a及第二氧化物半導體層130b可包含氧化物半導體材料。第一氧化物半導體層130a及第二氧化物半導體層130b可包含相同的氧化物半導體材料或可包含相異的氧化物半導體材料。Referring to FIG. 4 , the
第一氧化物半導體層130a可支撐第二氧化物半導體層130b。因此,第一氧化物半導體層130a可稱為支撐層。主要的通道可形成於第二氧化物半導體層130b上。因此,第二氧化物半導體層130b可稱為通道層。然而,本發明的實施例並不以此為限,且通道可形成於第一氧化物半導體層130a中。The first
如圖4所示,包含第一氧化物半導體層130a及第二氧化物半導體層130b之半導體層的結構可稱為雙層結構。As shown in FIG. 4, the structure of the semiconductor layer including the first
作為支撐層的第一氧化物半導體層130a可具有良好的薄膜穩定度及機械特性。為了薄膜穩定度,第一氧化物半導體層130a可包含鎵(Ga)。鎵可與氧形成穩定的鍵結(bonding),且鎵的氧化物可具有良好的薄膜穩定度。The first
第一氧化物半導體層130a例如可包含至少一氧化物半導體材料,如氧化銦鎵鋅(InGaZnO,IGZO)、氧化銦鎵(InGaO,IGO)、氧化銦鎵錫(InGaSnO,IGTO)、氧化銦鎵鋅錫(InGaZnSnO,IGZTO)、氧化鎵鋅錫(GaZnSnO,GZTO)、氧化鎵鋅(GaZnO,GZO)及氧化鎵(GaO,GO)。The first
作為通道層的第二氧化物半導體層130b例如可包含至少一氧化物半導體材料,如氧化銦鋅(InZnO,IZO)、氧化銦鎵(InGaO,IGO)、氧化銦錫(InSnO,ITO)、氧化銦鎵鋅(InGaZnO,IGZO)、氧化銦鎵鋅錫(InGaZnSnO,IGZTO)、氧化鎵鋅錫(GaZnSnO,GZTO)及氧化銦錫鋅(InSnZnO,ITZO)。然,本發明的另一實施例並不以此為限,且第二氧化物半導體層130b可包含另一氧化物半導體材料。The second
圖5為根據本發明另一實施例的薄膜電晶體500之剖面示意圖。FIG. 5 is a schematic cross-sectional view of a
根據本發明另一實施例之薄膜電晶體500可包含主動層130、閘極電極140、閘極絕緣層150、源極電極161以及汲極電極162。主動層130位於基板110上。閘極電極140分離於主動層130以在其至少一部分重疊於主動層130。閘極絕緣層150位於主動層130及閘極電極140之間。源極電極161位於閘極絕緣層150上。汲極電極162分離於閘極絕緣層150上的源極電極161。The
請參閱圖5,閘極絕緣層150可覆蓋主動層130的整個頂面。源極電極161及汲極電極162可形成於閘極絕緣層150上。於此情況中,源極電極161及汲極電極162可與閘極電極140設置在相同的層體上,且可與閘極電極140包含相同的材料。各個源極電極161及汲極電極162可藉由接觸孔連接於主動層130,其中接觸孔形成於閘極絕緣層150中。Referring to FIG. 5 , the
圖6為根據本發明另一實施例之薄膜電晶體基板600的剖面示意圖。6 is a schematic cross-sectional view of a thin
根據本發明另一實施例之薄膜電晶體基板600可包含一基座基板210、一第一薄膜電晶體TR1以及一第二薄膜電晶體TR2。第一薄膜電晶體TR1位於基座基板210上。第二薄膜電晶體TR2位於基座基板210上。The thin
第一薄膜電晶體TR1可包含一第一主動層270以及一第一閘極電極280。第一主動層270位於基座基板210上。第一閘極電極280分離於第一主動層270以至少部分地重疊於第一主動層270。並且,第一薄膜電晶體TR1可包含一閘極絕緣層181,且閘極絕緣層181位於第一主動層270及第一閘極電極280之間。The first thin film transistor TR1 may include a first
位於第一主動層270及第一閘極電極280之間的閘極絕緣層181可稱為第一閘極絕緣層。The
第一薄膜電晶體TR1可更包含一第一源極電極281以及一第一汲極電極282。第一源極電極281及第一汲極電極282可彼此分離且可連接於第一主動層270。The first thin film transistor TR1 may further include a
根據本發明另一實施例,第一主動層270可由矽半導體層形成,且可包含通道部271及多個導體提供部272、273。According to another embodiment of the present invention, the first
第二薄膜電晶體TR2可包含一第二主動層230以及一第二閘極電極240。第二主動層230位於基座基板210上,且第二閘極電極240分離於第二主動層230以至少部分地重疊於第二主動層230。第二主動層230可為氧化物半導體層。The second thin film transistor TR2 may include a second
在根據本發明另一實施例之薄膜電晶體基板600中,第二薄膜電晶體TR2與分別繪示於圖1至圖5中的各個薄膜電晶體100至薄膜電晶體500具有相同的構造。In the thin
於根據本發明另一實施例之薄膜電晶體基板600中,第一主動層270及第二主動層230可設置於不同的層體上。請參閱圖6,相較於第二主動層230,第一主動層270可設置在較靠近基座基板210之位置。然,本發明的另一實施例並不以此為限,且相較於第一主動層270,第二主動層230可設置在較靠近基座基板210之位置。並且,第一主動層270可由氧化物半導體層形成,且第二主動層230可由矽半導體層形成。In the thin
請參閱圖6,鈍化層182可設置於第一閘極電極280上,且中間層185可設置於鈍化層182上。Referring to FIG. 6 , the
請參閱圖6,第二薄膜電晶體TR2的第二主動層230可設置於中間層185上。中間層185可為氮化矽層或氧化矽層的單個層體。或者,中間層185可由氮化矽層及氧化矽層堆疊而成的多層結構形成。Referring to FIG. 6 , the second
閘極絕緣層150可設置於第二主動層230上,且第二閘極電極240可設置於閘極絕緣層150上。位於第二主動層230及第二閘極電極240之間的閘極絕緣層150可稱為第二閘極絕緣層。The
閘極絕緣層150可覆蓋面對第二閘極電極240的第二主動層230之整個頂面。閘極絕緣層150例如可設置於包含第二主動層230的基座基板210之整個表面上。The
第二主動層230可包含一通道部231、多個導體提供部233a、233b及多個偏差部232a、232b。偏差部232a、232b位於通道部231及導體提供部233a、233b之間。The second
第二主動層230的通道部231可重疊於第二閘極電極240。第二主動層230的導體提供部233a、233b可無須重疊於第二閘極電極240。偏差部232a、232b可無須重疊於第二閘極電極240。The
導體提供部233a、233b可摻雜有摻雜物。The
第二薄膜電晶體TR2可包含位於一中間絕緣層155上的一第二源極電極261以及一第二汲極電極262。中間絕緣層155可設置於第二閘極電極240及閘極絕緣層150上並可包含絕緣材料。第二源極電極261及第二汲極電極262可於中間絕緣層155上彼此分離且可連接於第二主動層230。一平坦化層192可設置於第一源極電極281、第一汲極電極282、第二源極電極261及第二汲極電極262與中間絕緣層155上。The second thin film transistor TR2 may include a
於圖6中繪示有第一源極電極281、第一汲極電極282、第二源極電極261及第二汲極電極262之構造。然,本發明的另一實施例並不以此為限。舉例來說,第一汲極電極282、第二源極電極261及第二汲極電極262可分別設置於不同的層體上。The structure of the
此外,第一閘極電極280及第二閘極電極240的位置並不以圖6中呈現的態樣為限。當第一主動層270及第二主動層230設置在不同的層體上時,第一閘極電極280及第二閘極電極240可設置在不同於圖6中的位置之位置。In addition, the positions of the
圖7為描述根據本發明一實施例的摻雜方法之圖式。FIG. 7 is a diagram illustrating a doping method according to an embodiment of the present invention.
根據本發明一實施例,可藉由透過摻雜選擇性地提供傳導性給主動層130而形成多個導體提供部133a、133b。According to an embodiment of the present invention, the plurality of
摻雜物可用於摻雜。摻雜物可包含硼(B)、磷(P)、氟(F)及氫(H)其中至少一者。舉例來說,硼、磷及氟其中至少一者可作為摻雜物,或者氫可作為摻雜物。摻雜物可以離子狀態進行摻雜。Dopants can be used for doping. The dopant may include at least one of boron (B), phosphorus (P), fluorine (F), and hydrogen (H). For example, at least one of boron, phosphorus, and fluorine can be used as the dopant, or hydrogen can be used as the dopant. The dopant can be doped in an ionic state.
根據本發明一實施例,可無須在主動層130的通道部131進行摻雜。為了避免對通道部131進行摻雜,可藉由在摻雜製程中針對摻雜物保護或罩住通道部131而使得摻雜物不會植入到通道部131中。According to an embodiment of the present invention, it is not necessary to perform doping on the
如圖7所示,在摻雜製程中,殘留於閘極電極140上的一光阻圖案40可作為用來保護通道部131的遮罩。As shown in FIG. 7 , in the doping process, a
請參閱圖7,相對於剖面示意圖來說,光阻圖案40的寬度可大於閘極電極140的寬度。相對於剖面示意圖來說,閘極電極140可完全地重疊於光阻圖案40。Referring to FIG. 7 , the width of the
相對於平面圖來說,光阻圖案40的面積可大於閘極電極140的面積。舉例來說,相對於平面來說,閘極電極140可設置於由光阻圖案40所界定的區域中。With respect to a plan view, the area of the
根據本發明一實施例,可在閘極絕緣層150上為閘極電極形成閘極電極材料層,可在閘極電極材料層上塗佈光阻材料,且可藉由曝光及產生光阻材料而形成光阻圖案40。According to an embodiment of the present invention, a gate electrode material layer can be formed for the gate electrode on the
隨後,可藉由使用光阻圖案40作為遮罩而透過蝕刻閘極電極材料層來形成閘極電極140。此時,閘極電極材料層可相對光阻圖案40的邊緣被蝕刻至內部,進而形成閘極電極140,其中閘極電極140的面積小於光阻圖案40的面積。Subsequently, the
如圖7所示,主動層130中沒有重疊於光阻圖案40的區域可藉由摻雜製程摻雜有摻雜物,其中摻雜製程使用閘極電極140上的光阻圖案40作為遮罩。因此,可形成這些導體提供部133a、133b。As shown in FIG. 7 , the region of the
摻雜物可不摻雜於受光阻圖案40保護的通道部131。因此,通道部131可維持半導體特性。The dopant may not be doped into the
透過使用摻雜物的摻雜製程而提供有傳導性的導體提供部133a、133b之摻雜濃度可高於通道部131的摻雜濃度,且導體提供部133a、133b之電阻率可低於通道部131的電阻率。The doping concentration of the
請參閱圖7,多個偏差部(如第一及第二偏差部)132a、132b可受光阻圖案40保護。因此,可防止摻雜物直接植入到偏差部132a、132b中。然,摻雜於導體提供部133a、133b的摻雜物可擴散至偏差部132a、132b。因此,可獲得摻雜物部分地摻雜於偏差部132a、132b的效果。Referring to FIG. 7 , a plurality of offset parts (eg, the first and second offset parts) 132 a and 132 b can be protected by the
於圖7中,當閘極電極140具有寬度LG且從閘極電極140凸出的光阻圖案40具有寬度Loh時,可在滿足以下之方程式2之條件下進行摻雜。In FIG. 7 , when the
[方程式2][Equation 2]
LG x Loh x 1/η2 ≥ 1LG x Loh x 1/η2 ≥ 1
其中η2 = 0.5平方微米where η2 = 0.5 square microns
各個第一偏差部132a及第二偏差部132b可具有對應於凸出的寬度Loh之寬度。當閘極電極140的寬度LG以及從閘極電極140凸出的光阻圖案40之寬度Loh滿足方程式2時,可形成滿足方程式2的偏差部132a、132b。Each of the
根據本發明另一實施例,在方程式2中,η2 = 1.5平方微米。或者,η2可滿足以下關係式:0.5平方微米≤ η2 ≤ 1.5平方微米。According to another embodiment of the present invention, in
圖8為呈現根據本發明一實施例的主動層之區域取向摻雜物分佈情形之圖式。FIG. 8 is a diagram showing the distribution of area-oriented dopants of the active layer according to an embodiment of the present invention.
於圖8中,原點表示摻雜物。請參閱圖8,摻雜物的濃度可在多個導體提供部133a、133b中為最高的。多個偏差部132a、132b的摻雜濃度可低於各個導體提供部133a、133b的摻雜濃度。少量的摻雜物可能擴散至沒有直接摻雜有摻雜物的通道部131。通道部131可幾乎沒有包含摻雜物或可具有濃度非常低的摻雜物。In Figure 8, the origin represents the dopant. Referring to FIG. 8, the concentration of the dopant may be the highest among the plurality of
圖9為呈現根據本發明一實施例之主動層的區域取向摻雜物之濃度的圖式。9 is a graph presenting the concentration of the area orientation dopant of the active layer according to one embodiment of the present invention.
請參閱圖9,多個偏差部(如第一及第二偏差部)132a、132b之摻雜物的濃度梯度可在從通道部131到多個導體提供部(如第一及第二導體提供部)133a、133b之方向中增加。舉例來說,第一偏差部132a的摻雜物之濃度梯度可在從通道部131到第一導體提供部133a的方向中增加,且第二偏差部132b的摻雜物之濃度梯度可在從通道部131到第二導體提供部133b之方向中增加。Referring to FIG. 9 , the concentration gradients of the dopants of the plurality of deviation parts (eg, the first and second deviation parts) 132 a and 132 b may vary from the
圖10為呈現根據本發明一實施例之主動層130的區域取向電阻率之程度的圖式。FIG. 10 is a graph presenting the extent of the area-oriented resistivity of the
請參閱圖10,各個偏差部132a、132b的電阻率可低於通道部131的電阻率並可高於各個導體提供部133a、133b的電阻率。偏差部132a、132b的摻雜物的濃度梯度可在從通道部131到導體提供部133a、133b的方向中增加。Referring to FIG. 10 , the resistivity of each
因此,偏差部132a、132b可在沒有提供傳導性的通道部131以及導體提供部133a、133b之間執行電性緩衝的功能。Therefore, the
舉例來說,因為偏差部132a、132b設置於通道部131及導體提供部133a、133b之間,所以可防止漏電流在薄膜電晶體100處於關閉狀態時流動於通道部131及導體提供部133a、133b之間。如上所述,偏差部132a、132b可防止漏電流在薄膜電晶體100處於關閉狀態時出現在薄膜電晶體100中。For example, since the
圖11為根據本發明一實施例呈現在薄膜電晶體100的開啟狀態中之半導體層的區域取向導電度分佈情形之圖式。FIG. 11 is a graph showing the distribution of the area-oriented conductivity of the semiconductor layer in the on-state of the
當薄膜電晶體100根據施加到閘極電極140的閘極電壓而開啟時,各個偏差部132a、132b的導電度可能不會大幅地增加,其中偏差部132a、132b不會被產生在閘極電極140中的電場大幅度地影響。因此,當薄膜電晶體100開啟時,各個偏差部132a、132b的導電度可低於通道部131的導電度及各個導體提供部133a、133b的導電度。因此,偏差部132a、132b可防止薄膜電晶體100的臨界電壓發生偏移。因此,可提升薄膜電晶體100的電性穩定度。When the
圖12為根據本發明一實施例呈現在重疊於導體提供部的區域中基於深度的元素之濃度(原子濃度)的圖式。基於深度的元素之濃度已經由飛行時間二次離子質譜分析法(time of flight secondary ion mass spectrometry,TOF-SIMS)確認過。FIG. 12 is a graph representing the concentration (atomic concentration) of elements based on depth in a region overlapping a conductor providing portion according to an embodiment of the present invention. Depth-based element concentrations have been confirmed by time of flight secondary ion mass spectrometry (TOF-SIMS).
圖12呈現閘極絕緣層150、第一導體提供部133a及緩衝層120中的氧(O)、矽(Si)、銦(In)及硼(B)之濃度。氧(O)可用來形成閘極絕緣層150、主動層130及緩衝層120。矽(Si)可用來形成閘極絕緣層150及緩衝層120。銦(In)可用來形成主動層130。硼(B)可為透過摻雜添加作為摻雜物之元素。FIG. 12 shows the concentrations of oxygen (O), silicon (Si), indium (In) and boron (B) in the
請參閱圖12,可以看到作為摻雜物的硼(B)在第一導體提供部133a中具有最大的濃度。Referring to FIG. 12, it can be seen that boron (B) as a dopant has the largest concentration in the first
圖13為根據本發明一實施例呈現重疊於導體提供部的區域中基於深度的元素的濃度(原子濃度)之圖式。13 is a graph showing the concentration (atomic concentration) of elements based on depth in a region overlapping a conductor providing portion according to an embodiment of the present invention.
請參閱圖13,可以看到作為摻雜物的硼(B)在緩衝層120中具有最大的濃度。Referring to FIG. 13 , it can be seen that boron (B) as a dopant has the largest concentration in the
請參閱圖13,在重疊於這些導體提供部133a、133b的區域中,各個導體提供部133a、133b的摻雜濃度可高於閘極絕緣層150的摻雜濃度以及緩衝層120的摻雜濃度。並且,請參閱圖13,在重疊於導體提供部133a、133b的區域中,緩衝層120的摻雜濃度可高於閘極絕緣層150的摻雜濃度以及各個導體提供部133a、133b的摻雜濃度。Referring to FIG. 13 , in the regions overlapping the
可藉由在摻雜製程中調整施加到摻雜物的加速電壓來調整閘極絕緣層150的摻雜濃度、各個導體提供部133a、133b的摻雜濃度以及緩衝層120的摻雜濃度。The doping concentration of the
當增加施加到摻雜物的加速電壓以將摻雜物充分地摻雜於導體提供部133a、133b時,摻雜物可摻雜於導體提供部133a、133b以及緩衝層120。當用於摻雜的加速電壓增加到非預期的位準時,主動層130可能受到損壞。因此,根據本發明一實施例,可調整加速電壓而使得導體提供部133a、133b中的摻雜濃度為最大值或使緩衝層120的頂部中的摻雜濃度為最大值。When the accelerating voltage applied to the dopant is increased to sufficiently dope the
根據本發明一實施例,當導體提供部133a、133b中的摻雜濃度為最大值或是緩衝層120中的摻雜濃度為最大值時,可有效地於導體提供部133a、133b進行摻雜。並且,當導體提供部133a、133b中的摻雜濃度為最大值或緩衝層120中的摻雜濃度為最大值時,可視為薄膜電晶體100以有效的方式運作。According to an embodiment of the present invention, when the doping concentration in the
圖14A及圖14B為根據比較示例的導體提供方法之圖式。14A and 14B are diagrams of a conductor providing method according to a comparative example.
請參閱圖14A,可形成閘極電極140,且接著可藉由使用閘極電極140作為遮罩提供傳導性。舉例來說,傳導性可透過乾蝕刻(dry etching)提供。根據比較示例,閘極絕緣層150可於形成閘極電極140的過程中被圖案化,且可移除設置在主動層130上待提供有傳導性的區域上之閘極絕緣層。因此,應用於乾蝕刻製程的蝕刻氣體可直接接觸主動層130的表面,且因此可將傳導性提供至主動層130中所選擇的部分。於圖14A及圖14B中,係繪示以乾蝕刻作為導體提供方法的示例,但傳導性可透過基於離子植入的摻雜方式提供。Referring to Figure 14A,
請參閱圖14B,在光阻圖案45殘留於閘極電極140上的狀態中,可藉由使用光阻圖案45作為遮罩來提供傳導性。然,請參閱圖14B,光阻圖案45與閘極電極140可具有相同的平面,且光阻圖案45可不凸出到閘極電極140的區域之外側。於圖14B中,光阻圖案45凸出到閘極電極140的外側之凸出的寬度Loh可為0。Referring to FIG. 14B, in a state where the
根據圖14A或圖14B中繪示的方法,在藉由提供傳導性給主動層130中所選擇的部分來形成這些導體提供部133a、133b的製程中,傳導性可部分地被提供至通道部131。舉例來說,傳導性可被提供到相鄰於導體提供部133a、133b的通道部131之區域。然,當應用根據比較示例的導體提供方法時,可能會難以決定傳導性需藉由多少寬度被提供至通道部131的邊緣。According to the method shown in FIG. 14A or FIG. 14B, in the process of forming these
在導體提供製程中,通道部131的導體提供寬度或距離可稱為導體提供穿設深度(conductivity-providing penetration depth)∆L。In the conductor provision process, the conductor provision width or distance of the
圖15為根據比較示例描述導體提供穿設深度∆L之示意圖。FIG. 15 is a schematic diagram illustrating a conductor providing penetration depth ΔL according to a comparative example.
請參閱圖15,通道部131在主動層130中可具有重疊於閘極電極140的寬度Lideal
。圖15中的寬度Lideal
可為通道部131的理想寬度。Referring to FIG. 15 , the
在提供傳導性給主動層130中所選擇的部分之製程中,傳導性可被提供給部分的通道部131,且導體提供區域可能無法作為通道。通道部131的導體提供部的寬度可由導體提供穿設深度∆L表示。並且,通道部131中沒有提供傳導性且有效地作為通道的區域可具有有效通道寬度Leff
。當導體提供穿設深度∆L增加時,有效通道寬度Leff
可能會減少。In the process of providing conductivity to selected portions of the
為了讓薄膜電晶體執行開關功能,有效通道寬度Leff
應維持於特定或更高的量值。然,當沒有決定出通道部131的邊緣之導體提供程度時,可能會難以設計通道部131的寬度。為了確保有效通道寬度Leff
,當沒有決定出通道部131的邊緣之導體提供程度時,通道部131的寬度應設計為寬的。在此情況中,薄膜電晶體的尺寸可能會增加且可能會難以微型化及高度整合裝置。In order for the thin film transistor to perform the switching function, the effective channel width Leff should be maintained at a certain or higher magnitude. Of course, it may be difficult to design the width of the
根據本發明一實施例,偏差部132a、132b可設置於通道部131及導體提供部133a、133b之間且可在通道部131及導體提供部133a、133b之間執行緩衝的功能,因此大部分的通道部131可有效地作為通道。如上所述,根據本發明一實施例,可有效地確保有效通道寬度Leff
,因此可輕易決定並設計通道部131的寬度。According to an embodiment of the present invention, the
根據本發明一實施例,對於有效通道寬度Leff
來說,各個偏差部132a、132b的寬度L2可根據通道部131的寬度L1改變,且舉例來說,可根據方程式1決定各個偏差部132a、132b的寬度L2。According to an embodiment of the present invention, for the effective channel width Leff , the width L2 of each
圖16為根據比較示例及本發明的實施例之薄膜電晶體的總導體提供穿設深度2∆L之圖表。16 is a graph of the total conductors of thin film transistors according to comparative examples and embodiments of the present invention providing a penetration depth 2ΔL.
相對於剖面示意圖來說,在通道部131的兩側皆有導體提供穿設深度∆L,因此總導體提供穿設深度2∆L係計算為「2 x ΔL」。Compared with the cross-sectional schematic diagram, there are conductors on both sides of the
於圖16中,比較示例1(Comp. 1)係關於藉由使用圖14A中繪示的方法來將傳導性提供到部分的主動層130之薄膜電晶體。In FIG. 16, Comparative Example 1 (Comp. 1) relates to a thin film transistor that provides conductivity to a portion of the
於圖16中,實施例1(EX. 1)係關於藉由使用圖7中繪示的方法透過摻雜硼(B)離子而製造的薄膜電晶體,實施例2(EX. 2)係關於藉由使用圖7中繪示的方法透過摻雜磷(P)離子而製造的薄膜電晶體,且實施例3(EX. 3)係關於藉由使用圖7中繪示的方法透過摻雜氟(F)離子而製造的薄膜電晶體。In FIG. 16, Example 1 (EX. 1) relates to a thin film transistor fabricated by doping boron (B) ions using the method shown in FIG. 7, and Example 2 (EX. 2) relates to Thin film transistors fabricated by doping phosphorus (P) ions using the method depicted in FIG. 7, and Example 3 (EX.3) pertaining to doping fluorine by using the method depicted in FIG. 7 (F) Thin film transistor produced by ion.
在根據比較示例1(Comp. 1)的薄膜電晶體中,總導體提供穿設深度2∆L約為1.0微米,且通道部131中對應於1.0微米的部分沒有作為通道。因此,通道部131區域的損失為嚴重的。In the thin film transistor according to Comparative Example 1 (Comp. 1), the total conductor provision penetration depth 2ΔL was about 1.0 μm, and the portion corresponding to 1.0 μm in the
另一方面,根據實施例1、實施例2及實施例3,總導體提供穿設深度2∆L小於約0.6微米,且通道部131區域的損失小於1。於實施例1、實施例2及實施例3中,通道部131區域的損失因這些偏差部132a、132b而降低。On the other hand, according to Example 1, Example 2 and Example 3, the total conductor provided penetration depth 2ΔL is less than about 0.6 μm, and the loss in the area of the
圖17A至圖17E為根據比較示例及本發明的實施例之薄膜電晶體的臨界電壓圖表。17A-17E are graphs of threshold voltages of thin film transistors according to comparative examples and embodiments of the present invention.
圖17A呈現根據比較示例1的薄膜電晶體的臨界電壓,圖17B呈現根據比較示例2的薄膜電晶體的臨界電壓,圖17C呈現根據實施例1的薄膜電晶體的臨界電壓,圖17D呈現根據實施例2的薄膜電晶體的臨界電壓,且圖17E呈現根據實施例3的薄膜電晶體的臨界電壓。圖式中的Ids 代表薄膜電晶體的汲極源極間電流,且圖式中的Vgs 代表薄膜電晶體的閘極-源極電壓。17A presents the threshold voltage of the thin film transistor according to Comparative Example 1, FIG. 17B presents the threshold voltage of the thin film transistor according to Comparative Example 2, FIG. 17C presents the threshold voltage of the thin film transistor according to Example 1, and FIG. 17D presents the threshold voltage according to the implementation The threshold voltage of the thin film transistor of Example 2, and FIG. 17E presents the threshold voltage of the thin film transistor according to Example 3. I ds in the figure represents the drain-source current of the thin film transistor, and V gs in the figure represents the gate-source voltage of the thin film transistor.
比較示例2係關於具有如圖1所示的閘極絕緣層150之結構但因沒有摻雜離子而不包含偏差部132a、132b的薄膜電晶體。Comparative Example 2 relates to a thin film transistor having the structure of the
在比較示例1、比較示例2及實施例1至3的薄膜電晶體中,主動層使用氧化銦鎵鋅(IGZO)作為氧化物半導體。In the thin film transistors of Comparative Example 1, Comparative Example 2, and Examples 1 to 3, indium gallium zinc oxide (IGZO) was used as the oxide semiconductor for the active layer.
對於比較示例1、比較示例2及實施例1至3的薄膜電晶體來說,已量測初始臨界電壓、移動率、偏差區域的電阻、正偏溫壓(positive bias temperature stress,PBTS)及負偏溫壓(negative bias temperature stress,NBTS)。量測結果呈現於圖17A至圖17E以及表1中。For the thin film transistors of Comparative Example 1, Comparative Example 2, and Examples 1 to 3, the initial threshold voltage, mobility, resistance of the bias region, positive bias temperature stress (PBTS) and negative Negative bias temperature stress (NBTS). The measurement results are presented in FIGS. 17A-17E and in Table 1 .
[表1]
請參閱表1及圖17C、圖17D與圖17E,根據實施例1至3的各個薄膜電晶體的臨界電壓特性相似於比較示例1中根據習知技術的方法製造的薄膜電晶體(圖17A)的臨界電壓特性。另一方面,可確認到根據比較示例2的薄膜電晶體之臨界電壓特性非常弱。Referring to Table 1 and FIGS. 17C , 17D and 17E, the threshold voltage characteristics of the respective thin film transistors according to Examples 1 to 3 are similar to those of the thin film transistor manufactured according to the conventional method in Comparative Example 1 ( FIG. 17A ) critical voltage characteristics. On the other hand, it was confirmed that the threshold voltage characteristic of the thin film transistor according to Comparative Example 2 was very weak.
此外,請參閱表1,可確認到根據實施例1至3的各個薄膜電晶體的移動率相似於比較示例1的薄膜電晶體的移動率。Further, referring to Table 1, it was confirmed that the mobility of each of the thin film transistors according to Examples 1 to 3 was similar to that of the thin film transistor of Comparative Example 1.
於表1中,導體提供電阻代表各個導體提供部133a、133b的電阻值。於比較示例2中,無法量測導體提供電阻。In Table 1, the conductor supply resistance represents the resistance value of each
於表1中,正偏溫壓代表施加到薄膜電晶體的壓力,此壓力係在特定溫度施加正(+)偏壓的情況下所施加,且正偏溫壓通常具有正(+)值。當正偏溫壓增加時,各個主動層130及薄膜電晶體的壓力可增加,進而可增加臨界電壓變化∆Vth。In Table 1, the positive bias temperature voltage represents the pressure applied to the thin film transistor, which is applied with a positive (+) bias voltage applied at a specific temperature, and the positive bias temperature voltage usually has a positive (+) value. When the forward bias temperature and voltage increase, the pressure of each
負偏溫壓代表施加到薄膜電晶體的壓力,此壓力係在特定溫度施加負(-)偏壓的情況下所施加,且負偏溫壓通常具有負(-)值。當負偏溫壓的絕對值增加時,各個主動層130及薄膜電晶體相對溫度的壓力可增加,進而可增加臨界電壓變化∆Vth並可能會降低可靠度。The negative temperature bias represents the pressure applied to the thin film transistor, which pressure is applied with a negative (-) bias applied at a specific temperature, and the negative temperature bias usually has a negative (-) value. When the absolute value of the negative bias temperature increases, the pressure of each
請參閱表1,可以確認到在60℃的溫度持續一小時施加30伏特(V)的電壓之情況下,根據實施例1至3的各個薄膜電晶體的正偏溫壓大於比較示例1的薄膜電晶體的正偏溫壓,且在60℃的溫度持續一小時施加-30 V的電壓之情況下,根據實施例1至3的各個薄膜電晶體的負溫偏壓之絕對值小於比較示例1的薄膜電晶體的負溫偏壓之絕對值。Referring to Table 1, it can be confirmed that in the case where a voltage of 30 volts (V) is applied at a temperature of 60° C. for one hour, the forward bias temperature voltage of each of the thin film transistors according to Examples 1 to 3 is larger than that of the thin film of Comparative Example 1 The positive bias temperature and voltage of the transistor, and in the case where a voltage of -30 V is applied at a temperature of 60° C. for one hour, the absolute value of the negative temperature bias voltage of each thin film transistor according to Examples 1 to 3 is smaller than that of Comparative Example 1 The absolute value of the negative temperature bias of the thin film transistor.
圖18為根據比較示例及本發明的實施例之薄膜電晶體的臨界電壓相對熱處理時間之圖表。18 is a graph of threshold voltage versus heat treatment time for thin film transistors according to comparative examples and embodiments of the present invention.
圖18呈現薄膜電晶體的臨界電壓相對熱處理時間的變化,且熱處理是在230℃的溫度執行於比較示例1(Comp. 1)、實施例1(EX. 1)、實施例2(EX. 2)及實施例3(EX. 3)的薄膜電晶體。18 presents the variation of the threshold voltage of the thin film transistor with respect to the heat treatment time, and the heat treatment was performed at a temperature of 230° C. in Comparative Example 1 (Comp. 1), Example 1 (EX. 1), and Example 2 (EX. 2 ) and the thin film transistors of Example 3 (EX. 3).
在對薄膜電晶體長時間持續進行熱處理的情況中,主動層130的電性特性可根據設置在主動層130附近的絕緣層及/或相似的結構之影響而改變。於此情況中,薄膜電晶體的可靠度可能會降低。In the case of continuous heat treatment of the thin film transistor for a long time, the electrical characteristics of the
舉例來說,在對薄膜電晶體長時間持續進行熱處理的情況中,導體提供部133a、133b的傳導性可能會損失(導體提供的情況可能會回復成非導體的情況)。於此情況中,薄膜電晶體的效能可能會降低並可為不均勻的,而造成可靠度降低。For example, in the case where the thin film transistor is continuously heat-treated for a long time, the conductivity of the conductor-providing
然而,請參閱圖18,可以確認到儘管對本發明的實施例1至3的薄膜電晶體進行熱處理,臨界電壓仍沒有大幅度地改變。However, referring to FIG. 18 , it can be confirmed that the threshold voltage is not largely changed despite the heat treatment of the thin film transistors of Examples 1 to 3 of the present invention.
圖19為根據比較示例及本發明的實施例之薄膜電晶體的移動率相對熱處理時間的圖表。19 is a graph of mobility versus heat treatment time for thin film transistors according to comparative examples and embodiments of the present invention.
圖19呈現薄膜電晶體的移動率相對熱處理時間的變化,且熱處理是在230℃的溫度執行於比較示例1(Comp. 1)、實施例1(EX. 1)、實施例2(EX. 2)及實施例3(EX. 3)的薄膜電晶體。19 presents the change of the mobility of the thin film transistor with respect to the heat treatment time, and the heat treatment was performed at a temperature of 230° C. in Comparative Example 1 (Comp. 1), Example 1 (EX. 1), and Example 2 (EX. 2 ) and the thin film transistors of Example 3 (EX. 3).
請參閱圖19,可以確認到儘管對本發明的實施例1至3的薄膜電晶體進行熱處理,移動率仍沒有大幅度地降低。Referring to FIG. 19, it can be confirmed that despite the heat treatment of the thin film transistors of Examples 1 to 3 of the present invention, the mobility is not greatly reduced.
請參閱圖18及圖19,可確認到儘管對本發明的實施例1至3的薄膜電晶體進行熱處理,效能仍沒有大幅度地降低。Referring to FIG. 18 and FIG. 19 , it can be confirmed that the performance of the thin film transistors of Examples 1 to 3 of the present invention is not greatly reduced despite the heat treatment.
圖20為根據比較示例及本發明的實施例之薄膜電晶體的電阻率量測圖表。FIG. 20 is a resistivity measurement chart of thin film transistors according to comparative examples and embodiments of the present invention.
於圖20中,EX. 1、EX. 2及EX. 3分別對應到的量值分別代表本發明的實施例1的薄膜電晶體的導體提供部133a、133b之電阻率、本發明實施例2的薄膜電晶體的導體提供部133a、133b之電阻率,以及本發明實施例3的薄膜電晶體的導體提供部133a、133b之電阻率。於圖20中,Comp. 2對應到的量值代表根據比較示例2的薄膜電晶體中對應到本發明的實施例1之薄膜電晶體的各個導體提供部133a、133b的區域之電阻率。In FIG. 20 , the magnitudes corresponding to EX.1, EX.2 and EX.3 respectively represent the resistivity of the
如圖20所示,本發明之實施例1(EX. 1)、實施例2(EX. 2)及實施例3(EX. 3)的薄膜電晶體的電阻率低於比較示例2(Comp. 2)的薄膜電晶體之電阻率。根據本發明實施例1至3的薄膜電晶體例如可具有約10-2
至10-3
歐姆·公分(Ω·cm)的電阻率。As shown in FIG. 20, the resistivity of the thin film transistors of Example 1 (EX.1), Example 2 (EX.2) and Example 3 (EX.3) of the present invention is lower than that of Comparative Example 2 (Comp. 2) The resistivity of thin film transistors. The thin film transistors according to
圖21為根據比較示例及本發明的實施例之移動率相對主動層中植入的離子量之圖表。21 is a graph of mobility versus the amount of ions implanted in the active layer according to comparative examples and embodiments of the present invention.
於圖21中,比較示例1(Comp. 1)代表相對比較示例1的薄膜電晶體的移動率,且在比較示例1中傳導性透過乾蝕刻而不透過離子植入的方式提供到部分的主動層130。In FIG. 21, the comparative example 1 (Comp. 1) represents the mobility of the thin film transistor relative to the comparative example 1, and in the comparative example 1 conductivity is provided to the part of the active through dry etching but not through
於圖21中,比較示例3(Comp. 3)係關於與實施例1(EX. 1)具有相同構造的薄膜電晶體,且於此薄膜電晶體中作為摻雜物的硼(B)離子的濃度在閘極絕緣層150中具有最大值。於圖21中,實施例4(EX. 4)係關於與實施例1(EX. 1)具有相同結構的薄膜電晶體,且於此薄膜電晶體中作為摻雜物的硼(B)離子之濃度在緩衝層120中具有最大值。於圖21中,在比較示例3(Comp. 3)、實施例1(EX. 1)及實施例4(EX. 4)已用相同的濃度執行低濃度摻雜、中濃度摻雜及高濃度摻雜。圖21中沒有討論實施例1(EX. 1)的中濃度摻雜結果。In FIG. 21, Comparative Example 3 (Comp. 3) is related to a thin film transistor having the same configuration as that of Example 1 (EX. 1), and boron (B) ion as a dopant in this thin film transistor. The concentration has a maximum value in the
請參閱圖21,根據實施例1(EX. 1)及實施例4(EX. 4),可以確認到當植入的離子量從低濃度變成高濃度時,移動率差異不大。並且,可以確認到即使植入的離子量為低濃度,實施例1(EX. 1)及實施例4(EX. 4)的薄膜電晶體的移動率仍相似於根據比較示例(Comp. 1)的薄膜電晶體的移動率。Referring to FIG. 21 , according to Example 1 (EX.1) and Example 4 (EX.4), it can be confirmed that when the amount of implanted ions changes from a low concentration to a high concentration, there is little difference in the mobility. Also, it was confirmed that the mobility of the thin film transistors of Example 1 (EX. 1) and Example 4 (EX. 4) was similar to that according to the comparative example (Comp. 1) even if the amount of implanted ions was a low concentration the mobility of thin-film transistors.
另一方面,根據比較示例3(Comp. 3),可以確認到當植入的離子量從低濃度增加至高濃度時,移動率會增加。並且,可以確認到即使在植入的離子量為高濃度時,比較示例3(Comp. 3)的薄膜電晶體的移動率仍低於比較示例(Comp. 1)或實施例1(EX. 1)及實施例4(EX. 4)的薄膜電晶體的移動率。On the other hand, according to Comparative Example 3 (Comp. 3), it can be confirmed that the mobility increases when the amount of implanted ions increases from a low concentration to a high concentration. Furthermore, it was confirmed that the mobility of the thin film transistor of Comparative Example 3 (Comp. 3) was lower than that of Comparative Example (Comp. 1) or Example 1 (EX. 1) even when the amount of implanted ions was high ) and the mobility of the thin film transistors of Example 4 (EX. 4).
當植入的離子量增加到使得比較示例3(Comp. 3)的薄膜電晶體的移動率等於實施例1(EX. 1)及實施例4(EX. 4)之各個薄膜電晶體的移動率時,主動層130可能會受損。When the amount of implanted ions was increased so that the mobility of the thin film transistor of Comparative Example 3 (Comp. 3) was equal to the mobility of each of the thin film transistors of Example 1 (EX. 1) and Example 4 (EX. 4) , the
另一方面,即使在植入的離子量為低濃度時,根據本發明的實施例1(EX. 1)及實施例4(EX. 4)之薄膜電晶體仍可具有良好的移動率,且可在防止主動層130受到損害的範圍內執行根據離子植入的摻雜。On the other hand, the thin film transistors according to Example 1 (EX.1) and Example 4 (EX.4) of the present invention can have good mobility even when the amount of implanted ions is low, and Doping according to ion implantation may be performed within a range preventing the
圖22A至圖22C為根據比較示例及本發明的實施例之薄膜電晶體的臨界電壓相對通道部131的寬度之圖表。22A to 22C are graphs of threshold voltage versus width of the
圖22A為根據比較示例4的薄膜電晶體中的臨界電壓圖表,其中此臨界電壓圖表呈現通道部131的寬度為3微米至20微米(3微米、3.5微米、4微米、6微米、10微米、12微米及20微米)的情況,且在比較示例4中藉由使用閘極電極140作為遮罩且沒有使用光阻圖案40(凸出的寬度Loh為0微米)來進行離子摻雜。22A is a graph of the threshold voltage in the thin film transistor according to Comparative Example 4, wherein the graph of the threshold voltage presents that the width of the
圖22B為根據實施例1的薄膜電晶體中的臨界電壓圖表,其中此臨界電壓圖表呈現通道部131的寬度為3微米至20微米(3微米、3.5微米、4微米、6微米、10微米、12微米及20微米)的情況,且於實施例1中藉由使用光阻圖案40作為遮罩並使用凸出的寬度Loh(請參閱圖7)來進行離子摻雜。光阻圖案40以寬度Loh凸出至閘極電極140的外側,且寬度Loh為0.5微米。22B is a graph of the threshold voltage in the thin film transistor according to
圖22C為根據實施例5的薄膜電晶體中的臨界電壓圖表,其中此臨界電壓圖表呈現通道部131的寬度為3微米至20微米(3微米、3.5微米、4微米、6微米、10微米、12微米及20微米)的情況,且在實施例5中藉由使用光阻圖案40作為遮罩並使用凸出的寬度Loh(請參閱圖7)來進行離子摻雜。光阻圖案40以寬度Loh凸出至閘極電極140的外側,且寬度Loh為0.7微米。22C is a graph of the threshold voltage in the thin film transistor according to
圖23為呈現根據比較示例及本發明的實施例之薄膜電晶體的臨界電壓值相對通道部131的寬度(或長度)之圖表。FIG. 23 is a graph presenting threshold voltage values versus the width (or length) of the
請參閱圖22A及圖23,在根據比較示例4的薄膜電晶體中,可以確認到臨界電壓隨著通道部131的寬度改變。具體地,請參閱圖23,在根據比較示例4的薄膜電晶體中,可以確認到臨界電壓值在通道部131的寬度為4微米或更小時大幅地改變,且臨界電壓值在通道部131的寬度為6微米或更大時保持恆定。Referring to FIGS. 22A and 23 , in the thin film transistor according to Comparative Example 4, it can be confirmed that the threshold voltage varies with the width of the
此外,請參閱圖22B、圖22C及圖23,在根據本發明的實施例1及實施例5的薄膜電晶體中,可以確認到當通道部131的寬度改變時,汲極源極間電流Ids
會改變但臨界電壓幾乎沒有改變。並且,可以確認到即使在通道部131的寬度為3微米且非常狹窄時,根據本發明的實施例1及實施例5的薄膜電晶體仍具有優異的臨界電壓特性。In addition, referring to FIGS. 22B , 22C and 23 , in the thin film transistors according to
圖24為根據比較示例及本發明的實施例之臨界電壓相對閘極電極140的寬度(或長度)之圖表。24 is a graph of threshold voltage versus width (or length) of
根據本發明一實施例,閘極電極140的寬度對應於通道部131的寬度。According to an embodiment of the present invention, the width of the
請參閱圖24,在根據比較示例(Comp. 1)的薄膜電晶體中,可以確認到臨界電壓隨著閘極電極140的寬度改變。具體地,請參閱圖23,在根據比較示例1的薄膜電晶體中,可以確認到臨界電壓值在閘極電極140的寬度為5微米或更小時非常大幅地改變。Referring to FIG. 24, in the thin film transistor according to the comparative example (Comp. 1), it can be confirmed that the threshold voltage varies with the width of the
此外,請參閱圖24,在根據本發明的實施例1、實施例2及實施例3的薄膜電晶體中,可以確認到在閘極電極140的寬度改變時臨界電壓的變化並不大。In addition, referring to FIG. 24 , in the thin film transistors according to
圖25為呈現根據本發明的實施例之閘極電極附近產生的縫隙及金屬殘留層之圖式。圖26為呈現根據本發明的實施例之閘極電極附近沒有產生縫隙或金屬殘留層之態樣的圖式。FIG. 25 is a diagram showing a gap and a metal residual layer created near a gate electrode according to an embodiment of the present invention. FIG. 26 is a diagram showing a state in which no gap or metal residual layer is generated near the gate electrode according to an embodiment of the present invention.
圖25繪示閘極絕緣層150與閘極電極140一起被蝕刻的情況。FIG. 25 shows a case where the
如圖25中所示,在閘極絕緣層150與閘極電極140一起被蝕刻的情況中,可使閘極電極140及主動層130之間的階層高度(step height)增加。當閘極電極140及主動層130之間的階層高度增加時,可能會如圖25所示在設置於閘極電極140上的中間絕緣層155中產生如縫隙的缺陷,並因此會劣化閘極電極140及另一個電極或線路之間的絕緣特性,進而造成短路。As shown in FIG. 25, in the case where the
此外,如圖25所示,在閘極絕緣層150與閘極電極140一起被蝕刻的情況中,在執行於閘極電極140上的蝕刻製程中產生的金屬殘留材料MR1可能殘留於閘極絕緣層150的邊緣,進而劣化閘極電極140及主動層130之間的絕緣特性。In addition, as shown in FIG. 25, in the case where the
此外,如圖25中所示,在閘極電極140及主動層130之間的階層高度增加的情況中,可於中間絕緣層155中產生階層高度,且金屬殘留材料MR2(如用於形成源極電極或汲極電極的金屬殘留材料)可能殘留於階層高度上,進而使得薄膜電晶體的效能降低。Furthermore, as shown in FIG. 25, in the case where the step height between the
另一方面,如圖26中所示,在沒有圖案化閘極絕緣層150的情況中,可提升閘極電極140及主動層130之間的絕緣特性,且此外可降低閘極電極140及主動層130之間的階層高度。在閘極電極140及主動層130之間的階層高度降低的情況中,可降低在中間絕緣層155中產生如縫隙的缺陷之機率。如圖26所示,當中間絕緣層155的階層高度降低時,可降低金屬殘留材料MR2殘留於階梯部上的機率。On the other hand, as shown in FIG. 26, in the case where the
請參閱圖26,因為閘極絕緣層150沒有被蝕刻,所以不會有在閘極電極140上執行的蝕刻製程中所產生的金屬殘留材料MR1殘留在閘極絕緣層150的邊緣之可能。Referring to FIG. 26 , since the
圖27A至圖27G為根據本發明的實施例之薄膜電晶體的製造方法之製程示意圖。27A to 27G are schematic process diagrams of a method for manufacturing a thin film transistor according to an embodiment of the present invention.
請參閱圖27A,緩衝層120可形成於基板110上,且主動層130可形成於緩衝層120上。主動層130可包含氧化物半導體材料。詳細來說,主動層130可為氧化物半導體層。Referring to FIG. 27A , the
請參閱圖27B,閘極絕緣層150可形成於主動層130上,且一閘極電極材料層145可形成於閘極絕緣層150上。閘極電極材料層145可包含金屬。Referring to FIG. 27B , a
請參閱圖27C,光阻圖案40可形成於閘極電極材料層145上。Referring to FIG. 27C , a
可藉由在閘極電極材料層145的整個頂面上塗佈、曝光及產生光阻物而形成光阻圖案40。The
請參閱圖27D,可藉由使用光阻圖案40作為遮罩來蝕刻閘極電極材料層145。因此,可形成閘極電極140。Referring to FIG. 27D, the gate
如圖27D所示,在平面視角中,光阻圖案40的面積可大於閘極電極140的面積。因為閘極電極材料層145的過度蝕刻的緣故,可形成面積小於光阻圖案40的閘極電極140。於平面視角中,閘極電極140可設置於由光阻圖案40所界定的區域中。閘極絕緣層150可覆蓋主動層130的整個頂面。As shown in FIG. 27D , in a plan view, the area of the
可根據方程式2決定光阻圖案40的寬度。The width of the
舉例來說,當閘極電極140具有寬度LG且光阻圖案40具有從閘極電極140凸出的寬度Loh時(請參閱圖7),光阻圖案40的寬度可被設計成滿足下列方程式2。For example, when the
[方程式2][Equation 2]
LG x Loh x 1/η2 ≥ 1LG x Loh x 1/η2 ≥ 1
其中η2 = 0.5平方微米where η2 = 0.5 square microns
如圖27B至圖27D所示,形成閘極電極140的製程可包含在閘極絕緣層150上形成閘極電極材料層145的製程(圖27B)、在閘極電極材料層145上形成光阻圖案40的製程(圖27C)以及藉由使用光阻圖案40作為遮罩而蝕刻閘極電極材料層145的製程(圖27D)。As shown in FIGS. 27B to 27D , the process of forming the
請參閱圖27E,摻雜物可摻雜於主動層130。Referring to FIG. 27E, the
摻雜物可包含硼(B)、磷(P)、氟(F)及氫(H)其中至少一者。The dopant may include at least one of boron (B), phosphorus (P), fluorine (F), and hydrogen (H).
在摻雜物摻雜製程中,光阻圖案40可作為遮罩。請參閱圖27E,可選擇性地對主動層130中沒有受光阻圖案40保護的區域進行摻雜。In the dopant doping process, the
請參閱圖27F,可藉由摻雜形成多個導體提供部133a、133b。Referring to FIG. 27F, a plurality of
根據本發明一實施例,緩衝層120可透過摻雜製程摻雜有摻雜物。According to an embodiment of the present invention, the
主動層130的摻雜濃度可高於閘極絕緣層150的摻雜濃度以及緩衝層120的摻雜濃度。於此,主動層130的摻雜濃度可表示各個導體提供部133a、133b的摻雜濃度。The doping concentration of the
此外,緩衝層120的摻雜濃度可高於主動層130的摻雜濃度以及閘極絕緣層150的摻雜濃度。In addition, the doping concentration of the
請參閱圖27G,可藉由移除光阻圖案40來形成薄膜電晶體100。Referring to FIG. 27G , the
請參閱圖27G,主動層130可包含通道部131、這些導體提供部133a、133b以及多個偏差部132a、132b。通道部131重疊於閘極電極140。導體提供部133a、133b不重疊於閘極電極140。偏差部132a、132b介於通道部131及導體提供部133a、133b之間。Referring to FIG. 27G , the
通道部131及偏差部132a、132b可各自為重疊於光阻圖案40的區域。The
圖28A至圖28G為根據本發明另一實施例之薄膜電晶體的製造方法的製程示意圖。28A to 28G are schematic process diagrams of a manufacturing method of a thin film transistor according to another embodiment of the present invention.
請參閱圖28A,緩衝層120可形成於基板110上,且主動層130可形成於緩衝層120上。主動層130可包含氧化物半導體材料。詳細來說,主動層130可為氧化物半導體層。Referring to FIG. 28A , the
請參閱圖28B,閘極絕緣層150可形成於主動層130上。並且,多個接觸孔CH1、CH2可形成於閘極絕緣層150中。Referring to FIG. 28B , the
請參閱圖28C,閘極電極材料層145可形成於閘極絕緣層150上,且多個光阻圖案40、41、42可形成於閘極電極材料層145上。Referring to FIG. 28C , a gate
閘極電極材料層145可被填充於接觸孔CH1、CH2中。The gate
請參閱圖28D,可藉由使用光阻圖案40、41、42作為遮罩來蝕刻閘極電極材料層145。因此,可形成閘極電極140、源極電極161及汲極電極162。請參閱圖28D,閘極電極140、源極電極161及汲極電極162可設置於相同的層體且可包含相同的材料。Referring to FIG. 28D, the gate
請參閱圖28E,可於主動層130摻雜摻雜物。Referring to FIG. 28E, the
摻雜物可包含硼(B)、磷(P)、氟(F)及氫(H)其中至少一者。可透過根據硼(B)、磷(P)、氟(F)及氫(H)其中至少一者的離子植入進行摻雜。The dopant may include at least one of boron (B), phosphorus (P), fluorine (F), and hydrogen (H). Doping may be performed by ion implantation according to at least one of boron (B), phosphorus (P), fluorine (F) and hydrogen (H).
在摻雜物摻雜製程中,光阻圖案40、41、42可作為遮罩。請參閱圖28E,可選擇性地摻雜主動層130中沒有受光阻圖案40、41、42保護的區域。In the dopant doping process, the
請參閱圖28F,可藉由摻雜形成多個導體提供部133a、133b。Referring to FIG. 28F, a plurality of
請參閱圖28G,可藉由移除光阻圖案40來形成薄膜電晶體。Referring to FIG. 28G , a thin film transistor can be formed by removing the
圖29為呈現根據本發明另一實施例的顯示設備700之圖式。FIG. 29 is a diagram showing a
如圖29所示,根據本發明另一實施例之顯示設備700可包含一顯示面板310、一閘極驅動器320、一資料驅動器330以及一控制器340。As shown in FIG. 29 , a
顯示面板310可包含多個閘極線路GL、多個資料線路DL以及一像素P,其中像素P被提供於由閘極線路GL及資料線路DL交會而界定的多個像素區域中的每一者。像素P可包含一發光裝置710及用來驅動發光裝置710的一像素驅動電路PDC(請參閱圖30)。顯示面板310可根據像素P的驅動來顯示影像。The
控制器340可控制閘極驅動器320及資料驅動器330。The
根據從外部系統(未繪示)供應的同步訊號及時脈訊號,控制器340可輸出用來控制閘極驅動器320的閘極控制訊號GCS以及用來控制資料驅動器330的資料控制訊號DCS。並且,控制器340可將從外部系統接收的輸入影片資料取樣,並且可重新調整(realign)經取樣的影片資料以提供數位的影像資料RGB給資料驅動器330。The
閘極控制訊號GCS可包含一閘極啟動脈衝(GSP)、一閘極偏移時脈(GSC)、一閘極輸出致能訊號(GOE)、一啟動訊號(Vst)以及一閘極時脈(GCLK)。並且,閘極控制訊號GCS可包含用來控制偏移記錄器350的控制訊號。The gate control signal GCS may include a gate start pulse (GSP), a gate offset clock (GSC), a gate output enable signal (GOE), a start signal (Vst) and a gate clock (GCLK). Also, the gate control signal GCS may include a control signal for controlling the offset
資料控制訊號DCS可包含一源極啟動脈衝(SSP)、一源極偏移時脈訊號(SSC)、一源極輸出致能訊號(SOE)及一極性控制訊號(POL)。The data control signal DCS may include a source start pulse (SSP), a source offset clock signal (SSC), a source output enable signal (SOE) and a polarity control signal (POL).
資料驅動器330可將資料電壓供應給顯示面板310的資料線路DL。詳細來說,資料驅動器330可將從控制器340輸入的影像資料RGB轉換成類比的資料電壓,並可在每一個水平周期將一個水平線路的資料電壓提供給資料線路DL,且在每一個水平周期中一閘極脈衝(GP)會被供應至一個閘極線路GL。The
閘極驅動器320可包含偏移記錄器350。
偏移記錄器350可根據啟動訊號(Vst)及閘極時脈(GCLK)而在一個幀的期間內依序提供閘極脈衝(GP)給閘極線路GL,其中啟動訊號(Vst)及閘極時脈(GCLK)係從控制器340傳來。於此,一個幀的期間可指顯示面板310顯示一張影像的期間。閘極脈衝(GP)可具有用來開啟設置在像素P中的開關元件(薄膜電晶體)的開啟電壓。The offset
此外,為了關閉開關元件,偏移記錄器350可在一個幀的另一個期間將閘極關閉訊號(Goff)供應給閘極線路GL,且在此另一個期間中沒有供應閘極脈衝(GP)。以下,閘極脈衝(GP)及閘極關閉訊號(Goff)的通用名稱可為SS或Scan。Furthermore, in order to turn off the switching element, the offset
根據本發明一實施例,閘極驅動器320可安裝於顯示面板310上。這種閘極驅動器320直接安裝於顯示面板310上的結構可稱為閘極中面板(gate-in panel,GIP)結構。閘極驅動器320可包含圖1至圖5中繪示的薄膜電晶體100至薄膜電晶體500其中至少一者。According to an embodiment of the present invention, the
圖30為圖29中的一個像素P的電路圖。FIG. 30 is a circuit diagram of one pixel P in FIG. 29 .
請參閱圖30,包含於根據本發明另一實施例之顯示設備700中的像素P可包含像素驅動電路PDC及發光裝置710。Referring to FIG. 30 , a pixel P included in a
發光裝置710可使用有機發光二極體(organic light emitting diode,OLED)。然,本發明的實施例並不以此為限,且發光裝置710可使用量子點發光裝置、無機發光裝置、微發光二極體等等。發光裝置710可利用從像素驅動電路PDC提供的資料電流來發光。The
請參閱圖30,像素驅動電路PDC可包含第一薄膜電晶體T1、第二薄膜電晶體T2、第三薄膜電晶體T3、第四薄膜電晶體T4、第五薄膜電晶體T5、第六薄膜電晶體T6、第七薄膜電晶體T7以及第一電容器C1。Referring to FIG. 30, the pixel driving circuit PDC may include a first thin film transistor T1, a second thin film transistor T2, a third thin film transistor T3, a fourth thin film transistor T4, a fifth thin film transistor T5, and a sixth thin film transistor The crystal T6, the seventh thin film transistor T7 and the first capacitor C1.
圖30中的各個薄膜電晶體(如第一薄膜電晶體T1、第三薄膜電晶體T3、第四薄膜電晶體T4、第五薄膜電晶體T5及第六薄膜電晶體T6)的主動層可包含矽半導體材料且可由矽半導體層所形成。各個第二薄膜電晶體T2及第七薄膜電晶體T7的主動層例如可包含氧化物半導體材料且可由氧化物半導體層形成。The active layer of each thin film transistor (eg, the first thin film transistor T1, the third thin film transistor T3, the fourth thin film transistor T4, the fifth thin film transistor T5, and the sixth thin film transistor T6) in FIG. 30 may include The silicon semiconductor material can be formed from a silicon semiconductor layer. The active layer of each of the second thin film transistor T2 and the seventh thin film transistor T7 may include, for example, an oxide semiconductor material and may be formed of an oxide semiconductor layer.
根據本發明另一實施例,圖30中的第一薄膜電晶體T1、第三薄膜電晶體T3、第四薄膜電晶體T4、第五薄膜電晶體T5及第六薄膜電晶體T6可與圖6中的第一薄膜電晶體TR1具有相同的構造,且第二薄膜電晶體T2及第七薄膜電晶體T7可與圖6中的第二薄膜電晶體TR2具有相同的構造。並且,第二薄膜電晶體T2及第七薄膜電晶體T7其中至少一者可與圖1至圖5中所示的薄膜電晶體100、200、300、400、500其中至少一者具有相同的結構。According to another embodiment of the present invention, the first thin film transistor T1, the third thin film transistor T3, the fourth thin film transistor T4, the fifth thin film transistor T5 and the sixth thin film transistor T6 in FIG. The first thin film transistor TR1 in FIG. 6 has the same structure, and the second thin film transistor T2 and the seventh thin film transistor T7 may have the same structure as the second thin film transistor TR2 in FIG. 6 . Furthermore, at least one of the second thin film transistor T2 and the seventh thin film transistor T7 may have the same structure as at least one of the
根據本發明另一實施例,第一薄膜電晶體T1、第三薄膜電晶體T3、第四薄膜電晶體T4、第五薄膜電晶體T5及第六薄膜電晶體T6可設置於第二薄膜電晶體T2及第七薄膜電晶體T7之下。詳細來說,各個第一薄膜電晶體T1、第三薄膜電晶體T3、第四薄膜電晶體T4、第五薄膜電晶體T5及第六薄膜電晶體T6的主動層可設置於各個第二薄膜電晶體T2及第七薄膜電晶體T7的主動層之下。According to another embodiment of the present invention, the first thin film transistor T1, the third thin film transistor T3, the fourth thin film transistor T4, the fifth thin film transistor T5 and the sixth thin film transistor T6 may be disposed on the second thin film transistor Below T2 and the seventh thin film transistor T7. In detail, the active layers of each of the first thin film transistor T1, the third thin film transistor T3, the fourth thin film transistor T4, the fifth thin film transistor T5 and the sixth thin film transistor T6 may be disposed on each of the second thin film transistors Below the active layer of the crystal T2 and the seventh thin film transistor T7.
請參閱圖30,第一薄膜電晶體T1可為驅動薄膜電晶體,且第二薄膜電晶體T2可為開關薄膜電晶體。Referring to FIG. 30 , the first thin film transistor T1 can be a driving thin film transistor, and the second thin film transistor T2 can be a switching thin film transistor.
第二薄膜電晶體T2的閘極電極G2可被提供有第二掃描訊號Scan2。第二薄膜電晶體T2的汲極電極D2可被提供有資料電壓Vdata。第二薄膜電晶體T2的源極電極S2可連接於第一薄膜電晶體T1的汲極電極D1。第二薄膜電晶體T2可藉由第二掃描訊號Scan2而被開啟且可將資料電壓Vdata提供給第一薄膜電晶體T1的汲極電極D1。The gate electrode G2 of the second thin film transistor T2 may be supplied with the second scan signal Scan2. The drain electrode D2 of the second thin film transistor T2 may be supplied with the data voltage Vdata. The source electrode S2 of the second thin film transistor T2 can be connected to the drain electrode D1 of the first thin film transistor T1. The second thin film transistor T2 can be turned on by the second scan signal Scan2 and can provide the data voltage Vdata to the drain electrode D1 of the first thin film transistor T1.
第三薄膜電晶體T3的閘極電極G3可被提供有發光控制訊號EM。第三薄膜電晶體T3的汲極電極D3可被提供有高位準的像素驅動電壓VDD。第三薄膜電晶體T3的源極電極S3可連接於第一薄膜電晶體T1的汲極電極D1。第三薄膜電晶體T3可藉由發光控制訊號EM而被開啟且可將高位準的像素驅動電壓VDD提供給第一薄膜電晶體T1的汲極電極D1。The gate electrode G3 of the third thin film transistor T3 may be supplied with the light emission control signal EM. The drain electrode D3 of the third thin film transistor T3 may be supplied with a high-level pixel driving voltage VDD. The source electrode S3 of the third thin film transistor T3 may be connected to the drain electrode D1 of the first thin film transistor T1. The third thin film transistor T3 can be turned on by the light emission control signal EM and can provide the high-level pixel driving voltage VDD to the drain electrode D1 of the first thin film transistor T1.
第七薄膜電晶體T7的閘極電極G7可被提供有第二掃描訊號Scan2。第七薄膜電晶體T7的汲極電極D7可連接於第一薄膜電晶體T1的閘極電極G1。第七薄膜電晶體T7的源極電極S7可連接於第一薄膜電晶體T1的源極電極S1。第七薄膜電晶體T7可藉由第二掃描訊號Scan2開啟並可控制第一薄膜電晶體T1的閘極電極G1及源極電極S1之間的電壓差藉以驅動第一薄膜電晶體T1。The gate electrode G7 of the seventh thin film transistor T7 may be supplied with the second scan signal Scan2. The drain electrode D7 of the seventh thin film transistor T7 may be connected to the gate electrode G1 of the first thin film transistor T1. The source electrode S7 of the seventh thin film transistor T7 may be connected to the source electrode S1 of the first thin film transistor T1. The seventh thin film transistor T7 can be turned on by the second scan signal Scan2 and can control the voltage difference between the gate electrode G1 and the source electrode S1 of the first thin film transistor T1 to drive the first thin film transistor T1.
第五薄膜電晶體T5的閘極電極G5可被提供有第一掃描訊號Scan1。第五薄膜電晶體T5的汲極電極D5可被提供有初始化電壓Vini。第五薄膜電晶體T5的源極電極S5可連接於第一薄膜電晶體T1的閘極電極G1。第五薄膜電晶體T5可藉由第一掃描訊號Scan1開啟並可將初始化電壓Vini提供給第一薄膜電晶體T1的閘極電極G1。The gate electrode G5 of the fifth thin film transistor T5 may be supplied with the first scan signal Scan1. The drain electrode D5 of the fifth thin film transistor T5 may be supplied with the initialization voltage Vini. The source electrode S5 of the fifth thin film transistor T5 may be connected to the gate electrode G1 of the first thin film transistor T1. The fifth thin film transistor T5 can be turned on by the first scan signal Scan1 and can provide the initialization voltage Vini to the gate electrode G1 of the first thin film transistor T1.
第四薄膜電晶體T4的閘極電極G4可被提供有發光控制訊號EM。第四薄膜電晶體T4的汲極電極D4可連接於第一薄膜電晶體T1的源極電極S1。第四薄膜電晶體T4的源極電極S4可連接於發光裝置710的像素電極711(請參閱圖32)。第四薄膜電晶體T4可藉由發光控制訊號EM開啟並可將驅動電流提供給發光裝置710的像素電極711。於此,發光裝置710可為有機發光二極體,且像素電極711可為有機發光二極體的陽極。The gate electrode G4 of the fourth thin film transistor T4 may be supplied with the light emission control signal EM. The drain electrode D4 of the fourth thin film transistor T4 may be connected to the source electrode S1 of the first thin film transistor T1. The source electrode S4 of the fourth thin film transistor T4 can be connected to the
第六薄膜電晶體T6的閘極電極G6可被提供有第一掃描訊號Scan1。第六薄膜電晶體T6的汲極電極D6可被提供有初始化電壓Vini。第六薄膜電晶體T6的源極電極S6可連接於發光裝置710的像素電極711。第六薄膜電晶體T6可藉由第一掃描訊號Scan1被開啟並可將初始化電壓Vini提供給發光裝置710的像素電極711。The gate electrode G6 of the sixth thin film transistor T6 may be supplied with the first scan signal Scan1. The drain electrode D6 of the sixth thin film transistor T6 may be supplied with the initialization voltage Vini. The source electrode S6 of the sixth thin film transistor T6 may be connected to the
第一薄膜電晶體T1的閘極電極G1可連接於第七薄膜電晶體T7的汲極電極D7。第一薄膜電晶體T1的源極電極S1可連接於第七薄膜電晶體T7的源極電極S7。第一薄膜電晶體T1可藉由第七薄膜電晶體T7的源極電極S7及汲極電極D7之間的電壓差而被開啟,並可將驅動電流提供給發光裝置710。The gate electrode G1 of the first thin film transistor T1 can be connected to the drain electrode D7 of the seventh thin film transistor T7. The source electrode S1 of the first thin film transistor T1 may be connected to the source electrode S7 of the seventh thin film transistor T7. The first thin film transistor T1 can be turned on by the voltage difference between the source electrode S7 and the drain electrode D7 of the seventh thin film transistor T7 , and can provide a driving current to the
第一電容器C1的一側可被提供有高位準的像素驅動電壓VDD。第一電容器C1的另一側可連接於第一薄膜電晶體T1的閘極電極G1。第一電容器C1可將電壓儲存於第一薄膜電晶體T1的閘極電極G1。One side of the first capacitor C1 may be supplied with a high-level pixel driving voltage VDD. The other side of the first capacitor C1 may be connected to the gate electrode G1 of the first thin film transistor T1. The first capacitor C1 can store the voltage on the gate electrode G1 of the first thin film transistor T1.
發光裝置710的像素電極711可連接於第四薄膜電晶體T4的源極電極S4以及第六薄膜電晶體T6的源極電極S6。發光裝置710的共用電極713(請參閱圖32)可被提供有低位準的驅動電壓VSS。發光裝置710可根據流動於第一薄膜電晶體T1中的驅動電流發出具有亮度的光。The
請參閱圖30,在開啟提供初始化電壓Vini的第五薄膜電晶體T5時,像素驅動電路PDC可藉由使用發光控制訊號及掃描訊號,來關閉將第一薄膜電晶體T1的源極電極S1連接至發光裝置710的像素電極711之第四薄膜電晶體T4,藉以防止第一薄膜電晶體T1的驅動電流流動至發光裝置710的像素電極711且可構成像素電路而使像素電極711不會受除了用來重設陽極(像素電極)的電壓之外的其他電壓影響。Referring to FIG. 30 , when the fifth thin film transistor T5 that provides the initialization voltage Vini is turned on, the pixel driving circuit PDC can use the light emission control signal and the scan signal to close the connection to the source electrode S1 of the first thin film transistor T1 The fourth thin film transistor T4 to the
初始化電壓Vini可在第四薄膜電晶體T4被關閉的狀態中被供應至發光裝置710的像素電極711,其中第四薄膜電晶體T4設置於發光裝置710的像素電極711以及第一薄膜電晶體T1之間且由發光控制訊號EM控制。用來提供初始化電壓Vini的第六薄膜電晶體T6可連接於發光裝置710的像素電極711。The initialization voltage Vini may be supplied to the
圖31為圖30中的像素P之平面圖,且圖32為沿圖31中的割面線I-I'繪示的剖面示意圖。FIG. 31 is a plan view of the pixel P in FIG. 30 , and FIG. 32 is a schematic cross-sectional view along the secant line II′ in FIG. 31 .
請參閱圖30、圖31及圖32,根據本發明另一實施例之顯示設備700可包含基板(或基座基板)110、像素驅動電路PDC、發光裝置710以及像素驅動電路PDC。像素驅動電路PDC位於基板110上。發光裝置710連接於像素驅動電路PDC。像素驅動電路PDC可包含薄膜電晶體。像素驅動電路PDC可包含圖1至圖5中的薄膜電晶體100至薄膜電晶體500其中至少一者。Referring to FIGS. 30 , 31 and 32 , a
以下,將參照圖31及圖32詳細描述像素P的結構。Hereinafter, the structure of the pixel P will be described in detail with reference to FIGS. 31 and 32 .
請參閱圖32,緩衝層120可設置於基板110上,且第一主動層270可設置於緩衝層120上。第一主動層270可包含矽半導體材料。舉例來說,第一主動層270可由多晶矽半導體層形成。Referring to FIG. 32 , the
第一主動層270的一部分可包含第一薄膜電晶體T1的通道部A1以及第四薄膜電晶體T4的通道部A4,且第一主動層270的另一部分可具有傳導性且可作為線路。雖然未繪示,但第一主動層270的另一部分可包含各個第三薄膜電晶體T3、第五薄膜電晶體T5及第六薄膜電晶體T6的通道部。A portion of the first
閘極絕緣層181可設置於第一主動層270上。The
第一薄膜電晶體T1的第一閘極電極G1以及第四薄膜電晶體T4的第四閘極電極G4可設置於閘極絕緣層181上。第一閘極電極G1可作為第一電容器C1的第一電極CE1。The first gate electrode G1 of the first thin film transistor T1 and the fourth gate electrode G4 of the fourth thin film transistor T4 may be disposed on the
位於第一主動層270及第一閘極電極G1之間的閘極絕緣層181可稱為第一閘極絕緣層。The
鈍化層182可設置於閘極電極G1、G4以及第一電容器C1的第一電極CE1上。The
第一電容器C1的第二電極CE2可設置於鈍化層182上。因此,可完成第一電容器C1。The second electrode CE2 of the first capacitor C1 may be disposed on the
中間層185可設置於第一電容器C1的第二電極CE2上。中間層185可為用來將第一電容器C1的第二電極CE2之頂部平坦化的有機材料層。然,本發明並不以此為限,且中間層185可由單層結構形成,包含氮化矽(SiNx
)或氧化矽(SiOx
)或由上述之多層結構形成。The
第二主動層230可設置於中間層185上且可包含氧化物半導體材料。第二主動層230可為氧化物半導體層。The second
舉例來說,第二主動層230可由氧化物半導體層形成且可包含通道部231及多個導體提供部233a、233b。並且,第二主動層230可包含設置於通道部231及導體提供部233a、233b之間的多個偏差部232a、232b。For example, the second
第二主動層230的一部分可包含第二薄膜電晶體T2的通道部A2,且第二主動層230的另一部分可具有傳導性且可作為線路。詳細來說,第二主動層230的導體提供部233a、233b可各自作為線路。A portion of the second
第二主動層230的一部分可包含第七薄膜電晶體T7的通道部。A portion of the second
根據本發明另一實施例,圖1至圖5中繪示的薄膜電晶體100至500其中至少一者可應用於根據本發明另一實施例的顯示設備700之第二薄膜電晶體T2及第七薄膜電晶體T7其中至少一者。According to another embodiment of the present invention, at least one of the
閘極絕緣層150可設置於第二主動層230上。請參閱圖32,閘極絕緣層150可覆蓋第二主動層230的頂面。閘極絕緣層150可設置於包含第二主動層230的基板110之整個表面上。The
第二薄膜電晶體T2的第二閘極電極G2可設置於閘極絕緣層150上。第二閘極電極G2可重疊於第二薄膜電晶體T2的通道部A2。舉例來說,第二閘極電極G2可重疊於第二主動層230的通道部231且可不重疊於導體提供部233a、233b及偏差部232a、232b。The second gate electrode G2 of the second thin film transistor T2 may be disposed on the
位於第二主動層230及第二閘極電極G2之間的閘極絕緣層150可稱為第二閘極絕緣層。The
中間絕緣層155可設置於第二薄膜電晶體T2的第二閘極電極G2上。中間絕緣層155可包含絕緣材料。The intermediate
第一薄膜電晶體T1至第七薄膜電晶體T7的源極電極及汲極電極可設置於中間絕緣層155上,用於將電極連接至線路的多個橋接件(bridge)可設置於中間絕緣層155上。The source electrodes and drain electrodes of the first thin film transistor T1 to the seventh thin film transistor T7 may be disposed on the intermediate insulating
此外,資料線路DL及像素驅動電壓線路PL可設置於中間絕緣層155上。可透過資料線路DL供應資料電壓Vdata,且可透過像素驅動電壓線路PL供應高位準的像素驅動電壓VDD。In addition, the data line DL and the pixel driving voltage line PL may be disposed on the intermediate insulating
源極電極S1、S2、S4及汲極電極D1、D2、D4可透過接觸孔連接於第一主動層270或第二主動層230。舉例來說,第四薄膜電晶體T4的第四源極電極S4可透過第一接觸孔CH1連接於第一主動層270。並且,第四薄膜電晶體T4的第四汲極電極D4可透過第二接觸孔CH2連接於第一主動層270。並且,第二薄膜電晶體T2的第二源極電極S2可透過第三接觸孔CH3連接於第二主動層230。並且,第二薄膜電晶體T2的第二汲極電極D2可透過第四接觸孔CH4連接於第二主動層230。The source electrodes S1, S2, S4 and the drain electrodes D1, D2, D4 can be connected to the first
請參閱圖32,可形成中間絕緣層155,且接著可形成各自暴露第一主動層270及第二主動層230的第一接觸孔CH1、第二接觸孔CH2、第三接觸孔CH3及第四接觸孔CH4。並且,在形成第一接觸孔CH1、第二接觸孔CH2、第三接觸孔CH3及第四接觸孔CH4之後,為了將包含多晶矽的第一主動層270去氫化(dehydrogenate),可於350℃或更高的高溫進行高溫熱處理製程。因為高溫熱處理製程的緣故,包含氧化物半導體的第二主動層230中可能會產生氧空位(oxygen vacancy)。並且,如硼(B)、磷(P)、氟(F)及氫(H)的摻雜物可藉由氧空位而擴散,因此導體提供區域可延伸至第二主動層230的通道部A2。因此,因為於350℃或更高溫進行高溫熱處理製程,所以導體提供區域可能會延伸,且第二薄膜電晶體T2可能會劣化。Referring to FIG. 32 , an intermediate insulating
因此,在製造包含第四薄膜電晶體T4及第二薄膜電晶體T2的顯示設備700時,可在曝光第一主動層270及第二主動層230的製程以及高溫熱處理製程之後進行將傳導性提供給第二主動層230的離子摻雜製程,其中第四薄膜電晶體T4包含多晶矽且第二薄膜電晶體T2包含氧化物半導體。Therefore, when manufacturing the
圖33A至圖33C為在對應圖32中的區域A之第二薄膜電晶體T2上執行的某些製程之製程示意圖。FIGS. 33A to 33C are schematic process diagrams of some processes performed on the second thin film transistor T2 corresponding to the region A in FIG. 32 .
請參閱圖33A,第二主動層230可形成於中間層185上。並且,閘極絕緣層150可形成於第二主動層230上。並且,閘極電極G2可形成於閘極絕緣層150上。中間絕緣層155可形成於閘極電極G2及閘極絕緣層150上。並且,如圖33A所示,可為了形成用來暴露第二主動層230的接觸孔而形成光阻圖案50。為了形成接觸孔,光阻圖案50可包含暴露中間絕緣層155的頂面之開口區域。並且,為了透過光阻圖案50的開口區域形成接觸孔,可進行蝕刻製程。中間絕緣層155及閘極絕緣層150可透過蝕刻製程被移除。Referring to FIG. 33A , the second
如圖33B所示,藉由進行蝕刻製程可於中間絕緣層155及閘極絕緣層150a中形成各自暴露第二主動層230的第三接觸孔CH3以及第四接觸孔CH4。可於蝕刻製程中形成各自暴露第四薄膜電晶體T4的第一主動層270之第一接觸孔CH1以及第二接觸孔CH2。如上所述,在形成第一接觸孔CH1、第二接觸孔CH2、第三接觸孔CH3及第四接觸孔CH4之後,可為了將第一主動層270去氫化而於350℃或更高的高溫進行高溫熱處理製程。As shown in FIG. 33B , a third contact hole CH3 and a fourth contact hole CH4 respectively exposing the second
隨後,如圖33C所示,在進行高溫熱處理製程之後,可藉由使用閘極電極G2作為遮罩而進行離子摻雜製程。Subsequently, as shown in FIG. 33C, after the high temperature heat treatment process, an ion doping process may be performed by using the gate electrode G2 as a mask.
此外,可透過離子摻雜製程在第二主動層230中形成根據離子摻雜製程而具有傳導性的多個導體提供部233a、233b以及重疊於閘極電極G2的通道部231。In addition, a plurality of
此外,如圖32中所示,可形成第二薄膜電晶體T2的源極電極S2及汲極電極D2以及第四薄膜電晶體T4的源極電極S4及汲極電極D4。並且,第二薄膜電晶體T2的源極電極S2及汲極電極D2可透過第三接觸孔CH3及第四接觸孔CH4連接於第二主動層230。並且,第四薄膜電晶體T4的源極電極S4及汲極電極D4可透過第一接觸孔CH1及第二接觸孔CH2連接於第一主動層270。In addition, as shown in FIG. 32 , the source electrode S2 and the drain electrode D2 of the second thin film transistor T2 and the source electrode S4 and the drain electrode D4 of the fourth thin film transistor T4 may be formed. In addition, the source electrode S2 and the drain electrode D2 of the second thin film transistor T2 can be connected to the second
可透過相同的製程同時形成各自連接於第一主動層270的源極電極S1、S4與汲極電極D1、D4以及各自連接於第二主動層230的源極電極S2及汲極電極D2。The source electrodes S1 and S4 and the drain electrodes D1 and D4 respectively connected to the first
平坦化層192可設置於源極電極S1、S2、S4、汲極電極D1、D2、D4、橋接件、資料線路DL及像素驅動電壓線路PL上。The
發光裝置710的像素電極711可設置於平坦化層192上。像素電極711可稱為陽極電極或第一電極。像素電極711可連接於第一主動層270。請參閱圖30及圖31,像素電極711可透過第四薄膜電晶體T4的第四源極電極S4連接於第一主動層270。The
堤部層750可設置於像素電極711的邊緣。堤部層750可界定出發光裝置710的發光區域。The
發光層712可設置於像素電極711上,且共用電極713可設置於發光層712上。共用電極713可稱為陰極電極或第二電極。因此,可完成發光裝置710。圖32中的發光裝置710可為有機發光二極體,且根據本發明另一實施例之顯示設備700可為有機發光顯示設備。The light-emitting
圖34為根據本發明另一實施例之顯示設備800的一個像素P之電路圖。FIG. 34 is a circuit diagram of one pixel P of a
圖34中繪示的顯示設備800的像素P可包含作為發光裝置710的有機發光二極體以及用於驅動發光裝置710的像素驅動電路PDC。發光裝置710可連接於像素驅動電路PDC。The pixel P of the
像素驅動電路PDC可連接於閘極線路GL、初始化控制線路ICL、資料線路DL、像素驅動電壓線路PL及初始化電壓線路IL,且可將資料電流供應給發光裝置710,其中資料電流對應於被供應至資料線路DL的資料電壓Vdata。The pixel driving circuit PDC can be connected to the gate line GL, the initialization control line ICL, the data line DL, the pixel driving voltage line PL and the initialization voltage line IL, and can supply the data current to the light-emitting
資料電壓Vdata可被供應至資料線路DL,掃描訊號SS可被供應至閘極線路GL,像素驅動電壓VDD可被供應至像素驅動電壓線路PL,初始化電壓Vini可被供應至初始化電壓線路IL,且初始化控制訊號ICS可被供應至初始化控制線路ICL。The data voltage Vdata may be supplied to the data line DL, the scan signal SS may be supplied to the gate line GL, the pixel driving voltage VDD may be supplied to the pixel driving voltage line PL, the initialization voltage Vini may be supplied to the initialization voltage line IL, and The initialization control signal ICS may be supplied to the initialization control line ICL.
請參閱圖34,當第n個像素P的閘極線路以GLn表示時,鄰近於其的第n-1個像素P的閘極線路可以GLn-1表示,且第n-1個像素P的閘極線路GLn-1可作為第n個像素P的初始化控制線路ICL。Referring to FIG. 34, when the gate line of the nth pixel P is represented by GLn, the gate line of the n-1th pixel P adjacent to it can be represented by GLn-1, and the gate line of the n-1th pixel P is represented by GLn-1. The gate line GLn-1 can be used as the initialization control line ICL of the nth pixel P.
如圖34所示,像素驅動電路PDC例如可包含第二薄膜電晶體T2、第一薄膜電晶體T1以及第三薄膜電晶體T3。第二薄膜電晶體T2(開關電晶體)連接於閘極線路GL及資料線路DL。第一薄膜電晶體T1(驅動電晶體)用於控制基於透過第二薄膜電晶體T2傳來的資料電壓Vdata而輸出至發光裝置710的電流之位準。第三薄膜電晶體T3(初始化電晶體)用於感測第一薄膜電晶體T1的特性。As shown in FIG. 34 , the pixel driving circuit PDC may include, for example, a second thin film transistor T2 , a first thin film transistor T1 and a third thin film transistor T3 . The second thin film transistor T2 (switching transistor) is connected to the gate line GL and the data line DL. The first thin film transistor T1 (driving transistor) is used to control the level of the current output to the
第一電容器C1可設置於第一薄膜電晶體T1的閘極電極以及發光裝置710之間。第一電容器C1可稱為儲存電容器(Cst)。The first capacitor C1 may be disposed between the gate electrode of the first thin film transistor T1 and the
第二薄膜電晶體T2可藉由透過閘極線路GL供應的掃描訊號SS而被開啟,且可將透過資料線路DL供應的資料電壓Vdata傳送給第一薄膜電晶體T1的閘極電極。The second thin film transistor T2 can be turned on by the scan signal SS supplied through the gate line GL, and can transmit the data voltage Vdata supplied through the data line DL to the gate electrode of the first thin film transistor T1.
第三薄膜電晶體T3可連接於初始化電壓線路IL以及位於第一薄膜電晶體T1及發光裝置710之間的第一節點n1,且可藉由初始化控制訊號ICS開啟或關閉,藉以於感測期間感測第一薄膜電晶體T1(驅動電晶體)的特性。The third thin film transistor T3 can be connected to the initialization voltage line IL and the first node n1 between the first thin film transistor T1 and the
連接於第一薄膜電晶體T1的閘極電極之第二節點n2可連接於第二薄膜電晶體T2。第一電容器C1可形成於第二節點n2以及第一節點n1之間。The second node n2 connected to the gate electrode of the first thin film transistor T1 can be connected to the second thin film transistor T2. The first capacitor C1 may be formed between the second node n2 and the first node n1.
當第二薄膜電晶體T2開啟時,透過資料線路DL供應的資料電壓Vdata可被供應至第一薄膜電晶體T1的閘極電極。資料電壓Vdata可充(charged)至形成於第一薄膜電晶體T1的閘極電極及源極電極之間的電容器C1中。When the second thin film transistor T2 is turned on, the data voltage Vdata supplied through the data line DL can be supplied to the gate electrode of the first thin film transistor T1. The data voltage Vdata can be charged into the capacitor C1 formed between the gate electrode and the source electrode of the first thin film transistor T1.
當第一薄膜電晶體T1開啟時,電流可從像素驅動電壓VDD透過第一薄膜電晶體T1傳送,進而可從發光裝置710發光。When the first thin film transistor T1 is turned on, the current can be transmitted from the pixel driving voltage VDD through the first thin film transistor T1 , and then light can be emitted from the
圖35為根據本發明另一實施例之顯示設備900的像素P之電路圖。FIG. 35 is a circuit diagram of a pixel P of a
圖35中所繪示的顯示設備900之像素P可包含作為發光裝置710的有機發光二極體以及用於驅動發光裝置710的像素驅動電路PDC。The pixel P of the
像素驅動電路PDC可包含多個薄膜電晶體(如第一至第四薄膜電晶體)T1至T4。The pixel driving circuit PDC may include a plurality of thin film transistors (eg, first to fourth thin film transistors) T1 to T4.
可於像素P中設置用於將多個驅動訊號供應給像素驅動電路PDC的訊號線路(資料線路DL、發光控制線路EL、閘極線路GL、像素驅動電壓線路PL、初始化控制線路ICL及初始化電壓線路IL)。A signal line (a data line DL, a light emission control line EL, a gate line GL, a pixel driving voltage line PL, an initialization control line ICL, and an initialization voltage line) for supplying a plurality of driving signals to the pixel driving circuit PDC can be provided in the pixel P. line IL).
相較於圖34中的像素P,圖35中的像素P可更包含發光控制線路EL。發光控制訊號EM可被供應至發光控制線路EL。並且,相較於圖34中的像素驅動電路PDC,圖35中的像素驅動電路PDC可更包含第三薄膜電晶體T3,且第三薄膜電晶體T3為用於控制第一薄膜電晶體T1的發光時間的發光控制電晶體。Compared with the pixel P in FIG. 34 , the pixel P in FIG. 35 may further include an emission control line EL. The lighting control signal EM may be supplied to the lighting control line EL. Moreover, compared with the pixel driving circuit PDC in FIG. 34 , the pixel driving circuit PDC in FIG. 35 may further include a third thin film transistor T3 , and the third thin film transistor T3 is used for controlling the first thin film transistor T1 Light-emitting control transistor for light-emitting time.
然,本發明的另一實施例並不以此為限。像素驅動電路PDC可被提供於不同於上述之結構的各種結構中。像素驅動電路PDC例如可包含五個或六個薄膜電晶體。Of course, another embodiment of the present invention is not limited thereto. The pixel driving circuit PDC may be provided in various structures other than those described above. The pixel driving circuit PDC may include, for example, five or six thin film transistors.
請參閱圖35,當第n個像素P的閘極線路以GLn表示時,鄰近於其的第n-1個像素P的閘極線路可以GLn-1表示,且第n-1個像素P的閘極線路GLn-1可作為第n個像素P的初始化控制線路ICL。Referring to FIG. 35, when the gate line of the nth pixel P is represented by GLn, the gate line of the n-1th pixel P adjacent to it can be represented by GLn-1, and the gate line of the n-1th pixel P is represented by GLn-1. The gate line GLn-1 can be used as the initialization control line ICL of the nth pixel P.
第一電容器C1可設置於第一薄膜電晶體T1的閘極電極及發光裝置710的一個電極之間。並且,第二電容器C2可設置於發光裝置710的那一個電極以及第三薄膜電晶體T3的多個終端中供應有像素驅動電壓VDD的一者之間。The first capacitor C1 may be disposed between the gate electrode of the first thin film transistor T1 and one electrode of the
第二薄膜電晶體T2可藉由透過閘極線路GL供應的掃描訊號SS而被開啟,且可將透過資料線路DL供應的資料電壓Vdata傳送給第一薄膜電晶體T1的閘極電極。The second thin film transistor T2 can be turned on by the scan signal SS supplied through the gate line GL, and can transmit the data voltage Vdata supplied through the data line DL to the gate electrode of the first thin film transistor T1.
第四薄膜電晶體T4可連接於初始化電壓線路IL且可藉由初始化控制訊號ICS被開啟或關閉,藉以於感測期間感測第一薄膜電晶體T1(驅動電晶體)的特性。The fourth thin film transistor T4 can be connected to the initialization voltage line IL and can be turned on or off by the initialization control signal ICS, so as to sense the characteristics of the first thin film transistor T1 (driving transistor) during the sensing period.
根據發光控制訊號EM,第三薄膜電晶體T3可將像素驅動電壓VDD傳送給第一薄膜電晶體T1或可切斷像素驅動電壓VDD。當第三薄膜電晶體T3被開啟時,電流可被供應至第一薄膜電晶體T1,進而可從發光裝置710發光。According to the light emission control signal EM, the third thin film transistor T3 can transmit the pixel driving voltage VDD to the first thin film transistor T1 or can cut off the pixel driving voltage VDD. When the third thin film transistor T3 is turned on, a current may be supplied to the first thin film transistor T1 , which in turn may emit light from the
根據本發明另一實施例,第二薄膜電晶體T2及第三薄膜電晶體T3可彼此重疊,且可於第二薄膜電晶體T2及第三薄膜電晶體T3之間設置屏蔽電極(shield electrode)。屏蔽電極可連接於發光控制線路EL。並且,閘極線路GL及發光控制線路EL可彼此重疊。According to another embodiment of the present invention, the second thin film transistor T2 and the third thin film transistor T3 may overlap each other, and a shield electrode may be disposed between the second thin film transistor T2 and the third thin film transistor T3 . The shield electrode can be connected to the light emission control line EL. Also, the gate line GL and the light emission control line EL may overlap with each other.
圖36為繪示本發明另一實施例的剖面示意圖。FIG. 36 is a schematic cross-sectional view illustrating another embodiment of the present invention.
請參閱圖36,僅繪示根據本發明一實施例的各個第二薄膜電晶體T2及第四薄膜電晶體T4的剖面示意圖。Please refer to FIG. 36 , which only shows a schematic cross-sectional view of each of the second thin film transistor T2 and the fourth thin film transistor T4 according to an embodiment of the present invention.
根據本發明一實施例之顯示設備10可包含基板110、一第一緩衝層111、一第一閘極絕緣層112、一第一中間絕緣層113、一第二緩衝層114、一第二閘極絕緣層115、一第二中間絕緣層116、一鈍化層117、堤部層750、發光裝置710、封裝件(未繪示)、第二薄膜電晶體T2及第四薄膜電晶體T4。The
基板110可支撐顯示設備10的各種元件。基板110可包含具有可撓性的玻璃或塑膠材料。在基板110包含塑膠材料的情況中,基板110例如可包含聚醯亞胺(polyimide,PI)。在基板110包含聚醯亞胺的情況中,可以包含玻璃的支撐基板設置在基板110之下的條件進行顯示設備10的製程,且在完成顯示設備10的製程之後,支撐基板可被釋放。並且,在釋放支撐基板之後,用於支撐基板110的背板可設置於基板110之下。The
在基板110包含聚醯亞胺的情況中,水成份(water component)可能會穿過包含聚醯亞胺的基板110,且可能滲透至薄膜電晶體或是發光裝置710,進而降低顯示設備10之效能。為了防止顯示設備10的效能因水的滲透而降低,根據本發明另一實施例的顯示設備10可包含雙層聚醯亞胺。並且,可在兩個聚醯亞胺之間形成無機絕緣層,而可防止水成份穿過底層聚醯亞胺,進而提升顯示設備的可靠度。In the case where the
此外,在無機絕緣層形成於兩個聚醯亞胺之間的情況中,充至設置在底部的聚醯亞胺之電荷可形成回授偏壓(back bias)來影響第二薄膜電晶體T2或是第四薄膜電晶體T4。因此,為了防止電荷充至聚醯亞胺中,可能需要形成獨立的金屬層。然,在根據本發明另一實施例之顯示設備10中,因為無機絕緣層形成於兩個聚醯亞胺之間,所以無機絕緣層可阻擋電荷充至設置在底部的聚醯亞胺,進而提升產品的可靠度。無機絕緣層可由單層結構形成,包含氮化矽(SiNx
)或氧化矽(SiOx
)或由上述之多層結構形成。舉例來說,無機絕緣層可包含二氧化矽(silicon dioxide,SiO2
)。並且,可省略為了阻擋電荷充至聚醯亞胺而形成金屬層的製程,進而簡化製程並降低製造成本。In addition, in the case where the inorganic insulating layer is formed between two polyimides, the charge charged to the polyimide disposed at the bottom can form a back bias to affect the second thin film transistor T2 Or the fourth thin film transistor T4. Therefore, in order to prevent charge charging into the polyimide, it may be necessary to form a separate metal layer. However, in the
第一緩衝層111可形成於基板110的整個表面上。第一緩衝層111可由包含氮化矽(SiNx
)或氧化矽(SiOx
)的單層結構形成,或由上述之多層結構形成。根據本發明一實施例,第一緩衝層111可由氮化矽(SiNx
)及氧化矽(SiOx
)交錯形成的多層結構形成。舉例來說,第一緩衝層111可由n+1個層體形成。於此,n可為偶數,如0、2、4、6及8。因此,當n為0時,第一緩衝層111可由單層結構形成。並且,第一緩衝層111可包含氮化矽(SiNx
)或氧化矽(SiOx
)。當n為2時,第一緩衝層111可由三層結構形成。在第一緩衝層111由三層結構形成的情況中,頂層及底層可包含氧化矽(SiOx
),而設置在頂層及底層之間的中間層可包含氮化矽(SiNx
)。當n為4時,第一緩衝層111可由四層結構(quadruple layer)形成。The
如上所述,在第一緩衝層111由氮化矽(SiNx
)及氧化矽(SiOx
)交錯形成的多層結構形成的情況中,第一緩衝層111中最頂層以及最底層可包含氧化矽(SiOx
)。舉例來說,包含多個層體的第一緩衝層111可包含接觸第四薄膜電晶體T4的第一主動層270之頂層、接觸基板110之底層,以及設置於頂層及底層之間的中間層。並且,頂層及底層可包含氧化矽(SiOx
)。並且,由多層結構形成的第一緩衝層111之頂層的厚度可大於各個底層及中間層的厚度。As described above, in the case where the
第四薄膜電晶體T4可設置於第一緩衝層111上。第四薄膜電晶體T4可包含第一主動層270、第四閘極電極G4、第四源極電極S4及第四汲極電極D4。然,本實施例並不以此為限,且第四源極電極S4可為汲極電極且第四汲極電極D4可為源極電極。The fourth thin film transistor T4 may be disposed on the
第四薄膜電晶體T4的第一主動層270可設置於第一緩衝層111上。第一主動層270可包含多晶矽。舉例來說,第一主動層270可包含低溫多晶矽(low temperature polysilicon,LTPS)。The first
多晶矽材料可具有100 cm2
/Vs或更高的高移動率,而可具有低的功耗以及良好的可靠度,而使得多晶矽材料可應用於多工器(multiplexer,MUX)及/或閘極驅動器,多工器(multiplexer,MUX)及/或閘極驅動器用於為顯示像素驅動用於驅動薄膜電晶體的驅動元件。並且,在根據一實施例的顯示設備中,多晶矽材料可作為開關薄膜電晶體的半導體圖案應用,但並不以此為限。舉例來說,多晶矽材料可作為驅動薄膜電晶體的半導體圖案應用。在根據本發明一實施例之顯示設備中,包含多晶矽的第四薄膜電晶體T4可為電性連接於像素電極711以將電流傳送給發光裝置710的驅動薄膜電晶體。The polysilicon material can have a high mobility of 100 cm 2 /Vs or higher, and can have low power consumption and good reliability, so that the polysilicon material can be applied to multiplexers (MUX) and/or gates Drivers, multiplexers (MUXs) and/or gate drivers are used to drive driving elements for driving thin film transistors for display pixels. Also, in the display device according to an embodiment, the polysilicon material can be used as the semiconductor pattern of the switching thin film transistor, but it is not limited thereto. For example, polysilicon materials can be used as semiconductor patterns for driving thin film transistors. In the display device according to an embodiment of the present invention, the fourth thin film transistor T4 comprising polysilicon may be a driving thin film transistor that is electrically connected to the
第一主動層270可包含一第四通道區域270C、一第四源極區域270S以及一第四汲極區域270D。第四通道區域270C中形成有驅動第四薄膜電晶體T4的通道。第四源極區域270S及第四汲極區域270D各自提供於第四通道區域270C的兩側。第四源極區域270S可為第一主動層270中連接於第四源極電極S4的部分,且第四汲極區域270D可為第一主動層270中連接於第四汲極電極D4的部分。The first
第一閘極絕緣層112可設置於第四薄膜電晶體T4的第一主動層270上。第一閘極絕緣層112可由單層結構形成,包含氮化矽(SiNx
)或氧化矽(SiOx
),或由上述之多層結構形成。The first
第四薄膜電晶體T4的第四閘極電極G4可設置於第一閘極絕緣層112上。第四閘極電極G4可由單層結構或多層結構形成,其包含鉬(Mo)、銅(Cu)、鈦(Ti)、鋁(Al)、鉻(Cr)、金(Au)、鎳(Ni)及釹(Nd)或上述之合金其中一者。第四閘極電極G4可重疊於第一主動層270的第四通道區域270C且第一閘極絕緣層112位於第四閘極電極G4及第四通道區域270C之間。The fourth gate electrode G4 of the fourth thin film transistor T4 may be disposed on the first
第一中間絕緣層113可設置於第一閘極絕緣層112及第四閘極電極G4上。第一中間絕緣層113可由單層結構形成,包含氮化矽(SiNx
)或氧化矽(SiOx
),或由上述之多層結構形成。The first intermediate insulating
第二緩衝層114可形成於第一中間絕緣層113上。第二緩衝層114可由單層結構形成,包含氮化矽(SiNx
)或氧化矽(SiOx
),或由上述之多層結構形成。The
第二薄膜電晶體T2的第二主動層230可設置於第二緩衝層114上。第二主動層230可包含氧化物半導體圖案,且氧化物半導體圖案包含氧化物半導體。第二薄膜電晶體T2可包含第二主動層230、第二閘極電極G2、第二源極電極S2及第二汲極電極D2。於另一示例中,第二源極電極S2可為汲極電極且第二汲極電極D2可為源極電極。第二主動層230可包含一第二通道區域230C、一第二源極區域230S及一第二汲極區域230D。第二通道區域230C中形成有驅動第二薄膜電晶體T2的通道。第二源極區域230S及第二汲極區域230D各自被提供於第二通道區域230C的兩側。第二源極區域230S可為第二主動層230中連接於第二源極電極S2的部分,且第二汲極區域230D可為第二主動層230中連接於第二汲極電極D2的部分。The second
第二主動層230的氧化物半導體材料可為能帶隙(band gap)高於多晶矽材料的能帶隙的材料,而使得電子可無須在關閉狀態中通過能帶隙,進而使的關閉電流(off-current)可為低的。因此,包含包含氧化物半導體的主動層的薄膜電晶體可適用於開啟時間短且關閉時間長的開關薄膜電晶體,但本發明並不以此為限。舉例來說,薄膜電晶體可作為驅動薄膜電晶體應用。並且,關閉電流可為低的,而可減小輔助電容器的尺寸,進而使得薄膜電晶體可適用於高解析度的顯示設備。請參閱圖36,包含氧化物半導體的第二薄膜電晶體T2可為執行如開/關控制的開關功能的開關薄膜電晶體。The oxide semiconductor material of the second
第二閘極絕緣層115可形成於第二主動層230及第二緩衝層114上。第二閘極絕緣層115可由單層結構形成,包含氮化矽(SiNx
)或氧化矽(SiOx
),或由上述之多層結構形成。The second
第二閘極電極G2可形成於第二閘極絕緣層115上。第二閘極電極G2可重疊於第二主動層230的第二通道區域230C,且第二閘極絕緣層115位於第二閘極電極G2及第二通道區域230C之間。並且,第二閘極電極G2可由單層結構或多層結構形成,其包含鉬(Mo)、銅(Cu)、鈦(Ti)、鋁(Al)、鉻(Cr)、金(Au)、鎳(Ni)及釹(Nd)或上述之合金其中一者。The second gate electrode G2 may be formed on the second
第二中間絕緣層116可形成於第二閘極電極G2及第二閘極絕緣層115上。第二中間絕緣層116可由單層結構形成,包含氮化矽(SiNx
)或氧化矽(SiOx
),或由上述之多層結構形成。The second intermediate insulating
可藉由蝕刻第二中間絕緣層116、第二閘極絕緣層115、第二緩衝層114、第一中間絕緣層113及第一閘極絕緣層112來形成用於暴露第四薄膜電晶體T4的第一主動層270之接觸孔。因此,可形成暴露第一主動層270的第四源極區域270S及第四汲極區域270D之多個接觸孔(如第一及第二接觸孔)CH1、CH2。may be formed by etching the second intermediate insulating
此外,可藉由蝕刻第二中間絕緣層116及第二閘極絕緣層115來形成用於暴露第二薄膜電晶體T2的第二主動層230之接觸孔。因此,可形成暴露第二主動層230的第二源極區域230S及第二汲極區域230D的多個接觸孔CH3、CH4(如第三及第四接觸孔)。In addition, a contact hole for exposing the second
此外,可為了將第一主動層27去氫化0而透過第一接觸孔CH1及第二接觸孔CH2進行高溫熱處理製程。舉例來說,可於腔體中以350℃或更高的溫度持續一個小時進行高溫熱處理製程。隨後,為了將傳導性提供給第二主動層230的第二源極區域230S及第二汲極區域230D,可進行離子摻雜製程。用於離子摻雜製程的摻雜物可包含硼(B)、磷(P)、氟(F)及氫(H)其中至少一者。In addition, a high temperature heat treatment process may be performed through the first contact hole CH1 and the second contact hole CH2 in order to dehydrogenate the first active layer 27 . For example, the high temperature heat treatment process can be performed in the chamber at a temperature of 350° C. or higher for one hour. Subsequently, in order to provide conductivity to the
第二薄膜電晶體T2的第二源極電極S2及第二汲極電極D2以及第四薄膜電晶體T4的第四源極電極S4及第四汲極電極D4可設置於第二中間絕緣層116上。The second source electrode S2 and the second drain electrode D2 of the second thin film transistor T2 and the fourth source electrode S4 and the fourth drain electrode D4 of the fourth thin film transistor T4 may be disposed on the second intermediate insulating
第四薄膜電晶體T4的第四源極電極S4及第四汲極電極D4可透過第一接觸孔CH1及第二接觸孔CH2連接於第一主動層270的第四源極區域270S及第四汲極區域270D,其中第一接觸孔CH1及第二接觸孔CH2各自形成於第二中間絕緣層116、第二閘極絕緣層115、第二緩衝層114、第一中間絕緣層113及第一閘極絕緣層112中。The fourth source electrode S4 and the fourth drain electrode D4 of the fourth thin film transistor T4 can be connected to the
第二薄膜電晶體T2的第二源極電極S2及第二汲極電極D2可透過第三接觸孔CH3及第四接觸孔CH4連接於第二主動層230的第二源極區域230S及第二汲極區域230D,其中第三接觸孔CH3及第四接觸孔CH4各自形成於第二中間絕緣層116及第二閘極絕緣層115中。The second source electrode S2 and the second drain electrode D2 of the second thin film transistor T2 can be connected to the
第二薄膜電晶體T2的第二源極電極S2及第二汲極電極D2以及第四薄膜電晶體T4的第四源極電極S4及第四汲極電極D4可包含相同的材料且可設置於相同的層體上。並且,第二薄膜電晶體T2的第二源極電極S2及第二汲極電極D2以及第四薄膜電晶體T4的第四源極電極S4及第四汲極電極D4可由單層結構或多層結構形成,其包含鉬(Mo)、銅(Cu)、鈦(Ti)、鋁(Al)、鉻(Cr)、金(Au)、鎳(Ni)及釹(Nd)或上述之合金其中一者。The second source electrode S2 and the second drain electrode D2 of the second thin film transistor T2 and the fourth source electrode S4 and the fourth drain electrode D4 of the fourth thin film transistor T4 may include the same material and may be disposed in on the same layer. In addition, the second source electrode S2 and the second drain electrode D2 of the second thin film transistor T2 and the fourth source electrode S4 and the fourth drain electrode D4 of the fourth thin film transistor T4 may have a single-layer structure or a multi-layer structure Form, which includes molybdenum (Mo), copper (Cu), titanium (Ti), aluminum (Al), chromium (Cr), gold (Au), nickel (Ni) and neodymium (Nd) or one of the above alloys .
以下將參照圖37A至圖37D詳細描述形成用於暴露第二主動層230的第三接觸孔CH3及第四接觸孔CH4之製程、高溫熱處理製程,以及形成第二主動層230的第二源極區域230S及第二汲極區域230D之離子摻雜製程。圖37A至圖37D為詳細繪示圖36中所繪示的第二薄膜電晶體T2之區域B的剖面示意圖。The process of forming the third contact hole CH3 and the fourth contact hole CH4 for exposing the second
請參閱圖37A,為了蝕刻製程,光阻(photoresist,PR)圖案60可形成於第二中間絕緣層116上。光阻圖案60可包含一第二光阻圖案62、一第一光阻圖案61以及一第三光阻圖案63。第二光阻圖案62重疊於第二閘極電極G2。第一光阻圖案61分離於第二光阻圖案62的左表面。第三光阻圖案63分離於第二光阻圖案62的右表面。Referring to FIG. 37A , for the etching process, a photoresist (PR)
第一光阻圖案61及第二光阻圖案62的一個側面可彼此分離且可形成一第一開口部OP1,其中第一開口部OP1暴露對應於第二主動層230的第二源極區域230S之第二中間絕緣層116的頂面。並且,第二光阻圖案62及第三光阻圖案63的另一側面可彼此分離且可形成一第二開口部OP2,其中第二開口部OP2暴露對應於第二主動層230的第二汲極區域230D之第二中間絕緣層116的頂面。One side of the
請參閱圖37B,可透過蝕刻製程移除透過第一開口部OP1及第二開口部OP2暴露的第二中間絕緣層116。並且,可透過蝕刻製程移除形成於第二中間絕緣層116之下的第二閘極絕緣層115。如上所述,可藉由使用光阻圖案60作為遮罩來移除對應於暴露於第一開口部OP1及第二開口部OP2之區域的絕緣層,而可形成接觸孔。舉例來說,可藉由蝕刻對應於第一開口部OP1的第二閘極絕緣層115及第二中間絕緣層116來形成暴露第二主動層230的第三接觸孔CH3。並且,可藉由蝕刻對應於第二開口部OP2的第二閘極絕緣層115及第二中間絕緣層116來形成暴露第二主動層230的第四接觸孔CH4。Referring to FIG. 37B , the second
如圖37C所示,在形成第三接觸孔CH3及第四接觸孔CH4之後,可藉由灰化製程(ashing process)移除光阻圖案60。並且,可在350℃或更高的高溫進行高溫熱處理製程。請參閱圖36,可為了使第一主動層270去氫化或結晶而進行高溫熱處理製程。As shown in FIG. 37C , after the third contact hole CH3 and the fourth contact hole CH4 are formed, the
隨後,請參閱圖37D,可形成重疊於第二薄膜電晶體T2的第二閘極電極G2之摻雜遮罩圖案70。摻雜遮罩圖案70可為包含光阻物的光阻圖案。如圖37D所示,可藉由使用摻雜遮罩圖案70作為遮罩進行摻雜製程。摻雜製程可為使用摻雜物的摻雜製程,且摻雜物可包含硼(B)、磷(P)、氟(F)及氫(H)其中至少一者。第二主動層230沒有透過摻雜重疊於摻雜遮罩圖案70且可具有傳導性。因此,第二薄膜電晶體T2的第二主動層230可包含多個導體提供部233a、233b。並且,可不對第二主動層230的第二通道區域230C進行摻雜。為了防止第二通道區域230C受到摻雜,摻雜遮罩圖案70可在摻雜製程中防止摻雜物植入到第二通道區域230C中。因此,摻雜遮罩圖案70可作為用來防止對第二通道區域230C進行摻雜的遮罩。Then, referring to FIG. 37D , a
請參閱圖37D,對於剖面示意圖來說,摻雜遮罩圖案70的寬度可大於第二閘極電極G2的寬度。Referring to FIG. 37D , for a schematic cross-sectional view, the width of the
透過使用摻雜物的摻雜製程提供有傳導性的導體提供部233a、233b可具有較第二通道區域230C之摻雜濃度高的摻雜濃度,並可具有較第二通道區域230C的電阻率低的電阻率。
請參閱圖37D,多個偏差部(如第一及第二偏差部)232a、232b可受摻雜遮罩圖案70保護。因此,可防止摻雜物直接植入到偏差部232a、232b中。然,摻雜於導體提供部233a、233b的摻雜物可能會擴散至偏差部232a、232b。因此,可能會得到摻雜物部分地摻雜到偏差部232a、232b的效果。Referring to FIG. 37D , a plurality of offset parts (eg, the first and second offset parts) 232 a and 232 b can be protected by the
於圖37D中,當第二閘極電極G2具有寬度LG且摻雜遮罩圖案70具有從第二閘極電極G2凸出的寬度Loh時,可在滿足以下方程式2的條件下進行摻雜。In FIG. 37D, when the second gate electrode G2 has a width LG and the
[方程式2][Equation 2]
LG x Loh x 1/η2 ≥ 1LG x Loh x 1/η2 ≥ 1
其中η2 = 0.5平方微米where η2 = 0.5 square microns
各個第一偏差部232a及第二偏差部232b的寬度可對應於凸出的寬度Loh。當第二閘極電極G2的寬度LG以及從第二閘極電極G2凸出的摻雜遮罩圖案70的寬度Loh滿足方程式2時,可形成滿足方程式2的偏差部232a、232b。The width of each of the
根據本發明另一實施例,於方程式2中,η2 = 1.5平方微米。或者,η2可滿足以下關係式:0.5平方微米 ≤ η2 ≤ 1.5平方微米。According to another embodiment of the present invention, in
這些導體提供部233a、233b中摻雜物的濃度可為最高的。這些偏差部232a、232b的摻雜濃度可低於各個導體提供部233a、233b的摻雜濃度。少量的摻雜物可能會擴散至沒有直接摻雜有摻雜物的第二通道區域230C。第二通道區域230C可幾乎沒有包含摻雜物,或可具有非常低濃度的摻雜物。The concentration of dopants in these
因此,如圖37D所示,根據使用摻雜遮罩圖案70的摻雜製程,第二薄膜電晶體T2的第二主動層230可包含第二通道區域230C、導體提供部233a、233b以及偏差部232a、232b。第二通道區域230C具有相對較低的摻雜濃度。導體提供部233a、233b具有相對較高的摻雜濃度。偏差部232a、232b的摻雜濃度低於各個導體提供部233a、233b的摻雜濃度且高於第二通道區域230C的摻雜濃度。並且,第一導體提供部233a及第一偏差部232a可為第二源極區域230S。並且,第二導體提供部233b及第二偏差部232b可為第二汲極區域230D。Therefore, as shown in FIG. 37D, according to the doping process using the
偏差部232a、232b可在從第二通道區域230C到導體提供部233a、233b的方向中具有增加的摻雜物濃度梯度。舉例來說,第一偏差部232a可在從第二通道區域230C到第一導體提供部233a的方向中具有增加的摻雜物濃度梯度,且第二偏差部232b可在從第二通道區域230C到第二導體提供部233b的方向中具有增加的摻雜物濃度梯度。The
各個偏差部232a、232b的電阻率可低於第二通道區域230C的電阻率,且可高於各個導體提供部233a、233b的電阻率。偏差部232a、232b可在從第二通道區域230C到導體提供部233a、233b的方向中具有減少的電阻率梯度。The resistivity of the
因此,偏差部232a、232b可在沒有提供傳導性的第二通道區域230C以及導體提供部233a、233b之間執行電性緩衝的功能。Therefore, the offset
詳細來說,因為偏差部232a、232b設置於第二通道區域230C及導體提供部233a、233b之間,所以可防止漏電流在第二薄膜電晶體T2的關閉(OFF)狀態中流動於第二通道區域230C及導體提供部233a、233b之間。如上所述,偏差部232a、232b可在第二薄膜電晶體T2處於關閉(OFF)狀態的時候防止漏電流產生於第二薄膜電晶體T2中。In detail, since the
此外,如圖37D所示,第二中間絕緣層116可形成於第二閘極電極G2上,且接著可進行摻雜摻雜物的摻雜製程。因此,摻雜物可被摻雜於第二中間絕緣層116及第二閘極絕緣層115。因此,第二中間絕緣層116及第二閘極絕緣層115中重疊於第二主動層230的導體提供部233a、233b的區域可包含摻雜物。摻雜物可包含硼(B)、磷(P)、氟(F)及氫(H)其中至少一者。因此,第二中間絕緣層116及第二閘極絕緣層115可包含硼(B)、磷(P)、氟(F)及氫(H)其中至少一者。並且,摻雜物可摻雜於第二中間絕緣層116中重疊於第二閘極電極G2的區域。因此,第二中間絕緣層116中重疊於第二閘極電極G2的區域可包含硼(B)、磷(P)、氟(F)及氫(H)其中至少一者。並且,第二中間絕緣層116中重疊於第二閘極電極G2的區域可無須包含摻雜材料。In addition, as shown in FIG. 37D, a second intermediate insulating
在重疊於導體提供部233a、233b的區域中,各個導體提供部233a、233b的摻雜濃度可高於第二閘極絕緣層150的摻雜濃度、第二中間絕緣層116的摻雜濃度以及第二緩衝層114的摻雜濃度。並且,在重疊於導體提供部233a、233b的區域中,第二緩衝層114的摻雜濃度可高於各個導體提供部233a、233b的摻雜濃度、第二閘極絕緣層150的摻雜濃度以及第二中間絕緣層116的摻雜濃度。In the region overlapping the
可藉由調整在摻雜製程中施加到摻雜物的加速電壓來調整各個第二中間絕緣層116、第二閘極絕緣層115、導體提供部233a、233b及第二緩衝層114的摻雜濃度。The doping of each of the second intermediate insulating
當增加施加到摻雜物的加速電壓增加以將摻雜物充分地摻雜於導體提供部233a、233b時,摻雜物可被摻雜於導體提供部233a、233b,且此外可被摻雜於第二緩衝層114。當用於摻雜的加速電壓增加到非預期的位準時,第二主動層230可能會受到損害。因此,根據本發明一實施例,可調整加速電壓而使得導體提供部233a、233b中的摻雜濃度為最大值或是第二緩衝層114的頂部中的摻雜濃度為最大值。When the accelerating voltage applied to the dopant is increased to sufficiently dope the
根據本發明一實施例,當導體提供部233a、233b中的摻雜濃度為最大值或是第二緩衝層114中的摻雜濃度為最大值時,可有效地在導體提供部233a、233b進行摻雜。並且,當導體提供部233a、233b中的摻雜濃度為最大值或是第二緩衝層114中的摻雜濃度為最大值時,可視為第二薄膜電晶體T2以有效的方式運作。According to an embodiment of the present invention, when the doping concentration in the
根據本發明一實施例,因為係在形成用於暴露第一主動層270及第二主動層230的接觸孔的製程以及透過接觸孔進行的高溫熱處理製程之後才進行摻雜摻雜物的製程,所以摻雜物可被摻雜於第二中間絕緣層116及第二閘極絕緣層115,其中第二中間絕緣層116及第二閘極絕緣層115形成於第二主動層230上。因此,當從形成於第二主動層230上的第二中間絕緣層116及第二閘極絕緣層115檢測到摻雜物時,可以表示已在高溫熱處理製程之後進行摻雜摻雜物的製程。According to an embodiment of the present invention, since the process of doping the dopant is performed after the process of forming the contact holes for exposing the first
請參閱圖37E,第二源極電極S2及第二汲極電極D2可形成於第二中間絕緣層116上且可透過多個接觸孔CH3、CH4連接於第二主動層230,其中接觸孔CH3、CH4形成於第二中間絕緣層116及第二閘極絕緣層115中。Referring to FIG. 37E, the second source electrode S2 and the second drain electrode D2 can be formed on the second intermediate insulating
請參閱圖36,鈍化層117可形成於第四薄膜電晶體T4的第四源極電極S4及第四汲極電極D4以及第二薄膜電晶體T2的第二源極電極S2及第二汲極電極D2上。Referring to FIG. 36 , the
可於鈍化層117中形成用於暴露第四薄膜電晶體T4的第四源極電極S4之接觸孔。然,本實施例並不以此為限,且可於鈍化層117中形成用於暴露第四薄膜電晶體T4之第四汲極電極D4的接觸孔。鈍化層117可為有機材料層。舉例來說,鈍化層117可由單層結構或雙層結構形成,其包含如壓克力樹脂(acryl resin)、環氧樹脂(epoxy resin)、酚樹脂(phenolic resin)、聚醯胺樹脂(polyamide resin)或聚醯亞胺樹脂(polyimide resin)之有機材料。於另一示例中,鈍化層117可由單層結構形成,包含如氮化矽(SiNx
)或氧化矽(SiOx
)之無機材料,或由上述之多層結構形成。或者,鈍化層117可由包含無機材料及有機材料的多層結構形成。A contact hole for exposing the fourth source electrode S4 of the fourth thin film transistor T4 may be formed in the
發光裝置710的像素電極711可設置於鈍化層117上。像素電極711可透過形成在鈍化層117中的接觸孔電性連接於第四薄膜電晶體T4。連接於像素電極711的第四薄膜電晶體T4可為將電流傳送至發光裝置710的驅動薄膜電晶體。The
像素電極711可形成為多層結構,此多層結構包含透明導體層及具有高反射率的不透明導體層。透明導體層可包含具有高功函數值的材料,如氧化銦錫(ITO)或氧化銦鋅(IZO)。並且,不透明導體層可由單層結構或多層結構形成,其包含鋁(Al)、銀(Ag)、銅(Cu)、鉛(Pb)、鉬(Mo)、鈦(Ti)或上述之合金。舉例來說,像素電極711可包含依序形成的透明導體層、不透明導體層以及透明導體層。然,本實施例並不以此為限,且舉例來說,像素電極711可包含依序形成的透明導體層及不透明導體層。The
根據本發明一實施例之顯示設備可為頂發光顯示設備,因此像素電極711可為陽極電極。當顯示設備為底發光類型時,設置於鈍化層117上的像素電極711可為陰極電極。The display device according to an embodiment of the present invention may be a top emission display device, and thus the
堤部層750可設置於像素電極711及鈍化層117上。可於堤部層750中形成用於暴露像素電極711的開口部。堤部層750可界定顯示設備的發光區域,而可稱為像素界定層。可於堤部層750上更設置隔件(spacer)。並且,可於像素電極711上更設置發光裝置710的發光層712。The
發光層712可包含電洞層(HL)、發光材料層(EML)及電子層(EL),且這些層體以上述次序或相反於上述次序之次序形成於像素電極711上。The light-emitting
此外,發光層712可包含第一發光層及第二發光層,且第一發光層及第二發光層之間有電荷產生層(CGL)。於此情況中,第一發光層及第二發光層其中一者可發出藍光,且第一發光層及第二發光層其中另一者可發出黃綠光,進而透過第一發光層及第二發光層發出白光。透過第一發光層及第二發光層發出的白光可入射在設置於發光層上的色彩濾波器以實施彩色的影像。於另一示例中,在沒有獨立的色彩濾波器之情況中,各個發光層可發出對應於各個子像素的彩色光以實施彩色影像。也就是說,紅色子像素的發光層可發出紅光,綠色子像素的發光層可發出綠光,且藍色子像素的發光層可發出藍光。In addition, the
請參閱圖36,發光裝置710的共用電極713可更設置於發光層712上。共用電極713可重疊於像素電極711,且發光層712位於共用電極713及像素電極711之間。於根據本發明一實施例之顯示設備中,共用電極713可為陰極電極。Referring to FIG. 36 , the
用於防止水滲入的封裝件可更設置於共用電極713上。封裝件可包含第一封裝層、第二封裝層及第三封裝層。第二封裝層包含的材料可不同於各個第一封裝層及第三封裝層包含的材料。舉例來說,各個第一封裝層及第三封裝層可為包含無機絕緣材料的無機絕緣層,而第二封裝層可為包含有機絕緣材料的有機絕緣層。封裝件的第一封裝層可設置於共用電極713上。並且,第二封裝層可設置於第一封裝層上。並且,第三封裝層可設置於第二封裝層上。A package for preventing water infiltration can be further disposed on the
封裝件的第一封裝層及第三封裝層可包含無機材料,如氮化矽(SiNx )或氧化矽(SiOx )。封裝件的第二封裝層可由單層結構或雙層結構形成,其包含如壓克力樹脂、環氧樹脂、酚樹脂、聚醯胺樹脂或聚醯亞胺樹脂之有機材料。The first encapsulation layer and the third encapsulation layer of the package may include inorganic materials such as silicon nitride (SiN x ) or silicon oxide (SiO x ). The second encapsulation layer of the package may be formed of a single-layer structure or a double-layer structure, which includes an organic material such as acrylic resin, epoxy resin, phenol resin, polyamide resin or polyimide resin.
圖38、圖39A及圖39B為根據本發明另一實施例之顯示設備的剖面示意圖及製程示意圖。以下,將省略或簡短描述與以上參照圖36以及圖37A至圖37C進行的描述相同或相似之描述。舉例來說,基板110、第一緩衝層111、第一閘極絕緣層112、第一中間絕緣層113、第二緩衝層114、第二閘極絕緣層115、第二中間絕緣層116、鈍化層117、堤部層750、發光裝置710、封裝件及第四薄膜電晶體T4的描述可依序相同於以上的描述。因此,圖38中與36中呈現的構造實質上相同的構造之重複性描述將被省略或簡化。並且,與於圖37A至圖37C中呈現的製程實質上相同的製程之描述將被省略或簡化。38 , 39A and 39B are a schematic cross-sectional view and a schematic view of a process of a display device according to another embodiment of the present invention. Hereinafter, the same or similar descriptions as those described above with reference to FIG. 36 and FIGS. 37A to 37C will be omitted or briefly described. For example, the
請參閱圖38,根據本發明另一實施例之顯示設備20可包含基板110、第一緩衝層111、第一閘極絕緣層112、第一中間絕緣層113、第二緩衝層114、第二閘極絕緣層115、第二中間絕緣層116、鈍化層117、堤部層750、發光裝置710、封裝件、第四薄膜電晶體T4、第二薄膜電晶體T2以及一金屬圖案80。Referring to FIG. 38, a
金屬圖案80可設置於第二中間絕緣層116上並可重疊於第二閘極電極G2。The
請參閱圖38及圖39A,各自暴露第二主動層230的第三接觸孔CH3及第四接觸孔CH4可形成於第二閘極絕緣層115及第二中間絕緣層116中。可為了在第二閘極絕緣層115及第二中間絕緣層116中形成第三接觸孔CH3及第四接觸孔CH4而進行乾蝕刻製程。並且,第二主動層230中由接觸孔CH3、CH4暴露的區域可透過形成第三接觸孔CH3及第四接觸孔CH4的乾蝕刻製程而具有傳導性。Referring to FIGS. 38 and 39A , the third contact hole CH3 and the fourth contact hole CH4 respectively exposing the second
此外,如圖38中所示,可藉由蝕刻第二中間絕緣層116、第二閘極絕緣層115、第二緩衝層114、第一中間絕緣層113及第一閘極絕緣層112來形成各自暴露第一主動層270的第一接觸孔CH1及第二接觸孔CH2。並且,在形成第一接觸孔CH1至第四接觸孔CH4之後,可為了將第一主動層270去氫化或是結晶而在350℃或更高的高溫進行高溫熱處理製程。並且,第二主動層230中透過乾蝕刻製程提供有傳導性的導體提供區域可透過高溫熱處理製程部分地擴散至其兩端。Furthermore, as shown in FIG. 38 , it may be formed by etching the second intermediate insulating
在熱處理製程之後,可形成第四源極電極S4、第四汲極電極D4、第二源極電極S2、第二汲極電極D2及金屬圖案80。After the heat treatment process, the fourth source electrode S4, the fourth drain electrode D4, the second source electrode S2, the second drain electrode D2 and the
請參閱圖39B,第二源極電極S2及第二汲極電極D2可透過形成於第二中間絕緣層116及第二閘極絕緣層115中的接觸孔CH3、CH4連接於第二主動層230。第二源極電極S2可透過第三接觸孔CH3連接於第二主動層230的第二源極區域230S。並且,第二汲極電極D2可透過第四接觸孔CH4連接於第二主動層230的第二汲極區域230D。並且,金屬圖案80可設置於第二中間絕緣層116上且可重疊於第二閘極電極G2。並且,相對於剖面示意圖來說,金屬圖案80的寬度可大於第二閘極電極G2的寬度。相對於平面圖來說,金屬圖案80的面積可大於第二閘極電極G2的面積。舉例來說,第二閘極電極G2可設置於由金屬圖案80所界定的區域中。Referring to FIG. 39B , the second source electrode S2 and the second drain electrode D2 can be connected to the second
如圖39B所示,可進行使用摻雜物的摻雜製程。因為金屬圖案80的緣故,摻雜物可不被摻雜於第二通道區域230C。因此,第二通道區域230C可維持半導體特性。As shown in Figure 39B, a doping process using dopants can be performed. Due to the
透過使用摻雜物的摻雜製程提供有傳導性的多個導體提供部233a、233b可具有高於第二通道區域230C之摻雜濃度的摻雜濃度,且可具有低於第二通道區域230C的電阻率之電阻率。The plurality of
請參閱圖39B,多個偏差部(如第一及第二偏差部)232a、232b可受金屬圖案80保護。因此,可防止摻雜物直接植入到偏差部232a、232b中。然,摻雜於導體提供部233a、233b的摻雜物可能會擴散至偏差部232a、232b。因此,可得到摻雜物部分地被摻雜於偏差部232a、232b的效果。Referring to FIG. 39B , a plurality of offset parts (eg, the first and second offset parts) 232 a and 232 b can be protected by the
於圖39B中,當第二閘極電極G2具有寬度LG且金屬圖案80具有從第二閘極電極G2凸出的寬度Loh時,可在滿足以下方程式2的條件下進行摻雜。In FIG. 39B, when the second gate electrode G2 has a width LG and the
[方程式2][Equation 2]
LG x Loh x 1/η2 ≥ 1LG x Loh x 1/η2 ≥ 1
其中η2 = 0.5平方微米where η2 = 0.5 square microns
各個第一偏差部232a及第二偏差部232b的寬度可對應於凸出的寬度Loh。當第二閘極電極G2的寬度LG以及凸出的寬度Loh滿足方程式2時,可形成滿足方程式2的偏差部232a、232b。The width of each of the
根據本發明另一實施例,在方程式2中,η2為1.5平方微米。或者,η2可滿足以下關係式:0.5平方微米 ≤ η2 ≤ 1.5平方微米。According to another embodiment of the present invention, in
在這些導體提供部233a、233b中摻雜物的濃度可為最高的。這些偏差部232a、232b的摻雜濃度可低於各個導體提供部233a、233b的摻雜濃度。少量的摻雜物可能會擴散至沒有直接摻雜有摻雜物的第二通道區域230C。第二通道區域230C可幾乎沒有包含摻雜物,或可具有非常低濃度的摻雜物。The concentration of the dopant may be highest in these
偏差部232a、232b可在從第二通道區域230C到導體提供部233a、233b的方向中具有增加的摻雜物濃度梯度。舉例來說,第一偏差部232a可在從第二通道區域230C到第一導體提供部233a的方向中具有增加的摻雜物濃度梯度,且第二偏差部232b可在從第二通道區域230C到第二導體提供部233b的方向中具有增加的摻雜物濃度梯度。The
此外,各個偏差部232a、232b的電阻率可低於第二通道區域230C的電阻率,且可高於各個導體提供部233a、233b的電阻率。偏差部232a、232b可在從第二通道區域230C到導體提供部233a、233b的方向中具有減小的電阻率梯度。In addition, the resistivity of the
因此,偏差部232a、232b可在導體提供部233a、233b以及沒有提供傳導性的第二通道區域230C之間執行電性緩衝的功能。Therefore, the offset
詳細來說,因為偏差部232a、232b設置於第二通道區域230C及導體提供部233a、233b之間,所以可防止漏電流在第二薄膜電晶體T2的關閉(OFF)狀態中流動於第二通道區域230C及導體提供部233a、233b之間。如上所述,偏差部232a、232b可防止漏電流在第二薄膜電晶體T2處於關閉(OFF)狀態的時候產生於第二薄膜電晶體T2中。In detail, since the
當第二薄膜電晶體T2根據施加至第二閘極電極G2的閘極電壓而被開啟時,可增加第二通道區域230C的導電度,但各個偏差部232a、232b的導電度可不大幅地增加,其中各個偏差部232a、232b的導電度不會被產生於第二閘極電極G2中的電場大幅度地影響。因此,當第二薄膜電晶體T2被開啟時,各個偏差部232a、232b的傳導性可低於第二通道區域230C的傳導性以及各個導體提供部233a、233b的傳導性。因此,可藉由偏差部232a、232b防止第二薄膜電晶體T2的臨界電壓發生偏移。因此,可提升第二薄膜電晶體T2的電性穩定度。When the second thin film transistor T2 is turned on according to the gate voltage applied to the second gate electrode G2, the conductivity of the
此外,如圖39B所示,第二中間絕緣層116可形成於第二閘極電極G2上,且接著可進行摻雜摻雜物的摻雜製程。因此,摻雜物可被摻雜於第二中間絕緣層116及第二閘極絕緣層115。因此,第二中間絕緣層116及第二閘極絕緣層115中重疊於第二主動層230的導體提供部233a、233b的區域可包含摻雜物。摻雜物可包含硼(B)、磷(P)、氟(F)及氫(H)其中至少一者。因此,第二中間絕緣層116及第二閘極絕緣層115可包含硼(B)、磷(P)、氟(F)及氫(H)其中至少一者。並且,第二閘極絕緣層115中重疊於第二閘極電極G2的區域可不包含摻雜物材料。並且,第二中間絕緣層116中重疊於金屬圖案80及第二閘極電極G2的區域可不包含摻雜物材料。In addition, as shown in FIG. 39B, a second intermediate insulating
根據本發明一實施例,因為係在形成用於暴露第一主動層270及第二主動層230的接觸孔的製程以及透過接觸孔進行的高溫熱處理製程之後才進行摻雜摻雜物的製程,所以摻雜物可被摻雜於第二中間絕緣層116及第二閘極絕緣層115,其中第二中間絕緣層116及第二閘極絕緣層115形成於第二主動層230上。因此,當從形成於第二主動層230上的第二中間絕緣層116及第二閘極絕緣層115檢測到摻雜物時,可以表示已在高溫熱處理製程之後進行摻雜摻雜物的製程。According to an embodiment of the present invention, since the process of doping the dopant is performed after the process of forming the contact holes for exposing the first
根據本發明一實施例之薄膜電晶體包含一主動層、一閘極電極以及一閘極絕緣層。主動層位於一基板上。閘極電極分離於主動層以至少部分地重疊於主動層。閘極絕緣層位於主動層及閘極電極之間。閘極絕緣層覆蓋面對閘極電極的主動層的整個頂面。主動層包含一通道部、一導體提供部以及一偏差部。通道部重疊於閘極電極。導體提供部不重疊於閘極電極。偏差部位於通道部及導體提供部之間。偏差部不重疊於閘極電極。導體提供部摻雜有一摻雜物。A thin film transistor according to an embodiment of the present invention includes an active layer, a gate electrode, and a gate insulating layer. The active layer is located on a substrate. The gate electrode is separated from the active layer to at least partially overlap the active layer. The gate insulating layer is located between the active layer and the gate electrode. The gate insulating layer covers the entire top surface of the active layer facing the gate electrode. The active layer includes a channel part, a conductor supply part and a deviation part. The channel portion overlaps the gate electrode. The conductor supply portion does not overlap the gate electrode. The offset portion is located between the channel portion and the conductor providing portion. The offset portion does not overlap the gate electrode. The conductor supply portion is doped with a dopant.
根據本發明一實施例,當通道部的寬度為L1且偏差部的寬度為L2時,薄膜電晶體滿足以下的方程式1,According to an embodiment of the present invention, when the width of the channel portion is L1 and the width of the offset portion is L2, the thin film transistor satisfies the
[方程式1][Equation 1]
L1 x L2 x 1/η1 ≥ 1L1 x L2 x 1/η1 ≥ 1
其中η1為0.5平方微米。where η1 is 0.5 square microns.
根據本發明一實施例,主動層包含一氧化物半導體材料。According to an embodiment of the present invention, the active layer includes an oxide semiconductor material.
根據本發明一實施例,摻雜物包含硼、磷、氟及氫其中至少一者。According to an embodiment of the present invention, the dopant includes at least one of boron, phosphorus, fluorine and hydrogen.
根據本發明一實施例,偏差部在從通道部到導體提供部的方向中具有增加的摻雜物濃度梯度。According to an embodiment of the invention, the deviation portion has an increasing dopant concentration gradient in the direction from the channel portion to the conductor providing portion.
根據本發明一實施例,偏差部的電阻率低於通道部的電阻率並高於導體提供部的電阻率。According to an embodiment of the present invention, the resistivity of the deviation portion is lower than that of the channel portion and higher than that of the conductor providing portion.
根據本發明一實施例,偏差部的寬度為0.25微米或更大。According to an embodiment of the present invention, the width of the deviation portion is 0.25 micrometers or more.
根據本發明一實施例,通道部的寬度為2微米或更大。According to an embodiment of the present invention, the width of the channel portion is 2 micrometers or more.
根據本發明一實施例,薄膜電晶體更包含一緩衝層。緩衝層設置於基板及主動層之間。摻雜物被摻雜於緩衝層。According to an embodiment of the present invention, the thin film transistor further includes a buffer layer. The buffer layer is disposed between the substrate and the active layer. Dopants are doped into the buffer layer.
根據本發明一實施例,在重疊於導體提供部的區域中,導體提供部的摻雜濃度高於閘極絕緣層的摻雜濃度以及緩衝層的摻雜濃度。According to an embodiment of the present invention, in the region overlapping the conductor providing portion, the doping concentration of the conductor providing portion is higher than the doping concentration of the gate insulating layer and the doping concentration of the buffer layer.
根據本發明一實施例,在重疊於導體提供部的區域中,緩衝層的摻雜濃度高於導體提供部的摻雜濃度以及閘極絕緣層的摻雜濃度。According to an embodiment of the present invention, in the region overlapping the conductor providing portion, the doping concentration of the buffer layer is higher than the doping concentration of the conductor providing portion and the doping concentration of the gate insulating layer.
根據本發明一實施例,主動層更包含一第一氧化物半導體層以及一第二氧化物半導體層。第一氧化物半導體層位於基板上。。第二氧化物半導體層位於第一氧化物半導體層上。According to an embodiment of the present invention, the active layer further includes a first oxide semiconductor layer and a second oxide semiconductor layer. The first oxide semiconductor layer is on the substrate. . The second oxide semiconductor layer is on the first oxide semiconductor layer.
根據本發明一實施例,薄膜電晶體更包含一源極電極以及一汲極電極。源極電極及汲極電極彼此分離並連接於主動層。According to an embodiment of the present invention, the thin film transistor further includes a source electrode and a drain electrode. The source electrode and the drain electrode are separated from each other and connected to the active layer.
根據本發明一實施例,源極電極及汲極電極與閘極電極設置在相同的層體,且與閘極電極包含相同的材料。According to an embodiment of the present invention, the source electrode, the drain electrode and the gate electrode are disposed in the same layer body, and comprise the same material as the gate electrode.
根據本發明另一實施例之薄膜電晶體基板包含一基座基板、一第一薄膜電晶體以及一第二薄膜電晶體。第一薄膜電晶體以及第二薄膜電晶體位於基座基板上。第一薄膜電晶體包含一第一主動層及一第一閘極電極。第一主動層位於基座基板上。第一閘極電極分離於第一主動層以至少部分地重疊於第一主動層。第二薄膜電晶體包含一第二主動層、一閘極電極以及一閘極絕緣層。第二主動層位於基座基板上。閘極電極分離於第二主動層以至少部分地重疊於第二主動層。閘極絕緣層位於第二主動層及第二閘極電極之間。閘極絕緣層可覆蓋面對第二閘極電極的第二主動層的整個頂面。此外,第二主動層包含一通道部、一導體提供部以及一偏差部。通道部重疊於第二閘極電極。導體提供部不重疊於第二閘極電極。偏差部位於通道部及導體提供部之間。偏差部不重疊於第二閘極電極。導體提供部摻雜有一摻雜物。第一主動層及第二主動層可設置於不同的層體上。A thin film transistor substrate according to another embodiment of the present invention includes a base substrate, a first thin film transistor, and a second thin film transistor. The first thin film transistor and the second thin film transistor are located on the base substrate. The first thin film transistor includes a first active layer and a first gate electrode. The first active layer is on the base substrate. The first gate electrode is separated from the first active layer to at least partially overlap the first active layer. The second thin film transistor includes a second active layer, a gate electrode and a gate insulating layer. The second active layer is on the base substrate. The gate electrode is separated from the second active layer to at least partially overlap the second active layer. The gate insulating layer is located between the second active layer and the second gate electrode. The gate insulating layer may cover the entire top surface of the second active layer facing the second gate electrode. In addition, the second active layer includes a channel portion, a conductor providing portion, and an offset portion. The channel portion overlaps the second gate electrode. The conductor supply portion does not overlap the second gate electrode. The offset portion is located between the channel portion and the conductor providing portion. The offset portion does not overlap the second gate electrode. The conductor supply portion is doped with a dopant. The first active layer and the second active layer can be disposed on different layers.
根據本發明另一實施例,第一主動層為矽半導體層,且第二主動層為氧化物半導體層。According to another embodiment of the present invention, the first active layer is a silicon semiconductor layer, and the second active layer is an oxide semiconductor layer.
製造一薄膜電晶體的方法包含在一基板上形成一主動層、在主動層上形成一閘極絕緣層、在閘極絕緣層上形成一閘極電極以至少部分地重疊於主動層,以及在主動層摻雜一摻雜物。閘極絕緣層覆蓋面對閘極電極的主動層的整個頂面。形成閘極電極的步驟包含在閘極絕緣層上形成一閘極電極材料層、在閘極電極材料層上形成一光阻圖案、藉由使用光阻圖案作為遮罩來蝕刻閘極電極材料層。光阻圖案的面積大於閘極電極的面積。在平面視角中,閘極電極設置於由光阻圖案界定的區域中。在主動層上摻雜摻雜物的步驟中使用光阻圖案作為遮罩。A method of fabricating a thin film transistor includes forming an active layer on a substrate, forming a gate insulating layer on the active layer, forming a gate electrode on the gate insulating layer to at least partially overlap the active layer, and The active layer is doped with a dopant. The gate insulating layer covers the entire top surface of the active layer facing the gate electrode. The step of forming the gate electrode includes forming a gate electrode material layer on the gate insulating layer, forming a photoresist pattern on the gate electrode material layer, and etching the gate electrode material layer by using the photoresist pattern as a mask . The area of the photoresist pattern is larger than that of the gate electrode. In a plan view, the gate electrode is disposed in the area defined by the photoresist pattern. The photoresist pattern is used as a mask in the step of doping the dopant on the active layer.
根據本發明另一實施例,摻雜物包含硼、磷、氟及氫其中至少一者。According to another embodiment of the present invention, the dopant includes at least one of boron, phosphorus, fluorine and hydrogen.
根據本發明另一實施例,當閘極電極的寬度為LG且光阻圖案從閘極電極凸出的寬度為Loh時,此方法滿足下列方程式2,According to another embodiment of the present invention, when the width of the gate electrode is LG and the width of the photoresist pattern protruding from the gate electrode is Loh, the method satisfies the
[方程式2][Equation 2]
LG x Loh x 1/η2 ≥ 1LG x Loh x 1/η2 ≥ 1
其中η2為0.5平方微米。where η2 is 0.5 square microns.
根據本發明另一實施例之顯示設備包含一基板、一像素驅動電路以及一發光裝置。像素驅動電路位於基板上。發光裝置連接於像素驅動電路。像素驅動電路包含一薄膜電晶體。薄膜電晶體包含一主動層、一閘極電極以及一閘極絕緣層。主動層位於基板上。閘極電極分離於主動層以至少部分地重疊於主動層。閘極絕緣層位於主動層及閘極電極之間。閘極絕緣層覆蓋面對閘極電極的主動層的整個頂面。主動層包含一通道部、一導體提供部以及一偏差部。通道部重疊於閘極電極。導體提供部不重疊於閘極電極。偏差部位於通道部及導體提供部之間。偏差部不重疊於閘極電極。導體提供部摻雜有一摻雜物。A display apparatus according to another embodiment of the present invention includes a substrate, a pixel driving circuit, and a light emitting device. The pixel driving circuit is located on the substrate. The light-emitting device is connected to the pixel driving circuit. The pixel driving circuit includes a thin film transistor. The thin film transistor includes an active layer, a gate electrode and a gate insulating layer. The active layer is on the substrate. The gate electrode is separated from the active layer to at least partially overlap the active layer. The gate insulating layer is located between the active layer and the gate electrode. The gate insulating layer covers the entire top surface of the active layer facing the gate electrode. The active layer includes a channel part, a conductor supply part and a deviation part. The channel portion overlaps the gate electrode. The conductor supply portion does not overlap the gate electrode. The offset portion is located between the channel portion and the conductor providing portion. The offset portion does not overlap the gate electrode. The conductor supply portion is doped with a dopant.
根據本發明另一實施例之顯示設備包含一第一薄膜電晶體、一第一中間絕緣層、一第二薄膜電晶體以及一第二中間絕緣層。第一薄膜電晶體包含一第一主動層、一第一閘極電極、一第一閘極絕緣層、一第一源極電極及一第一汲極電極。第一主動層包含多晶矽。第一閘極電極重疊於第一主動層。第一閘極絕緣層位於第一主動層及第一閘極電極之間。第一源極電極及第一汲極電極各自連接於第一主動層。第一中間絕緣層設置於第一閘極電極上。第二薄膜電晶體包含一第二主動層、一第二閘極電極、一第二閘極絕緣層、一第二源極電極及一第二汲極電極。第二主動層包含氧化物半導體。第二閘極電極重疊於第二主動層。第二閘極絕緣層位於第二主動層及第二閘極電極之間。第二源極電極及第二汲極電極各自連接於第二主動層。第二中間絕緣層設置於第一閘極電極、第二閘極電極及第二閘極絕緣層上。第二閘極絕緣層及第二中間絕緣層包含用於摻雜第二主動層的一摻雜物。A display device according to another embodiment of the present invention includes a first thin film transistor, a first intermediate insulating layer, a second thin film transistor, and a second intermediate insulating layer. The first thin film transistor includes a first active layer, a first gate electrode, a first gate insulating layer, a first source electrode and a first drain electrode. The first active layer includes polysilicon. The first gate electrode overlaps the first active layer. The first gate insulating layer is located between the first active layer and the first gate electrode. The first source electrode and the first drain electrode are respectively connected to the first active layer. The first intermediate insulating layer is disposed on the first gate electrode. The second thin film transistor includes a second active layer, a second gate electrode, a second gate insulating layer, a second source electrode and a second drain electrode. The second active layer includes an oxide semiconductor. The second gate electrode overlaps the second active layer. The second gate insulating layer is located between the second active layer and the second gate electrode. The second source electrode and the second drain electrode are respectively connected to the second active layer. The second intermediate insulating layer is disposed on the first gate electrode, the second gate electrode and the second gate insulating layer. The second gate insulating layer and the second intermediate insulating layer include a dopant for doping the second active layer.
根據本發明另一實施例,摻雜於第二主動層的摻雜物包含硼、磷、氟及氫其中至少一者。According to another embodiment of the present invention, the dopant doped in the second active layer includes at least one of boron, phosphorus, fluorine and hydrogen.
根據本發明另一實施例,第二主動層包含一第二通道區域、一第二源極區域以及一第二汲極區域。第二通道區域重疊於第二閘極電極。第二源極區域設置於第二通道區域的一側並連接於第二源極電極。第二汲極區域設置於第二通道區域的另一側並連接於第二汲極電極。According to another embodiment of the present invention, the second active layer includes a second channel region, a second source region and a second drain region. The second channel region overlaps the second gate electrode. The second source region is disposed on one side of the second channel region and connected to the second source electrode. The second drain region is disposed on the other side of the second channel region and connected to the second drain electrode.
根據本發明另一實施例,第二源極區域包含一第一導體提供部及一第一偏差部。第一導體提供部設置於第二通道區域的那側。第一偏差部設置於第一導體提供部及第二通道區域的那側之間。第二汲極區域包含一第二導體提供部以及一第二偏差部。第二導體提供部設置於第二通道區域的另一側。第二偏差部設置於第二導體提供部及第二通道區域的另一側之間。According to another embodiment of the present invention, the second source region includes a first conductor providing portion and a first offset portion. The first conductor providing portion is provided on the side of the second channel region. The first deviation portion is disposed between the first conductor providing portion and the side of the second channel region. The second drain region includes a second conductor providing portion and a second offset portion. The second conductor providing portion is disposed on the other side of the second channel region. The second deviation portion is disposed between the second conductor providing portion and the other side of the second channel region.
根據本發明另一實施例,第一導體提供部、第二導體提供部、第一偏差部及第二偏差部包含摻雜物。According to another embodiment of the present invention, the first conductor providing portion, the second conductor providing portion, the first offset portion, and the second offset portion include dopants.
根據本發明另一實施例,各個第一導體提供部及第二導體提供部的摻雜物之濃度高於各個第一偏差部及第二偏差部的摻雜物之濃度。According to another embodiment of the present invention, the concentration of the dopant in each of the first conductor supply portion and the second conductor supply portion is higher than the concentration of the dopant in each of the first deviation portion and the second deviation portion.
根據本發明一實施例,可使用光阻圖案作為遮罩而在不圖案化閘極絕緣層的情況下透過摻雜製程在半導體層的導體提供部及通道部之間形成偏差部,並可基於偏差部確保薄膜電晶體的有效通道寬度。According to an embodiment of the present invention, the photoresist pattern can be used as a mask to form a deviation portion between the conductor supply portion and the channel portion of the semiconductor layer through a doping process without patterning the gate insulating layer, and the deviation portion can be formed based on the The offset portion ensures the effective channel width of the thin film transistor.
根據本發明另一實施例,因為薄膜電晶體的主動層包含偏差部,所以可確保導體提供區域及通道層的電性穩定度,且可使主動層上的絕緣層之影響最小化,進而確保薄膜電晶體的驅動穩定度。According to another embodiment of the present invention, since the active layer of the thin film transistor includes the deviation portion, the electrical stability of the conductor providing region and the channel layer can be ensured, and the influence of the insulating layer on the active layer can be minimized, thereby ensuring The driving stability of thin film transistors.
根據本發明另一實施例,可輕易確保薄膜電晶體的有效通道寬度,且可製造具有小尺寸的薄膜電晶體。薄膜電晶體可被整合及提供到各種電子產品中,且可藉由使用薄膜電晶體製造出高解析度的顯示設備。According to another embodiment of the present invention, the effective channel width of the thin film transistor can be easily ensured, and the thin film transistor with a small size can be manufactured. Thin film transistors can be integrated and provided in various electronic products, and high-resolution display devices can be fabricated by using thin film transistors.
本發明上述之特徵、結構及效果包含於本發明的至少一實施例中,但不限於僅一個實施例中。此外,在本發明的至少一實施例中描述的特徵、結構及效果可由熟悉本技藝者透過結合或修改其他實施例而實施。因此,相關於這種結合及修改的內容應被解釋為屬於本發明的範疇。The above-mentioned features, structures and effects of the present invention are included in at least one embodiment of the present invention, but are not limited to only one embodiment. Furthermore, the features, structures, and effects described in at least one embodiment of the present invention can be implemented by those skilled in the art by combining or modifying other embodiments. Therefore, contents related to such combination and modification should be construed as belonging to the scope of the present invention.
對熟悉本技藝者顯而易見的是,可在不脫離本發明的範圍或精神下對本發明進行各種修改及變化。因此,在這些修改及變化源自請求項的範圍或其均等範圍時,本發明應涵蓋這些修改及變化。It will be apparent to those skilled in the art that various modifications and variations can be made in the present invention without departing from the scope or spirit of the inventions. Accordingly, the present invention shall cover such modifications and variations as they fall within the scope of the claims or their equivalents.
10、20:顯示設備 100、200、300、400、500:薄膜電晶體 600:薄膜電晶體基板 110:基板 111:緩衝層 112:閘極絕緣層 113:中間絕緣層 114:緩衝層 115:閘極絕緣層 116:中間絕緣層 117:鈍化層 120:緩衝層 121:遮光層 130:主動層 130a:氧化物半導體層 130b:氧化物半導體層 131:通道部 132a、132b:偏差部 133a、133b:導體提供部 140:閘極電極 145:閘極電極材料層 150:閘極絕緣層 150a:閘極絕緣層 155:中間絕緣層 161:源極電極 162:汲極電極 181:閘極絕緣層 182:鈍化層 185:中間層 192:平坦化層 210:基座基板 230:主動層 230C:通道區域 230S:源極區域 230D:汲極區域 231:通道部 232a、232b:偏差部 233a、233b:導體提供部 240:閘極電極 261:源極電極 262:汲極電極 270:主動層 270C:通道區域 270S:源極區域 270D:汲極區域 271:通道部 272、273:導體提供部 280:閘極電極 281:源極電極 282:汲極電極 40、41、42、45、50、60、61、62、63:光阻圖案 70:摻雜遮罩圖案 80:金屬圖案 310:顯示面板 320:閘極驅動器 330:資料驅動器 340:控制器 350:偏移記錄器 700:顯示設備 710:發光裝置 711:像素電極 712:發光層 713:共用電極 750:堤部層 800、900:顯示設備 TR1、TR2:薄膜電晶體 L1、L2、LG、Loh:寬度 ∆L:導體提供穿設深度 Lideal :寬度 Leff :有效通道寬度 MR1、MR2:金屬殘留材料 H1、H2、CH1、CH2、CH3、CH4:接觸孔 GL:閘極線路 DL:資料線路 P:像素 PDC:像素驅動電路 GCS:閘極控制訊號 DCS:資料控制訊號 RGB:影像資料 T1、T2、T3、T4、T5、T6、T7:薄膜電晶體 C1、C2:電容器 Scan1、Scan2:掃描訊號 Vdata:資料電壓 D1:汲極電極 G1:閘極電極 S1:源極電極 D2:汲極電極 G2:閘極電極 S2:源極電極 D4:汲極電極 G4:閘極電極 S4:源極電極 EM:發光控制訊號 EL:發光控制線路 VDD:像素驅動電壓 Vini:初始化電壓 VSS:驅動電壓 CE1、CE2:電極 A1、A2、A4:通道部 PL:像素驅動電壓線路 ICL:初始化控制線路 IL:初始化電壓線路 SS:掃描訊號 ICS:初始化控制訊號 n1、n2:節點 OP1、OP2:開口部10, 20: Display device 100, 200, 300, 400, 500: Thin film transistor 600: Thin film transistor substrate 110: Substrate 111: Buffer layer 112: Gate insulating layer 113: Intermediate insulating layer 114: Buffer layer 115: Gate Polar insulating layer 116: Intermediate insulating layer 117: Passivation layer 120: Buffer layer 121: Light shielding layer 130: Active layer 130a: Oxide semiconductor layer 130b: Oxide semiconductor layer 131: Channel parts 132a, 132b: Deviation parts 133a, 133b: Conductor supply part 140: gate electrode 145: gate electrode material layer 150: gate insulating layer 150a: gate insulating layer 155: intermediate insulating layer 161: source electrode 162: drain electrode 181: gate insulating layer 182: Passivation layer 185: Intermediate layer 192: Planarization layer 210: Base substrate 230: Active layer 230C: Channel region 230S: Source region 230D: Drain region 231: Channel portion 232a, 232b: Deviation portion 233a, 233b: Conductor supply Section 240: Gate electrode 261: Source electrode 262: Drain electrode 270: Active layer 270C: Channel region 270S: Source region 270D: Drain region 271: Channel sections 272, 273: Conductor supply section 280: Gate electrode 281: Source electrode 282: Drain electrode 40, 41, 42, 45, 50, 60, 61, 62, 63: Photoresist pattern 70: Doping mask pattern 80: Metal pattern 310: Display panel 320: Gate Driver 330: Data driver 340: Controller 350: Offset recorder 700: Display device 710: Light-emitting device 711: Pixel electrode 712: Light-emitting layer 713: Common electrode 750: Bank layer 800, 900: Display device TR1, TR2: Thin film transistors L1, L2, LG, Loh: width ∆L: conductor provided penetration depth L ideal : width L eff : effective channel width MR1, MR2: metal residual material H1, H2, CH1, CH2, CH3, CH4: contact Hole GL: Gate Line DL: Data Line P: Pixel PDC: Pixel Driving Circuit GCS: Gate Control Signal DCS: Data Control Signal RGB: Image Data T1, T2, T3, T4, T5, T6, T7: Thin Film Transistor C1, C2: Capacitors Scan1, Scan2: Scan signal Vdata: Data voltage D1: Drain electrode G1: Gate electrode S1: Source electrode D2: Drain electrode G2: Gate electrode S2: Source electrode D4: Drain electrode G4: gate electrode S4: source electrode EM: light emission control signal EL: light emission control line VDD: pixel driving voltage Vini: initialization voltage VSS: driving voltage CE1, CE2: electrodes A1, A2, A4: channel part PL: pixel driving Voltage line ICL: Initialization control line IL: Initialization voltage line SS: Scanning signal IC S: Initialization control signal n1, n2: Node OP1, OP2: Opening
附圖用於提供本發明更進一步的理解並併入且構成本申請之一部分,本發明所繪示的實施例及描述係用於解釋本發明的原理。於附圖中: 圖1為根據本發明一實施例的薄膜電晶體之剖面示意圖。 圖2為根據本發明另一實施例之薄膜電晶體之剖面示意圖。 圖3為根據本發明另一實施例的薄膜電晶體之剖面示意圖。 圖4為根據本發明另一實施例的薄膜電晶體之剖面示意圖。 圖5為根據本發明另一實施例的薄膜電晶體之剖面示意圖。 圖6為根據本發明另一實施例之薄膜電晶體基板的剖面示意圖。 圖7為描述根據本發明一實施例的摻雜方法之圖式。 圖8為呈現根據本發明一實施例的主動層之區域取向摻雜物分佈情形之圖式。 圖9為呈現根據本發明一實施例之主動層的區域取向摻雜物之濃度的圖式。 圖10為呈現根據本發明一實施例之主動層的區域取向電阻率的程度之圖式。 圖11為根據本發明一實施例呈現在薄膜電晶體的開啟狀態中之半導體層的區域取向導電度分佈情形之圖式。 圖12為根據本發明一實施例呈現在重疊於導體提供部的區域中基於深度的元素的濃度之圖式。 圖13為根據本發明一實施例呈現重疊於導體提供部的區域中基於深度的元素的濃度之圖式。 圖14A及圖14B為根據比較示例的導體提供方法之圖式。 圖15為根據比較示例描述導體提供穿設深度∆L之示意圖。 圖16為根據比較示例及本發明一實施例之薄膜電晶體的總導體提供穿設深度2∆L之圖表。 圖17A至圖17E為根據比較示例及本發明一實施例之薄膜電晶體的臨界電壓圖表。 圖18為根據比較示例及本發明一實施例之薄膜電晶體的臨界電壓相對熱處理時間之圖表。 圖19為根據比較示例及本發明一實施例之薄膜電晶體的移動率相對熱處理時間的圖表。 圖20為根據比較示例及本發明一實施例之薄膜電晶體的電阻率量測圖表。 圖21為根據比較示例及本發明一實施例之移動率相對主動層中植入的離子量之圖表。 圖22A至圖22C為根據比較示例及本發明一實施例之薄膜電晶體的臨界電壓相對通道部的寬度之圖表。 圖23為呈現根據比較示例及本發明一實施例之薄膜電晶體的臨界電壓值相對通道部的寬度之圖表。 圖24為根據比較示例及本發明一實施例之臨界電壓相對閘極電極的寬度之圖表。 圖25為呈現根據本發明一實施例之閘極電極附近產生的縫隙及金屬殘留層之圖式。 圖26為呈現根據本發明一實施例之閘極電極附近沒有產生縫隙或金屬殘留層之態樣的圖式。 圖27A至圖27G為根據本發明一實施例之薄膜電晶體的製造方法之製程示意圖。 圖28A至圖28G為根據本發明另一實施例之薄膜電晶體的製造方法的製程示意圖。 圖29為呈現根據本發明另一實施例的顯示設備之圖式。 圖30為圖29中的一個像素的電路圖。 圖31為圖30中的像素之平面圖。 圖32為沿圖31中的割面線I-I'繪示的剖面示意圖。 圖33A至圖33C為根據本發明另一實施例之薄膜電晶體的製造方法的製程示意圖。 圖34為根據本發明另一實施例之顯示設備的一個像素之電路圖。 圖35為根據本發明另一實施例之顯示設備的一個像素之電路圖。 圖36為根據本發明另一實施例的顯示設備之剖面示意圖。 圖37A至圖37E為設置在圖36中的區域B中的薄膜電晶體之製造方法的製程示意圖。 圖38為根據本發明另一實施例之顯示設備的剖面示意圖。 圖39A及圖39B為設置在圖38中的區域B中的薄膜電晶體之製造方法的製程示意圖。The accompanying drawings are used to provide a further understanding of the invention and are incorporated in and constitute a part of this application, and the illustrated embodiments and description of the invention are intended to explain the principles of the invention. In the attached image: FIG. 1 is a schematic cross-sectional view of a thin film transistor according to an embodiment of the present invention. 2 is a schematic cross-sectional view of a thin film transistor according to another embodiment of the present invention. 3 is a schematic cross-sectional view of a thin film transistor according to another embodiment of the present invention. 4 is a schematic cross-sectional view of a thin film transistor according to another embodiment of the present invention. 5 is a schematic cross-sectional view of a thin film transistor according to another embodiment of the present invention. 6 is a schematic cross-sectional view of a thin film transistor substrate according to another embodiment of the present invention. FIG. 7 is a diagram illustrating a doping method according to an embodiment of the present invention. FIG. 8 is a diagram showing the distribution of area-oriented dopants of the active layer according to an embodiment of the present invention. 9 is a graph presenting the concentration of the area orientation dopant of the active layer according to one embodiment of the present invention. FIG. 10 is a graph presenting the extent of the area orientation resistivity of an active layer according to an embodiment of the present invention. FIG. 11 is a graph showing the area-oriented conductivity distribution of the semiconductor layer in the on-state of the thin film transistor according to an embodiment of the present invention. 12 is a graph presenting the concentration of depth-based elements in a region overlapping a conductor provider according to an embodiment of the present invention. FIG. 13 is a graph presenting the concentration of depth-based elements in a region that overlaps a conductor provider, according to an embodiment of the present invention. 14A and 14B are diagrams of a conductor providing method according to a comparative example. FIG. 15 is a schematic diagram illustrating a conductor providing penetration depth ΔL according to a comparative example. FIG. 16 is a graph of providing a penetration depth 2ΔL for the overall conductor of a thin film transistor according to a comparative example and an embodiment of the present invention. 17A-17E are graphs of threshold voltages of thin film transistors according to a comparative example and an embodiment of the present invention. 18 is a graph of threshold voltage versus heat treatment time for thin film transistors according to a comparative example and an embodiment of the present invention. 19 is a graph of mobility versus heat treatment time for thin film transistors according to a comparative example and an embodiment of the present invention. FIG. 20 is a resistivity measurement chart of a thin film transistor according to a comparative example and an embodiment of the present invention. 21 is a graph of mobility versus the amount of ions implanted in the active layer according to a comparative example and an embodiment of the present invention. 22A to 22C are graphs of threshold voltage versus channel width of thin film transistors according to a comparative example and an embodiment of the present invention. 23 is a graph showing threshold voltage values versus channel widths for thin film transistors according to a comparative example and an embodiment of the present invention. 24 is a graph of threshold voltage versus gate electrode width according to a comparative example and an embodiment of the present invention. FIG. 25 is a diagram showing a gap and a metal residual layer created near the gate electrode according to an embodiment of the present invention. FIG. 26 is a diagram showing a state in which no gap or metal residual layer is generated near the gate electrode according to an embodiment of the present invention. 27A to 27G are schematic diagrams of the manufacturing process of a method for manufacturing a thin film transistor according to an embodiment of the present invention. 28A to 28G are schematic process diagrams of a manufacturing method of a thin film transistor according to another embodiment of the present invention. FIG. 29 is a diagram showing a display device according to another embodiment of the present invention. FIG. 30 is a circuit diagram of one pixel in FIG. 29 . FIG. 31 is a plan view of the pixel in FIG. 30 . FIG. 32 is a schematic cross-sectional view along the secant line II′ in FIG. 31 . 33A to 33C are schematic process diagrams of a method for manufacturing a thin film transistor according to another embodiment of the present invention. 34 is a circuit diagram of one pixel of a display device according to another embodiment of the present invention. 35 is a circuit diagram of one pixel of a display device according to another embodiment of the present invention. 36 is a schematic cross-sectional view of a display device according to another embodiment of the present invention. 37A to 37E are schematic process diagrams of a method for manufacturing the thin film transistor disposed in the region B in FIG. 36 . 38 is a schematic cross-sectional view of a display device according to another embodiment of the present invention. FIG. 39A and FIG. 39B are schematic process diagrams of the manufacturing method of the thin film transistor disposed in the region B in FIG. 38 .
100:薄膜電晶體100: thin film transistor
110:基板110: Substrate
120:緩衝層120: Buffer layer
130:主動層130: Active layer
131:通道部131: Channel Department
132a、132b:偏差部132a, 132b: Deviation section
133a、133b:導體提供部133a, 133b: conductor supply part
140:閘極電極140: gate electrode
150:閘極絕緣層150: gate insulating layer
L1、L2:寬度L1, L2: width
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Citations (4)
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US6268625B1 (en) * | 1997-08-14 | 2001-07-31 | Lg Semicon Co., Ltd. | Trench-type thin film transistor |
US20070069209A1 (en) * | 2005-09-27 | 2007-03-29 | Jae-Kyeong Jeong | Transparent thin film transistor (TFT) and its method of manufacture |
US20090283763A1 (en) * | 2008-05-15 | 2009-11-19 | Samsung Electronics Co., Ltd. | Transistors, semiconductor devices and methods of manufacturing the same |
US20110175646A1 (en) * | 2010-01-20 | 2011-07-21 | Semiconductor Energy Laboratory Co., Ltd. | Semiconductor device |
-
2019
- 2019-12-31 KR KR1020190179566A patent/KR20210035694A/en not_active Application Discontinuation
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2020
- 2020-09-23 TW TW109132901A patent/TWI775153B/en active
Patent Citations (4)
Publication number | Priority date | Publication date | Assignee | Title |
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US6268625B1 (en) * | 1997-08-14 | 2001-07-31 | Lg Semicon Co., Ltd. | Trench-type thin film transistor |
US20070069209A1 (en) * | 2005-09-27 | 2007-03-29 | Jae-Kyeong Jeong | Transparent thin film transistor (TFT) and its method of manufacture |
US20090283763A1 (en) * | 2008-05-15 | 2009-11-19 | Samsung Electronics Co., Ltd. | Transistors, semiconductor devices and methods of manufacturing the same |
US20110175646A1 (en) * | 2010-01-20 | 2011-07-21 | Semiconductor Energy Laboratory Co., Ltd. | Semiconductor device |
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