TWI775153B - Thin film transistor, method of manufacturing the thin film transistor, and display apparatus including the thin film transistor - Google Patents

Abstract

An embodiment of the present disclosure provides a thin film transistor, a method of manufacturing the thin film transistor and a display apparatus including the thin film transistor, The thin film transistor includes an active layer on a substrate, a gate electrode disposed apart from the active layer to at least partially overlap the active layer, and a gate insulation layer between the active layer and the gate electrode. The gate insulation layer may cover a whole top surface of the active layer facing the gate electrode. The active layer may include a channel part overlapping the gate electrode, a conductivity-providing part which does not overlap the gate electrode, and an offset part between the channel part and the conductivity-providing part. The offset part may not overlap the gate electrode, and the conductivity-providing part may be doped with a dopant.

Description

Thin film transistor, method of manufacturing thin film transistor, and display device including thin film transistor

The present invention relates to a thin film transistor, a method for manufacturing the thin film transistor, and a display device including the thin film transistor, and in particular, to a thin film transistor with excellent switching characteristics based on its own deviation, and the production of the thin film transistor Methods and display devices including such thin film transistors.

Thin-Film Transistor (TFT) can be fabricated on a glass substrate or a plastic substrate, so thin-film transistors are widely used as switching elements or driving elements of display devices, such as liquid crystal displays. , LCD) equipment and organic light-emitting display equipment.

According to the material of each active layer, thin film transistors can be classified into amorphous silicon thin film transistors using amorphous silicon (a-Si) as the active layer, polycrystalline silicon (poly-Si) as the active layer of polysilicon thin film transistors, and oxide semiconductor thin film transistors using oxide semiconductors as active layers.

The active layer can be formed by continuously depositing the amorphous silicon active layer for a short time, so the amorphous silicon thin film transistor has a short manufacturing time and low manufacturing cost. On the other hand, since the current driving performance is reduced due to the low mobility or shift of the threshold voltage, amorphous silicon thin film transistors are applied to active matrix organic light emitting diodes. , AMOLED), etc. will have limitations.

Polysilicon thin film transistors are fabricated by depositing and crystallizing amorphous silicon. Polysilicon thin film transistors have high electron mobility, good stability, thin thickness, and high energy efficiency, and can achieve high resolution. Examples of polysilicon thin film transistors include low temperature polysilicon (LTPS) thin film transistors and polysilicon thin film transistors. However, since the manufacturing process of the polysilicon thin film transistor needs to include a step of crystallizing the amorphous silicon and the amorphous silicon needs to be crystallized at a high processing temperature, the number of manufacturing processes is increased and the manufacturing cost is increased. Therefore, it is difficult to apply polysilicon thin film transistors to large-area display devices. Also, it is difficult to ensure the uniformity of polycrystalline silicon thin film transistors due to polycrystalline properties.

Based on the properties of oxygen, oxide semiconductor thin film transistors have high mobility and large resistance change, and thus can easily obtain desired physical properties. Also, in the process of manufacturing the oxide semiconductor thin film transistor, the oxide contained in the active layer can be formed at a relatively low temperature so that the manufacturing cost is low. Oxide semiconductors are transparent in terms of properties of oxides, and thus a transparent display device can be easily implemented. Of course, oxide semiconductor thin film transistors have lower stability and electron mobility than polysilicon thin film transistors.

The oxide semiconductor thin film transistor can be fabricated into a back channel etch (BCE) structure or an etch stopper (ES) structure in the form of a bottom gate, or a coplanar structure in the form of a top gate . In an oxide semiconductor thin film transistor having a coplanar structure, control of a conductor-providing region formed from an oxide semiconductor is very important, and the mobility of the oxide semiconductor thin film transistor may vary depending on the conductor The sheet resistance of the provided area varies. Therefore, it may be necessary to control the process conditions in order to form the conductor supply region, and it is necessary to minimize the influence of the insulating layer provided on or under the oxide semiconductor layer on the conductor supply region.

Accordingly, the present invention provides a thin film transistor, a method for manufacturing the thin film transistor, and a display device including the thin film transistor, which substantially solve one or more problems caused by the shortcomings or limitations of the prior art.

One aspect of the present invention is to provide a thin film transistor including a conductor supplying portion, wherein the conductor supplying portion is formed by doping without passing through a patterned gate insulating layer.

Another aspect of the present invention is to provide a thin film transistor that ensures the electrical stability of the channel portion and the conductor providing portion and minimizes the influence of the insulating layer on the active layer by using the active layer including the offset portion.

Another aspect of the present invention is to provide a thin film transistor that secures an effective channel width according to a deviation portion.

Another aspect of the present invention is to provide a technique for adjusting the size of a photoresist pattern to form an offset portion between a channel portion and a conductor providing portion of a semiconductor layer.

Another aspect of the present invention is to provide a display device including a thin film transistor.

Additional advantages and features of the present invention will be set forth in part in the description that follows, and in part will be apparent to those skilled in the art upon examination of the description that follows, or may be learned by practice of the invention. The objectives and other advantages of the invention will be realized and attained by the structure particularly pointed out in the following description, claims and appended drawings.

To achieve these and other advantages in accordance with the objectives of the present invention, as embodied and broadly described herein, there is provided a thin film transistor comprising an active layer, a gate electrode, and a gate insulating layer. The active layer is located on a substrate. The gate electrode is separated from the active layer to at least partially overlap the active layer. The gate insulating layer is located between the active layer and the gate electrode. The gate insulating layer may cover the entire top surface of the active layer facing the gate electrode. The active layer may include a channel portion, a conductor supply portion, and an offset portion. The channel portion overlaps the gate electrode. The conductor supply portion does not overlap the gate electrode. The offset portion is located between the channel portion and the conductor providing portion. The offset portion may not overlap with the gate electrode. The conductor supply portion may be doped with a dopant.

In another aspect of the present invention, a thin film transistor substrate is provided, which includes a base substrate, a first thin film transistor, and a second thin film transistor. The first thin film transistor and the second thin film transistor are located on the base substrate. The first thin film transistor may include a first active layer and a first gate electrode. The first active layer is on the base substrate. The first gate electrode is separated from the first active layer to at least partially overlap the first active layer. The second thin film transistor may include a second active layer, a gate electrode and a gate insulating layer. The second active layer is on the base substrate. The gate electrode is separated from the second active layer to at least partially overlap the second active layer. The gate insulating layer is located between the second active layer and the second gate electrode. The gate insulating layer may cover the entire top surface of the second active layer facing the second gate electrode. In addition, the second active layer may include a channel portion, a conductor providing portion, and an offset portion. The channel portion overlaps the second gate electrode. The conductor supply portion does not overlap the second gate electrode. The offset portion is located between the channel portion and the conductor providing portion. The offset portion does not overlap the second gate electrode. The conductor supply portion is doped with a dopant. The first active layer and the second active layer can be disposed on different layers.

In another aspect of the present invention, there is provided a method of manufacturing a thin film transistor. The method includes forming an active layer on a substrate, forming a gate insulating layer on the active layer, and forming a gate insulating layer on the gate insulating layer. A gate electrode at least partially overlaps the active layer, and the active layer is doped with a dopant. The gate insulating layer may cover the entire top surface of the active layer facing the gate electrode. The step of forming the gate electrode may include forming a gate electrode material layer on the gate insulating layer, forming a photoresist pattern on the gate electrode material layer, and etching the gate electrode material by using the photoresist pattern as a mask Floor. The area of the photoresist pattern is larger than that of the gate electrode. In a plan view, the gate electrode is disposed in the area defined by the photoresist pattern. Therefore, the photoresist pattern can be used as a mask in the step of doping the dopant on the active layer.

In another aspect of the present invention, a display device is provided, which includes a substrate, a pixel driving circuit, and a light-emitting device. The pixel driving circuit is located on the substrate. The light-emitting device is connected to the pixel driving circuit. The pixel driving circuit may include a thin film transistor. The thin film transistor may include an active layer, a gate electrode and a gate insulating layer. The active layer is on the substrate. The gate electrode is separated from the active layer to at least partially overlap the active layer. The gate insulating layer is located between the active layer and the gate electrode. The gate insulating layer may cover the entire top surface of the active layer facing the gate electrode. The active layer may include a channel portion, a conductor supply portion, and an offset portion. The channel portion overlaps the gate electrode. The conductor supply portion does not overlap the gate electrode. The offset portion is located between the channel portion and the conductor providing portion. The offset portion may not overlap with the gate electrode. The conductor supply portion may be doped with a dopant.

In another aspect of the present invention, a display device is provided, which includes a first thin film transistor, a first intermediate insulating layer, a second thin film transistor, and a second intermediate insulating layer. The first thin film transistor includes a first active layer, a first gate electrode, a first gate insulating layer, a first source electrode and a first drain electrode. The first active layer includes polysilicon. The first gate electrode overlaps the first active layer. The first gate insulating layer is located between the first active layer and the first gate electrode. The first source electrode and the first drain electrode are respectively connected to the first active layer. The first intermediate insulating layer is disposed on the first gate electrode. The second thin film transistor includes a second active layer, a second gate electrode, a second gate insulating layer, a second source electrode and a second drain electrode. The second active layer includes an oxide semiconductor. The second gate electrode overlaps the second active layer. The second gate insulating layer is located between the second active layer and the second gate electrode. The second source electrode and the second drain electrode are respectively connected to the second active layer. The second intermediate insulating layer is disposed on the first gate electrode, the second gate electrode and the second gate insulating layer. The second gate insulating layer and the second intermediate insulating layer include a dopant for doping the second active layer.

It is to be understood that the foregoing general description and the following embodiments of the present invention are exemplary only and are intended to provide further explanation of the claimed invention.

The advantages, features and implementation methods of the present invention will be illustrated by the following examples and drawings. However, the present invention may be embodied in various different forms and should not be limited by the examples set forth herein. Rather, these embodiments are only provided so that this disclosure will be thorough and complete, and will fully convey the scope of the present invention to those skilled in the art. Furthermore, the present invention is limited only by the scope of the claims.

The shapes, dimensions, proportions, angles and numbers of the embodiments used to describe the present invention in the drawings are only examples, and thus the present invention is not limited to the illustrated details. Like numbers refer to like elements throughout. In the following description, a detailed description of related conventional functions or constructions will be omitted when they would unnecessarily obscure the gist of the present invention.

When "comprising", "having" and "including" are used in this specification to describe, unless "only" is used, another component may be added. Terms in the singular may include the plural unless stated otherwise.

When explaining an element, even if the element is not described in detail, it should be interpreted as including a range of error.

When describing the positional relationship, for example, when the positional relationship between two components is described using "above", "above", "below" and "near", unless "immediately" or "directly" is used, it can be used here. One or more other components are placed between the two components.

The spatially relative terms "below," "below," "bottom," "above," and "top" may be used herein to simply describe the relationship between the devices or elements depicted in the figures. It will be appreciated that these spatially relative terms are intended to encompass different orientations of the device in addition to the orientations depicted in the figures. For example, if the device in the figures is reversed, elements described as being located below or below one side of other elements may be located above those sides of the other elements. The exemplary term "bottom" can encompass the orientation of bottom and top. Similarly, the exemplary terms "above" or "top" can express both an orientation of above and below.

When describing temporal relationships, such as when using "after", "subsequent to", "next" and "before", unless "immediately" or "directly" is used, discontinuities may be included.

It will be understood that, although the terms "first," "second," etc. may be used herein to describe various elements, these elements are not limited by these terms. These terms are only used to identify these elements. For example, a first element could be termed a second element, and, similarly, a second element could be termed a first element, without departing from the scope of the present invention.

In describing elements of the invention, terms such as first, second, A, B, (a), (b), etc. may be used. Such terms are only used to distinguish corresponding elements from other elements, and the nature, order, or priority of these elements is not limited by these terms. It will be understood that when an element or layer is referred to as being on or connected to another element or layer, it can be directly on or connected to the other element or layer, or it can be There are intermediate elements or layers. Also, it should be understood that when an element is disposed on or under another element, it may mean that the elements are in direct contact with each other or may mean that the elements are not in direct contact with each other.

The term "at least one" should be understood to include any and all combinations of one or more of the associated listed elements. For example, "at least one of the first, second, and third elements" means all combinations of two or more of the first, second, and third elements as well as the first, second, and element or third element.

The features of the various embodiments of the invention may be connected or combined with each other in part or in whole, and may technically interact and actuate with each other in various ways well understood by those skilled in the art. Embodiments of the invention may be performed independently of each other or may be performed together in a commonly related relationship.

Reference will now be made in detail to exemplary embodiments of the present invention, examples of which are illustrated in the accompanying drawings. Wherever possible, the same reference numbers will be used throughout the various drawings to refer to the same or like parts.

In the embodiments of the present invention, for convenience of description, the source electrode and the drain electrode may be different from each other, and the source electrode and the drain electrode may have the same meaning. The source electrode may be a drain electrode, and the drain electrode may be a source electrode. Also, the source electrode in one embodiment can be the drain electrode in another embodiment, and the drain electrode in one embodiment can be the source electrode in another embodiment.

In some embodiments of the present invention, for convenience of description, the source region and the source electrode may be different from each other and the drain region and the drain electrode may be different from each other, but the embodiments of the present invention are not limited thereto. The source region may be a source electrode, and the drain region may be a drain electrode. Also, the source region may be a drain electrode, and the drain region may be a source electrode.

FIG. 1 is a schematic cross-sectional view of a thin film transistor 100 according to an embodiment of the present invention.

The thin film transistor 100 according to an embodiment of the present invention may include an active layer 130 , a gate electrode 140 and a gate insulating layer 150 . The active layer 130 is located on a substrate 110 . The gate electrode 140 is separated from the active layer 130 to at least partially overlap the active layer 130 . The gate insulating layer 150 is located between the active layer 130 and the gate electrode 140 . The gate insulating layer 150 may cover the entire top surface of the active layer 130 facing the gate electrode 140 .

The active layer 130 may include a channel portion 131 , a plurality of conductor providing portions 133a, 133b, and a plurality of offset portions 132a, 132b. The channel portion 131 overlaps the gate electrode 140 . The conductor supply parts 133 a and 133 b do not overlap with the gate electrode 140 . The offset parts 132a and 132b are located between the channel part 131 and the conductor supply parts 133a and 133b. According to an embodiment of the present invention, the deviation portions 132a, 132b may not overlap the gate electrode 140, and the conductor providing portions 133a, 133b may be doped with dopants.

Hereinafter, the thin film transistor 100 according to an embodiment of the present invention will be described in detail with reference to FIG. 1 .

Referring to FIG. 1 , the active layer 130 may be disposed on the substrate 110 .

The substrate 110 can be made of glass or plastic. Plastics can be transparent plastics with flexible properties (such as polyimide). In the case of using polyimide as the substrate 110 , a heat-resistant polyimide with high temperature resistance may be used according to performing a high temperature deposition process on the substrate 110 .

The buffer layer 120 may be disposed on the substrate 110 . The buffer layer 120 may include at least one of silicon oxide and silicon nitride. The buffer layer 120 may protect the active layer 130 and may have planarization properties to planarize the top of the substrate 110 . The buffer layer 120 may be omitted.

According to an embodiment of the present invention, the active layer 130 may include an oxide semiconductor material. The active layer 130 may be an oxide semiconductor layer.

For example, the active layer 130 may include at least one oxide semiconductor material, such as indium zinc oxide (InZnO, IZO), indium gallium oxide (InGaO, IGO), indium tin oxide (InSnO, ITO), indium gallium zinc oxide (InGaZnO, IGZO) , indium gallium zinc tin oxide (InGaZnSnO, IGZTO), indium tin zinc oxide (InSnZnO, ITZO), indium gallium tin oxide (InGaSnO, IGTO), gallium oxide (GaO, GO), gallium zinc tin oxide (GaZnSnO, GZTO) and Gallium Zinc Oxide (GaZnO, GZO). However, the embodiments of the present invention are not limited thereto, and the active layer 130 may include another oxide semiconductor material.

The active layer 130 may include a channel portion 131 and conductor supply portions 133a and 133b. Also, the active layer 130 may include offset parts 132a and 132b disposed between the channel part 131 and the conductor supply parts 133a and 133b.

The gate insulating layer 150 may be disposed on the active layer 130 . The gate insulating layer 150 may have insulating properties and may include at least one of silicon oxide, silicon nitride and metal-based oxide. The gate insulating layer 150 may have a single-layer structure or may have a multi-layer structure.

The gate insulating layer 150 may cover the entire top surface of the active layer 130 . In FIG. 1 , a surface disposed in a direction toward the gate electrode 140 among the surfaces of the active layer 130 may be referred to as a top surface.

According to an embodiment of the present invention, as shown in FIG. 1 , the gate insulating layer 150 may not need to be patterned and may be formed to cover the entire surface of the substrate 110 including the active layer 130 .

However, the embodiments of the present invention are not limited thereto, and a contact hole may be formed in the gate insulating layer 150 . In the case where a contact hole is formed in the gate insulating layer 150, a portion of the active layer 130 may be exposed from the gate insulating layer 150 through the contact hole. In an embodiment of the present invention, the gate insulating layer 150 may cover the entire top surface of the active layer 130 except for the contact hole area. Moreover, in an embodiment of the present invention, the gate insulating layer 150 may cover the entire top surface of the active layer 130 except for the area contacting the conductor element. Here, the conductor element may refer to an element that is in contact with or connected to the active layer 130 and includes a conductor material, and the conductor material may include wiring lines, electrodes, pads, terminals, and the like. For example, the conductor elements may include a source electrode 161 and a drain electrode 162 each connected to the active layer 130 (see FIG. 2).

In an embodiment of the present invention, the gate insulating layer 150 may be disposed to cover at least the top surfaces of the deviation portions 132 a and 132 b of the active layer 130 and the channel portion 131 .

In one embodiment of the present invention, a portion of the active layer 130 may be conductive based on a doping process using dopants, and in this case, the dopants may pass through the gate insulating layer 150 and may be doped in the active layer 130 . Therefore, the active layer 130 can be doped even without being exposed from the gate insulating layer 150 . Therefore, in one embodiment of the present invention, the gate insulating layer 150 does not need to be patterned.

The gate electrode 140 may be disposed on the gate insulating layer 150 . The gate electrode 140 may include aluminum-based metal such as aluminum or aluminum alloy, silver-based metal such as silver or silver alloy, copper-based metal such as copper or copper alloy , At least one of molybdenum (molybdenum-based metal) such as molybdenum or molybdenum alloy, chromium (Cr), tantalum (Ta), neodymium (Nd) and titanium (Ti). The gate electrode 140 may have a multi-layer structure, and the multi-layer structure includes at least two conductor layers with different characteristics.

The gate electrode 140 may overlap the channel portion 131 of the active layer 130 . The portion of the active layer 130 overlapping the gate electrode 140 may be the channel portion 131 .

The conductor supply portions 133a and 133b need not overlap with the gate electrode 140 . One of the conductor supply parts 133a and 133b may be a source region, and the other of the conductor supply parts 133a and 133b may be a drain region. According to actual conditions, the source region can be used as a source electrode, and the drain region can be used as a drain electrode. The conductor supply parts 133a, 133b may each serve as a line.

According to an embodiment of the present invention, the conductor providing parts 133 a and 133 b may be formed by selectively providing conductivity to the active layer 130 . For example, the conductor providing portions 133a, 133b may be formed by a doping process using dopants. According to an embodiment of the present invention, the conductor providing parts 133a and 133b may be in a state of being doped with dopants.

The dopant may include at least one of boron (B), phosphorus (P), fluorine (F), and hydrogen (H). At least one of boron ion, phosphorus ion and fluoride ion can be used for doping. Hydrogen ions can be used for doping.

The doping concentration of the conductor providing parts 133 a and 133 b may be higher than that of the channel part 131 , and the resistivity of the conductor providing parts 133 a and 133 b may be lower than that of the channel part 131 . The conductivity of the conductor providing parts 133a, 133b may be higher than that of the respective deviation parts 132a, 132b, and the conductivity of the conductor providing parts 133a, 133b may be similar to that of the conductors.

According to an embodiment of the present invention, the deviation portions 132 a and 132 b may be disposed between the channel portion and the conductor providing portions 133 a and 133 b and may not overlap with the gate electrode 140 .

Although dopants are not directly implanted into the offset portions 132a, 132b in the process of manufacturing the thin film transistor 100 (refer to FIG. 7), in the process of implanting the dopants into the conductor providing portions 133a, 133b Medium dopants may diffuse into the offset portions 132a, 132b. Therefore, some dopants may be doped into the offset portions 132a, 132b.

According to an embodiment of the present invention, the resistivity of each deviation portion 132a, 132b may be lower than that of the channel portion 131 and may be higher than the resistivity of each conductor providing portion 133a, 133b. The deviation portions 132 a and 132 b having such resistivity characteristics can perform a buffering function between the conductor supplying portions 133 a and 133 b and the channel portion 131 .

In the case where the channel portion 131 is directly connected to the conductor supplying portions 133a, 133b, a leakage current may be generated when the thin film transistor 100 is in an off state. On the other hand, when the deviation portions 132a, 132b having higher resistivity than the respective conductor supply portions 133a, 133b are provided between the conductor supply portions 133a, 133b and the channel portion 131, the channel can be prevented when the thin film transistor 100 is in an off state A leakage current occurs between the portion 131 and the conductor supplying portions 133a and 133b.

As described above, when the deviation parts 132a and 132b are disposed between the conductor supply parts 133a and 133b and the channel part 131, the electrical stability of the channel part 131 and the conductor supply parts 133a and 133b can be improved.

Even when the thin film transistor 100 is turned on according to the gate voltage applied to the gate electrode 140 , the conductivity of the deviation portions 132 a and 132 b may not be increased, wherein the deviation portions 132 a and 132 b are not generated in the gate electrode 140 . The electric field is greatly affected. Therefore, when the thin film transistor 100 is turned on, the resistivity of the deviation parts 132a, 132b may be higher than the resistivity of the channel part 131 and the resistivity of the respective conductor providing parts 133a, 133b. Therefore, the threshold voltage shift of the thin film transistor 100 can be prevented or slowed down by the deviation portions 132a and 132b.

According to an embodiment of the present invention, the width L2 of each deviation portion 132a, 132b can be set in a specific range to prevent the leakage current of the thin film transistor 100 and the leakage current of the thin film transistor 100 without disturbing the driving of the thin film transistor 100. Threshold voltage shift.

According to an embodiment of the present invention, the width of the first deviation portion 132a may be the same or different from the width of the second deviation portion 132b. In an embodiment of the present invention, for the convenience of description, the width of the first deviation portion 132a and the width of the second deviation portion 132b may be the same as each other and may be the width L2.

According to an embodiment of the present invention, when the channel portion 131 has a width L1 and each of the deviation portions 132a, 132b has a width L2, the thin film transistor 100 may satisfy the following equation 1.

[Equation 1]

L1 x L2 x 1/η1 ≥ 1

where η1 = 0.5 square microns

When the width L1 of the channel portion 131 and the width L2 of each deviation portion 132a, 132b satisfy Equation 1, the deviation portion 132a, 132b can prevent the leakage current of the thin film transistor 100 and the thin film without disturbing the driving of the thin film transistor 100 The threshold voltage of the transistor 100 is shifted.

According to another embodiment of the present invention, in Equation 1, η1 = 1.5 square micrometers. Alternatively, η1 may satisfy the following relationship: 0.5 square microns ≤ η1 ≤ 1.5 square microns.

According to an embodiment of the present invention, the width L2 of each deviation portion 132a, 132b may be 0.25 μm or more. When the width L2 of each of the deviation portions 132a, 132b is less than 0.3 μm, the effect of preventing the leakage current of the thin film transistor 100 and the effect of preventing the threshold voltage shift of the thin film transistor 100 may not be sufficient. According to another embodiment of the present invention, the width L2 of each deviation portion 132a, 132b may be 0.3 μm or more. In detail, the width L2 of each deviation portion 132a, 132b may be 0.5 micrometer or more.

According to an embodiment of the present invention, the width L2 of each deviation portion 132a, 132b can be maintained at 2.5 microns. When the width L2 of each of the deviation portions 132a, 132b is larger than 2.5 micrometers, the driving characteristics of the thin film transistor 100 may be degraded, which may be disadvantageous to miniaturize each of the thin film transistors.

According to an embodiment of the present invention, the deviation portions 132a, 132b can be disposed between the channel portion 131 and the conductor providing portions 133a, 133b, so even when the width L1 of the channel portion 131 is narrow, the channel portion 131 can still effectively serve as a aisle. Therefore, the thin film transistor 100 can be miniaturized.

According to an embodiment of the present invention, the width L1 of the channel portion 131 may be 2 μm or more. According to an embodiment of the present invention, the deviation portions 132a, 132b can be disposed between the channel portion 131 and the conductor providing portions 133a, 133b, so even when the width L1 of the channel portion 131 is about 2 μm, the thin film transistor 100 can still be effective to perform the switch function. For example, the width of the channel portion 131 may be 2 micrometers to 20 micrometers. Alternatively, the width of the channel portion 131 may be 2 micrometers to 40 micrometers.

In addition, according to an embodiment of the present invention, the width L1 of the channel portion 131 may be 3 micrometers or more, and for example, may be 4 micrometers or more. For example, the width of the channel portion 131 may be 3 microns to 20 microns, 3 microns to 10 microns, 3 microns to 8 microns, or 4 microns to 6 microns.

According to an embodiment of the present invention, the buffer layer 120 may be disposed between the substrate 110 and the active layer 130 , and dopants may be doped into the buffer layer 120 .

The doping concentration of each conductor providing portion 133a, 133b, the doping concentration of the gate insulating layer 150 and the doping concentration of the buffer layer 120 can be adjusted by adjusting the accelerating voltage applied to the dopant during the doping process.

The accelerating voltage applied to the dopant may be increased to sufficiently dope the conductor providing portions 133a, 133b with the dopant. In this case, the dopant may pass through the conductor providing parts 133a, 133b and may be doped into the buffer layer 120. When the concentration of the dopant doped in the buffer layer 120 is increased, the doping concentration of the buffer layer 120 may be higher than the doping concentration of the respective conductor providing portions 133a, 133b.

FIG. 2 is a schematic cross-sectional view of a thin film transistor 200 according to another embodiment of the present invention.

Compared with the thin film transistor 100 shown in FIG. 1 , the thin film transistor 200 in FIG. 2 may further include an intermediate insulating layer 155 , a source electrode 161 and a drain electrode 162 .

The intermediate insulating layer 155 may be disposed on the gate electrode 140 and the gate insulating layer 150 and may include insulating materials.

The source electrode 161 and the drain electrode 162 may be disposed on the intermediate insulating layer 155 . The source electrode 161 and the drain electrode 162 may be separated from each other and may be connected to the active layer 130 .

Referring to FIG. 2 , the source electrode 161 can be connected to the first conductor providing part 133a through the contact hole H1, and the drain electrode 162 can be connected to the second conductor providing part 133b through the contact hole H2. The first conductor providing portion 133a connected to the source electrode 161 may be referred to as a source connection portion, and the second conductor providing portion 133b connected to the drain electrode 162 may be referred to as a drain connection portion.

Referring to FIG. 2 , the contact holes H1 and H2 can pass through the intermediate insulating layer 155 and the gate insulating layer 150 . A portion of the active layer 130 may be exposed from the gate insulating layer 150 through the contact holes H1, H2. For example, part of the first conductor providing part 133a and part of the second conductor providing part 133b may be exposed from the gate insulating layer 150 through the contact holes H1, H2.

FIG. 3 is a schematic cross-sectional view of a thin film transistor 300 according to another embodiment of the present invention.

Referring to FIG. 3 , a thin film transistor 300 according to another embodiment of the present invention may include a light shielding layer 121 , and the light shielding layer 121 is disposed on the substrate 110 . The light shielding layer 121 can be disposed to overlap the active layer 130 and can shield the light incident on the substrate 110 , thereby protecting the active layer 130 . For example, the light shielding layer 121 may be disposed to overlap the channel portion 131 of the active layer 130 .

FIG. 4 is a schematic cross-sectional view of a thin film transistor 400 according to another embodiment of the present invention.

Referring to FIG. 4 , the active layer 130 may have a multi-layer structure. The active layer 130 of the thin film transistor 400 according to the embodiment in FIG. 4 may include a first oxide semiconductor layer 130a and a second oxide semiconductor layer 130b, wherein the first oxide semiconductor layer 130a is located on the substrate 110 and the third The dioxide semiconductor layer 130b is located on the first oxide semiconductor layer 130a. Each of the first oxide semiconductor layer 130a and the second oxide semiconductor layer 130b may include an oxide semiconductor material. The first oxide semiconductor layer 130a and the second oxide semiconductor layer 130b may include the same oxide semiconductor material or may include different oxide semiconductor materials.

The first oxide semiconductor layer 130a may support the second oxide semiconductor layer 130b. Therefore, the first oxide semiconductor layer 130a may be referred to as a support layer. The main channel may be formed on the second oxide semiconductor layer 130b. Therefore, the second oxide semiconductor layer 130b may be referred to as a channel layer. However, embodiments of the present invention are not limited thereto, and a channel may be formed in the first oxide semiconductor layer 130a.

As shown in FIG. 4, the structure of the semiconductor layer including the first oxide semiconductor layer 130a and the second oxide semiconductor layer 130b may be referred to as a double-layer structure.

The first oxide semiconductor layer 130a serving as a support layer may have good film stability and mechanical properties. For film stability, the first oxide semiconductor layer 130a may contain gallium (Ga). Gallium can form stable bonding with oxygen, and oxides of gallium can have good film stability.

The first oxide semiconductor layer 130a may include, for example, at least one oxide semiconductor material, such as indium gallium zinc oxide (InGaZnO, IGZO), indium gallium oxide (InGaO, IGO), indium gallium tin oxide (InGaSnO, IGTO), indium gallium oxide (InGaSnO, IGTO) Zinc tin (InGaZnSnO, IGZTO), gallium zinc tin oxide (GaZnSnO, GZTO), gallium zinc oxide (GaZnO, GZO) and gallium oxide (GaO, GO).

The second oxide semiconductor layer 130b serving as a channel layer may include, for example, at least one oxide semiconductor material, such as indium zinc oxide (InZnO, IZO), indium gallium oxide (InGaO, IGO), indium tin oxide (InSnO, ITO), oxide Indium gallium zinc (InGaZnO, IGZO), indium gallium zinc tin oxide (InGaZnSnO, IGZTO), gallium zinc tin oxide (GaZnSnO, GZTO) and indium tin zinc oxide (InSnZnO, ITZO). However, another embodiment of the present invention is not limited thereto, and the second oxide semiconductor layer 130b may include another oxide semiconductor material.

FIG. 5 is a schematic cross-sectional view of a thin film transistor 500 according to another embodiment of the present invention.

The thin film transistor 500 according to another embodiment of the present invention may include an active layer 130 , a gate electrode 140 , a gate insulating layer 150 , a source electrode 161 and a drain electrode 162 . The active layer 130 is located on the substrate 110 . The gate electrode 140 is separated from the active layer 130 so as to overlap the active layer 130 in at least a part thereof. The gate insulating layer 150 is located between the active layer 130 and the gate electrode 140 . The source electrode 161 is located on the gate insulating layer 150 . The drain electrode 162 is separated from the source electrode 161 on the gate insulating layer 150 .

Referring to FIG. 5 , the gate insulating layer 150 may cover the entire top surface of the active layer 130 . The source electrode 161 and the drain electrode 162 may be formed on the gate insulating layer 150 . In this case, the source electrode 161 and the drain electrode 162 may be disposed on the same layer as the gate electrode 140 , and may include the same material as the gate electrode 140 . Each of the source electrode 161 and the drain electrode 162 can be connected to the active layer 130 through a contact hole formed in the gate insulating layer 150 .

6 is a schematic cross-sectional view of a thin film transistor substrate 600 according to another embodiment of the present invention.

The thin film transistor substrate 600 according to another embodiment of the present invention may include a base substrate 210 , a first thin film transistor TR1 and a second thin film transistor TR2 . The first thin film transistor TR1 is located on the base substrate 210 . The second thin film transistor TR2 is located on the base substrate 210 .

The first thin film transistor TR1 may include a first active layer 270 and a first gate electrode 280 . The first active layer 270 is located on the base substrate 210 . The first gate electrode 280 is separated from the first active layer 270 to at least partially overlap the first active layer 270 . Moreover, the first thin film transistor TR1 may include a gate insulating layer 181 , and the gate insulating layer 181 is located between the first active layer 270 and the first gate electrode 280 .

The gate insulating layer 181 located between the first active layer 270 and the first gate electrode 280 may be referred to as a first gate insulating layer.

The first thin film transistor TR1 may further include a first source electrode 281 and a first drain electrode 282 . The first source electrode 281 and the first drain electrode 282 may be separated from each other and may be connected to the first active layer 270 .

According to another embodiment of the present invention, the first active layer 270 may be formed of a silicon semiconductor layer, and may include a channel portion 271 and a plurality of conductor supply portions 272 and 273 .

The second thin film transistor TR2 may include a second active layer 230 and a second gate electrode 240 . The second active layer 230 is located on the base substrate 210 , and the second gate electrode 240 is separated from the second active layer 230 to at least partially overlap the second active layer 230 . The second active layer 230 may be an oxide semiconductor layer.

In the thin film transistor substrate 600 according to another embodiment of the present invention, the second thin film transistor TR2 has the same structure as each of the thin film transistors 100 to 500 shown in FIGS. 1 to 5 , respectively.

In the thin film transistor substrate 600 according to another embodiment of the present invention, the first active layer 270 and the second active layer 230 may be disposed on different layers. Referring to FIG. 6 , compared with the second active layer 230 , the first active layer 270 can be disposed at a position closer to the base substrate 210 . However, another embodiment of the present invention is not limited thereto, and the second active layer 230 may be disposed at a position closer to the base substrate 210 than the first active layer 270 . Also, the first active layer 270 may be formed of an oxide semiconductor layer, and the second active layer 230 may be formed of a silicon semiconductor layer.

Referring to FIG. 6 , the passivation layer 182 may be disposed on the first gate electrode 280 , and the intermediate layer 185 may be disposed on the passivation layer 182 .

Referring to FIG. 6 , the second active layer 230 of the second thin film transistor TR2 may be disposed on the intermediate layer 185 . The intermediate layer 185 may be a single layer of silicon nitride layers or silicon oxide layers. Alternatively, the intermediate layer 185 may be formed of a multi-layer structure in which a silicon nitride layer and a silicon oxide layer are stacked.

The gate insulating layer 150 may be disposed on the second active layer 230 , and the second gate electrode 240 may be disposed on the gate insulating layer 150 . The gate insulating layer 150 located between the second active layer 230 and the second gate electrode 240 may be referred to as a second gate insulating layer.

The gate insulating layer 150 may cover the entire top surface of the second active layer 230 facing the second gate electrode 240 . The gate insulating layer 150 may be disposed, for example, on the entire surface of the base substrate 210 including the second active layer 230 .

The second active layer 230 may include a channel portion 231 , a plurality of conductor providing portions 233a, 233b, and a plurality of offset portions 232a, 232b. The offset parts 232a and 232b are located between the channel part 231 and the conductor supply parts 233a and 233b.

The channel portion 231 of the second active layer 230 may overlap the second gate electrode 240 . The conductor providing portions 233 a and 233 b of the second active layer 230 need not overlap with the second gate electrode 240 . The offset portions 232a and 232b need not overlap with the second gate electrode 240 .

The conductor supply parts 233a, 233b may be doped with dopants.

The second thin film transistor TR2 may include a second source electrode 261 and a second drain electrode 262 on an intermediate insulating layer 155 . The intermediate insulating layer 155 may be disposed on the second gate electrode 240 and the gate insulating layer 150 and may include insulating materials. The second source electrode 261 and the second drain electrode 262 may be separated from each other on the intermediate insulating layer 155 and may be connected to the second active layer 230 . A planarization layer 192 may be disposed on the first source electrode 281 , the first drain electrode 282 , the second source electrode 261 , the second drain electrode 262 and the intermediate insulating layer 155 .

The structure of the first source electrode 281 , the first drain electrode 282 , the second source electrode 261 and the second drain electrode 262 is shown in FIG. 6 . Of course, another embodiment of the present invention is not limited thereto. For example, the first drain electrode 282, the second source electrode 261 and the second drain electrode 262 may be disposed on different layers, respectively.

In addition, the positions of the first gate electrode 280 and the second gate electrode 240 are not limited to those shown in FIG. 6 . When the first active layer 270 and the second active layer 230 are disposed on different layers, the first gate electrode 280 and the second gate electrode 240 may be disposed at positions different from those in FIG. 6 .

FIG. 7 is a diagram illustrating a doping method according to an embodiment of the present invention.

According to an embodiment of the present invention, the plurality of conductor providing portions 133a, 133b may be formed by selectively providing conductivity to the active layer 130 through doping.

Dopants can be used for doping. The dopant may include at least one of boron (B), phosphorus (P), fluorine (F), and hydrogen (H). For example, at least one of boron, phosphorus, and fluorine can be used as the dopant, or hydrogen can be used as the dopant. The dopant can be doped in an ionic state.

According to an embodiment of the present invention, it is not necessary to perform doping on the channel portion 131 of the active layer 130 . In order to avoid doping the channel portion 131 , the channel portion 131 can be protected or shielded from the dopant during the doping process so that the dopant is not implanted into the channel portion 131 .

As shown in FIG. 7 , in the doping process, a photoresist pattern 40 remaining on the gate electrode 140 can be used as a mask for protecting the channel portion 131 .

Referring to FIG. 7 , the width of the photoresist pattern 40 may be greater than the width of the gate electrode 140 in view of the cross-sectional view. Compared to the schematic cross-sectional view, the gate electrode 140 may completely overlap the photoresist pattern 40 .

With respect to a plan view, the area of the photoresist pattern 40 may be larger than that of the gate electrode 140 . For example, with respect to a plane, the gate electrode 140 may be disposed in an area defined by the photoresist pattern 40 .

According to an embodiment of the present invention, a gate electrode material layer can be formed for the gate electrode on the gate insulating layer 150, a photoresist material can be coated on the gate electrode material layer, and the photoresist material can be generated by exposing And the photoresist pattern 40 is formed.

Subsequently, the gate electrode 140 may be formed by etching the gate electrode material layer by using the photoresist pattern 40 as a mask. At this time, the gate electrode material layer may be etched to the inside relative to the edge of the photoresist pattern 40 to form the gate electrode 140 , wherein the area of the gate electrode 140 is smaller than that of the photoresist pattern 40 .

As shown in FIG. 7 , the region of the active layer 130 that does not overlap the photoresist pattern 40 can be doped with dopants through a doping process, wherein the doping process uses the photoresist pattern 40 on the gate electrode 140 as a mask . Therefore, these conductor supply parts 133a, 133b can be formed.

The dopant may not be doped into the channel portion 131 protected by the photoresist pattern 40 . Therefore, the channel portion 131 can maintain semiconductor characteristics.

The doping concentration of the conductor providing parts 133a, 133b provided with conductivity through a doping process using a dopant can be higher than the doping concentration of the channel part 131, and the resistivity of the conductor providing parts 133a, 133b can be lower than that of the channel resistivity of the portion 131 .

Referring to FIG. 7 , a plurality of offset parts (eg, the first and second offset parts) 132 a and 132 b can be protected by the photoresist pattern 40 . Therefore, direct implantation of dopants into the deviation portions 132a, 132b can be prevented. Of course, the dopant doped in the conductor supplying portions 133a, 133b may diffuse to the offset portions 132a, 132b. Therefore, it is possible to obtain the effect that the dopant is partially doped in the deviation portions 132a and 132b.

In FIG. 7 , when the gate electrode 140 has a width LG and the photoresist pattern 40 protruding from the gate electrode 140 has a width Loh, doping may be performed under the condition that Equation 2 below is satisfied.

[Equation 2]

LG x Loh x 1/η2 ≥ 1

where η2 = 0.5 square microns

Each of the first deviation portion 132a and the second deviation portion 132b may have a width corresponding to the width Loh of the protrusion. When the width LG of the gate electrode 140 and the width Loh of the photoresist pattern 40 protruding from the gate electrode 140 satisfy Equation 2, the deviation portions 132a and 132b satisfying Equation 2 can be formed.

According to another embodiment of the present invention, in Equation 2, η2 = 1.5 square micrometers. Alternatively, η2 may satisfy the following relationship: 0.5 square microns ≤ η2 ≤ 1.5 square microns.

FIG. 8 is a diagram showing the distribution of area-oriented dopants of the active layer according to an embodiment of the present invention.

In Figure 8, the origin represents the dopant. Referring to FIG. 8, the concentration of the dopant may be the highest among the plurality of conductor providing parts 133a, 133b. The doping concentration of the plurality of deviation portions 132a, 132b may be lower than the doping concentration of the respective conductor providing portions 133a, 133b. A small amount of dopant may diffuse into the channel portion 131 that is not directly doped with the dopant. The channel portion 131 may contain little or no dopant or may have a very low concentration of the dopant.

9 is a graph presenting the concentration of the area orientation dopant of the active layer according to one embodiment of the present invention.

Referring to FIG. 9 , the concentration gradients of the dopants of the plurality of deviation parts (eg, the first and second deviation parts) 132 a and 132 b may vary from the channel part 131 to the plurality of conductor supply parts (eg, the first and second conductor supply parts) 132 a and 132 b parts) 133a, 133b increase in the direction. For example, the concentration gradient of the dopant of the first deviation portion 132a may increase in the direction from the channel portion 131 to the first conductor providing portion 133a, and the concentration gradient of the dopant of the second deviation portion 132b may increase from The channel portion 131 increases in the direction of the second conductor providing portion 133b.

FIG. 10 is a graph presenting the extent of the area-oriented resistivity of the active layer 130 according to an embodiment of the present invention.

Referring to FIG. 10 , the resistivity of each deviation portion 132a, 132b may be lower than that of the channel portion 131 and may be higher than the resistivity of each conductor providing portion 133a, 133b. The concentration gradient of the dopant of the deviation parts 132a, 132b may increase in the direction from the channel part 131 to the conductor providing parts 133a, 133b.

Therefore, the deviation portions 132a, 132b may perform the function of electrical buffering between the channel portion 131 that does not provide conductivity and the conductor providing portions 133a, 133b.

For example, since the deviation parts 132a and 132b are disposed between the channel part 131 and the conductor supply parts 133a and 133b, leakage current can be prevented from flowing in the channel part 131 and the conductor supply parts 133a and 133b when the thin film transistor 100 is in an off state. 133b. As described above, the offset portions 132a, 132b can prevent leakage current from occurring in the thin film transistor 100 when the thin film transistor 100 is in an off state.

FIG. 11 is a graph showing the distribution of the area-oriented conductivity of the semiconductor layer in the on-state of the thin film transistor 100 according to an embodiment of the present invention.

When the thin film transistor 100 is turned on according to the gate voltage applied to the gate electrode 140, the conductivity of the respective offset portions 132a, 132b may not be greatly increased, wherein the offset portions 132a, 132b are not generated at the gate electrode The electric field in 140 greatly affects. Therefore, when the thin film transistor 100 is turned on, the conductivity of each deviation portion 132a, 132b may be lower than the conductivity of the channel portion 131 and the conductivity of each conductor providing portion 133a, 133b. Therefore, the deviation portions 132a and 132b can prevent the threshold voltage of the thin film transistor 100 from being shifted. Therefore, the electrical stability of the thin film transistor 100 can be improved.

FIG. 12 is a graph representing the concentration (atomic concentration) of elements based on depth in a region overlapping a conductor providing portion according to an embodiment of the present invention. Depth-based element concentrations have been confirmed by time of flight secondary ion mass spectrometry (TOF-SIMS).

FIG. 12 shows the concentrations of oxygen (O), silicon (Si), indium (In) and boron (B) in the gate insulating layer 150 , the first conductor providing portion 133 a and the buffer layer 120 . Oxygen (O) may be used to form the gate insulating layer 150 , the active layer 130 and the buffer layer 120 . Silicon (Si) may be used to form the gate insulating layer 150 and the buffer layer 120 . Indium (In) may be used to form the active layer 130 . Boron (B) may be an element added as a dopant through doping.

Referring to FIG. 12, it can be seen that boron (B) as a dopant has the largest concentration in the first conductor providing portion 133a.

13 is a graph showing the concentration (atomic concentration) of elements based on depth in a region overlapping a conductor providing portion according to an embodiment of the present invention.

Referring to FIG. 13 , it can be seen that boron (B) as a dopant has the largest concentration in the buffer layer 120 .

Referring to FIG. 13 , in the regions overlapping the conductor supplying parts 133 a and 133 b , the doping concentration of each of the conductor supplying parts 133 a and 133 b may be higher than the doping concentration of the gate insulating layer 150 and the doping concentration of the buffer layer 120 . Also, referring to FIG. 13 , in the region overlapping the conductor supplying parts 133a and 133b, the doping concentration of the buffer layer 120 may be higher than the doping concentration of the gate insulating layer 150 and the doping concentration of the respective conductor supplying parts 133a and 133b. concentration.

The doping concentration of the gate insulating layer 150 , the doping concentration of the respective conductor supply portions 133 a and 133 b and the doping concentration of the buffer layer 120 can be adjusted by adjusting the accelerating voltage applied to the dopant during the doping process.

When the accelerating voltage applied to the dopant is increased to sufficiently dope the conductor supplying parts 133a, 133b with the dopant, the dopant may be doped into the conductor supplying parts 133a, 133b and the buffer layer 120. When the accelerating voltage for doping is increased to an unintended level, the active layer 130 may be damaged. Therefore, according to an embodiment of the present invention, the accelerating voltage can be adjusted so that the doping concentration in the conductor providing parts 133a, 133b is the maximum or the doping concentration in the top of the buffer layer 120 is the maximum.

According to an embodiment of the present invention, when the doping concentration in the conductor supplying parts 133a, 133b is the maximum value or the doping concentration in the buffer layer 120 is the maximum value, the conductor supplying parts 133a, 133b can be effectively doped . Also, when the doping concentration in the conductor providing parts 133a and 133b is at the maximum value or the doping concentration in the buffer layer 120 is at the maximum value, it can be considered that the thin film transistor 100 operates in an efficient manner.

14A and 14B are diagrams of a conductor providing method according to a comparative example.

Referring to Figure 14A, gate electrode 140 can be formed, and then conductivity can be provided by using gate electrode 140 as a mask. For example, conductivity can be provided by dry etching. According to the comparative example, the gate insulating layer 150 may be patterned in the process of forming the gate electrode 140 , and the gate insulating layer disposed on the region to be provided with conductivity on the active layer 130 may be removed. Therefore, the etching gas applied to the dry etching process can directly contact the surface of the active layer 130 and thus can provide conductivity to selected portions of the active layer 130 . In FIGS. 14A and 14B , an example of using dry etching as the conductor providing method is shown, but conductivity can be provided by doping based on ion implantation.

Referring to FIG. 14B, in a state where the photoresist pattern 45 remains on the gate electrode 140, conductivity can be provided by using the photoresist pattern 45 as a mask. However, referring to FIG. 14B , the photoresist pattern 45 and the gate electrode 140 may have the same plane, and the photoresist pattern 45 may not protrude outside the region of the gate electrode 140 . In FIG. 14B , the protruding width Loh of the photoresist pattern 45 protruding to the outside of the gate electrode 140 may be zero.

According to the method shown in FIG. 14A or FIG. 14B, in the process of forming these conductor providing portions 133a, 133b by providing conductivity to selected portions of the active layer 130, conductivity may be partially provided to the channel portion 131. For example, conductivity may be provided to regions of the channel portion 131 adjacent to the conductor providing portions 133a, 133b. Of course, when the conductor providing method according to the comparative example is applied, it may be difficult to decide by what width the conductivity needs to be provided to the edge of the channel portion 131 .

In the conductor provision process, the conductor provision width or distance of the channel portion 131 may be referred to as the conductor provision penetration depth (conductivity-providing penetration depth) ΔL.

FIG. 15 is a schematic diagram illustrating a conductor providing penetration depth ΔL according to a comparative example.

Referring to FIG. 15 , the channel portion 131 in the active layer 130 may have a width L _ideal overlapping the gate electrode 140 . The width L _ideal in FIG. 15 may be an ideal width of the channel portion 131 .

In the process of providing conductivity to selected portions of the active layer 130, conductivity may be provided to portions of the channel portion 131, and the conductor-providing regions may not function as channels. The width of the conductor supply portion of the channel portion 131 can be represented by the conductor supply penetration depth ΔL. Also, a region in the channel portion 131 that does not provide conductivity and effectively acts as a channel may have an effective channel width L _eff . The effective channel width L _eff may decrease as the conductor provided penetration depth ΔL increases.

In order for the thin film transistor to perform the switching function, the effective channel width _Leff should be maintained at a certain or higher magnitude. Of course, it may be difficult to design the width of the channel portion 131 when the degree of conductor provision at the edge of the channel portion 131 is not determined. In order to ensure the effective channel width L _eff , the width of the channel portion 131 should be designed to be wide when the degree of conductor provision at the edge of the channel portion 131 is not determined. In this case, the size of the thin film transistor may increase and it may be difficult to miniaturize and highly integrate the device.

According to an embodiment of the present invention, the deviation parts 132a, 132b can be disposed between the channel part 131 and the conductor supply parts 133a, 133b and can perform a buffering function between the channel part 131 and the conductor supply parts 133a, 133b, so most of the The channel portion 131 can effectively serve as a channel. As described above, according to an embodiment of the present invention, the effective channel width L _eff can be effectively ensured, so the width of the channel portion 131 can be easily determined and designed.

According to an embodiment of the present invention, for the effective channel width _Leff , the width L2 of each deviation portion 132a, 132b can be changed according to the width L1 of the channel portion 131, and for example, each deviation portion 132a, 132b can be determined according to Equation 1. Width L2 of 132b.

16 is a graph of the total conductors of thin film transistors according to comparative examples and embodiments of the present invention providing a penetration depth 2ΔL.

Compared with the cross-sectional schematic diagram, there are conductors on both sides of the channel portion 131 to provide the penetration depth ΔL, so the total conductor provided penetration depth 2ΔL is calculated as “2 x ΔL”.

In FIG. 16, Comparative Example 1 (Comp. 1) relates to a thin film transistor that provides conductivity to a portion of the active layer 130 by using the method depicted in FIG. 14A.

In FIG. 16, Example 1 (EX. 1) relates to a thin film transistor fabricated by doping boron (B) ions using the method shown in FIG. 7, and Example 2 (EX. 2) relates to Thin film transistors fabricated by doping phosphorus (P) ions using the method depicted in FIG. 7, and Example 3 (EX.3) pertaining to doping fluorine by using the method depicted in FIG. 7 (F) Thin film transistor produced by ion.

In the thin film transistor according to Comparative Example 1 (Comp. 1), the total conductor provision penetration depth 2ΔL was about 1.0 μm, and the portion corresponding to 1.0 μm in the channel portion 131 did not serve as a channel. Therefore, the loss of the channel portion 131 region is severe.

On the other hand, according to Example 1, Example 2 and Example 3, the total conductor provided penetration depth 2ΔL is less than about 0.6 μm, and the loss in the area of the channel portion 131 is less than 1. In Example 1, Example 2, and Example 3, the loss in the region of the channel portion 131 was reduced by these uneven portions 132a, 132b.

17A-17E are graphs of threshold voltages of thin film transistors according to comparative examples and embodiments of the present invention.

17A presents the threshold voltage of the thin film transistor according to Comparative Example 1, FIG. 17B presents the threshold voltage of the thin film transistor according to Comparative Example 2, FIG. 17C presents the threshold voltage of the thin film transistor according to Example 1, and FIG. 17D presents the threshold voltage according to the implementation The threshold voltage of the thin film transistor of Example 2, and FIG. 17E presents the threshold voltage of the thin film transistor according to Example 3. I _ds in the figure represents the drain-source current of the thin film transistor, and V _gs in the figure represents the gate-source voltage of the thin film transistor.

Comparative Example 2 relates to a thin film transistor having the structure of the gate insulating layer 150 as shown in FIG. 1 but not including the deviation portions 132a, 132b due to no doping ions.

In the thin film transistors of Comparative Example 1, Comparative Example 2, and Examples 1 to 3, indium gallium zinc oxide (IGZO) was used as the oxide semiconductor for the active layer.

For the thin film transistors of Comparative Example 1, Comparative Example 2, and Examples 1 to 3, the initial threshold voltage, mobility, resistance of the bias region, positive bias temperature stress (PBTS) and negative Negative bias temperature stress (NBTS). The measurement results are presented in FIGS. 17A-17E and in Table 1 .

[Table 1] separate Initial threshold voltage Mobility (cm ² /vs) Conductor provides resistance (kΩ/sq) Forward bias temperature and voltage (30V, 1h, 60℃) Negative bias temperature and voltage (-30V, 1h, 60℃) Comparative Example 1 1.00 (0.88~1.09) 23.08 (21.87~24.29) 1.88 0.28 -0.17 Comparative Example 2 cannot measure 0.29 (0.21~0.38) cannot measure cannot measure cannot measure Example 1 0.90 (0.81~1.00) 22.62 (20.94~24.18) 2.86 0.4 -0.07 Example 2 0.92 (0.82~1.02) 22.35 (20.53~24.54) 2.94 0.36 -0.08 Example 3 0.85 (0.74~0.95) 22.72 (21.14~24.23) 4.78 0.41 -0.08

Referring to Table 1 and FIGS. 17C , 17D and 17E, the threshold voltage characteristics of the respective thin film transistors according to Examples 1 to 3 are similar to those of the thin film transistor manufactured according to the conventional method in Comparative Example 1 ( FIG. 17A ) critical voltage characteristics. On the other hand, it was confirmed that the threshold voltage characteristic of the thin film transistor according to Comparative Example 2 was very weak.

Further, referring to Table 1, it was confirmed that the mobility of each of the thin film transistors according to Examples 1 to 3 was similar to that of the thin film transistor of Comparative Example 1.

In Table 1, the conductor supply resistance represents the resistance value of each conductor supply part 133a, 133b. In Comparative Example 2, the resistance provided by the conductor could not be measured.

In Table 1, the positive bias temperature voltage represents the pressure applied to the thin film transistor, which is applied with a positive (+) bias voltage applied at a specific temperature, and the positive bias temperature voltage usually has a positive (+) value. When the forward bias temperature and voltage increase, the pressure of each active layer 130 and the thin film transistor can increase, thereby increasing the threshold voltage variation ΔVth.

The negative temperature bias represents the pressure applied to the thin film transistor, which pressure is applied with a negative (-) bias applied at a specific temperature, and the negative temperature bias usually has a negative (-) value. When the absolute value of the negative bias temperature increases, the pressure of each active layer 130 and the thin film transistor relative to the temperature may increase, thereby increasing the threshold voltage variation ΔVth and possibly reducing reliability.

Referring to Table 1, it can be confirmed that in the case where a voltage of 30 volts (V) is applied at a temperature of 60° C. for one hour, the forward bias temperature voltage of each of the thin film transistors according to Examples 1 to 3 is larger than that of the thin film of Comparative Example 1 The positive bias temperature and voltage of the transistor, and in the case where a voltage of -30 V is applied at a temperature of 60° C. for one hour, the absolute value of the negative temperature bias voltage of each thin film transistor according to Examples 1 to 3 is smaller than that of Comparative Example 1 The absolute value of the negative temperature bias of the thin film transistor.

18 is a graph of threshold voltage versus heat treatment time for thin film transistors according to comparative examples and embodiments of the present invention.

18 presents the variation of the threshold voltage of the thin film transistor with respect to the heat treatment time, and the heat treatment was performed at a temperature of 230° C. in Comparative Example 1 (Comp. 1), Example 1 (EX. 1), and Example 2 (EX. 2 ) and the thin film transistors of Example 3 (EX. 3).

In the case of continuous heat treatment of the thin film transistor for a long time, the electrical characteristics of the active layer 130 may be changed according to the influence of the insulating layer and/or similar structures disposed near the active layer 130 . In this case, the reliability of the thin film transistor may be reduced.

For example, in the case where the thin film transistor is continuously heat-treated for a long time, the conductivity of the conductor-providing portions 133a, 133b may be lost (the conductor-provided case may revert to the non-conductor case). In this case, the performance of the thin film transistor may be reduced and may be non-uniform, resulting in reduced reliability.

However, referring to FIG. 18 , it can be confirmed that the threshold voltage is not largely changed despite the heat treatment of the thin film transistors of Examples 1 to 3 of the present invention.

19 is a graph of mobility versus heat treatment time for thin film transistors according to comparative examples and embodiments of the present invention.

19 presents the change of the mobility of the thin film transistor with respect to the heat treatment time, and the heat treatment was performed at a temperature of 230° C. in Comparative Example 1 (Comp. 1), Example 1 (EX. 1), and Example 2 (EX. 2 ) and the thin film transistors of Example 3 (EX. 3).

Referring to FIG. 19, it can be confirmed that despite the heat treatment of the thin film transistors of Examples 1 to 3 of the present invention, the mobility is not greatly reduced.

Referring to FIG. 18 and FIG. 19 , it can be confirmed that the performance of the thin film transistors of Examples 1 to 3 of the present invention is not greatly reduced despite the heat treatment.

FIG. 20 is a resistivity measurement chart of thin film transistors according to comparative examples and embodiments of the present invention.

In FIG. 20 , the magnitudes corresponding to EX.1, EX.2 and EX.3 respectively represent the resistivity of the conductor providing parts 133a and 133b of the thin film transistor according to the first embodiment of the present invention, and the second embodiment of the present invention. The resistivity of the conductor supplying parts 133a and 133b of the thin film transistor, and the resistivity of the conductor supplying parts 133a and 133b of the thin film transistor according to the third embodiment of the present invention. In FIG. 20 , the magnitude corresponding to Comp. 2 represents the resistivity of the regions corresponding to the respective conductor providing portions 133a, 133b of the thin film transistor according to Comparative Example 2 in the thin film transistor according to Embodiment 1 of the present invention.

As shown in FIG. 20, the resistivity of the thin film transistors of Example 1 (EX.1), Example 2 (EX.2) and Example 3 (EX.3) of the present invention is lower than that of Comparative Example 2 (Comp. 2) The resistivity of thin film transistors. The thin film transistors according to Embodiments 1 to 3 of the present invention may have, for example, a resistivity of about 10 ⁻² to 10 ⁻³ ohm·centimeter (Ω·cm).

21 is a graph of mobility versus the amount of ions implanted in the active layer according to comparative examples and embodiments of the present invention.

In FIG. 21, the comparative example 1 (Comp. 1) represents the mobility of the thin film transistor relative to the comparative example 1, and in the comparative example 1 conductivity is provided to the part of the active through dry etching but not through ion implantation Layer 130.

In FIG. 21, Comparative Example 3 (Comp. 3) is related to a thin film transistor having the same configuration as that of Example 1 (EX. 1), and boron (B) ion as a dopant in this thin film transistor. The concentration has a maximum value in the gate insulating layer 150 . In FIG. 21, Example 4 (EX.4) relates to a thin film transistor having the same structure as Example 1 (EX.1), and the difference between boron (B) ions as a dopant in this thin film transistor is The concentration has a maximum value in the buffer layer 120 . In FIG. 21, low-concentration doping, medium-concentration doping, and high-concentration doping have been performed with the same concentration in Comparative Example 3 (Comp. 3), Example 1 (EX. 1), and Example 4 (EX. 4) doping. The medium-concentration doping results of Example 1 (EX. 1) are not discussed in FIG. 21 .

Referring to FIG. 21 , according to Example 1 (EX.1) and Example 4 (EX.4), it can be confirmed that when the amount of implanted ions changes from a low concentration to a high concentration, there is little difference in the mobility. Also, it was confirmed that the mobility of the thin film transistors of Example 1 (EX. 1) and Example 4 (EX. 4) was similar to that according to the comparative example (Comp. 1) even if the amount of implanted ions was a low concentration the mobility of thin-film transistors.

On the other hand, according to Comparative Example 3 (Comp. 3), it can be confirmed that the mobility increases when the amount of implanted ions increases from a low concentration to a high concentration. Furthermore, it was confirmed that the mobility of the thin film transistor of Comparative Example 3 (Comp. 3) was lower than that of Comparative Example (Comp. 1) or Example 1 (EX. 1) even when the amount of implanted ions was high ) and the mobility of the thin film transistors of Example 4 (EX. 4).

When the amount of implanted ions was increased so that the mobility of the thin film transistor of Comparative Example 3 (Comp. 3) was equal to the mobility of each of the thin film transistors of Example 1 (EX. 1) and Example 4 (EX. 4) , the active layer 130 may be damaged.

On the other hand, the thin film transistors according to Example 1 (EX.1) and Example 4 (EX.4) of the present invention can have good mobility even when the amount of implanted ions is low, and Doping according to ion implantation may be performed within a range preventing the active layer 130 from being damaged.

22A to 22C are graphs of threshold voltage versus width of the channel portion 131 for thin film transistors according to comparative examples and embodiments of the present invention.

22A is a graph of the threshold voltage in the thin film transistor according to Comparative Example 4, wherein the graph of the threshold voltage presents that the width of the channel portion 131 is 3 μm to 20 μm (3 μm, 3.5 μm, 4 μm, 6 μm, 10 μm, 12 μm and 20 μm), and ion doping was performed in Comparative Example 4 by using the gate electrode 140 as a mask and not using the photoresist pattern 40 (the protrusion width Loh was 0 μm).

22B is a graph of the threshold voltage in the thin film transistor according to Embodiment 1, wherein the graph of the threshold voltage shows that the width of the channel portion 131 is 3 μm to 20 μm (3 μm, 3.5 μm, 4 μm, 6 μm, 10 μm, 12 μm and 20 μm), and ion doping was performed in Example 1 by using the photoresist pattern 40 as a mask and using the protruding width Loh (see FIG. 7 ). The photoresist pattern 40 protrudes to the outside of the gate electrode 140 with a width Loh, and the width Loh is 0.5 μm.

22C is a graph of the threshold voltage in the thin film transistor according to Embodiment 5, wherein the graph of the threshold voltage shows that the width of the channel portion 131 is 3 μm to 20 μm (3 μm, 3.5 μm, 4 μm, 6 μm, 10 μm, 12 μm and 20 μm), and ion doping was performed in Example 5 by using the photoresist pattern 40 as a mask and using the protrusion width Loh (see FIG. 7 ). The photoresist pattern 40 protrudes to the outside of the gate electrode 140 with a width Loh, and the width Loh is 0.7 μm.

FIG. 23 is a graph presenting threshold voltage values versus the width (or length) of the channel portion 131 for thin film transistors according to comparative examples and embodiments of the present invention.

Referring to FIGS. 22A and 23 , in the thin film transistor according to Comparative Example 4, it can be confirmed that the threshold voltage varies with the width of the channel portion 131 . Specifically, referring to FIG. 23 , in the thin film transistor according to Comparative Example 4, it can be confirmed that the threshold voltage value is greatly changed when the width of the channel portion 131 is 4 μm or less, and the threshold voltage value is Constant for widths of 6 microns or greater.

In addition, referring to FIGS. 22B , 22C and 23 , in the thin film transistors according to Embodiment 1 and Embodiment 5 of the present invention, it can be confirmed that when the width of the channel portion 131 is changed, the drain-source current I _ds changes but the critical voltage hardly changes. Also, it was confirmed that the thin film transistors according to Example 1 and Example 5 of the present invention have excellent threshold voltage characteristics even when the width of the channel portion 131 is 3 μm and is very narrow.

24 is a graph of threshold voltage versus width (or length) of gate electrode 140 according to comparative examples and embodiments of the present invention.

According to an embodiment of the present invention, the width of the gate electrode 140 corresponds to the width of the channel portion 131 .

Referring to FIG. 24, in the thin film transistor according to the comparative example (Comp. 1), it can be confirmed that the threshold voltage varies with the width of the gate electrode 140. Specifically, referring to FIG. 23 , in the thin film transistor according to Comparative Example 1, it can be confirmed that the threshold voltage value changes very greatly when the width of the gate electrode 140 is 5 μm or less.

In addition, referring to FIG. 24 , in the thin film transistors according to Embodiment 1, Embodiment 2 and Embodiment 3 of the present invention, it can be confirmed that the threshold voltage does not change much when the width of the gate electrode 140 is changed.

FIG. 25 is a diagram showing a gap and a metal residual layer created near a gate electrode according to an embodiment of the present invention. FIG. 26 is a diagram showing a state in which no gap or metal residual layer is generated near the gate electrode according to an embodiment of the present invention.

FIG. 25 shows a case where the gate insulating layer 150 is etched together with the gate electrode 140 .

As shown in FIG. 25, in the case where the gate insulating layer 150 is etched together with the gate electrode 140, the step height between the gate electrode 140 and the active layer 130 can be increased. When the layer height between the gate electrode 140 and the active layer 130 is increased, defects such as gaps may be generated in the intermediate insulating layer 155 provided on the gate electrode 140 as shown in FIG. 25 , and thus the gate electrode may be deteriorated Insulation properties between electrode 140 and another electrode or line, thereby causing a short circuit.

In addition, as shown in FIG. 25, in the case where the gate insulating layer 150 is etched together with the gate electrode 140, the metal residual material MR1 generated during the etching process performed on the gate electrode 140 may remain on the gate insulating layer edge of the layer 150 , thereby deteriorating the insulating properties between the gate electrode 140 and the active layer 130 .

Furthermore, as shown in FIG. 25, in the case where the step height between the gate electrode 140 and the active layer 130 is increased, the step height may be created in the intermediate insulating layer 155, and the metal residual material MR2 (eg, used to form the source The metal residue material of the electrode electrode or the drain electrode) may remain on the step height, thereby reducing the performance of the thin film transistor.

On the other hand, as shown in FIG. 26, in the case where the gate insulating layer 150 is not patterned, the insulating property between the gate electrode 140 and the active layer 130 can be improved, and in addition, the gate electrode 140 and the active layer 130 can be lowered Hierarchy height between layers 130. In the case where the level height between the gate electrode 140 and the active layer 130 is reduced, the probability of generating defects such as gaps in the intermediate insulating layer 155 can be reduced. As shown in FIG. 26 , when the level of the intermediate insulating layer 155 is reduced, the probability that the metal residual material MR2 remains on the stepped portion can be reduced.

Referring to FIG. 26 , since the gate insulating layer 150 is not etched, there is no possibility that the metal residual material MR1 generated in the etching process performed on the gate electrode 140 remains on the edge of the gate insulating layer 150 .

27A to 27G are schematic process diagrams of a method for manufacturing a thin film transistor according to an embodiment of the present invention.

Referring to FIG. 27A , the buffer layer 120 may be formed on the substrate 110 , and the active layer 130 may be formed on the buffer layer 120 . The active layer 130 may include an oxide semiconductor material. In detail, the active layer 130 may be an oxide semiconductor layer.

Referring to FIG. 27B , a gate insulating layer 150 may be formed on the active layer 130 , and a gate electrode material layer 145 may be formed on the gate insulating layer 150 . The gate electrode material layer 145 may include metal.

Referring to FIG. 27C , a photoresist pattern 40 may be formed on the gate electrode material layer 145 .

The photoresist pattern 40 may be formed by coating, exposing, and producing a photoresist on the entire top surface of the gate electrode material layer 145 .

Referring to FIG. 27D, the gate electrode material layer 145 can be etched by using the photoresist pattern 40 as a mask. Thus, the gate electrode 140 can be formed.

As shown in FIG. 27D , in a plan view, the area of the photoresist pattern 40 may be larger than that of the gate electrode 140 . Due to the over-etching of the gate electrode material layer 145, the gate electrode 140 having an area smaller than that of the photoresist pattern 40 may be formed. In a plan view, the gate electrode 140 may be disposed in an area defined by the photoresist pattern 40 . The gate insulating layer 150 may cover the entire top surface of the active layer 130 .

The width of the photoresist pattern 40 can be determined according to Equation 2.

For example, when the gate electrode 140 has a width LG and the photoresist pattern 40 has a width Loh protruding from the gate electrode 140 (refer to FIG. 7 ), the width of the photoresist pattern 40 can be designed to satisfy the following Equation 2 .

[Equation 2]

LG x Loh x 1/η2 ≥ 1

where η2 = 0.5 square microns

As shown in FIGS. 27B to 27D , the process of forming the gate electrode 140 may include a process of forming the gate electrode material layer 145 on the gate insulating layer 150 ( FIG. 27B ), and forming a photoresist on the gate electrode material layer 145 The process of pattern 40 (FIG. 27C) and the process of etching gate electrode material layer 145 by using photoresist pattern 40 as a mask (FIG. 27D).

Referring to FIG. 27E, the active layer 130 may be doped with dopants.

The dopant may include at least one of boron (B), phosphorus (P), fluorine (F), and hydrogen (H).

In the dopant doping process, the photoresist pattern 40 can serve as a mask. Referring to FIG. 27E, regions of the active layer 130 not protected by the photoresist pattern 40 can be selectively doped.

Referring to FIG. 27F, a plurality of conductor providing portions 133a, 133b can be formed by doping.

According to an embodiment of the present invention, the buffer layer 120 may be doped with dopants through a doping process.

The doping concentration of the active layer 130 may be higher than the doping concentration of the gate insulating layer 150 and the doping concentration of the buffer layer 120 . Here, the doping concentration of the active layer 130 may represent the doping concentration of each of the conductor supply portions 133a and 133b.

In addition, the doping concentration of the buffer layer 120 may be higher than the doping concentration of the active layer 130 and the doping concentration of the gate insulating layer 150 .

Referring to FIG. 27G , the thin film transistor 100 can be formed by removing the photoresist pattern 40 .

Referring to FIG. 27G , the active layer 130 may include a channel portion 131 , the conductor providing portions 133 a and 133 b and a plurality of offset portions 132 a and 132 b. The channel portion 131 overlaps the gate electrode 140 . The conductor supply parts 133 a and 133 b do not overlap with the gate electrode 140 . The offset parts 132a and 132b are interposed between the channel part 131 and the conductor supply parts 133a and 133b.

The channel portion 131 and the offset portions 132 a and 132 b may each be a region overlapping the photoresist pattern 40 .

28A to 28G are schematic process diagrams of a manufacturing method of a thin film transistor according to another embodiment of the present invention.

Referring to FIG. 28A , the buffer layer 120 may be formed on the substrate 110 , and the active layer 130 may be formed on the buffer layer 120 . The active layer 130 may include an oxide semiconductor material. In detail, the active layer 130 may be an oxide semiconductor layer.

Referring to FIG. 28B , the gate insulating layer 150 may be formed on the active layer 130 . Also, a plurality of contact holes CH1 and CH2 may be formed in the gate insulating layer 150 .

Referring to FIG. 28C , a gate electrode material layer 145 may be formed on the gate insulating layer 150 , and a plurality of photoresist patterns 40 , 41 , and 42 may be formed on the gate electrode material layer 145 .

The gate electrode material layer 145 may be filled in the contact holes CH1, CH2.

Referring to FIG. 28D, the gate electrode material layer 145 can be etched by using the photoresist patterns 40, 41, 42 as masks. Therefore, the gate electrode 140, the source electrode 161, and the drain electrode 162 can be formed. Referring to FIG. 28D, the gate electrode 140, the source electrode 161 and the drain electrode 162 may be disposed in the same layer and may contain the same material.

Referring to FIG. 28E, the active layer 130 may be doped with dopants.

The dopant may include at least one of boron (B), phosphorus (P), fluorine (F), and hydrogen (H). Doping may be performed by ion implantation according to at least one of boron (B), phosphorus (P), fluorine (F) and hydrogen (H).

In the dopant doping process, the photoresist patterns 40, 41, and 42 can be used as masks. Referring to FIG. 28E, regions of the active layer 130 not protected by the photoresist patterns 40, 41, and 42 can be selectively doped.

Referring to FIG. 28F, a plurality of conductor providing portions 133a, 133b can be formed by doping.

Referring to FIG. 28G , a thin film transistor can be formed by removing the photoresist pattern 40 .

FIG. 29 is a diagram showing a display device 700 according to another embodiment of the present invention.

As shown in FIG. 29 , a display device 700 according to another embodiment of the present invention may include a display panel 310 , a gate driver 320 , a data driver 330 and a controller 340 .

The display panel 310 may include a plurality of gate lines GL, a plurality of data lines DL, and a pixel P, wherein the pixel P is provided in each of a plurality of pixel regions defined by the intersection of the gate lines GL and the data lines DL . The pixel P may include a light-emitting device 710 and a pixel driving circuit PDC (please refer to FIG. 30 ) for driving the light-emitting device 710 . The display panel 310 can display images according to the driving of the pixels P.

The controller 340 can control the gate driver 320 and the data driver 330 .

The controller 340 can output the gate control signal GCS for controlling the gate driver 320 and the data control signal DCS for controlling the data driver 330 according to the synchronization signal and the clock signal supplied from an external system (not shown). Also, the controller 340 can sample the input video data received from the external system, and can realign the sampled video data to provide the digital image data RGB to the data driver 330 .

The gate control signal GCS may include a gate start pulse (GSP), a gate offset clock (GSC), a gate output enable signal (GOE), a start signal (Vst) and a gate clock (GCLK). Also, the gate control signal GCS may include a control signal for controlling the offset recorder 350 .

The data control signal DCS may include a source start pulse (SSP), a source offset clock signal (SSC), a source output enable signal (SOE) and a polarity control signal (POL).

The data driver 330 may supply data voltages to the data lines DL of the display panel 310 . Specifically, the data driver 330 can convert the image data RGB input from the controller 340 into analog data voltages, and can provide the data voltage of one horizontal line to the data line DL in each horizontal period, and at each horizontal period A gate pulse (GP) is supplied to a gate line GL during the cycle.

Gate driver 320 may include offset recorder 350 .

The offset recorder 350 can sequentially provide a gate pulse (GP) to the gate line GL within a frame period according to the enable signal (Vst) and the gate clock (GCLK), wherein the enable signal (Vst) and the gate The pole clock (GCLK) is transmitted from the controller 340 . Here, the period of one frame may refer to the period during which the display panel 310 displays one image. The gate pulse (GP) may have a turn-on voltage for turning on a switching element (thin film transistor) provided in the pixel P.

Furthermore, in order to turn off the switching element, the offset recorder 350 may supply a gate off signal (Goff) to the gate line GL during another period of one frame, and no gate pulse (GP) is supplied during the other period . Hereinafter, the common names of the gate pulse (GP) and the gate off signal (Goff) may be SS or Scan.

According to an embodiment of the present invention, the gate driver 320 may be mounted on the display panel 310 . The structure in which the gate driver 320 is directly mounted on the display panel 310 may be referred to as a gate-in panel (GIP) structure. The gate driver 320 may include at least one of the thin film transistors 100 to 500 shown in FIGS. 1 to 5 .

FIG. 30 is a circuit diagram of one pixel P in FIG. 29 .

Referring to FIG. 30 , a pixel P included in a display apparatus 700 according to another embodiment of the present invention may include a pixel driving circuit PDC and a light emitting device 710 .

The light emitting device 710 may use an organic light emitting diode (OLED). However, the embodiments of the present invention are not limited thereto, and the light emitting device 710 may use a quantum dot light emitting device, an inorganic light emitting device, a micro light emitting diode, or the like. The light emitting device 710 can emit light using the data current supplied from the pixel driving circuit PDC.

Referring to FIG. 30, the pixel driving circuit PDC may include a first thin film transistor T1, a second thin film transistor T2, a third thin film transistor T3, a fourth thin film transistor T4, a fifth thin film transistor T5, and a sixth thin film transistor The crystal T6, the seventh thin film transistor T7 and the first capacitor C1.

The active layer of each thin film transistor (eg, the first thin film transistor T1, the third thin film transistor T3, the fourth thin film transistor T4, the fifth thin film transistor T5, and the sixth thin film transistor T6) in FIG. 30 may include The silicon semiconductor material can be formed from a silicon semiconductor layer. The active layer of each of the second thin film transistor T2 and the seventh thin film transistor T7 may include, for example, an oxide semiconductor material and may be formed of an oxide semiconductor layer.

According to another embodiment of the present invention, the first thin film transistor T1, the third thin film transistor T3, the fourth thin film transistor T4, the fifth thin film transistor T5 and the sixth thin film transistor T6 in FIG. The first thin film transistor TR1 in FIG. 6 has the same structure, and the second thin film transistor T2 and the seventh thin film transistor T7 may have the same structure as the second thin film transistor TR2 in FIG. 6 . Furthermore, at least one of the second thin film transistor T2 and the seventh thin film transistor T7 may have the same structure as at least one of the thin film transistors 100 , 200 , 300 , 400 and 500 shown in FIGS. 1 to 5 . .

According to another embodiment of the present invention, the first thin film transistor T1, the third thin film transistor T3, the fourth thin film transistor T4, the fifth thin film transistor T5 and the sixth thin film transistor T6 may be disposed on the second thin film transistor Below T2 and the seventh thin film transistor T7. In detail, the active layers of each of the first thin film transistor T1, the third thin film transistor T3, the fourth thin film transistor T4, the fifth thin film transistor T5 and the sixth thin film transistor T6 may be disposed on each of the second thin film transistors Below the active layer of the crystal T2 and the seventh thin film transistor T7.

Referring to FIG. 30 , the first thin film transistor T1 can be a driving thin film transistor, and the second thin film transistor T2 can be a switching thin film transistor.

The gate electrode G2 of the second thin film transistor T2 may be supplied with the second scan signal Scan2. The drain electrode D2 of the second thin film transistor T2 may be supplied with the data voltage Vdata. The source electrode S2 of the second thin film transistor T2 can be connected to the drain electrode D1 of the first thin film transistor T1. The second thin film transistor T2 can be turned on by the second scan signal Scan2 and can provide the data voltage Vdata to the drain electrode D1 of the first thin film transistor T1.

The gate electrode G3 of the third thin film transistor T3 may be supplied with the light emission control signal EM. The drain electrode D3 of the third thin film transistor T3 may be supplied with a high-level pixel driving voltage VDD. The source electrode S3 of the third thin film transistor T3 may be connected to the drain electrode D1 of the first thin film transistor T1. The third thin film transistor T3 can be turned on by the light emission control signal EM and can provide the high-level pixel driving voltage VDD to the drain electrode D1 of the first thin film transistor T1.

The gate electrode G7 of the seventh thin film transistor T7 may be supplied with the second scan signal Scan2. The drain electrode D7 of the seventh thin film transistor T7 may be connected to the gate electrode G1 of the first thin film transistor T1. The source electrode S7 of the seventh thin film transistor T7 may be connected to the source electrode S1 of the first thin film transistor T1. The seventh thin film transistor T7 can be turned on by the second scan signal Scan2 and can control the voltage difference between the gate electrode G1 and the source electrode S1 of the first thin film transistor T1 to drive the first thin film transistor T1.

The gate electrode G5 of the fifth thin film transistor T5 may be supplied with the first scan signal Scan1. The drain electrode D5 of the fifth thin film transistor T5 may be supplied with the initialization voltage Vini. The source electrode S5 of the fifth thin film transistor T5 may be connected to the gate electrode G1 of the first thin film transistor T1. The fifth thin film transistor T5 can be turned on by the first scan signal Scan1 and can provide the initialization voltage Vini to the gate electrode G1 of the first thin film transistor T1.

The gate electrode G4 of the fourth thin film transistor T4 may be supplied with the light emission control signal EM. The drain electrode D4 of the fourth thin film transistor T4 may be connected to the source electrode S1 of the first thin film transistor T1. The source electrode S4 of the fourth thin film transistor T4 can be connected to the pixel electrode 711 of the light emitting device 710 (please refer to FIG. 32 ). The fourth thin film transistor T4 can be turned on by the light emission control signal EM and can provide a driving current to the pixel electrode 711 of the light emitting device 710 . Here, the light emitting device 710 can be an organic light emitting diode, and the pixel electrode 711 can be an anode of the organic light emitting diode.

The gate electrode G6 of the sixth thin film transistor T6 may be supplied with the first scan signal Scan1. The drain electrode D6 of the sixth thin film transistor T6 may be supplied with the initialization voltage Vini. The source electrode S6 of the sixth thin film transistor T6 may be connected to the pixel electrode 711 of the light emitting device 710 . The sixth thin film transistor T6 can be turned on by the first scan signal Scan1 and can provide the initialization voltage Vini to the pixel electrode 711 of the light emitting device 710 .

The gate electrode G1 of the first thin film transistor T1 can be connected to the drain electrode D7 of the seventh thin film transistor T7. The source electrode S1 of the first thin film transistor T1 may be connected to the source electrode S7 of the seventh thin film transistor T7. The first thin film transistor T1 can be turned on by the voltage difference between the source electrode S7 and the drain electrode D7 of the seventh thin film transistor T7 , and can provide a driving current to the light emitting device 710 .

One side of the first capacitor C1 may be supplied with a high-level pixel driving voltage VDD. The other side of the first capacitor C1 may be connected to the gate electrode G1 of the first thin film transistor T1. The first capacitor C1 can store the voltage on the gate electrode G1 of the first thin film transistor T1.

The pixel electrode 711 of the light emitting device 710 can be connected to the source electrode S4 of the fourth thin film transistor T4 and the source electrode S6 of the sixth thin film transistor T6. The common electrode 713 (refer to FIG. 32 ) of the light emitting device 710 may be supplied with the low-level driving voltage VSS. The light emitting device 710 can emit light with brightness according to the driving current flowing in the first thin film transistor T1.

Referring to FIG. 30 , when the fifth thin film transistor T5 that provides the initialization voltage Vini is turned on, the pixel driving circuit PDC can use the light emission control signal and the scan signal to close the connection to the source electrode S1 of the first thin film transistor T1 The fourth thin film transistor T4 to the pixel electrode 711 of the light emitting device 710 prevents the driving current of the first thin film transistor T1 from flowing to the pixel electrode 711 of the light emitting device 710 and can constitute a pixel circuit so that the pixel electrode 711 is not affected by Voltage effects other than the voltage used to reset the anode (pixel electrode).

The initialization voltage Vini may be supplied to the pixel electrode 711 of the light emitting device 710 in a state where the fourth thin film transistor T4 is turned off, wherein the fourth thin film transistor T4 is provided at the pixel electrode 711 of the light emitting device 710 and the first thin film transistor T1 between and controlled by the light-emitting control signal EM. The sixth thin film transistor T6 for providing the initialization voltage Vini can be connected to the pixel electrode 711 of the light emitting device 710 .

FIG. 31 is a plan view of the pixel P in FIG. 30 , and FIG. 32 is a schematic cross-sectional view along the secant line II′ in FIG. 31 .

Referring to FIGS. 30 , 31 and 32 , a display apparatus 700 according to another embodiment of the present invention may include a substrate (or base substrate) 110 , a pixel driving circuit PDC, a light emitting device 710 and a pixel driving circuit PDC. The pixel driving circuit PDC is located on the substrate 110 . The light emitting device 710 is connected to the pixel driving circuit PDC. The pixel driving circuit PDC may include thin film transistors. The pixel driving circuit PDC may include at least one of the thin film transistors 100 to 500 in FIGS. 1 to 5 .

Hereinafter, the structure of the pixel P will be described in detail with reference to FIGS. 31 and 32 .

Referring to FIG. 32 , the buffer layer 120 may be disposed on the substrate 110 , and the first active layer 270 may be disposed on the buffer layer 120 . The first active layer 270 may include a silicon semiconductor material. For example, the first active layer 270 may be formed of a polysilicon semiconductor layer.

A portion of the first active layer 270 may include the channel portion A1 of the first thin film transistor T1 and the channel portion A4 of the fourth thin film transistor T4, and another portion of the first active layer 270 may have conductivity and may serve as a line. Although not shown, another portion of the first active layer 270 may include channel portions of each of the third thin film transistor T3 , the fifth thin film transistor T5 and the sixth thin film transistor T6 .

The gate insulating layer 181 may be disposed on the first active layer 270 .

The first gate electrode G1 of the first thin film transistor T1 and the fourth gate electrode G4 of the fourth thin film transistor T4 may be disposed on the gate insulating layer 181 . The first gate electrode G1 may serve as the first electrode CE1 of the first capacitor C1.

The gate insulating layer 181 located between the first active layer 270 and the first gate electrode G1 may be referred to as a first gate insulating layer.

The passivation layer 182 may be disposed on the gate electrodes G1, G4 and the first electrode CE1 of the first capacitor C1.

The second electrode CE2 of the first capacitor C1 may be disposed on the passivation layer 182 . Therefore, the first capacitor C1 can be completed.

The intermediate layer 185 may be disposed on the second electrode CE2 of the first capacitor C1. The intermediate layer 185 may be an organic material layer used to planarize the top of the second electrode CE2 of the first capacitor C1. However, the present invention is not limited thereto, and the intermediate layer 185 may be formed of a single-layer structure, including silicon nitride (SiN _x ) or silicon oxide (SiO _x ), or formed of the above-mentioned multi-layer structure.

The second active layer 230 may be disposed on the intermediate layer 185 and may include an oxide semiconductor material. The second active layer 230 may be an oxide semiconductor layer.

For example, the second active layer 230 may be formed of an oxide semiconductor layer and may include a channel portion 231 and a plurality of conductor supply portions 233a, 233b. Also, the second active layer 230 may include a plurality of offset portions 232a, 232b disposed between the channel portion 231 and the conductor providing portions 233a, 233b.

A portion of the second active layer 230 may include the channel portion A2 of the second thin film transistor T2, and another portion of the second active layer 230 may have conductivity and may serve as a line. In detail, the conductor providing parts 233a and 233b of the second active layer 230 can each serve as a line.

A portion of the second active layer 230 may include the channel portion of the seventh thin film transistor T7.

According to another embodiment of the present invention, at least one of the thin film transistors 100 to 500 shown in FIGS. 1 to 5 can be applied to the second thin film transistor T2 and the first thin film transistor T2 of the display device 700 according to another embodiment of the present invention At least one of seven thin film transistors T7.

The gate insulating layer 150 may be disposed on the second active layer 230 . Referring to FIG. 32 , the gate insulating layer 150 may cover the top surface of the second active layer 230 . The gate insulating layer 150 may be disposed on the entire surface of the substrate 110 including the second active layer 230 .

The second gate electrode G2 of the second thin film transistor T2 may be disposed on the gate insulating layer 150 . The second gate electrode G2 may overlap the channel portion A2 of the second thin film transistor T2. For example, the second gate electrode G2 may overlap the channel portion 231 of the second active layer 230 and may not overlap the conductor providing portions 233a, 233b and the deviation portions 232a, 232b.

The gate insulating layer 150 located between the second active layer 230 and the second gate electrode G2 may be referred to as a second gate insulating layer.

The intermediate insulating layer 155 may be disposed on the second gate electrode G2 of the second thin film transistor T2. The intermediate insulating layer 155 may include insulating material.

The source electrodes and drain electrodes of the first thin film transistor T1 to the seventh thin film transistor T7 may be disposed on the intermediate insulating layer 155, and a plurality of bridges for connecting electrodes to lines may be disposed on the intermediate insulating layer on layer 155.

In addition, the data line DL and the pixel driving voltage line PL may be disposed on the intermediate insulating layer 155 . The data voltage Vdata can be supplied through the data line DL, and the high-level pixel driving voltage VDD can be supplied through the pixel driving voltage line PL.

The source electrodes S1, S2, S4 and the drain electrodes D1, D2, D4 can be connected to the first active layer 270 or the second active layer 230 through contact holes. For example, the fourth source electrode S4 of the fourth thin film transistor T4 can be connected to the first active layer 270 through the first contact hole CH1. In addition, the fourth drain electrode D4 of the fourth thin film transistor T4 can be connected to the first active layer 270 through the second contact hole CH2. In addition, the second source electrode S2 of the second thin film transistor T2 can be connected to the second active layer 230 through the third contact hole CH3. In addition, the second drain electrode D2 of the second thin film transistor T2 can be connected to the second active layer 230 through the fourth contact hole CH4.

Referring to FIG. 32 , an intermediate insulating layer 155 may be formed, and then a first contact hole CH1 , a second contact hole CH2 , a third contact hole CH3 , and a fourth contact hole CH1 , a second contact hole CH2 , a third contact hole CH3 and a fourth contact hole each exposing the first active layer 270 and the second active layer 230 may be formed Contact hole CH4. In addition, after forming the first contact hole CH1 , the second contact hole CH2 , the third contact hole CH3 and the fourth contact hole CH4 , in order to dehydrogenate the first active layer 270 including polysilicon, the temperature can be adjusted at 350° C. or Higher temperature for high temperature heat treatment process. Oxygen vacancy may be generated in the second active layer 230 including the oxide semiconductor due to the high temperature heat treatment process. Also, dopants such as boron (B), phosphorus (P), fluorine (F) and hydrogen (H) can be diffused through oxygen vacancies, so the conductor providing region can extend to the channel portion A2 of the second active layer 230 . Therefore, since the high-temperature heat treatment process is performed at 350° C. or higher, the conductor providing region may be extended, and the second thin film transistor T2 may be deteriorated.

Therefore, when manufacturing the display device 700 including the fourth thin film transistor T4 and the second thin film transistor T2, the process of exposing the first active layer 270 and the second active layer 230 and the high temperature heat treatment process may be performed to provide conductivity The ion doping process for the second active layer 230, wherein the fourth thin film transistor T4 includes polysilicon and the second thin film transistor T2 includes oxide semiconductor.

FIGS. 33A to 33C are schematic process diagrams of some processes performed on the second thin film transistor T2 corresponding to the region A in FIG. 32 .

Referring to FIG. 33A , the second active layer 230 may be formed on the intermediate layer 185 . Also, the gate insulating layer 150 may be formed on the second active layer 230 . Also, the gate electrode G2 may be formed on the gate insulating layer 150 . The intermediate insulating layer 155 may be formed on the gate electrode G2 and the gate insulating layer 150 . Also, as shown in FIG. 33A , a photoresist pattern 50 may be formed in order to form a contact hole for exposing the second active layer 230 . In order to form the contact holes, the photoresist pattern 50 may include open regions exposing the top surface of the interlayer insulating layer 155 . Furthermore, in order to form contact holes through the opening regions of the photoresist pattern 50, an etching process may be performed. The intermediate insulating layer 155 and the gate insulating layer 150 may be removed through an etching process.

As shown in FIG. 33B , a third contact hole CH3 and a fourth contact hole CH4 respectively exposing the second active layer 230 can be formed in the intermediate insulating layer 155 and the gate insulating layer 150a by performing an etching process. The first contact hole CH1 and the second contact hole CH2 each exposing the first active layer 270 of the fourth thin film transistor T4 may be formed in the etching process. As described above, after the first contact hole CH1 , the second contact hole CH2 , the third contact hole CH3 and the fourth contact hole CH4 are formed, the first active layer 270 may be dehydrogenated at a high temperature of 350° C. or higher. High temperature heat treatment process.

Subsequently, as shown in FIG. 33C, after the high temperature heat treatment process, an ion doping process may be performed by using the gate electrode G2 as a mask.

In addition, a plurality of conductor supply portions 233a and 233b having conductivity according to the ion doping process and the channel portion 231 overlapping the gate electrode G2 can be formed in the second active layer 230 through the ion doping process.

In addition, as shown in FIG. 32 , the source electrode S2 and the drain electrode D2 of the second thin film transistor T2 and the source electrode S4 and the drain electrode D4 of the fourth thin film transistor T4 may be formed. In addition, the source electrode S2 and the drain electrode D2 of the second thin film transistor T2 can be connected to the second active layer 230 through the third contact hole CH3 and the fourth contact hole CH4. In addition, the source electrode S4 and the drain electrode D4 of the fourth thin film transistor T4 can be connected to the first active layer 270 through the first contact hole CH1 and the second contact hole CH2.

The source electrodes S1 and S4 and the drain electrodes D1 and D4 respectively connected to the first active layer 270 and the source electrode S2 and the drain electrode D2 respectively connected to the second active layer 230 can be simultaneously formed through the same process.

The planarization layer 192 may be disposed on the source electrodes S1, S2, S4, the drain electrodes D1, D2, D4, the bridge, the data line DL and the pixel driving voltage line PL.

The pixel electrode 711 of the light emitting device 710 may be disposed on the planarization layer 192 . The pixel electrode 711 may be referred to as an anode electrode or a first electrode. The pixel electrode 711 may be connected to the first active layer 270 . Please refer to FIG. 30 and FIG. 31 , the pixel electrode 711 can be connected to the first active layer 270 through the fourth source electrode S4 of the fourth thin film transistor T4.

The bank layer 750 may be disposed on the edge of the pixel electrode 711 . The bank layer 750 may define a light-emitting region of the light-emitting device 710 .

The light-emitting layer 712 may be disposed on the pixel electrode 711 , and the common electrode 713 may be disposed on the light-emitting layer 712 . The common electrode 713 may be referred to as a cathode electrode or a second electrode. Thus, the light emitting device 710 can be completed. The light emitting device 710 in FIG. 32 may be an organic light emitting diode, and the display apparatus 700 according to another embodiment of the present invention may be an organic light emitting display apparatus.

FIG. 34 is a circuit diagram of one pixel P of a display device 800 according to another embodiment of the present invention.

The pixel P of the display apparatus 800 shown in FIG. 34 may include an organic light emitting diode as the light emitting device 710 and a pixel driving circuit PDC for driving the light emitting device 710 . The light emitting device 710 can be connected to the pixel driving circuit PDC.

The pixel driving circuit PDC can be connected to the gate line GL, the initialization control line ICL, the data line DL, the pixel driving voltage line PL and the initialization voltage line IL, and can supply the data current to the light-emitting device 710, wherein the data current corresponds to the supplied The data voltage Vdata to the data line DL.

The data voltage Vdata may be supplied to the data line DL, the scan signal SS may be supplied to the gate line GL, the pixel driving voltage VDD may be supplied to the pixel driving voltage line PL, the initialization voltage Vini may be supplied to the initialization voltage line IL, and The initialization control signal ICS may be supplied to the initialization control line ICL.

Referring to FIG. 34, when the gate line of the nth pixel P is represented by GLn, the gate line of the n-1th pixel P adjacent to it can be represented by GLn-1, and the gate line of the n-1th pixel P is represented by GLn-1. The gate line GLn-1 can be used as the initialization control line ICL of the nth pixel P.

As shown in FIG. 34 , the pixel driving circuit PDC may include, for example, a second thin film transistor T2 , a first thin film transistor T1 and a third thin film transistor T3 . The second thin film transistor T2 (switching transistor) is connected to the gate line GL and the data line DL. The first thin film transistor T1 (driving transistor) is used to control the level of the current output to the light emitting device 710 based on the data voltage Vdata transmitted through the second thin film transistor T2. The third thin film transistor T3 (initialization transistor) is used to sense the characteristics of the first thin film transistor T1.

The first capacitor C1 may be disposed between the gate electrode of the first thin film transistor T1 and the light emitting device 710 . The first capacitor C1 may be referred to as a storage capacitor (Cst).

The second thin film transistor T2 can be turned on by the scan signal SS supplied through the gate line GL, and can transmit the data voltage Vdata supplied through the data line DL to the gate electrode of the first thin film transistor T1.

The third thin film transistor T3 can be connected to the initialization voltage line IL and the first node n1 between the first thin film transistor T1 and the light emitting device 710, and can be turned on or off by the initialization control signal ICS, so as to be in the sensing period The characteristics of the first thin film transistor T1 (driving transistor) are sensed.

The second node n2 connected to the gate electrode of the first thin film transistor T1 can be connected to the second thin film transistor T2. The first capacitor C1 may be formed between the second node n2 and the first node n1.

When the second thin film transistor T2 is turned on, the data voltage Vdata supplied through the data line DL can be supplied to the gate electrode of the first thin film transistor T1. The data voltage Vdata can be charged into the capacitor C1 formed between the gate electrode and the source electrode of the first thin film transistor T1.

When the first thin film transistor T1 is turned on, the current can be transmitted from the pixel driving voltage VDD through the first thin film transistor T1 , and then light can be emitted from the light emitting device 710 .

FIG. 35 is a circuit diagram of a pixel P of a display device 900 according to another embodiment of the present invention.

The pixel P of the display apparatus 900 shown in FIG. 35 may include an organic light emitting diode as the light emitting device 710 and a pixel driving circuit PDC for driving the light emitting device 710 .

The pixel driving circuit PDC may include a plurality of thin film transistors (eg, first to fourth thin film transistors) T1 to T4.

A signal line (a data line DL, a light emission control line EL, a gate line GL, a pixel driving voltage line PL, an initialization control line ICL, and an initialization voltage line) for supplying a plurality of driving signals to the pixel driving circuit PDC can be provided in the pixel P. line IL).

Compared with the pixel P in FIG. 34 , the pixel P in FIG. 35 may further include an emission control line EL. The lighting control signal EM may be supplied to the lighting control line EL. Moreover, compared with the pixel driving circuit PDC in FIG. 34 , the pixel driving circuit PDC in FIG. 35 may further include a third thin film transistor T3 , and the third thin film transistor T3 is used for controlling the first thin film transistor T1 Light-emitting control transistor for light-emitting time.

Of course, another embodiment of the present invention is not limited thereto. The pixel driving circuit PDC may be provided in various structures other than those described above. The pixel driving circuit PDC may include, for example, five or six thin film transistors.

Referring to FIG. 35, when the gate line of the nth pixel P is represented by GLn, the gate line of the n-1th pixel P adjacent to it can be represented by GLn-1, and the gate line of the n-1th pixel P is represented by GLn-1. The gate line GLn-1 can be used as the initialization control line ICL of the nth pixel P.

The first capacitor C1 may be disposed between the gate electrode of the first thin film transistor T1 and one electrode of the light emitting device 710 . Also, the second capacitor C2 may be disposed between the electrode of the light emitting device 710 and one of the terminals of the third thin film transistor T3 to which the pixel driving voltage VDD is supplied.

The second thin film transistor T2 can be turned on by the scan signal SS supplied through the gate line GL, and can transmit the data voltage Vdata supplied through the data line DL to the gate electrode of the first thin film transistor T1.

The fourth thin film transistor T4 can be connected to the initialization voltage line IL and can be turned on or off by the initialization control signal ICS, so as to sense the characteristics of the first thin film transistor T1 (driving transistor) during the sensing period.

According to the light emission control signal EM, the third thin film transistor T3 can transmit the pixel driving voltage VDD to the first thin film transistor T1 or can cut off the pixel driving voltage VDD. When the third thin film transistor T3 is turned on, a current may be supplied to the first thin film transistor T1 , which in turn may emit light from the light emitting device 710 .

According to another embodiment of the present invention, the second thin film transistor T2 and the third thin film transistor T3 may overlap each other, and a shield electrode may be disposed between the second thin film transistor T2 and the third thin film transistor T3 . The shield electrode can be connected to the light emission control line EL. Also, the gate line GL and the light emission control line EL may overlap with each other.

FIG. 36 is a schematic cross-sectional view illustrating another embodiment of the present invention.

Please refer to FIG. 36 , which only shows a schematic cross-sectional view of each of the second thin film transistor T2 and the fourth thin film transistor T4 according to an embodiment of the present invention.

The display device 10 according to an embodiment of the present invention may include a substrate 110 , a first buffer layer 111 , a first gate insulating layer 112 , a first intermediate insulating layer 113 , a second buffer layer 114 , and a second gate The polar insulating layer 115, a second intermediate insulating layer 116, a passivation layer 117, a bank layer 750, a light emitting device 710, a package (not shown), a second thin film transistor T2 and a fourth thin film transistor T4.

The substrate 110 may support various elements of the display device 10 . The substrate 110 may include a flexible glass or plastic material. In the case where the substrate 110 includes a plastic material, the substrate 110 may include, for example, polyimide (PI). In the case where the substrate 110 includes polyimide, the process of the display device 10 may be performed with a support substrate including glass disposed under the substrate 110 , and after the process of the display device 10 is completed, the support substrate may be released. And, after the supporting substrate is released, a back plate for supporting the substrate 110 may be disposed under the substrate 110 .

In the case where the substrate 110 includes polyimide, the water component may pass through the substrate 110 including polyimide, and may penetrate into the thin film transistor or the light-emitting device 710, thereby reducing the performance of the display device 10. efficacy. In order to prevent the performance of the display device 10 from being reduced due to the penetration of water, the display device 10 according to another embodiment of the present invention may include a double-layered polyimide. In addition, an inorganic insulating layer can be formed between the two polyimides, which can prevent water components from passing through the underlying polyimides, thereby improving the reliability of the display device.

In addition, in the case where the inorganic insulating layer is formed between two polyimides, the charge charged to the polyimide disposed at the bottom can form a back bias to affect the second thin film transistor T2 Or the fourth thin film transistor T4. Therefore, in order to prevent charge charging into the polyimide, it may be necessary to form a separate metal layer. However, in the display device 10 according to another embodiment of the present invention, since the inorganic insulating layer is formed between the two polyimides, the inorganic insulating layer can block charges from being charged to the polyimide disposed at the bottom, thereby further Improve product reliability. The inorganic insulating layer may be formed of a single-layer structure, including silicon nitride (SiN _x ) or silicon oxide (SiO _x ), or may be formed of a multi-layer structure as described above. For example, the inorganic insulating layer may include silicon dioxide (SiO ₂ ). In addition, the process of forming a metal layer in order to block the charge from being charged to the polyimide can be omitted, thereby simplifying the process and reducing the manufacturing cost.

The first buffer layer 111 may be formed on the entire surface of the substrate 110 . The first buffer layer 111 may be formed of a single-layer structure including silicon nitride (SiN _x ) or silicon oxide (SiO _x ), or may be formed of the above-mentioned multi-layer structure. According to an embodiment of the present invention, the first buffer layer 111 may be formed of a multi-layer structure in which silicon nitride (SiN _x ) and silicon oxide (SiO _x ) are alternately formed. For example, the first buffer layer 111 may be formed of n+1 layers. Here, n can be an even number, such as 0, 2, 4, 6 and 8. Therefore, when n is 0, the first buffer layer 111 may be formed of a single-layer structure. Also, the first buffer layer 111 may include silicon nitride (SiN _x ) or silicon oxide (SiO _x ). When n is 2, the first buffer layer 111 may be formed of a three-layer structure. In the case where the first buffer layer 111 is formed of a three-layer structure, the top layer and the bottom layer may include silicon oxide (SiO _x ), and the intermediate layer disposed between the top layer and the bottom layer may include silicon nitride (SiN _x ). When n is 4, the first buffer layer 111 may be formed of a quadruple layer.

As described above, in the case where the first buffer layer 111 is formed of a multi-layer structure in which silicon nitride (SiN _x ) and silicon oxide (SiO _x ) are alternately formed, the topmost layer and the bottommost layer of the first buffer layer 111 may include silicon oxide ( _SiOx ). For example, the first buffer layer 111 including a plurality of layers may include a top layer contacting the first active layer 270 of the fourth thin film transistor T4, a bottom layer contacting the substrate 110, and an intermediate layer disposed between the top layer and the bottom layer . Also, the top layer and the bottom layer may include silicon oxide (SiO _x ). Also, the thickness of the top layer of the first buffer layer 111 formed by the multi-layer structure may be greater than the thicknesses of the respective bottom layers and the intermediate layers.

The fourth thin film transistor T4 may be disposed on the first buffer layer 111 . The fourth thin film transistor T4 may include a first active layer 270, a fourth gate electrode G4, a fourth source electrode S4, and a fourth drain electrode D4. However, this embodiment is not limited to this, and the fourth source electrode S4 can be a drain electrode and the fourth drain electrode D4 can be a source electrode.

The first active layer 270 of the fourth thin film transistor T4 may be disposed on the first buffer layer 111 . The first active layer 270 may include polysilicon. For example, the first active layer 270 may include low temperature polysilicon (LTPS).

The polysilicon material can have a high mobility of 100 cm ² /Vs or higher, and can have low power consumption and good reliability, so that the polysilicon material can be applied to multiplexers (MUX) and/or gates Drivers, multiplexers (MUXs) and/or gate drivers are used to drive driving elements for driving thin film transistors for display pixels. Also, in the display device according to an embodiment, the polysilicon material can be used as the semiconductor pattern of the switching thin film transistor, but it is not limited thereto. For example, polysilicon materials can be used as semiconductor patterns for driving thin film transistors. In the display device according to an embodiment of the present invention, the fourth thin film transistor T4 comprising polysilicon may be a driving thin film transistor that is electrically connected to the pixel electrode 711 to transmit current to the light emitting device 710 .

The first active layer 270 may include a fourth channel region 270C, a fourth source region 270S and a fourth drain region 270D. A channel for driving the fourth thin film transistor T4 is formed in the fourth channel region 270C. The fourth source region 270S and the fourth drain region 270D are respectively provided on both sides of the fourth channel region 270C. The fourth source region 270S may be a portion of the first active layer 270 connected to the fourth source electrode S4, and the fourth drain region 270D may be a portion of the first active layer 270 connected to the fourth drain electrode D4 .

The first gate insulating layer 112 may be disposed on the first active layer 270 of the fourth thin film transistor T4. The first gate insulating layer 112 may be formed of a single-layer structure including silicon nitride (SiN _x ) or silicon oxide (SiO _x ), or may be formed of the above-mentioned multi-layer structure.

The fourth gate electrode G4 of the fourth thin film transistor T4 may be disposed on the first gate insulating layer 112 . The fourth gate electrode G4 may be formed of a single-layer structure or a multi-layer structure including molybdenum (Mo), copper (Cu), titanium (Ti), aluminum (Al), chromium (Cr), gold (Au), nickel (Ni) ) and neodymium (Nd) or one of the above alloys. The fourth gate electrode G4 may overlap the fourth channel region 270C of the first active layer 270 and the first gate insulating layer 112 is located between the fourth gate electrode G4 and the fourth channel region 270C.

The first intermediate insulating layer 113 may be disposed on the first gate insulating layer 112 and the fourth gate electrode G4. The first intermediate insulating layer 113 may be formed of a single-layer structure including silicon nitride (SiN _x ) or silicon oxide (SiO _x ), or may be formed of the above-mentioned multi-layer structure.

The second buffer layer 114 may be formed on the first intermediate insulating layer 113 . The second buffer layer 114 may be formed of a single-layer structure including silicon nitride (SiN _x ) or silicon oxide (SiO _x ), or may be formed of the above-mentioned multi-layer structure.

The second active layer 230 of the second thin film transistor T2 may be disposed on the second buffer layer 114 . The second active layer 230 may include an oxide semiconductor pattern, and the oxide semiconductor pattern includes an oxide semiconductor. The second thin film transistor T2 may include a second active layer 230, a second gate electrode G2, a second source electrode S2 and a second drain electrode D2. In another example, the second source electrode S2 may be a drain electrode and the second drain electrode D2 may be a source electrode. The second active layer 230 may include a second channel region 230C, a second source region 230S and a second drain region 230D. A channel for driving the second thin film transistor T2 is formed in the second channel region 230C. The second source region 230S and the second drain region 230D are respectively provided on both sides of the second channel region 230C. The second source region 230S may be a portion of the second active layer 230 connected to the second source electrode S2, and the second drain region 230D may be a portion of the second active layer 230 connected to the second drain electrode D2 .

The oxide semiconductor material of the second active layer 230 can be a material with an energy band gap higher than that of the polysilicon material, so that electrons do not need to pass through the energy band gap in the off state, so that the off current ( off-current) can be low. Therefore, the thin film transistor including the active layer including the oxide semiconductor may be suitable for the switching thin film transistor with short turn-on time and long turn-off time, but the present invention is not limited thereto. For example, thin film transistors can be used as driving thin film transistors. Also, the off current can be low, and the size of the auxiliary capacitor can be reduced, thereby making the thin film transistor suitable for high-resolution display devices. Referring to FIG. 36, the second thin film transistor T2 including an oxide semiconductor may be a switching thin film transistor that performs switching functions such as on/off control.

The second gate insulating layer 115 may be formed on the second active layer 230 and the second buffer layer 114 . The second gate insulating layer 115 may be formed of a single-layer structure including silicon nitride (SiN _x ) or silicon oxide (SiO _x ), or may be formed of the above-mentioned multi-layer structure.

The second gate electrode G2 may be formed on the second gate insulating layer 115 . The second gate electrode G2 may overlap the second channel region 230C of the second active layer 230 , and the second gate insulating layer 115 is located between the second gate electrode G2 and the second channel region 230C. Also, the second gate electrode G2 may be formed of a single-layer structure or a multi-layer structure including molybdenum (Mo), copper (Cu), titanium (Ti), aluminum (Al), chromium (Cr), gold (Au), nickel (Ni) and neodymium (Nd) or one of the above alloys.

The second intermediate insulating layer 116 may be formed on the second gate electrode G2 and the second gate insulating layer 115 . The second interlayer insulating layer 116 may be formed of a single-layer structure including silicon nitride (SiN _x ) or silicon oxide (SiO _x ), or may be formed of the above-mentioned multi-layer structure.

may be formed by etching the second intermediate insulating layer 116 , the second gate insulating layer 115 , the second buffer layer 114 , the first intermediate insulating layer 113 and the first gate insulating layer 112 for exposing the fourth thin film transistor T4 contact holes of the first active layer 270 . Therefore, a plurality of contact holes (eg, first and second contact holes) CH1 and CH2 exposing the fourth source region 270S and the fourth drain region 270D of the first active layer 270 can be formed.

In addition, a contact hole for exposing the second active layer 230 of the second thin film transistor T2 may be formed by etching the second intermediate insulating layer 116 and the second gate insulating layer 115 . Therefore, a plurality of contact holes CH3 and CH4 (eg, third and fourth contact holes) exposing the second source region 230S and the second drain region 230D of the second active layer 230 can be formed.

In addition, a high temperature heat treatment process may be performed through the first contact hole CH1 and the second contact hole CH2 in order to dehydrogenate the first active layer 27 . For example, the high temperature heat treatment process can be performed in the chamber at a temperature of 350° C. or higher for one hour. Subsequently, in order to provide conductivity to the second source region 230S and the second drain region 230D of the second active layer 230, an ion doping process may be performed. The dopant used in the ion doping process may include at least one of boron (B), phosphorus (P), fluorine (F) and hydrogen (H).

The second source electrode S2 and the second drain electrode D2 of the second thin film transistor T2 and the fourth source electrode S4 and the fourth drain electrode D4 of the fourth thin film transistor T4 may be disposed on the second intermediate insulating layer 116 superior.

The fourth source electrode S4 and the fourth drain electrode D4 of the fourth thin film transistor T4 can be connected to the fourth source region 270S and the fourth source region 270S of the first active layer 270 through the first contact hole CH1 and the second contact hole CH2 The drain region 270D, wherein the first contact hole CH1 and the second contact hole CH2 are respectively formed in the second intermediate insulating layer 116 , the second gate insulating layer 115 , the second buffer layer 114 , the first intermediate insulating layer 113 and the first in the gate insulating layer 112 .

The second source electrode S2 and the second drain electrode D2 of the second thin film transistor T2 can be connected to the second source region 230S and the second source region 230S of the second active layer 230 through the third contact hole CH3 and the fourth contact hole CH4 In the drain region 230D, the third contact hole CH3 and the fourth contact hole CH4 are respectively formed in the second intermediate insulating layer 116 and the second gate insulating layer 115 .

The second source electrode S2 and the second drain electrode D2 of the second thin film transistor T2 and the fourth source electrode S4 and the fourth drain electrode D4 of the fourth thin film transistor T4 may include the same material and may be disposed in on the same layer. In addition, the second source electrode S2 and the second drain electrode D2 of the second thin film transistor T2 and the fourth source electrode S4 and the fourth drain electrode D4 of the fourth thin film transistor T4 may have a single-layer structure or a multi-layer structure Form, which includes molybdenum (Mo), copper (Cu), titanium (Ti), aluminum (Al), chromium (Cr), gold (Au), nickel (Ni) and neodymium (Nd) or one of the above alloys .

The process of forming the third contact hole CH3 and the fourth contact hole CH4 for exposing the second active layer 230 , the high-temperature heat treatment process, and the forming of the second source electrode of the second active layer 230 will be described in detail below with reference to FIGS. 37A to 37D . The ion doping process of the region 230S and the second drain region 230D. 37A to FIG. 37D are schematic cross-sectional views illustrating the region B of the second thin film transistor T2 shown in FIG. 36 in detail.

Referring to FIG. 37A , for the etching process, a photoresist (PR) pattern 60 may be formed on the second interlayer insulating layer 116 . The photoresist pattern 60 may include a second photoresist pattern 62 , a first photoresist pattern 61 and a third photoresist pattern 63 . The second photoresist pattern 62 overlaps the second gate electrode G2. The first photoresist pattern 61 is separated from the left surface of the second photoresist pattern 62 . The third photoresist pattern 63 is separated from the right surface of the second photoresist pattern 62 .

One side of the first photoresist pattern 61 and the second photoresist pattern 62 may be separated from each other and a first opening OP1 may be formed, wherein the first opening OP1 exposes the second source region 230S corresponding to the second active layer 230 the top surface of the second intermediate insulating layer 116 . In addition, the other side surfaces of the second photoresist pattern 62 and the third photoresist pattern 63 may be separated from each other and a second opening OP2 may be formed, wherein the second opening OP2 exposes the second drain corresponding to the second active layer 230 . The top surface of the second intermediate insulating layer 116 of the pole region 230D.

Referring to FIG. 37B , the second interlayer insulating layer 116 exposed through the first opening OP1 and the second opening OP2 may be removed through an etching process. Also, the second gate insulating layer 115 formed under the second intermediate insulating layer 116 can be removed through an etching process. As described above, the contact hole can be formed by removing the insulating layer corresponding to the region exposed to the first opening portion OP1 and the second opening portion OP2 by using the photoresist pattern 60 as a mask. For example, the third contact hole CH3 exposing the second active layer 230 may be formed by etching the second gate insulating layer 115 and the second intermediate insulating layer 116 corresponding to the first opening portion OP1. Also, the fourth contact hole CH4 exposing the second active layer 230 may be formed by etching the second gate insulating layer 115 and the second intermediate insulating layer 116 corresponding to the second opening portion OP2.

As shown in FIG. 37C , after the third contact hole CH3 and the fourth contact hole CH4 are formed, the photoresist pattern 60 may be removed by an ashing process. Also, a high temperature heat treatment process can be performed at a high temperature of 350°C or higher. Referring to FIG. 36 , a high temperature heat treatment process may be performed in order to dehydrogenate or crystallize the first active layer 270 .

Then, referring to FIG. 37D , a doping mask pattern 70 overlapping the second gate electrode G2 of the second thin film transistor T2 can be formed. The doping mask pattern 70 may be a photoresist pattern including a photoresist. As shown in FIG. 37D, the doping process can be performed by using the doping mask pattern 70 as a mask. The doping process may be a doping process using a dopant, and the dopant may include at least one of boron (B), phosphorus (P), fluorine (F), and hydrogen (H). The second active layer 230 does not overlap the doping mask pattern 70 through doping and may have conductivity. Therefore, the second active layer 230 of the second thin film transistor T2 may include a plurality of conductor providing parts 233a, 233b. Also, the second channel region 230C of the second active layer 230 may not be doped. In order to prevent the second channel region 230C from being doped, the doping mask pattern 70 can prevent dopants from being implanted into the second channel region 230C during the doping process. Therefore, the doping mask pattern 70 may serve as a mask for preventing doping of the second channel region 230C.

Referring to FIG. 37D , for a schematic cross-sectional view, the width of the doping mask pattern 70 may be greater than the width of the second gate electrode G2.

Conductor providing portions 233a, 233b provided with conductivity through a doping process using dopants may have a higher doping concentration than that of the second channel region 230C, and may have a resistivity higher than that of the second channel region 230C low resistivity.

Referring to FIG. 37D , a plurality of offset parts (eg, the first and second offset parts) 232 a and 232 b can be protected by the doping mask pattern 70 . Therefore, direct implantation of dopants into the deviation portions 232a, 232b can be prevented. Of course, the dopants doped in the conductor supply portions 233a, 233b may diffuse to the offset portions 232a, 232b. Therefore, it is possible to obtain an effect that the dopant is partially doped to the deviation portions 232a, 232b.

In FIG. 37D, when the second gate electrode G2 has a width LG and the doping mask pattern 70 has a width Loh protruding from the second gate electrode G2, doping may be performed under the condition that the following Equation 2 is satisfied.

[Equation 2]

LG x Loh x 1/η2 ≥ 1

where η2 = 0.5 square microns

The width of each of the first deviation portion 232a and the second deviation portion 232b may correspond to the width Loh of the protrusion. When the width LG of the second gate electrode G2 and the width Loh of the doping mask pattern 70 protruding from the second gate electrode G2 satisfy Equation 2, the deviation portions 232a, 232b satisfying Equation 2 may be formed.

According to another embodiment of the present invention, in Equation 2, η2 = 1.5 square micrometers. Alternatively, η2 may satisfy the following relationship: 0.5 square microns ≤ η2 ≤ 1.5 square microns.

The concentration of dopants in these conductor providing portions 233a, 233b may be the highest. The doping concentration of these deviation portions 232a, 232b may be lower than the doping concentration of the respective conductor providing portions 233a, 233b. A small amount of dopant may diffuse into the second channel region 230C that is not directly doped with the dopant. The second channel region 230C may contain little or no dopant, or may have a very low concentration of the dopant.

Therefore, as shown in FIG. 37D, according to the doping process using the doping mask pattern 70, the second active layer 230 of the second thin film transistor T2 may include the second channel region 230C, the conductor supplying parts 233a, 233b and the offset part 232a, 232b. The second channel region 230C has a relatively low doping concentration. The conductor supply portions 233a, 233b have relatively high doping concentrations. The doping concentration of the deviation portions 232a, 232b is lower than the doping concentration of the respective conductor providing portions 233a, 233b and higher than the doping concentration of the second channel region 230C. Also, the first conductor providing portion 233a and the first deviation portion 232a may be the second source region 230S. Also, the second conductor providing portion 233b and the second offset portion 232b may be the second drain region 230D.

The deviation portions 232a, 232b may have an increasing dopant concentration gradient in a direction from the second channel region 230C to the conductor providing portions 233a, 233b. For example, the first deviation portion 232a may have an increasing dopant concentration gradient in the direction from the second channel region 230C to the first conductor providing portion 233a, and the second deviation portion 232b may have an increasing dopant concentration gradient from the second channel region 230C There is an increasing dopant concentration gradient in the direction to the second conductor providing portion 233b.

The resistivity of the respective deviation portions 232a, 232b may be lower than the resistivity of the second channel region 230C, and may be higher than the resistivity of the respective conductor providing portions 233a, 233b. The offset portions 232a, 232b may have a decreasing resistivity gradient in the direction from the second channel region 230C to the conductor providing portions 233a, 233b.

Therefore, the offset parts 232a, 232b may perform the function of electrical buffering between the second channel region 230C that does not provide conductivity and the conductor providing parts 233a, 233b.

In detail, since the deviation portions 232a, 232b are provided between the second channel region 230C and the conductor supply portions 233a, 233b, leakage current can be prevented from flowing in the second thin film transistor T2 in the OFF state of the second thin film transistor T2 Between the channel region 230C and the conductor supply parts 233a, 233b. As described above, the deviation portions 232a, 232b can prevent the leakage current from being generated in the second thin film transistor T2 when the second thin film transistor T2 is in an OFF state.

In addition, as shown in FIG. 37D, a second intermediate insulating layer 116 may be formed on the second gate electrode G2, and then a doping process of doping dopant may be performed. Therefore, dopants may be doped into the second intermediate insulating layer 116 and the second gate insulating layer 115 . Therefore, the regions of the second intermediate insulating layer 116 and the second gate insulating layer 115 overlapping the conductor supplying portions 233a and 233b of the second active layer 230 may contain dopants. The dopant may include at least one of boron (B), phosphorus (P), fluorine (F), and hydrogen (H). Therefore, the second intermediate insulating layer 116 and the second gate insulating layer 115 may include at least one of boron (B), phosphorus (P), fluorine (F) and hydrogen (H). Also, the dopant can be doped in the region of the second intermediate insulating layer 116 overlapping the second gate electrode G2. Therefore, the region of the second intermediate insulating layer 116 overlapping the second gate electrode G2 may include at least one of boron (B), phosphorus (P), fluorine (F) and hydrogen (H). In addition, the region of the second intermediate insulating layer 116 overlapping the second gate electrode G2 may not need to contain a dopant material.

In the region overlapping the conductor supplying parts 233a, 233b, the doping concentration of the respective conductor supplying parts 233a, 233b may be higher than the doping concentration of the second gate insulating layer 150, the doping concentration of the second intermediate insulating layer 116, and Doping concentration of the second buffer layer 114 . In addition, in the region overlapping the conductor supplying parts 233a and 233b, the doping concentration of the second buffer layer 114 may be higher than the doping concentration of the conductor supplying parts 233a and 233b and the doping concentration of the second gate insulating layer 150 and the doping concentration of the second intermediate insulating layer 116 .

The doping of each of the second intermediate insulating layer 116 , the second gate insulating layer 115 , the conductor supply portions 233 a , 233 b and the second buffer layer 114 can be adjusted by adjusting the accelerating voltage applied to the dopant during the doping process concentration.

When the accelerating voltage applied to the dopant is increased to sufficiently dope the conductor supply parts 233a, 233b with the dopant, the dopant may be doped to the conductor supply parts 233a, 233b, and in addition may be doped on the second buffer layer 114 . When the accelerating voltage for doping is increased to an unintended level, the second active layer 230 may be damaged. Therefore, according to an embodiment of the present invention, the accelerating voltage can be adjusted so that the doping concentration in the conductor providing parts 233a, 233b is the maximum or the doping concentration in the top of the second buffer layer 114 is the maximum.

According to an embodiment of the present invention, when the doping concentration in the conductor supplying parts 233a and 233b is at the maximum value or the doping concentration in the second buffer layer 114 is at the maximum value, the conductor supplying parts 233a and 233b can be effectively treated with doping. In addition, when the doping concentration in the conductor providing parts 233a and 233b is at the maximum value or the doping concentration in the second buffer layer 114 is at the maximum value, it can be considered that the second thin film transistor T2 operates in an efficient manner.

According to an embodiment of the present invention, since the process of doping the dopant is performed after the process of forming the contact holes for exposing the first active layer 270 and the second active layer 230 and the process of high temperature heat treatment through the contact holes, Therefore, dopants can be doped into the second intermediate insulating layer 116 and the second gate insulating layer 115 , wherein the second intermediate insulating layer 116 and the second gate insulating layer 115 are formed on the second active layer 230 . Therefore, when the dopant is detected from the second intermediate insulating layer 116 and the second gate insulating layer 115 formed on the second active layer 230, it can indicate that the dopant doping process has been performed after the high temperature heat treatment process. .

Referring to FIG. 37E, the second source electrode S2 and the second drain electrode D2 can be formed on the second intermediate insulating layer 116 and can be connected to the second active layer 230 through a plurality of contact holes CH3 and CH4, wherein the contact hole CH3 , CH4 is formed in the second intermediate insulating layer 116 and the second gate insulating layer 115 .

Referring to FIG. 36 , the passivation layer 117 may be formed on the fourth source electrode S4 and the fourth drain electrode D4 of the fourth thin film transistor T4 and the second source electrode S2 and the second drain electrode of the second thin film transistor T2 on electrode D2.

A contact hole for exposing the fourth source electrode S4 of the fourth thin film transistor T4 may be formed in the passivation layer 117 . However, this embodiment is not limited to this, and a contact hole for exposing the fourth drain electrode D4 of the fourth thin film transistor T4 may be formed in the passivation layer 117 . The passivation layer 117 may be an organic material layer. For example, the passivation layer 117 can be formed of a single-layer structure or a double-layer structure, which includes, for example, acryl resin, epoxy resin, phenolic resin, and polyamide resin. resin) or polyimide resin (polyimide resin) organic material. In another example, the passivation layer 117 may be formed of a single-layer structure including inorganic materials such as silicon nitride (SiN _x ) or silicon oxide (SiO _x ), or may be formed of a multi-layer structure as described above. Alternatively, the passivation layer 117 may be formed of a multi-layer structure including inorganic materials and organic materials.

The pixel electrode 711 of the light emitting device 710 may be disposed on the passivation layer 117 . The pixel electrode 711 can be electrically connected to the fourth thin film transistor T4 through a contact hole formed in the passivation layer 117 . The fourth thin film transistor T4 connected to the pixel electrode 711 may be a driving thin film transistor that transmits current to the light emitting device 710 .

The pixel electrode 711 can be formed as a multi-layer structure, and the multi-layer structure includes a transparent conductor layer and an opaque conductor layer with high reflectivity. The transparent conductor layer may contain a material with a high work function value, such as indium tin oxide (ITO) or indium zinc oxide (IZO). Also, the opaque conductor layer may be formed of a single-layer structure or a multi-layer structure, which includes aluminum (Al), silver (Ag), copper (Cu), lead (Pb), molybdenum (Mo), titanium (Ti) or alloys thereof. For example, the pixel electrode 711 may include a transparent conductor layer, an opaque conductor layer, and a transparent conductor layer formed in sequence. However, the present embodiment is not limited to this, and for example, the pixel electrode 711 may include a transparent conductor layer and an opaque conductor layer formed in sequence.

The display device according to an embodiment of the present invention may be a top emission display device, and thus the pixel electrode 711 may be an anode electrode. When the display device is of bottom emission type, the pixel electrode 711 disposed on the passivation layer 117 may be a cathode electrode.

The bank layer 750 may be disposed on the pixel electrode 711 and the passivation layer 117 . An opening for exposing the pixel electrode 711 may be formed in the bank layer 750 . The bank layer 750 may define the light emitting area of the display device and may be referred to as a pixel defining layer. A spacer may be further provided on the bank layer 750 . In addition, the light emitting layer 712 of the light emitting device 710 can be further disposed on the pixel electrode 711 .

The light-emitting layer 712 may include a hole layer (HL), a light-emitting material layer (EML), and an electron layer (EL), and these layers are formed on the pixel electrode 711 in the above-mentioned order or an order opposite to the above-mentioned order.

In addition, the light emitting layer 712 may include a first light emitting layer and a second light emitting layer, and a charge generating layer (CGL) is disposed between the first light emitting layer and the second light emitting layer. In this case, one of the first light-emitting layer and the second light-emitting layer can emit blue light, and the other one of the first light-emitting layer and the second light-emitting layer can emit yellow-green light, and then pass through the first light-emitting layer and the second light-emitting layer Emits white light. The white light emitted through the first light-emitting layer and the second light-emitting layer can be incident on the color filter disposed on the light-emitting layer to implement a color image. In another example, without separate color filters, each light-emitting layer may emit colored light corresponding to each sub-pixel to implement a color image. That is, the light-emitting layer of the red sub-pixel can emit red light, the light-emitting layer of the green sub-pixel can emit green light, and the light-emitting layer of the blue sub-pixel can emit blue light.

Referring to FIG. 36 , the common electrode 713 of the light emitting device 710 can be further disposed on the light emitting layer 712 . The common electrode 713 may overlap the pixel electrode 711 , and the light emitting layer 712 is located between the common electrode 713 and the pixel electrode 711 . In a display device according to an embodiment of the present invention, the common electrode 713 may be a cathode electrode.

A package for preventing water infiltration can be further disposed on the common electrode 713 . The package may include a first encapsulation layer, a second encapsulation layer, and a third encapsulation layer. The material contained in the second encapsulation layer may be different from the material contained in each of the first encapsulation layer and the third encapsulation layer. For example, each of the first encapsulation layer and the third encapsulation layer may be an inorganic insulating layer including an inorganic insulating material, and the second encapsulation layer may be an organic insulating layer including an organic insulating material. The first encapsulation layer of the package may be disposed on the common electrode 713 . Also, the second encapsulation layer may be disposed on the first encapsulation layer. Also, the third encapsulation layer may be disposed on the second encapsulation layer.

The first encapsulation layer and the third encapsulation layer of the package may include inorganic materials such as silicon nitride (SiN _x ) or silicon oxide (SiO _x ). The second encapsulation layer of the package may be formed of a single-layer structure or a double-layer structure, which includes an organic material such as acrylic resin, epoxy resin, phenol resin, polyamide resin or polyimide resin.

38 , 39A and 39B are a schematic cross-sectional view and a schematic view of a process of a display device according to another embodiment of the present invention. Hereinafter, the same or similar descriptions as those described above with reference to FIG. 36 and FIGS. 37A to 37C will be omitted or briefly described. For example, the substrate 110, the first buffer layer 111, the first gate insulating layer 112, the first intermediate insulating layer 113, the second buffer layer 114, the second gate insulating layer 115, the second intermediate insulating layer 116, the passivation The descriptions of the layer 117 , the bank layer 750 , the light emitting device 710 , the package, and the fourth thin film transistor T4 may be sequentially the same as those described above. Therefore, repetitive descriptions of configurations in FIG. 38 that are substantially the same as those presented in 36 will be omitted or simplified. Also, descriptions of processes that are substantially the same as those presented in FIGS. 37A-37C will be omitted or simplified.

Referring to FIG. 38, a display device 20 according to another embodiment of the present invention may include a substrate 110, a first buffer layer 111, a first gate insulating layer 112, a first intermediate insulating layer 113, a second buffer layer 114, a second The gate insulating layer 115 , the second intermediate insulating layer 116 , the passivation layer 117 , the bank layer 750 , the light emitting device 710 , the package, the fourth thin film transistor T4 , the second thin film transistor T2 and a metal pattern 80 .

The metal pattern 80 may be disposed on the second intermediate insulating layer 116 and may overlap the second gate electrode G2.

Referring to FIGS. 38 and 39A , the third contact hole CH3 and the fourth contact hole CH4 respectively exposing the second active layer 230 may be formed in the second gate insulating layer 115 and the second intermediate insulating layer 116 . A dry etching process may be performed in order to form the third contact hole CH3 and the fourth contact hole CH4 in the second gate insulating layer 115 and the second intermediate insulating layer 116 . In addition, the regions of the second active layer 230 exposed by the contact holes CH3 and CH4 can be made conductive through the dry etching process of forming the third contact hole CH3 and the fourth contact hole CH4.

Furthermore, as shown in FIG. 38 , it may be formed by etching the second intermediate insulating layer 116 , the second gate insulating layer 115 , the second buffer layer 114 , the first intermediate insulating layer 113 and the first gate insulating layer 112 The first contact hole CH1 and the second contact hole CH2 of the first active layer 270 are respectively exposed. Furthermore, after the first to fourth contact holes CH1 to CH4 are formed, a high temperature heat treatment process may be performed at a temperature of 350° C. or higher in order to dehydrogenate or crystallize the first active layer 270 . In addition, the conductor providing region in the second active layer 230 provided with conductivity through the dry etching process can be partially diffused to both ends thereof through the high temperature heat treatment process.

After the heat treatment process, the fourth source electrode S4, the fourth drain electrode D4, the second source electrode S2, the second drain electrode D2 and the metal pattern 80 can be formed.

Referring to FIG. 39B , the second source electrode S2 and the second drain electrode D2 can be connected to the second active layer 230 through the contact holes CH3 and CH4 formed in the second intermediate insulating layer 116 and the second gate insulating layer 115 . The second source electrode S2 can be connected to the second source region 230S of the second active layer 230 through the third contact hole CH3. Moreover, the second drain electrode D2 can be connected to the second drain region 230D of the second active layer 230 through the fourth contact hole CH4. Also, the metal pattern 80 may be disposed on the second intermediate insulating layer 116 and may overlap the second gate electrode G2. Moreover, compared to the schematic cross-sectional view, the width of the metal pattern 80 may be greater than the width of the second gate electrode G2. With respect to the plan view, the area of the metal pattern 80 may be larger than that of the second gate electrode G2. For example, the second gate electrode G2 may be disposed in the area defined by the metal pattern 80 .

As shown in Figure 39B, a doping process using dopants can be performed. Due to the metal pattern 80, the dopant may not be doped in the second channel region 230C. Therefore, the second channel region 230C can maintain semiconductor characteristics.

The plurality of conductor providing portions 233a, 233b provided with conductivity through a doping process using dopants may have a doping concentration higher than that of the second channel region 230C, and may have a lower doping concentration than the second channel region 230C The resistivity of the resistivity.

Referring to FIG. 39B , a plurality of offset parts (eg, the first and second offset parts) 232 a and 232 b can be protected by the metal pattern 80 . Therefore, direct implantation of dopants into the deviation portions 232a, 232b can be prevented. Of course, the dopants doped in the conductor supply portions 233a, 233b may diffuse to the offset portions 232a, 232b. Therefore, the effect that the dopant is partially doped in the deviation portions 232a and 232b can be obtained.

In FIG. 39B, when the second gate electrode G2 has a width LG and the metal pattern 80 has a width Loh protruding from the second gate electrode G2, doping may be performed under the condition that the following Equation 2 is satisfied.

[Equation 2]

LG x Loh x 1/η2 ≥ 1

where η2 = 0.5 square microns

The width of each of the first deviation portion 232a and the second deviation portion 232b may correspond to the width Loh of the protrusion. When the width LG of the second gate electrode G2 and the protruding width Loh satisfy Equation 2, the deviation portions 232a and 232b satisfying Equation 2 can be formed.

According to another embodiment of the present invention, in Equation 2, η2 is 1.5 square micrometers. Alternatively, η2 may satisfy the following relationship: 0.5 square microns ≤ η2 ≤ 1.5 square microns.

The concentration of the dopant may be highest in these conductor providing portions 233a, 233b. The doping concentration of these deviation portions 232a, 232b may be lower than the doping concentration of the respective conductor providing portions 233a, 233b. A small amount of dopant may diffuse into the second channel region 230C that is not directly doped with the dopant. The second channel region 230C may contain little or no dopant, or may have a very low concentration of the dopant.

The deviation portions 232a, 232b may have an increasing dopant concentration gradient in a direction from the second channel region 230C to the conductor providing portions 233a, 233b. For example, the first deviation portion 232a may have an increasing dopant concentration gradient in the direction from the second channel region 230C to the first conductor providing portion 233a, and the second deviation portion 232b may have an increasing dopant concentration gradient from the second channel region 230C There is an increasing dopant concentration gradient in the direction to the second conductor providing portion 233b.

In addition, the resistivity of the respective deviation portions 232a, 232b may be lower than the resistivity of the second channel region 230C, and may be higher than the resistivity of the respective conductor providing portions 233a, 233b. The offset portions 232a, 232b may have a decreasing resistivity gradient in the direction from the second channel region 230C to the conductor providing portions 233a, 233b.

Therefore, the offset portions 232a, 232b may perform the function of electrical buffering between the conductor providing portions 233a, 233b and the second channel region 230C that does not provide conductivity.

In detail, since the deviation portions 232a, 232b are provided between the second channel region 230C and the conductor supply portions 233a, 233b, leakage current can be prevented from flowing in the second thin film transistor T2 in the OFF state of the second thin film transistor T2 Between the channel region 230C and the conductor supply parts 233a, 233b. As described above, the offset portions 232a, 232b can prevent leakage current from being generated in the second thin film transistor T2 when the second thin film transistor T2 is in an OFF state.

When the second thin film transistor T2 is turned on according to the gate voltage applied to the second gate electrode G2, the conductivity of the second channel region 230C may be increased, but the conductivity of the respective deviation portions 232a, 232b may not be greatly increased , wherein the conductivity of each deviation portion 232a, 232b is not greatly affected by the electric field generated in the second gate electrode G2. Therefore, when the second thin film transistor T2 is turned on, the conductivity of the respective offset portions 232a, 232b may be lower than the conductivity of the second channel region 230C and the conductivity of the respective conductor providing portions 233a, 233b. Therefore, the deviation of the threshold voltage of the second thin film transistor T2 can be prevented by the deviation portions 232a and 232b. Therefore, the electrical stability of the second thin film transistor T2 can be improved.

In addition, as shown in FIG. 39B, a second intermediate insulating layer 116 may be formed on the second gate electrode G2, and then a doping process of doping dopant may be performed. Therefore, dopants can be doped into the second intermediate insulating layer 116 and the second gate insulating layer 115 . Therefore, the regions of the second intermediate insulating layer 116 and the second gate insulating layer 115 overlapping the conductor supplying portions 233a and 233b of the second active layer 230 may contain dopants. The dopant may include at least one of boron (B), phosphorus (P), fluorine (F), and hydrogen (H). Therefore, the second intermediate insulating layer 116 and the second gate insulating layer 115 may include at least one of boron (B), phosphorus (P), fluorine (F) and hydrogen (H). Also, the region of the second gate insulating layer 115 overlapping the second gate electrode G2 may not contain dopant material. Also, the region of the second intermediate insulating layer 116 overlapping the metal pattern 80 and the second gate electrode G2 may not contain dopant material.

According to an embodiment of the present invention, since the process of doping the dopant is performed after the process of forming the contact holes for exposing the first active layer 270 and the second active layer 230 and the process of high temperature heat treatment through the contact holes, Therefore, dopants can be doped into the second intermediate insulating layer 116 and the second gate insulating layer 115 , wherein the second intermediate insulating layer 116 and the second gate insulating layer 115 are formed on the second active layer 230 . Therefore, when the dopant is detected from the second intermediate insulating layer 116 and the second gate insulating layer 115 formed on the second active layer 230, it can indicate that the dopant doping process has been performed after the high temperature heat treatment process. .

A thin film transistor according to an embodiment of the present invention includes an active layer, a gate electrode, and a gate insulating layer. The active layer is located on a substrate. The gate electrode is separated from the active layer to at least partially overlap the active layer. The gate insulating layer is located between the active layer and the gate electrode. The gate insulating layer covers the entire top surface of the active layer facing the gate electrode. The active layer includes a channel part, a conductor supply part and a deviation part. The channel portion overlaps the gate electrode. The conductor supply portion does not overlap the gate electrode. The offset portion is located between the channel portion and the conductor providing portion. The offset portion does not overlap the gate electrode. The conductor supply portion is doped with a dopant.

According to an embodiment of the present invention, when the width of the channel portion is L1 and the width of the offset portion is L2, the thin film transistor satisfies the following equation 1,

[Equation 1]

L1 x L2 x 1/η1 ≥ 1

where η1 is 0.5 square microns.

According to an embodiment of the present invention, the active layer includes an oxide semiconductor material.

According to an embodiment of the present invention, the dopant includes at least one of boron, phosphorus, fluorine and hydrogen.

According to an embodiment of the invention, the deviation portion has an increasing dopant concentration gradient in the direction from the channel portion to the conductor providing portion.

According to an embodiment of the present invention, the resistivity of the deviation portion is lower than that of the channel portion and higher than that of the conductor providing portion.

According to an embodiment of the present invention, the width of the deviation portion is 0.25 micrometers or more.

According to an embodiment of the present invention, the width of the channel portion is 2 micrometers or more.

According to an embodiment of the present invention, the thin film transistor further includes a buffer layer. The buffer layer is disposed between the substrate and the active layer. Dopants are doped into the buffer layer.

According to an embodiment of the present invention, in the region overlapping the conductor providing portion, the doping concentration of the conductor providing portion is higher than the doping concentration of the gate insulating layer and the doping concentration of the buffer layer.

According to an embodiment of the present invention, in the region overlapping the conductor providing portion, the doping concentration of the buffer layer is higher than the doping concentration of the conductor providing portion and the doping concentration of the gate insulating layer.

According to an embodiment of the present invention, the active layer further includes a first oxide semiconductor layer and a second oxide semiconductor layer. The first oxide semiconductor layer is on the substrate. . The second oxide semiconductor layer is on the first oxide semiconductor layer.

According to an embodiment of the present invention, the thin film transistor further includes a source electrode and a drain electrode. The source electrode and the drain electrode are separated from each other and connected to the active layer.

According to an embodiment of the present invention, the source electrode, the drain electrode and the gate electrode are disposed in the same layer body, and comprise the same material as the gate electrode.

A thin film transistor substrate according to another embodiment of the present invention includes a base substrate, a first thin film transistor, and a second thin film transistor. The first thin film transistor and the second thin film transistor are located on the base substrate. The first thin film transistor includes a first active layer and a first gate electrode. The first active layer is on the base substrate. The first gate electrode is separated from the first active layer to at least partially overlap the first active layer. The second thin film transistor includes a second active layer, a gate electrode and a gate insulating layer. The second active layer is on the base substrate. The gate electrode is separated from the second active layer to at least partially overlap the second active layer. The gate insulating layer is located between the second active layer and the second gate electrode. The gate insulating layer may cover the entire top surface of the second active layer facing the second gate electrode. In addition, the second active layer includes a channel portion, a conductor providing portion, and an offset portion. The channel portion overlaps the second gate electrode. The conductor supply portion does not overlap the second gate electrode. The offset portion is located between the channel portion and the conductor providing portion. The offset portion does not overlap the second gate electrode. The conductor supply portion is doped with a dopant. The first active layer and the second active layer can be disposed on different layers.

According to another embodiment of the present invention, the first active layer is a silicon semiconductor layer, and the second active layer is an oxide semiconductor layer.

A method of fabricating a thin film transistor includes forming an active layer on a substrate, forming a gate insulating layer on the active layer, forming a gate electrode on the gate insulating layer to at least partially overlap the active layer, and The active layer is doped with a dopant. The gate insulating layer covers the entire top surface of the active layer facing the gate electrode. The step of forming the gate electrode includes forming a gate electrode material layer on the gate insulating layer, forming a photoresist pattern on the gate electrode material layer, and etching the gate electrode material layer by using the photoresist pattern as a mask . The area of the photoresist pattern is larger than that of the gate electrode. In a plan view, the gate electrode is disposed in the area defined by the photoresist pattern. The photoresist pattern is used as a mask in the step of doping the dopant on the active layer.

According to another embodiment of the present invention, the dopant includes at least one of boron, phosphorus, fluorine and hydrogen.

According to another embodiment of the present invention, when the width of the gate electrode is LG and the width of the photoresist pattern protruding from the gate electrode is Loh, the method satisfies the following equation 2,

[Equation 2]

LG x Loh x 1/η2 ≥ 1

where η2 is 0.5 square microns.

A display apparatus according to another embodiment of the present invention includes a substrate, a pixel driving circuit, and a light emitting device. The pixel driving circuit is located on the substrate. The light-emitting device is connected to the pixel driving circuit. The pixel driving circuit includes a thin film transistor. The thin film transistor includes an active layer, a gate electrode and a gate insulating layer. The active layer is on the substrate. The gate electrode is separated from the active layer to at least partially overlap the active layer. The gate insulating layer is located between the active layer and the gate electrode. The gate insulating layer covers the entire top surface of the active layer facing the gate electrode. The active layer includes a channel part, a conductor supply part and a deviation part. The channel portion overlaps the gate electrode. The conductor supply portion does not overlap the gate electrode. The offset portion is located between the channel portion and the conductor providing portion. The offset portion does not overlap the gate electrode. The conductor supply portion is doped with a dopant.

A display device according to another embodiment of the present invention includes a first thin film transistor, a first intermediate insulating layer, a second thin film transistor, and a second intermediate insulating layer. The first thin film transistor includes a first active layer, a first gate electrode, a first gate insulating layer, a first source electrode and a first drain electrode. The first active layer includes polysilicon. The first gate electrode overlaps the first active layer. The first gate insulating layer is located between the first active layer and the first gate electrode. The first source electrode and the first drain electrode are respectively connected to the first active layer. The first intermediate insulating layer is disposed on the first gate electrode. The second thin film transistor includes a second active layer, a second gate electrode, a second gate insulating layer, a second source electrode and a second drain electrode. The second active layer includes an oxide semiconductor. The second gate electrode overlaps the second active layer. The second gate insulating layer is located between the second active layer and the second gate electrode. The second source electrode and the second drain electrode are respectively connected to the second active layer. The second intermediate insulating layer is disposed on the first gate electrode, the second gate electrode and the second gate insulating layer. The second gate insulating layer and the second intermediate insulating layer include a dopant for doping the second active layer.

According to another embodiment of the present invention, the dopant doped in the second active layer includes at least one of boron, phosphorus, fluorine and hydrogen.

According to another embodiment of the present invention, the second active layer includes a second channel region, a second source region and a second drain region. The second channel region overlaps the second gate electrode. The second source region is disposed on one side of the second channel region and connected to the second source electrode. The second drain region is disposed on the other side of the second channel region and connected to the second drain electrode.

According to another embodiment of the present invention, the second source region includes a first conductor providing portion and a first offset portion. The first conductor providing portion is provided on the side of the second channel region. The first deviation portion is disposed between the first conductor providing portion and the side of the second channel region. The second drain region includes a second conductor providing portion and a second offset portion. The second conductor providing portion is disposed on the other side of the second channel region. The second deviation portion is disposed between the second conductor providing portion and the other side of the second channel region.

According to another embodiment of the present invention, the first conductor providing portion, the second conductor providing portion, the first offset portion, and the second offset portion include dopants.

According to another embodiment of the present invention, the concentration of the dopant in each of the first conductor supply portion and the second conductor supply portion is higher than the concentration of the dopant in each of the first deviation portion and the second deviation portion.

According to an embodiment of the present invention, the photoresist pattern can be used as a mask to form a deviation portion between the conductor supply portion and the channel portion of the semiconductor layer through a doping process without patterning the gate insulating layer, and the deviation portion can be formed based on the The offset portion ensures the effective channel width of the thin film transistor.

According to another embodiment of the present invention, since the active layer of the thin film transistor includes the deviation portion, the electrical stability of the conductor providing region and the channel layer can be ensured, and the influence of the insulating layer on the active layer can be minimized, thereby ensuring The driving stability of thin film transistors.

According to another embodiment of the present invention, the effective channel width of the thin film transistor can be easily ensured, and the thin film transistor with a small size can be manufactured. Thin film transistors can be integrated and provided in various electronic products, and high-resolution display devices can be fabricated by using thin film transistors.

The above-mentioned features, structures and effects of the present invention are included in at least one embodiment of the present invention, but are not limited to only one embodiment. Furthermore, the features, structures, and effects described in at least one embodiment of the present invention can be implemented by those skilled in the art by combining or modifying other embodiments. Therefore, contents related to such combination and modification should be construed as belonging to the scope of the present invention.

It will be apparent to those skilled in the art that various modifications and variations can be made in the present invention without departing from the scope or spirit of the inventions. Accordingly, the present invention shall cover such modifications and variations as they fall within the scope of the claims or their equivalents.

10, 20: Display device 100, 200, 300, 400, 500: Thin film transistor 600: Thin film transistor substrate 110: Substrate 111: Buffer layer 112: Gate insulating layer 113: Intermediate insulating layer 114: Buffer layer 115: Gate Polar insulating layer 116: Intermediate insulating layer 117: Passivation layer 120: Buffer layer 121: Light shielding layer 130: Active layer 130a: Oxide semiconductor layer 130b: Oxide semiconductor layer 131: Channel parts 132a, 132b: Deviation parts 133a, 133b: Conductor supply part 140: gate electrode 145: gate electrode material layer 150: gate insulating layer 150a: gate insulating layer 155: intermediate insulating layer 161: source electrode 162: drain electrode 181: gate insulating layer 182: Passivation layer 185: Intermediate layer 192: Planarization layer 210: Base substrate 230: Active layer 230C: Channel region 230S: Source region 230D: Drain region 231: Channel portion 232a, 232b: Deviation portion 233a, 233b: Conductor supply Section 240: Gate electrode 261: Source electrode 262: Drain electrode 270: Active layer 270C: Channel region 270S: Source region 270D: Drain region 271: Channel sections 272, 273: Conductor supply section 280: Gate electrode 281: Source electrode 282: Drain electrode 40, 41, 42, 45, 50, 60, 61, 62, 63: Photoresist pattern 70: Doping mask pattern 80: Metal pattern 310: Display panel 320: Gate Driver 330: Data driver 340: Controller 350: Offset recorder 700: Display device 710: Light-emitting device 711: Pixel electrode 712: Light-emitting layer 713: Common electrode 750: Bank layer 800, 900: Display device TR1, TR2: Thin film transistors L1, L2, LG, Loh: width ∆L: conductor provided penetration depth L _ideal : width L _eff : effective channel width MR1, MR2: metal residual material H1, H2, CH1, CH2, CH3, CH4: contact Hole GL: Gate Line DL: Data Line P: Pixel PDC: Pixel Driving Circuit GCS: Gate Control Signal DCS: Data Control Signal RGB: Image Data T1, T2, T3, T4, T5, T6, T7: Thin Film Transistor C1, C2: Capacitors Scan1, Scan2: Scan signal Vdata: Data voltage D1: Drain electrode G1: Gate electrode S1: Source electrode D2: Drain electrode G2: Gate electrode S2: Source electrode D4: Drain electrode G4: gate electrode S4: source electrode EM: light emission control signal EL: light emission control line VDD: pixel driving voltage Vini: initialization voltage VSS: driving voltage CE1, CE2: electrodes A1, A2, A4: channel part PL: pixel driving Voltage line ICL: Initialization control line IL: Initialization voltage line SS: Scanning signal IC S: Initialization control signal n1, n2: Node OP1, OP2: Opening

The accompanying drawings are used to provide a further understanding of the invention and are incorporated in and constitute a part of this application, and the illustrated embodiments and description of the invention are intended to explain the principles of the invention. In the attached image: FIG. 1 is a schematic cross-sectional view of a thin film transistor according to an embodiment of the present invention. 2 is a schematic cross-sectional view of a thin film transistor according to another embodiment of the present invention. 3 is a schematic cross-sectional view of a thin film transistor according to another embodiment of the present invention. 4 is a schematic cross-sectional view of a thin film transistor according to another embodiment of the present invention. 5 is a schematic cross-sectional view of a thin film transistor according to another embodiment of the present invention. 6 is a schematic cross-sectional view of a thin film transistor substrate according to another embodiment of the present invention. FIG. 7 is a diagram illustrating a doping method according to an embodiment of the present invention. FIG. 8 is a diagram showing the distribution of area-oriented dopants of the active layer according to an embodiment of the present invention. 9 is a graph presenting the concentration of the area orientation dopant of the active layer according to one embodiment of the present invention. FIG. 10 is a graph presenting the extent of the area orientation resistivity of an active layer according to an embodiment of the present invention. FIG. 11 is a graph showing the area-oriented conductivity distribution of the semiconductor layer in the on-state of the thin film transistor according to an embodiment of the present invention. 12 is a graph presenting the concentration of depth-based elements in a region overlapping a conductor provider according to an embodiment of the present invention. FIG. 13 is a graph presenting the concentration of depth-based elements in a region that overlaps a conductor provider, according to an embodiment of the present invention. 14A and 14B are diagrams of a conductor providing method according to a comparative example. FIG. 15 is a schematic diagram illustrating a conductor providing penetration depth ΔL according to a comparative example. FIG. 16 is a graph of providing a penetration depth 2ΔL for the overall conductor of a thin film transistor according to a comparative example and an embodiment of the present invention. 17A-17E are graphs of threshold voltages of thin film transistors according to a comparative example and an embodiment of the present invention. 18 is a graph of threshold voltage versus heat treatment time for thin film transistors according to a comparative example and an embodiment of the present invention. 19 is a graph of mobility versus heat treatment time for thin film transistors according to a comparative example and an embodiment of the present invention. FIG. 20 is a resistivity measurement chart of a thin film transistor according to a comparative example and an embodiment of the present invention. 21 is a graph of mobility versus the amount of ions implanted in the active layer according to a comparative example and an embodiment of the present invention. 22A to 22C are graphs of threshold voltage versus channel width of thin film transistors according to a comparative example and an embodiment of the present invention. 23 is a graph showing threshold voltage values versus channel widths for thin film transistors according to a comparative example and an embodiment of the present invention. 24 is a graph of threshold voltage versus gate electrode width according to a comparative example and an embodiment of the present invention. FIG. 25 is a diagram showing a gap and a metal residual layer created near the gate electrode according to an embodiment of the present invention. FIG. 26 is a diagram showing a state in which no gap or metal residual layer is generated near the gate electrode according to an embodiment of the present invention. 27A to 27G are schematic diagrams of the manufacturing process of a method for manufacturing a thin film transistor according to an embodiment of the present invention. 28A to 28G are schematic process diagrams of a manufacturing method of a thin film transistor according to another embodiment of the present invention. FIG. 29 is a diagram showing a display device according to another embodiment of the present invention. FIG. 30 is a circuit diagram of one pixel in FIG. 29 . FIG. 31 is a plan view of the pixel in FIG. 30 . FIG. 32 is a schematic cross-sectional view along the secant line II′ in FIG. 31 . 33A to 33C are schematic process diagrams of a method for manufacturing a thin film transistor according to another embodiment of the present invention. 34 is a circuit diagram of one pixel of a display device according to another embodiment of the present invention. 35 is a circuit diagram of one pixel of a display device according to another embodiment of the present invention. 36 is a schematic cross-sectional view of a display device according to another embodiment of the present invention. 37A to 37E are schematic process diagrams of a method for manufacturing the thin film transistor disposed in the region B in FIG. 36 . 38 is a schematic cross-sectional view of a display device according to another embodiment of the present invention. FIG. 39A and FIG. 39B are schematic process diagrams of the manufacturing method of the thin film transistor disposed in the region B in FIG. 38 .

100: thin film transistor

110: Substrate

120: Buffer layer

130: Active layer

131: Channel Department

132a, 132b: Deviation section

133a, 133b: conductor supply part

140: gate electrode

150: gate insulating layer

L1, L2: width

Claims (31)

A thin film transistor, comprising: an active layer on a substrate; a gate electrode separated from the active layer to at least partially overlap the active layer; and a gate insulating layer on the active layer and the gate electrode between the gate electrodes, wherein the gate insulating layer covers the entire top surface of the active layer facing the gate electrode, the active layer includes: a channel portion, overlapping the gate electrode; a conductor providing portion, not overlapping on the gate electrode; and an offset portion located between the channel portion and the conductor supply portion, the offset portion does not overlap the gate electrode, the conductor supply portion is doped with a dopant, and wherein the offset portion There is an increasing dopant concentration gradient in the direction from the channel portion to the conductor providing portion; when the width of the channel portion is L1 and the width of the offset portion is L2, the thin film transistor satisfies the following equation 1,

where η1 satisfies the following relation: 0.5 square microns

η1

1.5 square microns. The thin film transistor of claim 1, wherein η1 is 0.5 square micrometers. The thin film transistor of claim 1, wherein the active layer comprises an oxide semiconductor material. The thin film transistor of claim 1, wherein the dopant comprises at least one of boron, phosphorus, fluorine and hydrogen. The thin film transistor of claim 1, wherein the resistivity of the deviation portion is lower than the resistivity of the channel portion and higher than the resistivity of the conductor providing portion. The thin film transistor of claim 1, wherein the width of the deviation portion is 0.25 micrometers or more. The thin film transistor of claim 1, wherein the channel portion has a width of 2 microns or more. The thin film transistor of claim 1, further comprising a buffer layer disposed between the substrate and the active layer, wherein the dopant is doped into the buffer layer. The thin film transistor of claim 8, wherein in the region overlapping the conductor providing portion, the doping concentration of the conductor providing portion is higher than the doping concentration of the gate insulating layer and the doping concentration of the buffer layer . The thin film transistor according to claim 8, wherein in the region overlapping the conductor supplying portion, the doping concentration of the buffer layer is higher than the doping concentration of the conductor supplying portion and the doping concentration of the gate insulating layer . The thin film transistor of claim 1, wherein the active layer further comprises: a first oxide semiconductor layer on the substrate; and a second oxide semiconductor layer on the first oxide semiconductor layer. The thin film transistor of claim 1, further comprising a source electrode and a drain electrode, the source electrode and the drain electrode being separated from each other and connected to the active layer. The thin film transistor according to claim 12, wherein the source electrode, the drain electrode and the gate electrode are disposed in the same layer body, and comprise the same material as the gate electrode. The thin film transistor of claim 1, wherein when the thin film transistor is turned on, the resistivity of the deviation portion is higher than the resistivity of the channel portion and higher than the resistivity of the conductor providing portion. A thin film transistor substrate, comprising: a base substrate; and a first thin film transistor and a second thin film transistor on the base substrate, wherein the first thin film transistor includes a first active layer and a a first gate electrode, the first active layer is located on the base substrate, the first gate electrode is separated from the first active layer to at least partially overlap the first active layer, the second thin film transistor includes : a second active layer on the base substrate; a gate electrode separated from the second active layer to at least partially overlap the second active layer; and a gate insulating layer on the second active layer layer and the second gate electrode, wherein the gate insulating layer covers the entire top surface of the second active layer facing the second gate electrode, the second active layer includes: a channel portion overlapping on the second gate electrode; a conductor providing portion not overlapping the second gate electrode; and an offset portion located between the channel portion and the conductor providing portion, wherein the offset portion does not overlap the second gate electrode pole electrode, the conductor supply part is doped with a dopant, the first active layer and the second active layer are arranged on different layers, and the deviation part is in the direction from the channel part to the conductor supply part has an increasing dopant concentration gradient in ; when the width of the channel portion is L1 and the width of the deviation portion is L2, the thin film transistor satisfies the following equation 1,

where η1 satisfies the following relation: 0.5 square microns

η1

1.5 square microns. The thin film transistor substrate of claim 15, wherein the first active layer is a silicon semiconductor layer, and the second active layer is an oxide semiconductor layer. The thin film transistor substrate of claim 15, wherein the resistivity of the deviation portion is lower than the resistivity of the channel portion and higher than the resistivity of the conductor providing portion. The thin film transistor substrate of claim 15, wherein when the second thin film transistor is turned on, the resistivity of the deviation portion is higher than that of the channel portion and higher than that of the conductor providing portion. A method of manufacturing a thin film transistor, the method comprising: forming an active layer on a substrate; forming a gate insulating layer on the active layer; forming a gate electrode on the gate insulating layer to at least partially overlapping the active layer; and doping the active layer with a dopant, wherein the gate insulating layer covers the entire top surface of the active layer facing the gate electrode, the step of forming the gate electrode comprises: A gate electrode material layer is formed on the gate insulating layer; a photoresist pattern is formed on the gate electrode material layer; and the gate electrode material layer is etched by using the photoresist pattern as a mask, wherein the The area of the photoresist pattern is larger than the area of the gate electrode, in a plan view, the gate electrode is disposed in the area defined by the photoresist pattern, and is used in the step of doping the dopant on the active layer The photoresist pattern acts as a mask; when the width of the gate electrode is LG and the width of the photoresist pattern protruding from the gate electrode is Loh, the method satisfies the following equation 2,

where η2 satisfies the following relation: 0.5 square microns

η2

1.5 square microns. The method of claim 19, wherein the dopant comprises at least one of boron, phosphorus, fluorine, and hydrogen. The method of claim 19, wherein η2 is 0.5 square microns. A display device, comprising: a substrate; a pixel driving circuit on the substrate; and a light-emitting device connected to the pixel driving circuit, wherein the pixel driving circuit includes a thin film transistor, and the thin film transistor includes: an active layer on the substrate; a gate electrode separated from the active layer to at least partially overlap the active layer; and a gate insulating layer between the active layer and the gate electrode, wherein the gate The insulating layer covers the entire top surface of the active layer facing the gate electrode, the active layer includes: a channel portion overlapping the gate electrode; a conductor providing portion not overlapping the gate electrode; and a deviation part, located between the channel part and the conductor supply part, wherein the deviation part does not overlap the gate electrode, the conductor supply part is doped with a dopant, and wherein the deviation part is from the channel part to the conductor There is an increasing dopant concentration gradient in the direction of the providing portion; when the width of the channel portion is L1 and the width of the offset portion is L2, the thin film transistor satisfies the following equation 1,

where η1 satisfies the following relation: 0.5 square microns

η1

1.5 square microns. The display device of claim 22, wherein the resistivity of the deviation portion is lower than the resistivity of the channel portion and higher than the resistivity of the conductor providing portion. The display device of claim 22, wherein when the thin film transistor is turned on, the resistivity of the deviation portion is higher than the resistivity of the channel portion and higher than the resistivity of the conductor providing portion. A display device, comprising: a first thin film transistor, including a first active layer, a first gate electrode, a first gate insulating layer, a first source electrode and a first drain electrode, the The first active layer includes polysilicon, the first gate electrode overlaps the first active layer, the first gate insulating layer is located between the first active layer and the first gate electrode, and the first source electrode and the first drain electrode are respectively connected to the first active layer; a first intermediate insulating layer is disposed on the first gate electrode; a second thin film transistor includes a second active layer, a second gate electrode, a second gate insulating layer, a second source electrode and a second drain electrode, the second active layer includes oxide semiconductor, the second gate electrode overlaps the second active layer, The second gate insulating layer is located between the second active layer and the second gate electrode, the second source electrode and the second drain electrode are respectively connected to the second active layer, the second active layer It further includes a channel part, a conductor supply part and a deviation part, the deviation part is located between the channel part and the conductor supply part; and a second intermediate insulating layer, arranged on the first gate electrode, the second on the gate electrode and the second gate insulating layer, wherein the second gate insulating layer and the second intermediate insulating layer include a dopant for doping the second active layer, wherein the offset portion is The channel portion has an increasing dopant concentration gradient in the direction of the conductor providing portion; when the width of the channel portion is L1 and the width of the deviation portion is L2, the thin film transistor satisfies the following equation 1,

where η1 satisfies the following relation: 0.5 square microns

η1

1.5 square microns. The display device of claim 25, wherein the dopant doped in the second active layer comprises at least one of boron, phosphorus, fluorine and hydrogen. The display device of claim 25, wherein the second active layer further comprises: a second channel region overlapping the second gate electrode, the second channel region being the channel portion; a second source region , disposed on one side of the second channel region and connected to the second source electrode; and a second drain region, disposed on the other side of the second channel region and connected to the second drain electrode. The display device as claimed in claim 27, wherein the conductor supplying portion includes a first conductor supplying portion and a second conductor supplying portion, and the deviation portion includes a first deviation portion and a second deviation portion, The second source region includes the first conductor supplying part and the first deviation part, the first conductor supplying part is disposed on the side of the second channel region, and the first deviation part is disposed in the first conductor supplying part and between the side of the second channel region, and the second drain region includes the second conductor providing portion and the second offset portion, the second conductor providing portion is disposed on the other side of the second channel region side, the second deviation portion is disposed between the second conductor providing portion and the other side of the second channel region. The display device of claim 28, wherein the first conductor providing portion, the second conductor providing portion, the first offset portion, and the second offset portion include the dopant. The display device of claim 29, wherein the concentration of the dopant in each of the first conductor supplying portion and the second conductor supplying portion is higher than the doping concentration of each of the first deviation portion and the second deviation portion concentration of matter. The display device of claim 25, wherein the first gate insulating layer covers the entire top surface of the first active layer facing the first gate electrode, and the second gate insulating layer covers the entire top surface facing the first gate electrode The entire top surface of the second active layer of the second gate electrode.

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