TW202406157A - Active component substrate - Google Patents

Abstract

An active component substrate includes a substrate, a first active component and a second active component electrically connected to the first active component. The first active component includes a first bottom gate, a first semiconductor structure, a first top gate, a first source and a first drain. The first source is electrically connected to the first bottom gate. The second active component includes a second bottom gate, a second semiconductor structure, a second top gate, a second source and a second drain. The thickness of the second semiconductor structure is smaller than the thickness of the first semiconductor structure. The second bottom gate is electrically connected to the second top gate.

Description

Active component substrate

The invention relates to an active component substrate.

Thin film transistors are a type of field effect transistor that can be formed by depositing multiple layers of metal, semiconductor and dielectric layers on a glass substrate. Currently, many electronic devices include thin film transistors for different purposes. For example, many display devices include a thin film transistor array substrate, and the thin film transistor array includes switching elements and driving elements, where the switching elements are used to control the gates of the driving elements. By cooperating between the switching element and the driving element, the magnitude of the current passing through the driving element can be controlled.

The present invention provides an active component substrate that can improve the long-term turn-on reliability of the first active component and simultaneously increase the turn-on current of the second active component.

At least one embodiment of the present invention provides an active device substrate. The active component substrate includes a substrate, a first active component and a second active component electrically connected to the first active component. The first active component and the second active component are located on the substrate. The first active component includes a first bottom gate, a first semiconductor structure, a first top gate, a first source and a first drain. The first semiconductor structure is located between the first bottom gate and the first top gate. The first source and the first drain are electrically connected to the first semiconductor structure. The first source is electrically connected to the first bottom gate. The second active component includes a second bottom gate, a second semiconductor structure, a second top gate, a second source and a second drain. The second semiconductor structure is located between the second bottom gate and the second top gate. The thickness of the second semiconductor structure is less than the thickness of the first semiconductor structure. The second bottom gate is electrically connected to the second top gate. The second source electrode and the second drain electrode are electrically connected to the second semiconductor structure.

1A is a schematic top view of an active device substrate according to an embodiment of the present invention. Fig. 1B is a schematic cross-sectional view along lines a-a', b-b' and c-c' of Fig. 1A. For convenience of explanation, FIG. 1A shows the first bottom gate BG1, the first top gate TG1, the first source S1, the first drain D1, the second bottom gate BG2, and the second top gate of the active component substrate 10. TG2, the second source S2 and the second drain D2, and other components are omitted from illustration.

Referring to FIGS. 1A and 1B , the active device substrate 10 includes a substrate SB, a first active device TFT1 and a second active device TFT2 . In some embodiments, the second active element TFT2 is electrically connected to the first active element TFT1, but the invention is not limited thereto.

The material of the substrate SB can be glass, quartz, organic polymer or opaque/reflective material (such as conductive material, metal, wafer, ceramic or other applicable materials) or other applicable materials. If conductive materials or metals are used, an insulating layer (not shown) is covered on the substrate SB to avoid short circuit problems. In some embodiments, the substrate SB is a flexible substrate, and the material of the substrate SB is, for example, polyethylene terephthalate (PET), polyethylene naphthalate (PEN), polyester (polyester, PES), polymethylmethacrylate (PMMA), polycarbonate (PC), polyimide (PI) or metal foil (Metal Foil) or other flexible materials .

The buffer layer BL is located on the substrate SB. The buffer layer BL has a single-layer or multi-layer structure, and the material of the buffer layer BL may include silicon oxide, silicon oxynitride or other suitable materials or stacked layers of the above materials.

The first active element TFT1 and the second active element TFT2 are located on the substrate SB. In this embodiment, the first active element TFT1 and the second active element TFT2 are located on the buffer layer BL.

The first active element TFT1 includes a first bottom gate BG1, a first semiconductor structure SM1, a first top gate TG1, a first source S1 and a first drain D1. The second active element TFT2 includes a second bottom gate BG2, a second semiconductor structure SM2, a second top gate TG2, a second source S2 and a second drain D2.

The first bottom gate BG1 and the second bottom gate BG2 are located on the buffer layer BL. In some embodiments, the first bottom gate BG1 and the second bottom gate BG2 include the same or different materials. In some embodiments, the materials of the first bottom gate BG1 and the second bottom gate BG2 may include metals, such as chromium (Cr), gold (Au), silver (Ag), copper (Cu), and tin (Sn). , lead (Pb), hafnium (Hf), tungsten (W), molybdenum (Mo), neodymium (Nd), titanium (Ti), tantalum (Ta), aluminum (Al), zinc (Zn) or any of the above metals A combination of alloys or a laminate of the above-mentioned metals and/or alloys, but the invention is not limited thereto. The first bottom gate BG1 and the second bottom gate BG2 can also use other conductive materials, such as metal nitride, metal oxide, metal oxynitride, stacked layers of metal and other conductive materials, or other materials with Materials with conductive properties.

The first gate dielectric layer GI1 is located on the first bottom gate BG1 and the second bottom gate BG2. In this embodiment, the first gate dielectric layer GI1 contacts the upper surfaces of the first bottom gate BG1 and the second bottom gate BG2. In some embodiments, the material of the first gate dielectric layer GI1 includes silicon oxide, silicon oxynitride, aluminum oxide, hafnium oxide or other suitable materials.

The first semiconductor structure SM1 and the second semiconductor structure SM2 are located on the first gate dielectric layer GI1. The first gate dielectric layer GI1 is located between the first bottom gate BG1 and the first semiconductor structure SM1 and between the second bottom gate BG2 and the second semiconductor structure SM2. In some embodiments, the first semiconductor structure SM1 includes a first source region sr1, a first drain region dr1, and a first channel region ch1 located between the first source region sr1 and the first drain region dr1. Similarly, the second semiconductor structure SM2 includes a second source region sr2, a second drain region dr2, and a second channel region ch2 located between the second source region sr2 and the second drain region dr2. The first source region sr1, the first drain region dr1, the second source region sr2 and the second drain region dr2 are doped (for example, hydrogen doped) to have a lower thickness than the first channel region ch1 and the second channel region Resistivity of ch2.

In this embodiment, the thickness t2 of the second semiconductor structure SM2 is smaller than the thickness t1 of the first semiconductor structure SM1. In some embodiments, by increasing the thickness t1 of the first semiconductor structure SM1, the resistivity of the first channel region ch1 can be reduced, thereby reducing the threshold voltage (Vth) of the first active element TFT1 and increasing the first active element TFT1. Turn-on current of TFT1.

The first semiconductor structure SM1 may be a single-layer structure or a multi-layer structure. In this embodiment, the first semiconductor structure SM1 is a multi-layer structure and includes a first semiconductor layer OS1 and a second semiconductor layer OS2. The second semiconductor layer OS2 overlaps the first semiconductor layer OS1, and the first semiconductor layer OS1 is closer to the substrate SB than the second semiconductor layer OS2. In some embodiments, the second semiconductor structure SM2 is a single-layer structure, and the second semiconductor layer OS2 and the second semiconductor structure SM2 belong to the same patterned layer.

In some embodiments, the materials of the first semiconductor layer OS1, the second semiconductor layer OS2 and the second semiconductor structure SM2 include indium gallium tin zinc oxide (IGTZO) or indium gallium zinc oxide (IGZO), indium tin zinc oxide (ITZO) ), aluminum zinc tin oxide (AZTO), indium tungsten zinc oxide (IWZO) and other quaternary metal compounds may contain gallium (Ga), zinc (Zn), indium (In), tin (Sn), aluminum (Al), tungsten (W) Any three oxides composed of ternary metals or lanthanide rare earth doped metal oxides (such as Ln-IZO). In some embodiments, the first semiconductor layer OS1 and the second semiconductor layer OS2 may include the same or different materials.

The second gate dielectric layer GI2 is located on the first gate dielectric layer GI1, the first semiconductor structure SM1 and the second semiconductor structure SM2. The first semiconductor structure SM1 and the second semiconductor structure SM2 are sandwiched between the first gate dielectric layer GI1 and the second gate dielectric layer GI2. In some embodiments, the material of the second gate dielectric layer GI2 includes silicon oxide, silicon oxynitride, aluminum oxide, hafnium oxide or other suitable materials.

The first top gate TG1 and the second top gate TG2 are located on the second gate dielectric layer GI2. The second gate dielectric layer GI2 is located between the first top gate TG1 and the first semiconductor structure SM1 and between the second top gate TG2 and the second semiconductor structure SM2. The first semiconductor structure SM1 is located between the first bottom gate BG1 and the first top gate TG1. The second semiconductor structure SM2 is located between the second bottom gate BG2 and the second top gate TG2. In some embodiments, the first top gate TG1 and the second top gate TG2 include the same or different materials. In some embodiments, the materials of the first top gate TG1 and the second top gate TG2 may include metals, such as chromium (Cr), gold (Au), silver (Ag), copper (Cu), and tin (Sn). , lead (Pb), hafnium (Hf), tungsten (W), molybdenum (Mo), neodymium (Nd), titanium (Ti), tantalum (Ta), aluminum (Al), zinc (Zn) or any of the above metals A combination of alloys or a laminate of the above-mentioned metals and/or alloys, but the invention is not limited thereto. The first top gate TG1 and the second top gate TG2 can also use other conductive materials, such as metal nitride, metal oxide, metal oxynitride, stacked layers of metal and other conductive materials, or other materials with Materials with conductive properties.

In this embodiment, the second active component TFT2 is a double-gate thin film transistor (herein referred to as a TG-sync thin film transistor) in which the second bottom gate BG2 is electrically connected to the second top gate TG2. For example, the second top gate TG2 is connected to the second bottom gate BG2 through the contact hole V1, wherein the contact hole V1 passes through the first gate dielectric layer GI1 and the second gate dielectric layer GI2.

The first interlayer dielectric layer ILD1 is located on the first top gate TG1 and the second top gate TG2. The second interlayer dielectric layer ILD2 is located on the first interlayer dielectric layer ILD1. In some embodiments, the materials of the first interlayer dielectric layer ILD1 and the second interlayer dielectric layer ILD2 include silicon oxide, silicon oxynitride, aluminum oxide, hafnium oxide, organic insulating materials or other suitable materials.

The first source electrode S1, the first drain electrode D1, the second source electrode S2 and the second drain electrode D2 are located on the second interlayer dielectric layer ILD2. The first source S1 and the first drain D1 are electrically connected to the first source region sr1 and the first drain region dr1 of the first semiconductor structure SM1 through the contact holes H1 and H2 respectively, and the second source S2 and the first drain region dr1 of the first semiconductor structure SM1. The two drains D2 are electrically connected to the second source region sr2 and the second drain region dr2 of the second semiconductor structure SM2 respectively through the contact holes H3 and H4, wherein the contact holes H1 to H4 pass through the second gate dielectric layer. GI2, the first interlayer dielectric layer ILD1 and the second interlayer dielectric layer ILD2. In some embodiments, the materials of the first source electrode S1, the first drain electrode D1, the second source electrode S2, and the second drain electrode D2 may include metals, such as chromium (Cr), gold (Au), and silver (Ag). , Copper (Cu), Tin (Sn), Lead (Pb), Hafnium (Hf), Tungsten (W), Molybdenum (Mo), Neodymium (Nd), Titanium (Ti), Tantalum (Ta), Aluminum (Al) , zinc (Zn) or an alloy of any combination of the above metals or a laminate of the above metals and/or alloys, but the invention is not limited thereto. The first source S1, the first drain D1, the second source S2 and the second drain D2 may also use other conductive materials, such as metal nitrides, metal oxides, metal oxynitrides, metal and Stacked layers of other conductive materials or other materials with conductive properties. The protective layer PL covers the first source electrode S1, the first drain electrode D1, the second source electrode S2 and the second drain electrode D2.

In this embodiment, the first active component TFT1 is a double-gate thin film transistor (referred to as a source-sync thin film transistor in this article) in which the first source S1 is electrically connected to the first bottom gate BG1. For example, the first source S1 is connected to the first bottom gate BG1 through the contact hole V2, wherein the contact hole V2 passes through the first gate dielectric layer GI1, the second gate dielectric layer GI2, and the first interlayer dielectric. The electrical layer ILD1 and the second interlayer dielectric layer ILD2. In other embodiments, the first source S1 does not directly contact the first bottom gate BG1, and the first source S1 is electrically connected to the first bottom gate BG1 through other transfer electrodes.

Table 1 shows the comparison of various characteristics of TG-sync thin film transistors and source-sync thin film transistors when the semiconductor structures are the same. In Table 1, ◎ represents excellent, ○ represents fair, and ▽ represents poor. Table 1 TG-sync source-sync Turn on current ( Ion ) ◎ ▽ Threshold voltage ( Vth ) ○ ◎ Threshold Voltage Uniformity ( Vth U% ) ◎ ○ Drain -side induced barrier lowering ( DIBL ) ◎ ◎ Saturation turn-on current ( Saturation Ion ) ◎ ◎ Positive Bias - Temperature Stress ( PBTS ) ▽ ◎ Negative Bias - Temperature Stress ( NBTS ) ◎ ◎ Negative Bias - Illumination Stress ( NBIS ) ◎ ◎

As can be seen from Table 1, TG-Sync thin film transistors are suitable for use as switching thin film transistors (Switching TFT). The arrangement of the top gate electrically connected to the bottom gate can increase the turn-on current. Although TG-Sync thin film transistors will have the problem of PBTS (Positive gate bias temperature stress). However, since the switching thin film transistor needs to be turned on for a relatively short time, using TG-Sync thin film transistors for switching thin film transistors is not prone to reliability problems.

In addition, Source-Sync thin film transistors are suitable for use as driving thin film transistors (Driving TFT). The arrangement of the bottom gate electrically connected to the source can increase long-term turn-on reliability. However, since the bottom gate is electrically connected to a low potential (such as ground potential), the turn-on current of the Source-Sync thin film transistor will become smaller.

In the embodiment of FIG. 1A to FIG. 1B , by increasing the thickness t1 of the first semiconductor structure SM1 , the problem of small turn-on current of the first active element TFT1 (Source-Sync thin film transistor) can be improved. In addition, since the thickness t2 of the second semiconductor structure SM2 is smaller, the leakage problem of the second active element TFT2 (TG-Sync thin film transistor) can be improved.

2A is an experimental data diagram of the thickness and threshold voltage of the first semiconductor structure of the first active component (Source-Sync thin film transistor) according to some embodiments of the present invention. 2A shows the relationship between the thickness of the first semiconductor structure and the threshold voltage under the first condition and the relationship between the thickness of the first semiconductor structure and the threshold voltage under the second condition, wherein the difference between the first condition and the second condition is shown in FIG. This is: in the first condition, when depositing the first gate dielectric layer GI1 (please refer to Figure 1B), the ratio of nitrogen dioxide to silica methane is relatively high, and the thickness of the first gate dielectric layer GI1 is 1800 angstroms. ; In the second condition, when depositing the first gate dielectric layer GI1 (please refer to FIG. 1B ), the ratio of nitrogen dioxide to silica methane is low, and the thickness of the first gate dielectric layer GI1 is 2150 angstroms.

FIG. 2B is an experimental data graph showing the thickness and turn-on current of the first semiconductor structure of the first active component (Source-Sync thin film transistor) according to some embodiments of the present invention.

It can be known from FIGS. 2A and 2B that as the thickness t1 of the first semiconductor structure SM1 (please refer to FIG. 1B ) increases, the threshold voltage of the first active element TFT1 decreases and the turn-on current increases.

Figure 3 shows the decay of the turn-on current (Ion drop) and the change of the threshold voltage (Vth shift) of the first active component (Source-Sync thin film transistor) after long-term operation according to some embodiments of the present invention. In Figure 3, the first active component is operated at 90˚C for 1 hour, where the voltage difference Vds between the first drain and the first source is 20V, and the operating current is 100uA. Furthermore, in the first active element of Figure 3, the first channel region is 50 microns wide and 6 microns long.

It can be seen from FIG. 3 that as the thickness of the first semiconductor structure increases, the current decline of the first active element after long-term operation is smaller, and the decline of the threshold voltage is also smaller.

4A to 4E are schematic cross-sectional views of the manufacturing method of the active device substrate 10 of FIG. 1 .

Referring to FIG. 4A , a first bottom gate BG1 and a second bottom gate BG2 are formed on the buffer layer BL. In some embodiments, the method of forming the first bottom gate BG1 and the second bottom gate BG2 includes: forming a conductive material layer (not shown) on the buffer layer BL; forming a patterned photoresist layer (not shown) On the conductive material layer; use the patterned photoresist layer as a mask to etch the conductive material layer to form the first bottom gate BG1 and the second bottom gate BG2; finally, remove the patterned photoresist layer. In other words, the first bottom gate BG1 and the second bottom gate BG2 belong to the same patterned layer.

Next, a first gate dielectric layer GI1 is formed on the first bottom gate BG1 and the second bottom gate BG2. Afterwards, a first semiconductor layer OS1' is formed on the first gate dielectric layer GI1. The first semiconductor layer OS1' overlaps the first bottom gate BG1.

Referring to FIG. 4B, a second semiconductor layer OS2' is formed on the first semiconductor layer OS1', and a second semiconductor structure SM2' is formed on the first gate dielectric layer GI1. The second semiconductor structure SM2' overlaps the second bottom gate BG2. In some embodiments, the method of forming the second semiconductor layer OS2' and the second semiconductor structure SM2' includes: forming a semiconductor material layer (not shown) on the first gate dielectric layer GI1 and the first semiconductor layer OS1'; Form a patterned photoresist layer (not shown) on the semiconductor material layer; use the patterned photoresist layer as a mask to etch the semiconductor material layer to form the second semiconductor layer OS2' and the second semiconductor structure SM2'; finally, move Remove the patterned photoresist layer. In other words, the second semiconductor layer OS2' and the second semiconductor structure SM2' belong to the same patterned layer.

In this embodiment, the first semiconductor structure SM1' includes a stack of the first semiconductor layer OS1' and the second semiconductor layer OS2'. Therefore, the thickness of the first semiconductor structure SM1' is greater than the thickness of the second semiconductor structure SM2'.

Referring to FIG. 4C, a second gate dielectric layer GI2 is formed on the first semiconductor structure SM1' and the second semiconductor structure SM2'.

Then, the first top gate TG1 and the second top gate TG2 are formed on the second gate dielectric layer GI2. In some embodiments, a method of forming the first top gate TG1 and the second top gate TG2 includes: forming a conductive material layer (not shown) on the second gate dielectric layer GI2; forming a patterned photoresist layer (not shown) (not shown) on the conductive material layer; use the patterned photoresist layer as a mask to etch the conductive material layer to form the first top gate TG1 and the second top gate TG2; finally, remove the patterned photoresist layer. In other words, the first top gate TG1 and the second top gate TG2 belong to the same patterned layer.

Using the first top gate TG1 and the second top gate TG2 as masks, a doping process P is performed to form a first semiconductor including a first source region sr1, a first drain region dr1 and a first channel region ch1. The structure SM1 and the second semiconductor structure SM2 including the second source region sr2, the second drain region dr2 and the second channel region ch2. In some embodiments, the doping process P is, for example, hydrogen plasma doping or other suitable processes.

In some embodiments, before forming the first top gate TG1 and the second top gate TG2, an etching process is performed on the first gate dielectric layer GI1 and the second gate dielectric layer GI2 to form an exposed second bottom gate. Contact hole V1 of gate BG2. Then, a second top gate TG2 is formed in the contact hole V1 to electrically connect the second bottom gate BG2.

Referring to FIG. 4D, a first interlayer dielectric layer ILD1 is formed on the first top gate TG1 and the second top gate TG2. A second interlayer dielectric layer ILD2 is formed on the first interlayer dielectric layer ILD1. Then, one or more etching processes are performed to form contact holes H1 to H4 exposing the first source region sr1, the first drain region dr1, the second source region sr2, and the second drain region dr2. In some embodiments, while forming the contact holes H1 to H4, a contact hole V2 exposing the first bottom gate BG1 is formed.

Finally, please return to FIG. 1A to FIG. 1B to form the first source electrode S1, the first drain electrode D1, the second source electrode S2 and the second drain electrode D2 on the second interlayer dielectric layer ILD2. The first source electrode S1 , the first drain electrode D1, the second source electrode S2 and the second drain electrode D2 are respectively filled in the contact holes H1~H4. In some embodiments, the first source S1 is also filled in the contact hole V2.

Finally, a protective layer PL is selectively formed on the first source electrode S1, the first drain electrode D1, the second source electrode S2 and the second drain electrode D2. At this point, the active device substrate 10 is substantially completed.

FIG. 5 is a schematic cross-sectional view of an active device substrate according to an embodiment of the present invention. It must be noted here that the embodiment of FIG. 5 follows the component numbers and part of the content of the embodiment of FIGS. 1A to 1B , where the same or similar numbers are used to represent the same or similar elements, and references with the same technical content are omitted. instruction. For descriptions of omitted parts, reference may be made to the foregoing embodiments and will not be described again here.

The main difference between the active component substrate 20 of FIG. 5 and the active component substrate 10 of FIGS. 1A to 1B is that in the active component substrate 20 , the first active component TFT1 selectively includes a transfer electrode TE.

Please refer to FIG. 5 . The transfer electrode TE is electrically connected to the first bottom gate BG1 and the first source S1 . The transfer electrode TE is separated from the first top gate electrode TG1 and the second top gate electrode TG2. For example, the transfer electrode TE is connected to the first bottom gate BG1 through the contact hole V2, wherein the contact hole V2 passes through the first gate dielectric layer GI1 and the second gate dielectric layer GI2. In some embodiments, the transfer electrode TE, the first top gate TG1 and the second top gate TG2 belong to the same patterned layer. In other words, the transfer electrode TE, the first top gate TG1 and the second top gate TG2 can be formed by the same patterning process. In addition, in this embodiment, before forming the first source electrode S1, while forming the contact holes H1 to H4, a contact hole V2' exposing the transfer electrode TE is formed. Next, the first source electrode S1 is formed in the contact hole V2' to connect to the transfer electrode TE.

FIG. 6 is a schematic cross-sectional view of an active device substrate according to an embodiment of the present invention. It must be noted here that the embodiment of FIG. 6 follows the component numbers and part of the content of the embodiment of FIGS. 1A to 1B , where the same or similar numbers are used to represent the same or similar elements, and references with the same technical content are omitted. instruction. For descriptions of omitted parts, reference may be made to the foregoing embodiments and will not be described again here.

The main difference between the active device substrate 30 of FIG. 6 and the active device substrate 10 of FIGS. 1A to 1B is that in the active device substrate 30 , the first semiconductor structure SM1 and the second semiconductor structure SM2 belong to different patterned layers.

Please refer to FIG. 6 , the first gate dielectric layer GI1 is located on the first bottom gate BG1 , the second bottom gate BG2 and the buffer layer BL. The first semiconductor structure SM1 is located on the first gate dielectric layer GI1. The first gate dielectric layer GI1 is located between the first bottom gate BG1 and the first semiconductor structure SM1.

The second gate dielectric layer GI2 is located on the first semiconductor structure SM1 and the first gate dielectric layer GI1. The second semiconductor structure SM2 is located on the second gate dielectric layer GI2. The second gate dielectric layer GI2 and the first gate dielectric layer GI1 are located between the second bottom gate BG2 and the second semiconductor structure SM2.

The third gate dielectric layer GI3 is located on the second gate dielectric layer GI2 and the second semiconductor structure SM2.

The first top gate TG1 and the second top gate TG2 are located on the third gate dielectric layer GI3. The second gate dielectric layer GI2 is located between the first top gate TG1 and the first semiconductor structure SM1. The third gate dielectric layer GI3 is located between the first top gate TG1 and the first semiconductor structure SM1 and between the second top gate TG2 and the second semiconductor structure SM2.

In this embodiment, both the first semiconductor structure SM1 and the second semiconductor structure SM2 are single-layer structures, but the invention is not limited thereto. In other embodiments, the first semiconductor structure SM1 is a multi-layer structure, and the second semiconductor structure SM2 is a single-layer structure.

In the embodiment of FIG. 6 , by increasing the thickness t1 of the first semiconductor structure SM1 , the problem of small turn-on current of the first active element TFT1 (Source-Sync thin film transistor) can be improved. In addition, since the thickness t2 of the second semiconductor structure SM2 is smaller, the leakage problem of the second active element TFT2 (TG-Sync thin film transistor) can be improved.

7A to 7D are schematic cross-sectional views of the manufacturing method of the active device substrate 30 of FIG. 6 .

Referring to FIG. 7A , a first bottom gate BG1 and a second bottom gate BG2 are formed on the buffer layer BL. In some embodiments, the first bottom gate BG1 and the second bottom gate BG2 belong to the same patterned layer.

Next, a first gate dielectric layer GI1 is formed on the first bottom gate BG1 and the second bottom gate BG2. Afterwards, a first semiconductor structure SM1' is formed on the first gate dielectric layer GI1. The first semiconductor structure SM1' overlaps the first bottom gate BG1.

Referring to FIG. 7B, a second gate dielectric layer GI2 is formed on the first semiconductor structure SM1' and the first gate dielectric layer GI1. Next, a second semiconductor structure SM2' is formed on the second gate dielectric layer GI2. The second semiconductor structure SM2' overlaps the second bottom gate BG2.

In this embodiment, the thickness of the first semiconductor structure SM1' is greater than the thickness of the second semiconductor structure SM2'.

In this embodiment, the first semiconductor structure SM1', the second gate dielectric layer GI2 and the second semiconductor structure SM2' are formed sequentially, but the invention is not limited thereto. In other embodiments, the second semiconductor structure SM2' is formed first, then the second gate dielectric layer GI2 is formed, and finally the first semiconductor structure SM1' is formed. In other words, in other embodiments, the second gate dielectric layer GI2 is formed on the second semiconductor structure SM2', and the first semiconductor structure SM1' is formed on the second gate dielectric layer GI2.

Referring to FIG. 7C, a third gate dielectric layer GI3 is formed on the second gate dielectric layer GI2 and the second semiconductor structure SM2'.

Then, the first top gate TG1 and the second top gate TG2 are formed on the second gate dielectric layer GI2. In some embodiments, the first top gate TG1 and the second top gate TG2 belong to the same patterned layer.

Using the first top gate TG1 and the second top gate TG2 as masks, a doping process P is performed to form a first semiconductor including a first source region sr1, a first drain region dr1 and a first channel region ch1. The structure SM1 and the second semiconductor structure SM2 including the second source region sr2, the second drain region dr2 and the second channel region ch2.

In some embodiments, before forming the first top gate TG1 and the second top gate TG2, an etching process is performed on the first gate dielectric layer GI1 and the second gate dielectric layer GI2 to form an exposed second bottom gate. Contact hole V1 of gate BG2. Then, a second top gate TG2 is formed in the contact hole V1 to electrically connect the second bottom gate BG2.

Referring to FIG. 7D, a first interlayer dielectric layer ILD1 is formed on the first top gate TG1 and the second top gate TG2. A second interlayer dielectric layer ILD2 is formed on the first interlayer dielectric layer ILD1. Then, one or more etching processes are performed to form contact holes H1 to H4 exposing the first source region sr1, the first drain region dr1, the second source region sr2, and the second drain region dr2. In some embodiments, while forming the contact holes H1 to H4, a contact hole V2 exposing the first bottom gate BG1 is formed.

Finally, please return to Figure 6. The first source electrode S1, the first drain electrode D1, the second source electrode S2 and the second drain electrode D2 are formed on the second interlayer dielectric layer ILD2. The drain electrode D1, the second source electrode S2 and the second drain electrode D2 are respectively filled in the contact holes H1~H4. In some embodiments, the first source S1 is also filled in the contact hole V2 to electrically connect the first bottom gate BG1.

Finally, a protective layer PL is selectively formed on the first source electrode S1, the first drain electrode D1, the second source electrode S2 and the second drain electrode D2. At this point, the active device substrate 30 is substantially completed.

FIG. 8 is a schematic cross-sectional view of an active device substrate according to an embodiment of the present invention. It must be noted here that the embodiment of FIG. 8 follows the component numbers and part of the content of the embodiment of FIG. 6 , where the same or similar numbers are used to represent the same or similar elements, and descriptions of the same technical content are omitted. For descriptions of omitted parts, reference may be made to the foregoing embodiments and will not be described again here.

The main difference between the active device substrate 40 of FIG. 8 and the active device substrate 30 of FIG. 6 is that in the active device substrate 40, the first semiconductor structure SM1 is located between the second gate dielectric layer GI2 and the third gate dielectric layer GI3. , and the second semiconductor structure SM2 is located between the first gate dielectric layer GI1 and the second gate dielectric layer GI2.

Referring to FIG. 8 , the first gate dielectric layer GI1 is located between the first bottom gate BG1 and the first semiconductor structure SM1 and between the second bottom gate BG2 and the second semiconductor structure SM2.

The second gate dielectric layer GI2 is located between the first bottom gate BG1 and the first semiconductor structure SM1 and between the second top gate TG1 and the second semiconductor structure SM2.

The third gate dielectric layer GI3 is located between the first top gate TG1 and the first semiconductor structure SM1 and between the second top gate TG2 and the second semiconductor structure SM2.

In this embodiment, both the first semiconductor structure SM1 and the second semiconductor structure SM2 are single-layer structures, but the invention is not limited thereto. In other embodiments, the first semiconductor structure SM1 is a multi-layer structure, and the second semiconductor structure SM2 is a single-layer structure.

In the embodiment of FIG. 8 , by increasing the thickness t1 of the first semiconductor structure SM1 , the problem of small turn-on current of the first active element TFT1 (Source-Sync thin film transistor) can be improved. In addition, since the thickness t2 of the second semiconductor structure SM2 is smaller, the leakage problem of the second active element TFT2 (TG-Sync thin film transistor) can be improved.

FIG. 9 is a schematic cross-sectional view of an active device substrate according to an embodiment of the present invention. FIG. 10 is a schematic diagram of a pixel circuit according to an embodiment of the present invention.

In this embodiment, the active device substrate includes a pixel circuit PX, and the pixel circuit includes a first active device TFT1, a second active device TFT2, a third active device TFT3, a light emitting diode LED, and a capacitor C. For the structures of the first active element TFT1 and the second active element TFT2, reference can be made to FIG. 1A, FIG. 1B and related contents, and will not be described again here.

Please refer to FIG. 1B and FIG. 9 . The third active element TFT3 has a structure similar to the second active element TFT2 . The third active element TFT3 is located on the substrate SB and includes a third bottom gate BG3, a third semiconductor structure SM3, a third top gate TG3, a third source S3 and a third drain D3.

The third bottom gate BG3 is located on the buffer layer BL. In some embodiments, the first bottom gate BG1, the second bottom gate BG2, and the third bottom gate BG3 include the same or different materials. In some embodiments, the first bottom gate BG1, the second bottom gate BG2, and the third bottom gate BG3 belong to the same patterned layer. In other words, the first bottom gate BG1, the second bottom gate BG2, and the third bottom gate BG3 are formed simultaneously.

The first gate dielectric layer GI1 is located on the third bottom gate BG3. In this embodiment, the first gate dielectric layer GI1 contacts the upper surface of the third bottom gate BG3.

The third semiconductor structure SM3 is located on the first gate dielectric layer GI1. The first gate dielectric layer GI1 is located between the third bottom gate BG3 and the third semiconductor structure SM3. In some embodiments, the third semiconductor structure SM3 includes a third source region sr3, a third drain region dr3, and a third channel region ch3 located between the third source region sr3 and the third drain region dr3. The third source region sr3 and the third drain region dr3 are doped (eg, hydrogen doped) to have a lower resistivity than the third channel region ch3.

In some embodiments, the third semiconductor structure SM3 and the second semiconductor structure SM2 belong to the same patterned layer. In other words, the third semiconductor structure SM3 and the second semiconductor structure SM2 are formed simultaneously. In some embodiments, the thickness t3 of the third semiconductor structure SM3 is the same as the thickness t2 of the second semiconductor structure SM2, and the third semiconductor structure SM3 and the second semiconductor structure SM2 include the same material.

The second gate dielectric layer GI2 is located on the third semiconductor structure SM3. The third semiconductor structure SM3 is sandwiched between the first gate dielectric layer GI1 and the second gate dielectric layer GI2.

The third top gate TG3 is located on the second gate dielectric layer GI2. The second gate dielectric layer GI2 is located between the third top gate TG3 and the third semiconductor structure SM3. The third semiconductor structure SM3 is located between the third bottom gate BG3 and the third top gate TG3. In some embodiments, the first top gate TG1, the second top gate TG2, and the third top gate TG3 include the same or different materials. In some embodiments, the first top gate TG1, the second top gate TG2, and the third top gate TG3 belong to the same patterned layer. In other words, the first top gate TG1, the second top gate TG2, and the third top gate TG3 are formed simultaneously.

In this embodiment, the third active component TFT3 is a dual-gate thin film transistor (TG-sync thin film transistor) in which the third bottom gate BG3 is electrically connected to the third top gate TG3. For example, the third top gate TG3 is connected to the third bottom gate BG3 through the contact hole V3, wherein the contact hole V3 passes through the first gate dielectric layer GI1 and the second gate dielectric layer GI2.

The first interlayer dielectric layer ILD1 is located on the third top gate TG3. The second interlayer dielectric layer ILD2 is located on the first interlayer dielectric layer ILD1.

The third source S3 and the third drain D3 are located on the second interlayer dielectric layer ILD2. The third source S3 and the third drain D3 are respectively electrically connected to the third source region sr3 and the third drain region dr3 of the third semiconductor structure SM3 through the contact holes H5 and H6. through the second gate dielectric layer GI2, the first interlayer dielectric layer ILD1 and the second interlayer dielectric layer ILD2. In some embodiments, the first source S1, the first drain D1, the second source S2, the second drain D2, the third source S3 and the third drain D3 include the same or different materials. In some embodiments, the first source S1, the first drain D1, the second source S2, the second drain D2, the third source S3 and the third drain D3 belong to the same patterned layer. In other words, the first source S1, the first drain D1, the second source S2, the second drain D2, the third source S3 and the third drain D3 are formed simultaneously.

Please refer to Figure 1B, Figure 9 and Figure 10 at the same time. In the pixel circuit PX, the first drain D1 of the first active element TFT1 is electrically connected to the voltage V _DD , and the first source S1 is electrically connected to the light emitting diode. One end of the body LED (such as an organic light-emitting diode or an inorganic light-emitting diode), one end of the capacitor C and the third drain D3 of the third active component TFT3; the first top gate TG1 is electrically connected to the capacitor The other end of C and the second source S2 of the second active element TFT2. The other end of the light-emitting diode LED is electrically connected to the voltage V _SS , and the voltage V _DD is higher than V _SS .

The second drain D2 of the second active element TFT2 is electrically connected to the data line voltage V _DL , and the second top gate TG2 is electrically connected to the first scan line voltage V _SCAN1 .

The third source S3 of the third active element TFT3 is electrically connected to the common line voltage V _COM , and the third top gate TG3 is electrically connected to the second scan line voltage V _SCAN2 .

In this embodiment, the second active component TFT2 serves as a switching thin film transistor, the first active component TFT1 serves as a driving thin film transistor, and the second active component TFT2 is used to control the first top gate TG1 of the first active component TFT1 switch. The third active element TFT3 serves as a sensing thin film transistor for transmitting information on the driving current through the first active element TFT1 to an external chip.

To sum up, the present invention can improve the long-term turn-on reliability of the first active component and increase the turn-on current of the second active component and the third active component.

10, 20, 30, 40: Active component substrate a-a', b-b', c-c': line BG1: first bottom gate BG2: second bottom gate BG3: third bottom gate BL: Buffer layer C: capacitor ch1: first channel area ch2: second channel area ch3: third channel area D1: first drain D2: second drain D3: third drain dr1: first drain area dr2: The second drain region dr3: the third drain region GI1: the first gate dielectric layer GI2: the second gate dielectric layer GI3: the third gate dielectric layer H1~H6, V1~V3, V2': contact hole ILD1 : first interlayer dielectric layer ILD2: second interlayer dielectric layer OS1, OS1': first semiconductor layer OS2, OS2': second semiconductor layer P: doping process PL: protective layer PX: pixel circuit S1: First source S2: Second source S3: Third source SB: Substrate SM1, SM1': First semiconductor structure SM2, SM2': Second semiconductor structure SM3: Third semiconductor structure sr1: First source region sr2: second source area sr3: third source area TFT1: first active component TFT2: second active component TFT3: third active component TG1: first top gate TG2: second top gate TG3: third Top gate t1~t3: thickness V _COM : common line voltage V _DD , V _SS : voltage V _DL : data line voltage V _SCAN1 : first scan line voltage V _SCAN2 : second scan line voltage

1A is a schematic top view of an active device substrate according to an embodiment of the present invention. Fig. 1B is a schematic cross-sectional view along lines a-a', b-b' and c-c' of Fig. 1A. 2A is a graph of experimental data of thickness and threshold voltage of the first semiconductor structure of the first active device according to some embodiments of the present invention. FIG. 2B is an experimental data graph showing the thickness of the first semiconductor structure of the first active device and the turn-on current according to some embodiments of the present invention. FIG. 3 shows the decay of the turn-on current and the change of the threshold voltage of the first active element after long-term operation according to some embodiments of the present invention. 4A to 4D are schematic cross-sectional views of the manufacturing method of the active device substrate of FIG. 1 . FIG. 5 is a schematic cross-sectional view of an active device substrate according to an embodiment of the present invention. FIG. 6 is a schematic cross-sectional view of an active device substrate according to an embodiment of the present invention. 7A to 7D are schematic cross-sectional views of the manufacturing method of the active device substrate of FIG. 6 . Figure 8 is a schematic cross-sectional view of an active device substrate according to an embodiment of the present invention. FIG. 9 is a schematic cross-sectional view of an active device substrate according to an embodiment of the present invention. FIG. 10 is a schematic diagram of a pixel circuit according to an embodiment of the present invention.

10:Active component substrate

a-a’, b-b’, c-c’: line

BG1: first bottom gate

BG2: The second bottom gate

BL: buffer layer

ch1: first channel area

ch2: second channel area

D1: first drain

D2: The second drain

dr1: first drain area

dr2: second drain region

GI1: first gate dielectric layer

GI2: Second gate dielectric layer

H1~H4,V1,V2: Contact holes

ILD1: first interlayer dielectric layer

ILD2: second interlayer dielectric layer

OS1: first semiconductor layer

OS2: second semiconductor layer

PL: protective layer

S1: first source

S2: second source

SB:Substrate

SM1: First semiconductor structure

SM2: Second semiconductor structure

sr1: first source region

sr2: second source region

TFT1: the first active component

TFT2: the second active component

TG1: The first top gate

TG2: The second top gate

t1,t2:Thickness

Claims (10)

An active component substrate including: a substrate; A first active component is located on the substrate and includes: a first bottom gate, a first semiconductor structure and a first top gate, wherein the first semiconductor structure is located between the first bottom gate and the first top gate; and A first source and a first drain are electrically connected to the first semiconductor structure, and the first source is electrically connected to the first bottom gate; and A second active component is located on the substrate and electrically connected to the first active component, wherein the second active component includes: a second bottom gate, a second semiconductor structure and a second top gate, wherein the second semiconductor structure is located between the second bottom gate and the second top gate, and the second semiconductor structure The thickness is less than the thickness of the first semiconductor structure, and the second bottom gate is electrically connected to the second top gate; and A second source electrode and a second drain electrode are electrically connected to the second semiconductor structure. The active component substrate as described in claim 1 further includes: a first gate dielectric layer between the first bottom gate and the first semiconductor structure and between the second bottom gate and the second semiconductor structure; and A second gate dielectric layer is located between the first top gate and the first semiconductor structure and between the second top gate and the second semiconductor structure. The active component substrate as described in claim 1 further includes: a first gate dielectric layer located between the first bottom gate and the first semiconductor structure and between the second bottom gate and the second semiconductor structure; a second gate dielectric layer between the first top gate and the first semiconductor structure and between the second bottom gate and the second semiconductor structure; and A third gate dielectric layer is located between the first top gate and the first semiconductor structure and between the second top gate and the second semiconductor structure. The active component substrate as described in claim 1 further includes: a first gate dielectric layer located between the first bottom gate and the first semiconductor structure and between the second bottom gate and the second semiconductor structure; a second gate dielectric layer between the first bottom gate and the first semiconductor structure and between the second top gate and the second semiconductor structure; and A third gate dielectric layer is located between the first top gate and the first semiconductor structure and between the second top gate and the second semiconductor structure. The active component substrate as described in claim 1 further includes: A third active component is located on the substrate and includes: a third bottom gate, a third semiconductor structure and a third top gate, wherein the third semiconductor structure is located between the third bottom gate and the third top gate, and the third bottom gate electrically connecting the third top gate; and A third source and a third drain are electrically connected to the third semiconductor structure, wherein the second source is electrically connected to the first top gate, and the first source is electrically connected to the The third drain. The active device substrate of claim 5, wherein the third semiconductor structure and the second semiconductor structure include the same thickness. The active device substrate of claim 1, wherein the first semiconductor structure is a single-layer structure or a multi-layer structure. The active device substrate according to claim 7, wherein the first semiconductor structure is a multi-layer structure and includes: a first semiconductor layer; and A second semiconductor layer overlaps the first semiconductor layer, and the second semiconductor layer and the second semiconductor structure belong to the same patterned layer. The active device substrate of claim 8, wherein the first semiconductor layer and the second semiconductor layer include different materials. The active device substrate of claim 1, wherein the first bottom gate and the second bottom gate belong to the same patterned layer, and the first top gate and the second top gate belong to another same patterned layer. layer.

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