TWI772842B - 用於判定一ｎ維張量之元素之記憶體位址之設備、系統、及方法 - Google Patents

用於判定一ｎ維張量之元素之記憶體位址之設備、系統、及方法 Download PDF

Info

Publication number
TWI772842B
TWI772842B TW109123874A TW109123874A TWI772842B TW I772842 B TWI772842 B TW I772842B TW 109123874 A TW109123874 A TW 109123874A TW 109123874 A TW109123874 A TW 109123874A TW I772842 B TWI772842 B TW I772842B
Authority
TW
Taiwan
Prior art keywords
tensor
dimension
index
elements
dimensional
Prior art date
Application number
TW109123874A
Other languages
English (en)
Chinese (zh)
Other versions
TW202040359A (zh
Inventor
禹同爀
安德魯 艾佛列特 菲而普斯
Original Assignee
美商谷歌有限責任公司
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by 美商谷歌有限責任公司 filed Critical 美商谷歌有限責任公司
Publication of TW202040359A publication Critical patent/TW202040359A/zh
Application granted granted Critical
Publication of TWI772842B publication Critical patent/TWI772842B/zh

Links

Images

Classifications

    • G—PHYSICS
    • G06—COMPUTING OR CALCULATING; COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F9/00—Arrangements for program control, e.g. control units
    • G06F9/06—Arrangements for program control, e.g. control units using stored programs, i.e. using an internal store of processing equipment to receive or retain programs
    • G06F9/30—Arrangements for executing machine instructions, e.g. instruction decode
    • G06F9/34—Addressing or accessing the instruction operand or the result ; Formation of operand address; Addressing modes
    • G06F9/355—Indexed addressing
    • G—PHYSICS
    • G06—COMPUTING OR CALCULATING; COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F17/00—Digital computing or data processing equipment or methods, specially adapted for specific functions
    • G06F17/10—Complex mathematical operations
    • G06F17/16—Matrix or vector computation, e.g. matrix-matrix or matrix-vector multiplication, matrix factorization
    • G—PHYSICS
    • G06—COMPUTING OR CALCULATING; COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F9/00—Arrangements for program control, e.g. control units
    • G06F9/06—Arrangements for program control, e.g. control units using stored programs, i.e. using an internal store of processing equipment to receive or retain programs
    • G06F9/30—Arrangements for executing machine instructions, e.g. instruction decode
    • G06F9/30098—Register arrangements
    • G06F9/3012—Organisation of register space, e.g. banked or distributed register file
    • G06F9/3013—Organisation of register space, e.g. banked or distributed register file according to data content, e.g. floating-point registers, address registers
    • G—PHYSICS
    • G06—COMPUTING OR CALCULATING; COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F12/00—Accessing, addressing or allocating within memory systems or architectures
    • G06F12/02—Addressing or allocation; Relocation
    • G06F12/0223—User address space allocation, e.g. contiguous or non contiguous base addressing
    • G06F12/023—Free address space management
    • G—PHYSICS
    • G06—COMPUTING OR CALCULATING; COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F9/00—Arrangements for program control, e.g. control units
    • G06F9/06—Arrangements for program control, e.g. control units using stored programs, i.e. using an internal store of processing equipment to receive or retain programs
    • G06F9/30—Arrangements for executing machine instructions, e.g. instruction decode
    • G06F9/30003—Arrangements for executing specific machine instructions
    • G06F9/30007—Arrangements for executing specific machine instructions to perform operations on data operands
    • G06F9/3001—Arithmetic instructions
    • G—PHYSICS
    • G06—COMPUTING OR CALCULATING; COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F9/00—Arrangements for program control, e.g. control units
    • G06F9/06—Arrangements for program control, e.g. control units using stored programs, i.e. using an internal store of processing equipment to receive or retain programs
    • G06F9/30—Arrangements for executing machine instructions, e.g. instruction decode
    • G06F9/30003—Arrangements for executing specific machine instructions
    • G06F9/30007—Arrangements for executing specific machine instructions to perform operations on data operands
    • G06F9/30036—Instructions to perform operations on packed data, e.g. vector, tile or matrix operations
    • G—PHYSICS
    • G06—COMPUTING OR CALCULATING; COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F9/00—Arrangements for program control, e.g. control units
    • G06F9/06—Arrangements for program control, e.g. control units using stored programs, i.e. using an internal store of processing equipment to receive or retain programs
    • G06F9/30—Arrangements for executing machine instructions, e.g. instruction decode
    • G06F9/30003—Arrangements for executing specific machine instructions
    • G06F9/3005—Arrangements for executing specific machine instructions to perform operations for flow control
    • G06F9/30054—Unconditional branch instructions
    • G—PHYSICS
    • G06—COMPUTING OR CALCULATING; COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F9/00—Arrangements for program control, e.g. control units
    • G06F9/06—Arrangements for program control, e.g. control units using stored programs, i.e. using an internal store of processing equipment to receive or retain programs
    • G06F9/30—Arrangements for executing machine instructions, e.g. instruction decode
    • G06F9/30003—Arrangements for executing specific machine instructions
    • G06F9/3005—Arrangements for executing specific machine instructions to perform operations for flow control
    • G06F9/30061—Multi-way branch instructions, e.g. CASE
    • G—PHYSICS
    • G06—COMPUTING OR CALCULATING; COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F9/00—Arrangements for program control, e.g. control units
    • G06F9/06—Arrangements for program control, e.g. control units using stored programs, i.e. using an internal store of processing equipment to receive or retain programs
    • G06F9/30—Arrangements for executing machine instructions, e.g. instruction decode
    • G06F9/30003—Arrangements for executing specific machine instructions
    • G06F9/3005—Arrangements for executing specific machine instructions to perform operations for flow control
    • G06F9/30065—Loop control instructions; iterative instructions, e.g. LOOP, REPEAT
    • G—PHYSICS
    • G06—COMPUTING OR CALCULATING; COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F9/00—Arrangements for program control, e.g. control units
    • G06F9/06—Arrangements for program control, e.g. control units using stored programs, i.e. using an internal store of processing equipment to receive or retain programs
    • G06F9/30—Arrangements for executing machine instructions, e.g. instruction decode
    • G06F9/30098—Register arrangements
    • G06F9/30101—Special purpose registers
    • G—PHYSICS
    • G06—COMPUTING OR CALCULATING; COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F9/00—Arrangements for program control, e.g. control units
    • G06F9/06—Arrangements for program control, e.g. control units using stored programs, i.e. using an internal store of processing equipment to receive or retain programs
    • G06F9/30—Arrangements for executing machine instructions, e.g. instruction decode
    • G06F9/32—Address formation of the next instruction, e.g. by incrementing the instruction counter
    • G06F9/321—Program or instruction counter, e.g. incrementing
    • G—PHYSICS
    • G06—COMPUTING OR CALCULATING; COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F9/00—Arrangements for program control, e.g. control units
    • G06F9/06—Arrangements for program control, e.g. control units using stored programs, i.e. using an internal store of processing equipment to receive or retain programs
    • G06F9/30—Arrangements for executing machine instructions, e.g. instruction decode
    • G06F9/32—Address formation of the next instruction, e.g. by incrementing the instruction counter
    • G06F9/322—Address formation of the next instruction, e.g. by incrementing the instruction counter for non-sequential address
    • G06F9/325—Address formation of the next instruction, e.g. by incrementing the instruction counter for non-sequential address for loops, e.g. loop detection or loop counter
    • G—PHYSICS
    • G06—COMPUTING OR CALCULATING; COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F9/00—Arrangements for program control, e.g. control units
    • G06F9/06—Arrangements for program control, e.g. control units using stored programs, i.e. using an internal store of processing equipment to receive or retain programs
    • G06F9/30—Arrangements for executing machine instructions, e.g. instruction decode
    • G06F9/34—Addressing or accessing the instruction operand or the result ; Formation of operand address; Addressing modes
    • G06F9/345—Addressing or accessing the instruction operand or the result ; Formation of operand address; Addressing modes of multiple operands or results
    • G06F9/3455—Addressing or accessing the instruction operand or the result ; Formation of operand address; Addressing modes of multiple operands or results using stride
    • G—PHYSICS
    • G06—COMPUTING OR CALCULATING; COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F9/00—Arrangements for program control, e.g. control units
    • G06F9/06—Arrangements for program control, e.g. control units using stored programs, i.e. using an internal store of processing equipment to receive or retain programs
    • G06F9/30—Arrangements for executing machine instructions, e.g. instruction decode
    • G06F9/34—Addressing or accessing the instruction operand or the result ; Formation of operand address; Addressing modes
    • G06F9/355—Indexed addressing
    • G06F9/3555—Indexed addressing using scaling, e.g. multiplication of index
    • G—PHYSICS
    • G06—COMPUTING OR CALCULATING; COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F9/00—Arrangements for program control, e.g. control units
    • G06F9/06—Arrangements for program control, e.g. control units using stored programs, i.e. using an internal store of processing equipment to receive or retain programs
    • G06F9/30—Arrangements for executing machine instructions, e.g. instruction decode
    • G06F9/38—Concurrent instruction execution, e.g. pipeline or look ahead
    • G06F9/3836—Instruction issuing, e.g. dynamic instruction scheduling or out of order instruction execution
    • G—PHYSICS
    • G06—COMPUTING OR CALCULATING; COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F2212/00—Indexing scheme relating to accessing, addressing or allocation within memory systems or architectures
    • G06F2212/45—Caching of specific data in cache memory
    • G06F2212/454—Vector or matrix data

Landscapes

  • Engineering & Computer Science (AREA)
  • Theoretical Computer Science (AREA)
  • Software Systems (AREA)
  • Physics & Mathematics (AREA)
  • General Physics & Mathematics (AREA)
  • General Engineering & Computer Science (AREA)
  • Mathematical Physics (AREA)
  • Computational Mathematics (AREA)
  • Mathematical Analysis (AREA)
  • Mathematical Optimization (AREA)
  • Pure & Applied Mathematics (AREA)
  • Data Mining & Analysis (AREA)
  • Computing Systems (AREA)
  • Algebra (AREA)
  • Databases & Information Systems (AREA)
  • Advance Control (AREA)
  • Complex Calculations (AREA)
  • Executing Machine-Instructions (AREA)
  • Memory System (AREA)
  • Memory System Of A Hierarchy Structure (AREA)
TW109123874A 2016-02-03 2016-12-30 用於判定一ｎ維張量之元素之記憶體位址之設備、系統、及方法 TWI772842B (zh)

Applications Claiming Priority (2)

Application Number Priority Date Filing Date Title
US15/014,265 US9875104B2 (en) 2016-02-03 2016-02-03 Accessing data in multi-dimensional tensors
US15/014,265 2016-02-03

Publications (2)

Publication Number Publication Date
TW202040359A TW202040359A (zh) 2020-11-01
TWI772842B true TWI772842B (zh) 2022-08-01

Family

ID=57860636

Family Applications (4)

Application Number Title Priority Date Filing Date
TW109123874A TWI772842B (zh) 2016-02-03 2016-12-30 用於判定一ｎ維張量之元素之記憶體位址之設備、系統、及方法
TW105144084A TWI635390B (zh) 2016-02-03 2016-12-30 存取多維張量中之資料
TW108144554A TWI700587B (zh) 2016-02-03 2016-12-30 存取多維張量中之資料
TW107126366A TWI681291B (zh) 2016-02-03 2016-12-30 存取多維張量中之資料

Family Applications After (3)

Application Number Title Priority Date Filing Date
TW105144084A TWI635390B (zh) 2016-02-03 2016-12-30 存取多維張量中之資料
TW108144554A TWI700587B (zh) 2016-02-03 2016-12-30 存取多維張量中之資料
TW107126366A TWI681291B (zh) 2016-02-03 2016-12-30 存取多維張量中之資料

Country Status (7)

Country Link
US (4) US9875104B2 (enExample)
EP (1) EP3226121A3 (enExample)
JP (3) JP6896415B2 (enExample)
KR (4) KR101924500B1 (enExample)
CN (2) CN110457069B (enExample)
SG (2) SG10201610917TA (enExample)
TW (4) TWI772842B (enExample)

Families Citing this family (49)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US9256480B2 (en) * 2012-07-25 2016-02-09 Mobileye Vision Technologies Ltd. Computer architecture with a hardware accumulator reset
US9875104B2 (en) * 2016-02-03 2018-01-23 Google Llc Accessing data in multi-dimensional tensors
US10360163B2 (en) 2016-10-27 2019-07-23 Google Llc Exploiting input data sparsity in neural network compute units
US9959498B1 (en) 2016-10-27 2018-05-01 Google Llc Neural network instruction set architecture
US10175980B2 (en) 2016-10-27 2019-01-08 Google Llc Neural network compute tile
US10896367B2 (en) * 2017-03-07 2021-01-19 Google Llc Depth concatenation using a matrix computation unit
CN114461276A (zh) 2017-03-20 2022-05-10 英特尔公司 用于点积操作的系统、方法和装置
US10684955B2 (en) 2017-04-21 2020-06-16 Micron Technology, Inc. Memory devices and methods which may facilitate tensor memory access with memory maps based on memory operations
US10248908B2 (en) 2017-06-19 2019-04-02 Google Llc Alternative loop limits for accessing data in multi-dimensional tensors
WO2019009870A1 (en) 2017-07-01 2019-01-10 Intel Corporation SAVE BACKGROUND TO VARIABLE BACKUP STATUS SIZE
US10175912B1 (en) 2017-07-05 2019-01-08 Google Llc Hardware double buffering using a special purpose computational unit
GB2567038B (en) * 2017-07-31 2019-09-25 Google Llc Accessing prologue and epilogue data
US10108538B1 (en) 2017-07-31 2018-10-23 Google Llc Accessing prologue and epilogue data
GB2568776B (en) 2017-08-11 2020-10-28 Google Llc Neural network accelerator with parameters resident on chip
US11620490B2 (en) * 2017-10-17 2023-04-04 Xilinx, Inc. Multi-layer neural network processing by a neural network accelerator using host communicated merged weights and a package of per-layer instructions
KR102027034B1 (ko) * 2017-11-24 2019-09-30 서울대학교산학협력단 병렬 처리를 통한 다차원 데이터 분석을 지원하는 장치 및 그 방법
WO2019113007A1 (en) * 2017-12-05 2019-06-13 Wave Computing, Inc. Pipelined tensor manipulation within a reconfigurable fabric
US10373291B1 (en) * 2018-01-31 2019-08-06 Google Llc Image transformation for machine learning
US10956315B2 (en) * 2018-07-24 2021-03-23 Micron Technology, Inc. Memory devices and methods which may facilitate tensor memory access
CN109255438B (zh) * 2018-09-17 2020-07-17 地平线(上海)人工智能技术有限公司 调整张量数据的方法和装置
CN111191783B (zh) * 2018-11-15 2024-04-05 嘉楠明芯(北京)科技有限公司 一种自适应量化方法及装置、设备、介质
CN117785441A (zh) * 2018-12-06 2024-03-29 华为技术有限公司 处理数据的方法和数据处理装置
CN111324294B (zh) * 2018-12-17 2023-11-07 地平线(上海)人工智能技术有限公司 存取张量数据的方法和装置
CN109857744B (zh) * 2019-02-13 2020-03-20 上海燧原智能科技有限公司 稀疏张量计算方法、装置、设备及存储介质
CN111723917B (zh) * 2019-03-21 2022-11-01 中科寒武纪科技股份有限公司 运算方法、装置及相关产品
US11055095B2 (en) * 2019-05-24 2021-07-06 Texas Instruments Incorporated Nested loop control
CN112257857B (zh) * 2019-07-22 2024-06-04 中科寒武纪科技股份有限公司 张量处理方法及相关产品
CN110209503B (zh) * 2019-08-01 2019-10-25 上海燧原智能科技有限公司 多维张量的规约计算方法、装置、设备及介质
CN114270319A (zh) 2019-10-07 2022-04-01 谷歌有限责任公司 在机器学习计算单元之间重新分配张量元素
US12423007B1 (en) * 2020-03-31 2025-09-23 Nvidia Corporation Techniques for tensor memory allocation
US11687336B2 (en) * 2020-05-08 2023-06-27 Black Sesame Technologies Inc. Extensible multi-precision data pipeline for computing non-linear and arithmetic functions in artificial neural networks
WO2021248433A1 (en) * 2020-06-12 2021-12-16 Moffett Technologies Co., Limited Method and system for dual-sparse convolution processing and parallelization
CN111767508B (zh) * 2020-07-09 2024-02-23 地平线(上海)人工智能技术有限公司 计算机实现张量数据计算的方法、装置、介质和设备
US12353988B2 (en) 2020-07-09 2025-07-08 Celestial Ai Inc. Neuromorphic photonics with coherent linear neurons
CN111737007B (zh) * 2020-07-24 2021-06-18 北京一流科技有限公司 数据对象的分频处理系统及其方法
US11954580B2 (en) * 2020-09-16 2024-04-09 Meta Platforms, Inc. Spatial tiling of compute arrays with shared control
US12271595B2 (en) 2022-03-18 2025-04-08 Celestial Ai Inc. Photonic memory fabric for system memory interconnection
US20220405566A1 (en) 2021-06-18 2022-12-22 Celestial Ai Inc. Multi-chip electro-photonic network
CN113836049B (zh) * 2021-09-17 2023-08-08 海飞科(南京)信息技术有限公司 存储器访问方法和电子装置
US12099635B1 (en) * 2021-12-21 2024-09-24 Meta Platforms Technologies, Llc Opaque bound variables
KR102733032B1 (ko) * 2021-12-27 2024-11-20 서울대학교산학협력단 다차원 텐서의 주소 생성 장치 및 방법
CN114489798B (zh) * 2022-01-25 2024-04-05 海飞科(南京)信息技术有限公司 用于确定张量元素的越界状态的方法和电子装置
US12442999B2 (en) 2022-03-18 2025-10-14 Celestial Ai Inc. Optically bridged multicomponent package with extended temperature range
WO2023177848A1 (en) 2022-03-18 2023-09-21 Celestial Al Inc. Optical multi-die interconnect bridge (omib)
US11868329B2 (en) 2022-05-20 2024-01-09 International Business Machines Corporation Multidimensional cube multivariate regression
US12191257B2 (en) 2022-07-26 2025-01-07 Celestial Ai Inc. Electrical bridge package with integrated off-bridge photonic channel interface
US12283584B2 (en) 2022-07-26 2025-04-22 Celestial Ai Inc. Electrical bridge package with integrated off-bridge photonic channel interface
US20240069914A1 (en) * 2022-08-23 2024-02-29 Intel Corporation Hardware enhancements for matrix load/store instructions
US12217056B2 (en) * 2023-01-27 2025-02-04 Celestial Ai Inc. Load/store unit for a tensor engine and methods for loading or storing a tensor

Citations (7)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US5958048A (en) * 1996-08-07 1999-09-28 Elbrus International Ltd. Architectural support for software pipelining of nested loops
US20040034754A1 (en) * 2002-08-19 2004-02-19 Schreiber Robert S. Method and system for memory management optimization
US20040088529A1 (en) * 2002-10-31 2004-05-06 Schreiber Robert S. Method and system for the design of pipelines of processors
US20040093550A1 (en) * 2002-11-12 2004-05-13 Andrew Kadatch Matrix multiplication in a Galois field for forward error correction
US20040187102A1 (en) * 2003-03-21 2004-09-23 Garthwaite Alexander T. Combining write-barriers within an inner loop with fixed step
US20080301697A1 (en) * 2006-10-06 2008-12-04 Southgate Timothy J Multiple task management between processors
US20100122066A1 (en) * 2008-11-12 2010-05-13 Freescale Semiconductor, Inc. Instruction method for facilitating efficient coding and instruction fetch of loop construct

Family Cites Families (27)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS58114245A (ja) * 1981-12-28 1983-07-07 Fujitsu Ltd インデツクス・インクリメントのベクトル化方式
JP3102027B2 (ja) 1990-11-20 2000-10-23 日本電気株式会社 ループ制御のネスティング管理機構
US5357618A (en) * 1991-04-15 1994-10-18 International Business Machines Corporation Cache prefetch and bypass using stride registers
GB2359641B (en) 2000-02-25 2002-02-13 Siroyan Ltd Mapping circuitry and method
KR20030016234A (ko) * 2000-03-08 2003-02-26 선 마이크로시스템즈, 인코포레이티드 어레이 바운드 체크 수용능력을 가진 아퀴텍쳐 처리
WO2001090888A1 (en) * 2000-05-23 2001-11-29 Theis Jean Paul A data processing system having an address generation unit with hardwired multidimensional memory indexing support
US6647484B1 (en) * 2000-09-19 2003-11-11 3 Dsp Corporation Transpose address mode in general purpose DSP processor
US20040133745A1 (en) * 2002-10-28 2004-07-08 Quicksilver Technology, Inc. Adaptable datapath for a digital processing system
JP2003244190A (ja) * 2002-02-19 2003-08-29 Matsushita Electric Ind Co Ltd データフロー制御スイッチ用プロセッサ及びデータフロー制御スイッチ
CN1259617C (zh) * 2003-09-09 2006-06-14 大唐微电子技术有限公司 一种加快rsa加/解密过程的方法及其模乘、模幂运算电路
CN100520714C (zh) 2005-01-25 2009-07-29 Nxp股份有限公司 多线程处理器
US8806183B1 (en) 2006-02-01 2014-08-12 Ixys Ch Gmbh Blank bit and processor instructions employing the blank bit
US8904155B2 (en) 2006-03-17 2014-12-02 Qualcomm Incorporated Representing loop branches in a branch history register with multiple bits
ATE463788T1 (de) * 2007-06-26 2010-04-15 Ericsson Telefon Ab L M Datenverarbeitungseinheit für anweisungen in geschachtelten schleifen
US20100274972A1 (en) 2008-11-24 2010-10-28 Boris Babayan Systems, methods, and apparatuses for parallel computing
CA2684226A1 (en) 2009-10-30 2011-04-30 Ibm Canada Limited - Ibm Canada Limitee Eleminating redundant operations for common properties using shared real registers
US9519617B2 (en) * 2011-07-14 2016-12-13 Texas Instruments Incorporated Processor with instruction variable data distribution
WO2013095601A1 (en) * 2011-12-23 2013-06-27 Intel Corporation Instruction for element offset calculation in a multi-dimensional array
US20140181171A1 (en) 2012-12-24 2014-06-26 Pavel Dourbal Method and system for fast tensor-vector multiplication
US20140188961A1 (en) * 2012-12-27 2014-07-03 Mikhail Plotnikov Vectorization Of Collapsed Multi-Nested Loops
CN103440513B (zh) * 2013-09-17 2017-01-18 西安电子科技大学 基于稀疏非负张量分解的大脑特定视觉认知状态判定方法
US8928675B1 (en) 2014-02-13 2015-01-06 Raycast Systems, Inc. Computer hardware architecture and data structures for encoders to support incoherent ray traversal
CN105260322B (zh) * 2014-06-30 2020-09-01 中兴通讯股份有限公司 一种对循环缓冲区消除循环移位的方法和装置
US11170294B2 (en) 2016-01-07 2021-11-09 Intel Corporation Hardware accelerated machine learning
US9875104B2 (en) * 2016-02-03 2018-01-23 Google Llc Accessing data in multi-dimensional tensors
JP6890615B2 (ja) 2016-05-26 2021-06-18 タータン エーアイ リミテッド ディープニューラルネットワークについての加速器
US10175980B2 (en) 2016-10-27 2019-01-08 Google Llc Neural network compute tile

Patent Citations (7)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US5958048A (en) * 1996-08-07 1999-09-28 Elbrus International Ltd. Architectural support for software pipelining of nested loops
US20040034754A1 (en) * 2002-08-19 2004-02-19 Schreiber Robert S. Method and system for memory management optimization
US20040088529A1 (en) * 2002-10-31 2004-05-06 Schreiber Robert S. Method and system for the design of pipelines of processors
US20040093550A1 (en) * 2002-11-12 2004-05-13 Andrew Kadatch Matrix multiplication in a Galois field for forward error correction
US20040187102A1 (en) * 2003-03-21 2004-09-23 Garthwaite Alexander T. Combining write-barriers within an inner loop with fixed step
US20080301697A1 (en) * 2006-10-06 2008-12-04 Southgate Timothy J Multiple task management between processors
US20100122066A1 (en) * 2008-11-12 2010-05-13 Freescale Semiconductor, Inc. Instruction method for facilitating efficient coding and instruction fetch of loop construct

Also Published As

Publication number Publication date
US20190205141A1 (en) 2019-07-04
EP3226121A2 (en) 2017-10-04
TWI635390B (zh) 2018-09-11
US9875104B2 (en) 2018-01-23
CN107038018B (zh) 2019-07-19
KR102472424B1 (ko) 2022-11-29
US9875100B2 (en) 2018-01-23
KR102596365B1 (ko) 2023-10-31
TW202040359A (zh) 2020-11-01
JP7507271B2 (ja) 2024-06-27
KR101924500B1 (ko) 2018-12-03
JP2021128801A (ja) 2021-09-02
CN110457069A (zh) 2019-11-15
TW202014897A (zh) 2020-04-16
US20170220352A1 (en) 2017-08-03
JP2017138964A (ja) 2017-08-10
KR20180127945A (ko) 2018-11-30
US20170220345A1 (en) 2017-08-03
JP2023059898A (ja) 2023-04-27
SG10202104454YA (en) 2021-06-29
CN110457069B (zh) 2020-08-18
TWI681291B (zh) 2020-01-01
US10838724B2 (en) 2020-11-17
TW201907305A (zh) 2019-02-16
TWI700587B (zh) 2020-08-01
TW201729104A (zh) 2017-08-16
KR102788305B1 (ko) 2025-03-28
US10228947B2 (en) 2019-03-12
EP3226121A3 (en) 2018-10-31
US20180107483A1 (en) 2018-04-19
JP7225314B2 (ja) 2023-02-20
BR102016030825A2 (pt) 2018-10-09
KR20230004348A (ko) 2023-01-06
JP6896415B2 (ja) 2021-06-30
CN107038018A (zh) 2017-08-11
KR20230153972A (ko) 2023-11-07
SG10201610917TA (en) 2017-09-28
KR20170092445A (ko) 2017-08-11

Similar Documents

Publication Publication Date Title
TWI772842B (zh) 用於判定一ｎ維張量之元素之記憶體位址之設備、系統、及方法
US10534607B2 (en) Accessing data in multi-dimensional tensors using adders
US10108538B1 (en) Accessing prologue and epilogue data
US9946539B1 (en) Accessing data in multi-dimensional tensors using adders
HK40014403A (en) Accessing data in multi-dimensional tensors
HK40014403B (en) Accessing data in multi-dimensional tensors
HK1242809A1 (en) Accessing data in multi-dimensional tensors
HK1242809B (zh) 访问多维张量中的数据
BR102016030825B1 (pt) Equipamento e método implementado em computador para processar uma instrução para acessar um tensor n-dimensional
BR122023003223B1 (pt) Equipamento para processar uma instrução para processar um laço encaixado e método implementado em computador