TWI772034B - In-memory computation system - Google Patents

Abstract

An in-memory computation system includes a static random access memory (SRAM) array, a ripple carry computation unit, a computation control unit, and an automatic switching write-back unit. The computation control unit is used to control the output the logic data of the two stored data stored in the SRAM array for the computation. The ripple carry computation unit outputs the computation data of the two stored data according to the logic data, the automatic switching write-back unit restores the computation data to the SRAM array for completing the in-memory computation.

Description

in-memory computing system

The present invention relates to an in-memory computing system, in particular to an in-memory computing system with a static random access memory array.

Nowadays, computer systems have the demand for a large amount of computing resources for artificial intelligence, neural-like networks, etc., so that computing speed has always been the focus of the development of computer systems, but the computing speed of computer systems is based on its basic design and there is a Van Neumann bottleneck (von Neumann). Neumann bottleneck), that is, because the central processing unit and the memory are independently set up, the data transfer time between the central processing unit and the memory becomes an unreduced computing time, resulting in the central processing unit and the advanced semiconductor process. Although memory has a breakthrough computing speed, the computing speed of the overall computer system is still limited by the Van Neumann bottleneck. One of the research priorities of speed.

The main purpose of the present invention is to achieve the data operation of the in-memory computing system through the operation control unit and the automatic switching write-back unit and automatically store the operation results back into the memory, thereby breaking through the operation bottleneck and greatly improving the operation speed.

An in-memory computing system of the present invention includes a static random access memory array, a ripple carry operation unit, an operation control unit and an automatic switching write-back unit, and the static random access memory array has a plurality of memories unit, a plurality of 2T switch unit groups and a precharge circuit, each of the memory cells has a storage node and an inverse storage node, each of the 2T switch cell groups is electrically connected to the storage node and the inverse storage node of each of the memory cells a storage node, the precharge circuit is electrically connected to the 2T switch unit groups, the 2T switch unit groups output a plurality of logic data, the ripple carry operation unit is electrically connected to the 2T switch unit groups to receive the logic data , and the ripple carry operation unit outputs a plurality of operation data, the operation control unit is electrically connected to the SRAM array, and the operation control unit is used for outputting a plurality of control signals to the precharge circuit and the 2T A switch unit group to control the precharge circuit and each of the 2T switch unit groups to be turned on or off, the automatic switching write-back unit is electrically connected to the ripple carry operation unit and the SRAM array, so that the The ripple-carry operation units receive the operation data, and the automatic switching write-back unit writes the operation data back into the memory cells of the SRAM array.

In the present invention, the SRAM array is controlled by the signal output from the operation control unit to perform the logic data operations, and the ripple carry operation unit is used to obtain the required operation data according to the logic data. Finally, the operation data is written back into the SRAM array by the automatic switching write-back unit. Since the operation is directly completed in the memory, the operation bottleneck can be broken and the operation speed can be greatly improved.

Please refer to FIG. 1, which is a functional block diagram of an in-memory computing system 100 according to an embodiment of the present invention, which includes a static random access memory array 110, a ripple-carry operation unit 120, and an operation control unit 130 , an automatic switching write-back unit 140 , a SRAM control unit 150 and a column selector 160 .

Please refer to FIG. 2 , which is a circuit diagram of the SRAM array 110 of this embodiment. The SRAM array 110 has a plurality of memory cells 111 , a plurality of 2T switch unit groups 112 and a plurality of pre- In the charging circuit 113, each of the memory cells 111 has a storage node Q and an inverse storage node Qb, and each of the 2T switch cell groups 112 is electrically connected to the storage node Q and the inverse storage node Qb of each of the memory cells 111, The precharge circuit 113 is electrically connected to the 2T switch unit groups 112 , and the 2T switch unit groups 112 output a plurality of logic data.

In this embodiment, there are 16 memory cells 111 in 4 rows×4 columns in total, and each memory cell 111 is electrically connected to a group of the 2T switch cell groups. Please refer to FIG. The 2T switch unit group 112 has a carry-value 2T switch 112a, an inverse-OR 2T switch 112b, and an sum-value 2T switch 112c. The carry 2T switch 112a is electrically connected to the storage node Q of the memory cell 111 and an inverse carry line 11, and the carry 2T switch 112a receives a carry operation control signal S and the storage of the memory cell 111 Control of the potential of node Q. The inverse-OR 2T switch 112b is electrically connected to the storage node Q of the memory cell 111 and an inverse-OR line 12 , and the inverse-OR 2T switch 112b receives a logic operation control signal C and the memory cell 111 Control of the potential of the storage node Q. The sum-value 2T switch 112c is electrically connected to the inverse storage node Qb of the memory cell 111 and a sum-value line 13 , and the sum-value 2T switch 112c receives the logic operation control signal C and the inverse storage of the memory cell 111 Control of the potential of the node Qb.

Please refer to FIGS. 2 and 3 , the 2T switch unit group 112 of the memory unit 111 in the same column is electrically connected to the same precharge circuit 113 . Please refer to FIG. 3, the precharge circuit 113 has three precharge transistors 113a, and each of the charge transistors 113a is electrically connected to the inverse carry value line 11, the inverse OR value line 12 and the sum value line 13 respectively. , each of the charging transistors 113a is controlled by a precharge control signal PreC to pull the inverse carry value line 11 , the inverse OR value line 12 and the sum value line 13 to a high potential when turned on. In addition, the three bypass capacitors BC electrically connected to the inverse carry value line 11 , the inverse OR value line 12 and the sum value line 13 respectively are used for stabilizing the voltage value.

Please refer to FIG. 4 , which is a circuit diagram of the memory unit 111 of this embodiment. The memory unit 111 is a 7T SRAM single-ended read memory structure, which has two P-type transistors MP201-202 and five N-type transistors MN201-205, wherein the P-type transistors MP201-202 electrically connected to each other are used to latch the data stored in the storage node Q and the inverse storage node Qb, and the N-type transistors MN201- 203 is controlled by three control signals WL, WA, WAB to read or write data, and N-type transistors MN204~205 respectively provide a discharge circuit for the storage node Q and the reverse storage node Qb to avoid The leakage current accumulates and causes the inversion of the stored data.

Please refer to FIG. 4 again, an inversion bit line 14 is electrically connected to the memory cell 111 to read the data of the inversion storage node Qb of the memory cell 111 , or write data into the memory cell 111 , The bit line 15 is electrically connected to the inversion bit line 14 via an inverter INV to obtain the potential magnitude of the data stored in the storage node Q. The N-type transistor MN206 is controlled by a pre-discharge control signal PreD to discharge the inversion line 14 to a low potential when the memory cell 111 is turned on before writing, so as to avoid affecting the data of the memory cell 111 read and write.

In this embodiment, when the memory cell 111 is writing 0, the pre-discharge control signal PreD rises to a high level to turn on the N-type transistor MN206, the inversion line 14 is discharged to a low level, and at the same time, the control signal WL and WAB are at high potential, WA is at low potential, turn on N-type transistors MN201 and MN203, turn off N-type transistor MN202, and lower the storage node Q to a low potential to complete writing 0. When writing 1 in the memory cell 111, the pre-discharge control signal PreD rises to a high potential to turn on the N-type transistor MN206, the inversion line 14 is discharged to a low potential, and at the same time, the control signals WL and WA are at a high potential , WAB turns on the N-type transistors MN201 and MN202 at a low potential, and turns off the N-type transistor MN203, so that the reverse storage node Qb drops to a low potential and turns on the P-type transistor MP202 to complete writing 1. When the memory cell 111 is being read, the pre-discharge control signal PreD drops to a low potential to turn off the N-type transistor MN206, and at the same time, the control signals WL and WA are at a high potential, and WAB is at a low potential to turn on the N-type transistor MN201 and MN202 turn off the N-type transistor MN203, so that the potential of the inversion storage node Qb is transmitted to the inversion bit line 14, and is reversed to the bit line 15 through the inverter to complete the reading.

Please refer to FIGS. 5 and 6, the logic data output by the 2T switch unit groups 112 includes an inverse carry value CB, an inverse OR value NOR and an AND value AND, and when performing in-memory operations, one of the carry values 2T switch 112a and two of the inverse-OR 2T switches 112b and the sum 2T switch 112c are on, and the rest of the carry 2T switches 112a, the inverse-or 2T switches 112b and the sum 2T switches 112c are off .

Please refer to FIG. 5 , the inverse carry value CB is the inverse value of the carry value stored in the memory unit 111 , which is obtained by adding the previous bit when two sets of multi-bit data are added. Taking the carry value 1 stored in the memory cell 111 in the second bit as an example, when reading the reverse carry value CB, the precharge circuit 113 first pulls up the potential of the reverse carry value line 11, and then The carry operation control signal S2 is raised to a high level. Since the carry value stored in the storage node Q2 of the second bit is 1, the carry value 2T switch 112a of the second bit is turned on, and the inverse carry value line 11 is connected via The carry value 2T switch 112a is grounded and lowered to a low level, that is, the inverse value 0 of the carry value 1 is obtained.

Please refer to FIG. 6 , the inverse-OR value NOR and the AND-value AND are logical data stored between the data of the memory cell 111 of the two bits, respectively, to be stored in the value 1 and the value of the 0th bit. Take the value 0 stored in the first bit for operation as an example. The precharge circuit 113 is used to pull up the potentials of the inverse OR value line 12 and the sum value line 13 first, and then the logic operation control signals C0 and C1 are raised to a high potential, because the storage node Q0 of the 0th bit stores is 1, and the value stored in the inverse storage node Qb0 is 0, so that the inverse-OR value 2T switch 112b of the 0th bit is turned on, the AND-value 2T switch 112c is turned off, and the inverse-OR value line 12 passes through the inverse-OR value line 12. The value 2T switch 112b is grounded to a low potential. Since the value stored in the storage node Q1 of the first bit is 0, the value stored in the inverted storage node Qb1 is 1, so that the inverse OR 2T switch 112b of the first bit is turned off, and the sum 2T switch 112c is turned off. When turned on, the sum line 13 is grounded to a low level through the sum 2T switch 112c, and the result that the inverse OR value NOR and the sum value AND are both 0 can be obtained.

Please refer to FIG. 6, and then take the value 0 stored in the 0th bit and the value 0 stored in the 1st bit as an example, first, the precharge circuit 113 pulls up the inverse OR line 12 and the and The potential of the value line 13, and then the logic operation control signals C0 and C1 are raised to a high potential. Since the value stored in the storage node Q0 of the 0th bit is 0, the value stored in the inverse storage node Qb0 is 1, so that The inverse-OR 2T switch 112b of the 0th bit is turned off, the sum 2T switch 112c is turned on, and the sum line 13 is grounded to a low level through the sum 2T switch 112c. Since the value stored in the storage node Q1 of the first bit is 0, the value stored in the inverted storage node Qb1 is 1, so that the inverse OR 2T switch 112b of the first bit is turned off, and the sum 2T switch 112c is turned off. When turned on, the sum line 13 is grounded to a low level through the sum 2T switch 112c, and the result of the inverse OR value of 1 and the sum value of 0 can be obtained.

Please refer to FIG. 1 , the ripple-carry operation unit 120 is electrically connected to the 2T switch unit groups 112 to receive the logic data, and the ripple-carry operation unit 120 outputs a plurality of operation data according to the logic data. Please refer to FIG. 7. In this embodiment, the ripple-carry operation unit 120 has a logic calculation circuit 121, an addition circuit 122 and a carry circuit 123. The logic calculation circuit 121 is electrically connected to the 2T switch unit groups 112 receives the inverse carry value CB, the inverse OR value NOR and the sum value AND, and the logic calculation circuit 121 outputs a plurality of logical operation data according to the inverse carry value CB, the inverse OR value NOR and the sum value AND, In the present embodiment, the logical operation data includes an inverse AND value NAND, an inverse exclusive OR value XNOR, an exclusive OR value XOR, and a carry value C1. In this embodiment, the logic calculation circuit 121 has three inverters and an invertor gate, so as to obtain the logic operation data through the logic operation of the logic gates.

Please refer to FIG. 7, the addition circuit 122 is electrically connected to the 2T switch groups 112 and the logic calculation circuit 121 to receive the inverse carry value CB, the mutually exclusive OR value XOR, the carry value C1 and the inverse mutually exclusive OR value value XNOR, and the addition unit 122 outputs an addition value SUM according to the logic data and the logic operation data. In this embodiment, the addition circuit 122 consists of two P-type transistors MP6, MP7 and two N-type transistors Transistors MN9 and MN10 are formed, and these transistors output the added value SUM under the control of the inverse carry value CB, the mutually exclusive OR value XOR, the carry value C1 and the inverse mutually exclusive OR value XNOR.

The carry circuit 123 is electrically connected to the 2T switch unit groups 112 and the logic calculation circuit 121 to receive the sum value AND, the mutually exclusive OR value XOR, the carry value C1, the inverse mutex OR value XNOR and the inverse sum The value is NAND, and the addition unit 122 outputs a carry value CO according to the logic data and the logic operation data. In this embodiment, the carry circuit 123 is composed of three P-type transistors MP3, MP4, MP5 and three N-type transistors MN6, MN7, MN8. The control of the OR value XOR, the carry value C1, the inverse mutually exclusive OR value XNOR, and the inverse AND value NAND outputs the carry value CO.

Preferably, the AND value of the AND-value line 13 can also be used as the product value PRO obtained by multiplying the data of two bits, and the logical calculation circuit 121 obtains the mutually exclusive gate value XOR by logical operation. Then, it can also be used as the symbol value SIG obtained by multiplying the symbols of the two bits of data. Therefore, the ripple carry operation unit 120 can be used to calculate the addition operation between the two bits of data. Multiplication between two signed data.

Please refer to FIGS. 1 and 8 , the operation control unit 130 is electrically connected to the SRAM array 110 , and the operation control unit 130 is used for outputting a plurality of control signals to the SRAM array 110 . The precharge circuit 113 and the 2T switch unit groups 112 are used to control the precharge circuit 113 and each of the 2T switch unit groups 112 to be turned on or off, so as to allow the data stored in the memory unit 111 of the corresponding address to be added or multiplication.

Referring to FIG. 8, in this embodiment, the operation control unit 130 has an operation clock control circuit 131, an automatic precharge switching control circuit 132, an address selection circuit 133 and an internal operation control circuit 134. The operation clock control circuit 131 is used for receiving an addition operation signal ADD, a multiplication operation signal MUL and a clock signal Clk, and the operation clock control circuit 131 outputs an operation signal OP, a total operation signal Opprec, and a write select The signal Wrsel and an inverse read and write signal Dffwr. In this embodiment, the operation clock control circuit 131 has a first OR gate 131a, a first flip-flop 131b, a second flip-flop 131c, a The third flip-flop 131d and a fourth flip-flop 131e, the first OR gate 131a receives the addition operation signal ADD and the multiplication operation signal MUL, and the first OR gate 131a outputs the operation signal OP, wherein the When the addition operation signal ADD or the multiplication operation signal MUL rises to a high level, it indicates that the memory is ready to perform an addition or multiplication operation. Therefore, the operation signal OP rises to a high level.

The first flip-flop 131b receives a read-write control signal wr_en and the clock signal Clk, and the first flip-flop 131b outputs a read-write signal Dffwr through the buffer, which is output by the first flip-flop 131b The read-write signal Dffwr is used to synchronize the read-write control signal wr_en with the clock signal Clk. The second flip-flop 131c is electrically connected to the first OR gate 131a, the second flip-flop 131c receives the clock signal Clk and the operation signal OP, and the second flip-flop 131c outputs the total operation signal Opprec , the total operation signal Opprec output by the second flip-flop 131c is used to synchronize the operation signal OP with the clock signal Clk. The third flip-flop 131d is electrically connected to the first OR gate 131a and the first flip-flop 131b to receive the operation signal OP and the read-write signal Dffwr, and the third flip-flop 131d outputs the write signal the input selection signal Wrsel, the third flip-flop 131d is used for dividing the frequency of the read write signal Dffwr to output the write selection signal Wrsel. The fourth flip-flop 131e is electrically connected to the first flip-flop 131b, the fourth flip-flop receives the read and write signal Dffwr and the clock signal Clk, and the fourth flip-flop 131e outputs through a buffer The reverse read and write signal Dffwrb, the fourth flip-flop 131e is used for inverting the read and write signal Dffwr to output the reverse read and write signal Dffwrb.

The automatic precharge switching control circuit 132 is electrically connected to the operation clock control circuit 131 to receive the total operation signal Opprec, the write selection signal Wrsel and the reverse read write signal Dffwr, and the automatic precharge switch control circuit 132 outputs a precharge trigger signal PreC_bit. In this embodiment, the automatic precharge clock control circuit 132 has a fifth flip-flop 132a, a sixth flip-flop 132b, a counter 132c and a first decoder 132d. The fifth flip-flop 132a is electrically connected to the operation clock control circuit 131 to receive the total operation signal Opprec and the operation signal OP, and the fifth flip-flop 132a outputs a count start signal Cimp, the fifth flip-flop 132a The outputted counting start signal Cimp is used to start the counter 132c to count when the total operation signal Opprec rises to a high level.

The sixth flip-flop 132b is electrically connected to the third flip-flop 131d and the fourth flip-flop 131e to receive the write select signal Wrsel and the reverse read write signal Dffwrb, and the sixth flip-flop 132b outputs a precharge clock signal PreCclk, and the precharge clock signal PreCclk output by the sixth flip-flop 132b is the action between the write select signal Wrsel and the reverse read write signal Dffwrb, used to determine The frequency of the signal output by the first decoder 132d. The counter 132c is electrically connected to the fifth flip-flop 132a and the sixth flip-flop 132b to receive the count start signal Cimp and the precharge clock signal PreCclk, and the counter 132c starts after being triggered by the count start signal Cimp Counting and outputting a count signal ct, the first decoder 132d is electrically connected to the counter 132c to receive the count signal ct, and the first decoder 132d outputs the precharge trigger signal PreC_bit, the precharge trigger signal PreC_bit is used for The precharge circuits 113 of different columns are activated.

The address selection circuit 133 is electrically connected to the operation clock control circuit 131 to receive the operation signal OP. The address selection circuit 133 further receives a first operation address signal OpX_add, a second operation address signal OpY_add, a The symbol address signal MS_add and an operation result address signal CR_add, and the address selection circuit 133 outputs an operation address control signal w0, a carry address control signal w2 and an operation result address control signal CR_DFF, the operation bit The address control signal w0, the carry address control signal w2 and the operation result address control signal CR_DFF are used to determine the address of the memory unit 111 to perform the operation and the memory unit 111 bit to store the operation result after the operation site.

In this embodiment, the address selection circuit 133 has a seventh flip-flop 133a, an eighth flip-flop 133b, a ninth flip-flop 133c, a tenth flip-flop 133d, and a second decoder 133e, a third decoder 133f, a fourth decoder 133g, and a second OR gate 133h. The seventh flip-flop 133a is electrically connected to the first OR gate 131a, the seventh flip-flop 133a receives the operation signal OP and the first operation address signal OpX_add, and the seventh flip-flop 133a outputs a first For an operation column signal OpX, the eighth flip-flop 133b is electrically connected to the first OR gate 131a, the eighth flip-flop 133b receives the operation signal OP and the second operation address signal OpY_add, and the eighth positive flip-flop 133b receives the operation signal OP and the second operation address signal OpY_add. The inverter 133b outputs a second operation signal OpY, the ninth flip-flop 133c is electrically connected to the first OR gate 133c, the ninth flip-flop 133c receives the operation signal OP and the symbol address signal MS_add, and The ninth flip-flop 133c outputs a carry signal MS, the tenth flip-flop 133d is electrically connected to the first OR gate 131a, and the tenth flip-flop 133d receives the operation signal OP and the estimated result address signal CR_DFF, and the tenth flip-flop 133d outputs the operation result address control signal CR_DFF.

The second decoder 133e is electrically connected to the seventh flip-flop 133a to receive the first operational column signal OpX, the second decoder 133e outputs a first decoded signal, and the third decoder 133f is electrically connected to the The eighth flip-flop 133b receives the second operational column signal OpY, the third decoder 133f outputs a second decoded signal, and the fourth decoder 133g is electrically connected to the eighth flip-flop 133b to receive the input signal. bit column signal MS, and the fourth decoder 133g outputs the carry address control signal w2, the second OR gate 133h is electrically connected to the first decoder 132d and the second decoder 133e to receive the first decoded signal and the second decoded signal, and the second OR gate 133h outputs the operation address control signal w0.

The internal operation control circuit 134 is electrically connected to the operation clock control circuit 131 , the automatic precharge switching control circuit 132 and the address selection circuit 133 to receive the operation signal OP, the reverse read and write signal Dffwrb, the precharge The charging trigger signal PreC_bit, the operation address control signal w0 and the carry address control signal w2, and the internal operation control circuit 134 outputs a precharge control signal PreC, a logic operation control signal C and a carry operation control signal S to The precharge circuit 113 and the 2T switch unit groups 112 are controlled.

In this embodiment, the internal operation control circuit 134 has a precharge controller 134a and an internal operation memory controller 134b, and the precharge controller 134a is electrically connected to the operation clock control circuit 131 to receive the operation signal OP and the reverse read write signal Dffwrb, and the precharge controller 134a outputs an operation bit control signal sc and a precharge bit control signal pcc, since the in-memory operation requires the inverse carry value line 11, The inverse-OR line 12 and the sum-value line 13 are precharged before switching the 2T switch unit groups 112. Therefore, the precharge controller 134a uses a delay element to make the precharge bit control signal pcc first. After triggering the precharging circuit 113 to perform precharging, the 2T switch unit group 112 is triggered by the operation bit control signal sc.

The internal operation memory controller 134b is electrically connected to the precharge controller 134a, the automatic precharge switch control circuit 132 and the address selection circuit 133, and the internal operation memory controller 134b receives the operation bit control signal sc , the precharge bit control signal pcc, the precharge trigger signal PreC_bit, the operation address control signal w0 and the carry address control signal w2, and the internal operation memory controller 134b outputs the precharge control signal PreC, The logic operation control signal C and the carry operation control signal S. The internal operation memory controller 134b makes the precharge trigger signal PreC_bit triggered by the precharge bit control signal pcc to obtain the precharge control signal PreC, and makes the operation address control signal w0 and the carry address The control signal w2 is triggered by the operation bit control signal sc to obtain the logic operation control signal C and the carry operation control signal S. The precharge control signal PreC is used to control the precharge circuits. The logic operation control signal C and the carry operation control signal S are used to control the 2T switch unit groups 112 to perform operations on the stored data of two of the memory units 111 .

Please refer to FIG. 1 , the automatic switching write-back unit 140 is electrically connected to the ripple carry operation unit 120 and the SRAM array 110 , so that the ripple carry operation units 120 receive the operation data, And the automatic switching write-back unit 140 writes back the operation data to the memory cells 111 of the SRAM array 110 .

Please refer to FIG. 9, the automatic switching write-back unit 140 has a bit line automatic switching circuit 141, a data switching circuit 142 and a word line automatic switching circuit 143, the bit line automatic switching circuit 141 is electrically connected to the The operation clock control circuit 131 receives the write selection signal Wrsel and the read write signal Dffwr, and the bit line automatic switching circuit 141 outputs a bit line switching signal BL_auto. In this embodiment, the automatic switching The write-back unit 141 has an eleventh flip-flop 141a and a one-bit line counter 141b. The eleventh flip-flop 141a receives the reverse write selection signal Wrsel and the reverse read write signal Dffwr , and trigger the write selection signal Wrsel with the reverse read write signal Dffwr to output a bit line clock signal BL_Clk to the bit line counter 141b for counting, and the bit line counter 141b outputs the bit line The line switching signal BL_auto is used to determine the number of columns of the memory cell 111 to be stored.

The word line automatic switching circuit 143 is electrically connected to the operation clock control circuit 131 and the address selection circuit 133, and the word line automatic switching circuit 143 receives the addition operation signal ADD, the multiplication operation signal MUL, and the operation signal OP, the reverse read write signal Dffwrb, the symbol address signal MS_add, and the operation result address control signal CR_DFF, and the word line automatic switching circuit 143 outputs a word line switching signal WL_auto. In this embodiment, the word line automatic switching circuit 143 has an AND gate 143a, a twelfth flip-flop 143b, a first multiplexer 143c, a second multiplexer 143d and a third OR gate 143e. The AND gate 143a receives the reverse read and write signal Dffwrb and the operation signal OP, the twelfth flip-flop 143b is electrically connected to the AND gate 143a, and the twelfth flip-flop 143 outputs an in-memory operation selection The signal CIM_datasel, the in-memory operation selection signal CIM_datasel is used to alternately switch and store the addition value and the carry value in the addition operation, and alternately switch and store the product value and the sign value in the multiplication operation.

The first multiplexer 143c is electrically connected to the twelfth flip-flop 143b, and the first multiplexer receives the addition operation signal ADD, the symbol address signal MS_add, the operation result address control signal CR_DFF and the The in-memory operation selection signal CIM_datasel, when the addition signal ADD is at a high level, the first multiplexer 143c is activated, and the in-memory operation selection signal CIM_datasel selects its output to be the symbol address signal MS_add or the operation The resulting address control signal CR_DFF. The second multiplexer 143d is electrically connected to the twelfth flip-flop 143b, and the second multiplexer receives the multiplication signal MUL, the symbol address signal MS_add, the operation result address control signal CR_DFF and the In-memory operation selection signal CIM_datasel, when the multiplication operation signal MUL is high, the second multiplexer is activated, and the in-memory operation selection signal CIM_datasel outputs the symbol address signal MS_add or the operation result address Control signal CR_DFF. The third OR gate 143e is electrically connected to the first multiplexer 143c and the second multiplexer 143d, and the third OR gate 143e outputs the word line switching signal WL_auto to determine the memory to be stored The number of columns of cell 111.

The data switching circuit 142 is electrically connected to the bit line automatic switching circuit 141 and the ripple carry operation unit 120 , the data switching circuit 142 receives the bit line switching signal BL_auto and the operation data, and the data switching circuit 142 Output an in-memory operation data CIM_Data. In this embodiment, the data switching circuit 142 has a third multiplexer 142a, a fourth multiplexer 142b, a fifth multiplexer 142c, a sixth multiplexer 142d, and a seventh multiplexer 142e, an eighth multiplexer 142f, a second and gate 142g, a third and gate 142h, and a fourth OR gate 142i. The third multiplexer 142a receives the added value SUM and the bit line switching signal BL_auto, and outputs the added value SUM corresponding to the bit line according to the bit line switching signal BL_auto. The fourth multiplexer 142b receives the carry value CO and the bit line switching signal BL_auto, and outputs the carry value CO corresponding to the bit line according to the bit line switching signal BL_auto. The fifth multiplexer 142c receives the product value PRO and the bit line switching signal BL_auto, and outputs the product value SUM corresponding to the bit line according to the bit line switching signal BL_auto. The sixth multiplexer 142d receives the symbol value SIG and the bit line switching signal BL_auto, and outputs the symbol value SIG corresponding to the bit line according to the bit line switching signal BL_auto.

The seventh multiplexer 142e is electrically connected to the third multiplexer 142a and the fourth multiplexer 142b, and the seventh multiplexer 142e receives the in-memory operation selection signal CIM_datasel, and the seventh multiplexer 142e An addition operation result signal add_data is output, and the addition operation result signal add_data is switched to the addition value SUM or the carry value CO by the in-memory operation selection signal CIM_datasel. The eighth multiplexer 142f is electrically connected to the fifth multiplexer 142c and the sixth multiplexer 142d, and the eighth multiplexer 142f receives the in-memory operation selection signal CIM_datasel, and the eighth multiplexer 142f A multiplication result signal mul_data is output, and the multiplication result signal mul_data is switched to the product value PRO or the symbol value SIG by the in-memory operation selection signal CIM_datasel.

The second and gate 142g receives the addition operation result signal add_data and the addition operation signal ADD, so that the second and gate 142g is activated by the addition operation signal ADD to output the addition operation result signal add_data, and the third and gate 142h receives the addition operation signal add_data For the multiplication result signal mul_data and the multiplication signal MUL, the third gate 142h is activated by the multiplication signal MUL to output the multiplication result signal mul_data. The fourth OR gate 142i is electrically connected to the second and gate 142g and the third and gate 142h, and the fourth OR gate outputs the in-memory operation data CIM_Data.

Please refer to FIG. 1, the SRAM control unit 150 receives a reset signal rst, a word address signal W_add, a bit address signal B_add, an input data Data, the read/write control signal wr_en and the clock signal Clk. In the normal read/write mode, the SRAM control unit 150 outputs the reset signal rst, the word address signal W_add, the bit address signal B_add, the read/write control signal wr_en and the clock signal clk. The control signals WS, WA, WAB, WL and the precharge control signal PreD are sent to the SRAM array 110 for data writing or reading, and are selected by the column selector 160 and output as output data Data_out. In the in-memory operation mode, the SRAM control unit 150 receives the bit line switching signal BL_auto, the word line switching signal WL_auto, and the in-memory operation data CIM_Data of the automatic switching write-back unit 140, and according to the bit line The switching signal BL_auto and the word line switching signal WL_auto output the control signals WS, WA, WAB, WL to control the SRAM array 110 to store the in-memory operation data CIM_Data.

In the present invention, the SRAM array 110 is controlled by the signal output from the operation control unit 130 to perform the logic data operations, and the ripple carry operation unit 120 is used to obtain the required logic data according to the logic data. Some operation data are finally written back to the SRAM array 110 by the automatic switching write-back unit 140. Since the operation is directly completed in the memory, the operation bottleneck can be broken and the operation speed can be greatly improved .

The protection scope of the present invention shall be determined by the scope of the appended patent application. Any changes and modifications made by anyone who is familiar with the art without departing from the spirit and scope of the present invention shall fall within the protection scope of the present invention. .

100: In-Memory Computing System 110: Static Random Access Memory Array 111: memory unit Q: storage node Qb: Anti-storage node 112: 2T switch cell group 112a: carry value 2T switch 112b: reverse or value 2T switch 112c: Sum value 2T switch 113: Precharge circuit 120: Ripple carry operation unit 121: Logic calculation circuit 122: Addition circuit 123: Carry circuit 130: Operation control unit 131: Operation clock control circuit 131a: first or gate 131b: first flip-flop 131c second flip-flop 131d: third flip-flop 131e: fourth flip-flop 132: automatic precharge switching control circuit 132a: fifth flip-flop 132b: sixth flip-flop 132c: counter 132d: first decoder 133: address selection circuit 133a: seventh flip-flop 133b: Eighth flip-flop 133c: Ninth flip-flop 133d: Tenth flip-flop 133e: Second decoder 133f: Third Decoder 133g: Fourth Decoder 133h: Second OR gate 134: Internal operation control circuit 134a: precharge controller 134b: internal computing memory controller 140: Auto switch write back unit 141: Bit line auto switch circuit 141a: Eleventh flip-flop 141b: Bit line counter 142: data switching circuit 142a: third multiplexer 142b: Fourth multiplexer 142c: Fifth multiplexer 142d: sixth multiplexer 142e: seventh multiplexer 142f: Eighth Multiplexer 142g: Second and Gate 142h: third and gate 142i: fourth or gate 143: word line automatic switching circuit 143a: and gate 143b: Twelfth Flip-Flop 143c: First Multiplexer 143d: second multiplexer 143e: third OR gate 150: SRAM control unit 160: Column selector 11: Inverted carry value line 12: Inverted OR value line 13: Sum value line 14: Inverse bit line 15: bit line SUM: added value CO: Carry value ADD: Addition signal MUL: Multiplication unit Clk: Clock signal OP: operation signal Opprec: total operation signal Wrsel: write selection signal Dffwrb: reverse read write signal PreC_bit: Precharge trigger signal OpX_add: First operation address signal OpY_add: Second operation address signal MS_add: Symbol address signal CR_add: Operation result address signal w0: Operation address control signal w2: Carry address control signal CR_DFF: Operation result address control signal PreC: Precharge control signal C: Logic operation control signal S: carry operation control signal wr_en: read and write control signal Dffwr: read write signal Cimp: count start signal PreCclk: Precharge clock signal ct: Counting signal OpX: The first operation line signal OpY: The second operation line signal MS: Carry column signal sc: Operation bit control signal pcc: precharge bit control signal BL_auto: bit line control signal CIM_Data: In-memory operation data WL_auto: Word line switching signal MP201~202: P-type transistor MN201~206: N-type transistor WS, WA, WAB, WL: Control signal PRO: Product value SIG: Symbol value add_data: Addition result signal mul_data: Multiplication result signal Data_out: Output data BL_Clk: Bit line clock signal CIM_datasel: In-memory operation selection signal CB: Inverted carry value NOR: Inverted or value AND: and value NAND: inverse and value XNOR: anti-mutual exclusion or value XOR: mutual exclusion or value Cl: carry value rst: reset signal W_add: character address signal B_add: bit address signal Data: Input data PreD: Pre-discharge control signal

FIG. 1 is a functional block diagram of an in-memory computing system according to an embodiment of the present invention. Figure 2: A circuit diagram of a SRAM array according to an embodiment of the present invention. Figure 3: A partial circuit diagram of the SRAM array according to an embodiment of the present invention. Figure 4: A circuit diagram of a memory cell according to an embodiment of the present invention. FIG. 5 is a schematic diagram of the operation of a 2T switch with a carry value according to an embodiment of the present invention. FIG. 6 is a schematic diagram of the operation of an inverse-or-value 2T switch and a sum-value 2T switch according to an embodiment of the present invention. FIG. 7 is a circuit diagram of a ripple carry operation unit according to an embodiment of the present invention. Fig. 8: A circuit diagram of an arithmetic control unit according to an embodiment of the present invention. Figure 9: A circuit diagram of an automatic switching write-back unit according to an embodiment of the present invention.

100: In-Memory Computing System

110: Static random access memory array

120: Ripple carry operation unit

130: Operation control unit

140: Auto switch write back unit

150: SRAM control unit

160: Column selector

SUM: Summation value

CO: carry value

ADD: Addition signal

MUL: Multiplication unit

Clk: Clock signal

Wrsel: write select signal

Dffwrb: reverse read write signal

OpX_add: The first operation address signal

OpY_add: The second operation address signal

MS_add: Symbol address signal

CR_add: Operation result address signal

CR_DFF: Operation result address control signal

PreC: Precharge control signal

C: logic operation control signal

S: carry operation control signal

wr_en: read and write control signal

BL_auto: bit line control signal

CIM_Data: In-memory operation data

WL_auto: word line switching signal

WS, WA, WAB, WL: Control signal

PRO: product value

SIG: symbol value

Data_out: output data

BL_Clk: bit line clock signal

CB: reverse carry value

NOR: Negative or value

AND: and value

rst: reset signal

W_add: character address signal

B_add: bit address signal

Data: input data

PreD: Pre-discharge control signal

Claims (9)

An in-memory computing system, comprising: a static random access memory array having a plurality of memory units, a plurality of 2T switch unit groups and a pre-charging circuit, each of the memory units having a storage node and an inverse storage nodes, each of the 2T switch unit groups is electrically connected to the storage node and the inverse storage node of each of the memory cells, the precharge circuit is electrically connected to the 2T switch unit groups, and the 2T switch unit groups output a plurality of logic data; a ripple carry operation unit electrically connected to the 2T switch unit groups to receive the logic data, the ripple carry operation unit has a logic calculation circuit, an addition circuit and a carry circuit, the logic calculation circuit is electrically The 2T switch unit groups are electrically connected to receive the logic data, and the logic calculation circuit outputs a plurality of logic operation data according to the logic data, and the addition circuit is electrically connected to the 2T switch groups and the logic calculation circuit to receive the logic data and the logic operation data, the addition unit outputs an addition value according to the logic data and the logic operation data, the carry circuit is electrically connected to the 2T switch unit groups and the logic calculation circuit for receiving the logic data and the logic operation data, and the carry circuit outputs a carry value according to the logic data and the logic operation data; an operation control unit electrically connected to the SRAM array, the operation control unit The unit is used for outputting a plurality of control signals to the precharge circuit and the 2T switch unit groups to control the precharge circuit and each of the 2T switch unit groups to be turned on or off; and an automatic switching write-back unit, which is electrically connected The ripple carry operation unit receives the addition value and the carry value from the ripple carry operation unit, and the automatic switching write-back unit writes the addition value and the carry value back to the static random access memory via an SRAM control unit in the memory cells of the bulk array. The in-memory computing system of claim 1, wherein each of the 2T switch unit groups has a carry-value 2T switch, an inverse-or-value 2T switch, and a sum-value 2T switch, and the carry-value 2T switch is electrically connected to the The storage node of the memory cell and an inverse carry value line, the inverse-OR 2T switch is electrically connected to the storage node of the memory cell and an inverse-OR value line, the sum-value 2T switch is electrically connected to the memory cell the inverse storage node and a sum value line. The in-memory computing system of claim 2, wherein when performing in-memory operations, one of the carry value 2T switches and two of the inverse-OR 2T switches and the sum value 2T switch are turned on, and the rest of the carry value 2T switches are turned on. , the inverse-or value 2T switches and the sum value 2T switches are closed. The in-memory computing system of claim 1, wherein the computing control unit has an computing clock control circuit, an automatic precharge switching control circuit, an address selection circuit, and an internal computing control circuit, and the computing clock control circuit uses In order to receive an addition operation signal, a multiplication operation signal and a clock signal, and the operation clock control circuit outputs an operation signal, a total operation signal, a write selection signal and an inverse read write signal, the automatic presetting The charging switch control circuit is electrically connected to the operation clock control circuit to receive the total operation signal, the write selection signal and the reverse read write signal, and the automatic precharge switch control circuit outputs a precharge trigger signal. The address selection circuit is electrically connected to the operation clock control circuit to receive the operation signal, and the address selection circuit further receives a first operation address signal, a second operation address signal, a symbol address signal and an operation The result address signal, and the address selection circuit outputs an operation address control signal, a carry address control signal and an operation result address control signal, the internal operation control circuit is electrically connected to the operation clock control circuit, the The automatic precharge switching control circuit and the address selection circuit receive the operation signal, the reverse read and write signal, the precharge trigger signal, the operation address control signal and the carry address control signal, and the internal operation The control circuit outputs a precharge control signal, a logic operation control signal and a carry operation control signal to the precharge circuit and the 2T switch unit groups. The in-memory computing system of claim 4, wherein the computing clock control circuit has a first OR gate, a first flip-flop, a second flip-flop, a third flip-flop and a fourth flip-flop, the first OR gate receives the addition operation signal and the multiplication operation signal, And the first OR gate outputs the operation signal, the first flip-flop receives a read-write control signal and the clock signal, and the first flip-flop outputs a read-write signal, the second flip-flop The first or gate is electrically connected, the second flip-flop receives the clock signal and the operation signal, the second flip-flop outputs the total operation signal, and the third flip-flop is electrically connected to the first The OR gate and the first flip-flop receive the operation signal and the read-write signal, the third flip-flop outputs the write-select signal, and the fourth flip-flop is electrically connected to the first flip-flop , the fourth flip-flop receives the read-write signal and the clock signal, and the fourth flip-flop outputs the reverse read-write signal. The in-memory computing system of claim 4, wherein the automatic precharge clock control circuit has a fifth flip-flop, a sixth flip-flop, a counter and a first decoder, and the fifth flip-flop is electrically is electrically connected to the operation clock control circuit to receive the total operation signal and the operation signal, and the fifth flip-flop outputs a count start signal, and the sixth flip-flop is electrically connected to the third flip-flop and the fourth flip-flop The flip-flop receives the write selection signal and the reverse read write signal, and the sixth flip-flop outputs a precharge clock signal, and the counter is electrically connected to the fifth flip-flop and the sixth flip-flop The inverter receives the count start signal and the precharge clock signal, and the counter outputs a count signal, the first decoder is electrically connected to the counter to receive the count signal, and the first decoder outputs the precharge trigger signal. The in-memory computing system of claim 5, wherein the address selection circuit has a seventh flip-flop, an eighth flip-flop, a ninth flip-flop, a tenth flip-flop, and a second decoder , a third decoder, a fourth decoder and a second OR gate, the seventh flip-flop is electrically connected to the first OR gate, and the seventh flip-flop receives the operation signal and the first operation bit address signal, and the seventh flip-flop outputs a first operation column signal, the eighth flip-flop is electrically connected to the first OR gate, and the eighth flip-flop receives the operation signal and the second operation address signal, and the eighth flip-flop outputs a second operation column signal, the ninth flip-flop The ninth flip-flop is electrically connected to the first OR gate, the ninth flip-flop receives the operation signal and the symbol address signal, and the ninth flip-flop outputs a carry column signal, and the tenth flip-flop is electrically connected The first OR gate, the tenth flip-flop receive the operation signal and the estimated result address signal, and the tenth flip-flop outputs the operation result address control signal, and the second decoder is electrically connected to the first Seven flip-flops receive the first operational column signal, the second decoder outputs a first decoding signal, the third decoder is electrically connected to the eighth flip-flop to receive the second operational column signal, and The third decoder outputs a second decoded signal, the fourth decoder is electrically connected to the ninth flip-flop to receive the carry column signal, and the fourth decoder outputs the carry address control signal, the first The second OR gate is electrically connected to the first decoder and the second decoder to receive the first decoded signal and the second decoded signal, and the second OR gate outputs the operation address control signal. As claimed in the in-memory computing system of claim 5, the internal computing control circuit has a precharge controller and an internal computing memory controller, the precharge controller is electrically connected to the computing clock control circuit to receive the computing signal and The reverse read and write signal, and the precharge controller outputs an operation bit control signal and a precharge bit control signal, the internal operation memory controller is electrically connected to the precharge controller, the automatic precharge a switching control circuit and the address selection circuit, the internal operation memory controller receives the operation bit control signal, the precharge bit control signal, the precharge trigger signal, the operation address control signal and the carry address a control signal, and the internal operation memory controller outputs the precharge control signal, the logic operation control signal and the carry operation control signal. The in-memory computing system of claim 4, wherein the automatic switching write-back unit has a bit line automatic switching circuit, a data switching circuit and a word line automatic switching circuit, and the bit line automatic switching circuit is electrically connected to the The operation clock control circuit receives the write selection signal and the read write signal, and the bit line automatic switching circuit outputs a bit line switching signal, and the data switching circuit is electrically connected to the bit line automatic switching circuit and the ripple carry operation unit, the data switching circuit receives the bit The line switching signal and the operation data, and the data switching circuit outputs an in-memory operation data, the word line automatic switching circuit is electrically connected to the operation clock control circuit and the address selection circuit, and the word line automatically switches The circuit receives the addition operation signal, the multiplication operation signal, the operation signal, the reverse read write signal, the symbol address signal and the operation result address control signal, and the word line automatic switching circuit outputs a word line switching signal.

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