TWI771671B - Semiconductor wafer fabrication system and method of fabricating semiconductor wafer - Google Patents

Abstract

Embodiment of the disclosure provides a method for fabricating semiconductor wafer, moving lift pins of a wafer chuck to an elevated position; moving a semiconductor wafer over the wafer chuck and placing the semiconductor wafer on the lift pins on the elevated position; producing image in relation to the semiconductor wafer and the wafer chuck; calculating a position shift data based on the image; determine the position shift data is in an acceptable range; and when the position shift data is in the acceptable range, issuing a control signal to an actuator that is connected to the lift pins to change the position of the semiconductor wafer relative to the wafer chuck.

Description

Semiconductor wafer manufacturing system and method for manufacturing semiconductor wafers

The present disclosure relates to a method for manufacturing a semiconductor wafer and a semiconductor wafer manufacturing system, and more particularly, to a method and system for calibrating the position of a semiconductor wafer relative to a wafer seat.

Semiconductor devices are used in a variety of electronic applications, such as personal computers, mobile phones, digital cameras, and other electronic equipment. Semiconductor devices are usually fabricated by sequentially depositing insulating or dielectric layer materials, conductive layer materials, and semiconductor layer materials on a semiconductor substrate, and then patterning the resulting layers of various materials using a lithography process to form circuit components and parts on the semiconductor substrate. Technological advances in IC materials and their design have resulted in multiple generations of ICs. Each generation has smaller and more complex circuits than the previous generation.

In the fabrication of semiconductor devices, various fabrication tools are used in sequence to fabricate integrated circuits on semiconductor wafers. In manufacturing tools, a wafer carrier is often used to carry semiconductor wafers. However, if the semiconductor wafer placed above the wafer seat is not centered on the wafer seat, it will lead to defects of poor uniformity during semiconductor processing.

An embodiment of the present disclosure provides a method of manufacturing a semiconductor wafer, which includes moving a plurality of lift pins of a wafer holder to a raised position; moving a semiconductor wafer over the wafer holder and placing the semiconductor wafer at the raised position position on the lift pins; use a camera to generate an image about the semiconductor wafer and the wafer seat; calculate a position offset information of the semiconductor wafer according to the image; determine whether the position offset information of the semiconductor wafer is within the acceptable range acceptance range; and when the position offset information is within the acceptable range, send a driving signal to an actuator connected to the lift pin according to the calculated position offset information, so that the actuator drives the semiconductor wafer relative to the wafer displacement of the seat.

Another embodiment of the present disclosure provides a semiconductor wafer manufacturing system, including a body configured to carry a semiconductor wafer and having a plurality of through holes; a rod located under the body; a plurality of lift pins connected to The rod is movably arranged in the perforation; a photographing assembly is disposed above the body and configured to generate an image about the body; a first actuator is connected to the rod and configured to control the rod displacement in a vertical direction; a plurality of second actuators, each connected to the lift pin and configured to control the displacement of the lift pin in a horizontal direction; and a control module electrically connected to the photographing element and the first Two actuators, wherein the control module sends a control signal to the second actuator according to the image generated by the photographing element to control the displacement of the lift pin in the horizontal direction.

The following disclosure provides many different embodiments or examples for implementing different features of the present disclosure, and the following disclosure of this specification describes specific examples of various components and their arrangements in order to simplify the description of the invention. Of course, these specific examples are not intended to limit the present disclosure. For example, if the following disclosure of this specification describes that a first feature is formed on or over a second feature, it means that it includes an embodiment in which the first feature and the second feature are formed in direct contact with each other. , and also includes embodiments in which additional features may be formed between the first and second features, so that the first and second features may not be in direct contact. In addition, repeated reference symbols and/or words may be used in different examples in the description of the present disclosure. These repeated symbols or words are used for the purpose of simplicity and clarity, and are not used to limit the relationship between the various embodiments and/or the appearance structures.

Furthermore, for convenience in describing the relationship of one element or feature to another (plural) element or (plural) feature in the drawings, spatially relative terms such as "under", "under", "Lower", "upper", "upper" and similar terms, and the like. It will be understood that, in addition to the orientation depicted in the figures, spatially relative terms encompass different orientations of the device in use or operation. The device may also be otherwise oriented (eg, rotated 90 degrees or at other orientations) and the description of the spatially relative terms used interpreted accordingly. It will be appreciated that additional operational steps may be provided before, during, and after the described method, and that certain operational steps described may be replaced or omitted in certain method embodiments.

It should be noted that the embodiments discussed herein may not necessarily recite every component or feature that may be present within a structure. For example, one or more components may be omitted from the drawings, eg, when the discussion of a component may sufficiently convey aspects of the embodiments, it may be omitted from the drawings. Furthermore, the method embodiments discussed herein may be discussed in a particular order of execution, while in other method embodiments, they may be performed in any reasonable order.

FIG. 1 shows a schematic diagram of a semiconductor wafer fabrication system 1 for processing semiconductor wafers 5 in accordance with some embodiments. The semiconductor wafer fabrication system 1 in FIG. 1 includes a load port 2 , a load lock chamber 3 , a robotic arm 6 , a plurality of processing tools 10 , one or more metrology chambers 8 and a control module 90 .

According to some embodiments, the semiconductor wafer 5 is made of silicon, germanium or other semiconductor materials. According to some embodiments, the semiconductor wafer 5 is made of a compound semiconductor, such as silicon carbide (SiC), gallium arsenide (GaAs), indium arsenide (InAs) or indium phosphide (InP). According to some embodiments, the semiconductor wafer 5 is made of an alloy semiconductor, such as silicon germanium (SiGe), silicon germanium carbon (SiGeC), gallium arsenide phosphide (GaAsP) or gallium indium phosphide (GaInP). According to some embodiments, the semiconductor wafer 5 includes a crystalline film layer. For example, the semiconductor wafer 5 has a crystal film layer covering a bulk semiconductor. According to some embodiments, the semiconductor wafer 5 may be a silicon-on-insulator (SOI) or germanium-on-insulator (GOI) substrate.

A plurality of device elements may be included on the semiconductor wafer 5 . For example, the device elements formed on the semiconductor wafer 5 may include a transistor, such as metal oxide semiconductor field effect transistors (MOSFETs), complementary metal oxide semiconductor transistors (MOSFETs) metal oxide semiconductor (CMOS) transistors), bipolar junction transistors (BJT), high voltage transistors, high frequency transistors, p-channel and/or n- channel field-effect transistors (PFET) or n-channel field-effect transistors (NFET), etc., and or other components. The various device components on the semiconductor wafer 5 have undergone various processing steps , such as deposition, etching, ion implantation, photolithography, annealing, and or other processes.

The load port 2 is configured to support and dock the wafer carrier 4 to facilitate the feeding and subsequent removal of the semiconductor wafers 5 into the semiconductor wafer fabrication system 1 . The wafer carrier 4 is configured to transport a plurality of semiconductor wafers, eg, 6 wafers, 12 wafers, 24 wafers, and the like. The wafer carrier 4 may be a Standard Mechanical Interface (SMIF) for loading semiconductor wafers each having a diameter of 18 mm. Alternatively, the wafer carrier 4 may be a Front Opening Unified Pod (FOUP), which may be used to load 300mm or 450mm semiconductor wafers or semiconductor wafers with larger diameters. However, other types and/or sizes of wafer carriers are not excluded.

The load lock chamber 3 is provided between the semiconductor wafer fabrication system 1 and the load port 2 . The load lock chamber 3 is configured to preserve the pressure in the semiconductor wafer fabrication system 1 by isolating the air pressure in the semiconductor wafer fabrication system 1 from the external environment. When the semiconductor wafers 5 from the wafer carrier 4 are fed into the load lock chamber 3, the door of the load lock chamber 3 is sealed. In this way, an airtight environment is established in the load lock chamber 3 . The load lock chamber 3 can generate a pressure matched with that in the semiconductor wafer fabrication system 1 by changing the gas content inside. When the correct air pressure is reached, the robot arm 6 can transport the semiconductor wafer 5 from the load lock chamber 3 . Robot arm 6 transfers wafers between load lock chamber 3 , process tool 10 and metrology chamber 8 . Robotic arm 6 is operable to position and place semiconductor wafer 5 into processing tool 10 prior to processing and to remove semiconductor wafer 5 from processing tool 10 after processing.

The processing tool 10 is configured to perform one or more semiconductor processing processes, such as plasma processing, chemical vapor deposition (CVD), atomic layer deposition (ALD), physical vapor deposition (PVD), annealing, dry etching, degassing, Pre-cleaning, cleaning, post-cleaning, etc. The metrology chamber 8 is configured to measure various properties of the wafer before or after processing. In some embodiments, one or more metering chambers 8 are integrated into one or more process tools 10 . Although five processing tools 10 and two metering chambers 8 are shown in FIG. 1 , the remaining number of processing tools 10 and/or metering chambers 8 are included within the scope of the present disclosure. Likewise, in some embodiments, the semiconductor wafer fabrication system 1 includes more than one robot arm 6 and/or a load lock chamber 3 . The control module 90 is configured to control the processing, transport and measurement of the wafers. The detailed features of the control module 90 will be further described below with reference to FIG. 6 .

FIG. 2 shows a schematic diagram of partial elements of a machining tool 10 in accordance with some embodiments. In some embodiments, the processing tool 10 is a plasma reaction chamber and is used to perform semiconductor wafer processing procedures including plasma etching processing. However, the processing tool 10 is not limited to performing the above-described processing, and the processing tool 10 may be used to perform the processing of any semiconductor wafer. Although the embodiments of the present disclosure are expressed in this particular architecture, it is to be understood that the present disclosure may also be applied to various other architectures and designs. In addition, the processing tool 10 is only a simple schematic representation, and some elements of the processing tool 10 are not shown. For example, valves, seal assemblies and other similar items are not shown. Those skilled in the art will understand that these and other components that make up the machining tool 10 may be incorporated therein.

As shown in FIG. 2 , the processing tool 10 includes a reaction chamber 11 , an upper electrode assembly 12 , a radio frequency coil assembly 14 , a wafer seat 20 , a photographing assembly 140 and a control module 90 . The reaction chamber 11 defines an area for performing machining processes. In some embodiments, the reaction chamber 11 includes a reaction chamber wall 111 and a reaction chamber bottom 112 . The reaction chamber wall 111 extends vertically from the edge of the reaction chamber bottom 112 . In some embodiments, there may be a selectively sealable slit shutter on the reaction chamber wall 111 to facilitate transport of the semiconductor wafer 5 into and out of the processing tool 10 . In some embodiments, the reaction chamber bottom 112 includes a gas extraction port (not shown) for extracting gas from the reaction chamber 11 . For example, a pumping system (including a throttle valve and a vacuum pump, etc.) can be connected to the pumping port of the bottom 112 of the reaction chamber. Once the slit valve is sealed, the pumping system can be operated to draw and maintain the vacuum within the reaction chamber 11 .

The upper electrode assembly 12 is located above the reaction chamber 11 and includes a flat electrode 121 and a ring electrode 122 . The plate electrode 121 is located at the upper end of the reaction chamber 11 , and the ring electrode 122 is disposed between the plate electrode 121 and the reaction chamber wall 111 . In some embodiments, the plate electrode 121 defines a showerhead 120 for distributing the gas. So configured, the plate electrode 121 may serve as a component for distributing gas into the reaction chamber 11, coupled to a gas source (not shown). The gas source contains precursors or process gases used to process the reaction chamber 11 . In some embodiments, the plate electrode 121 is connected to a DC power source (eg, ground). In some embodiments, the plate electrode 121, the reaction chamber wall 111 and a reaction chamber bottom 112 are all connected to ground together.

In some embodiments, the RF coil set 14 surrounds the ring electrode 122 and is coupled to the first RF power source 15 , and generates and maintains the plasma 18 in the reaction chamber 11 by the RF power provided by the first RF power source 15 . . In one embodiment, the first radio frequency power supply 15 is a high frequency radio frequency power supply. The first RF power source 15 is connected to the RF coil assembly 14 via an impedance matching circuit 16 for enhancing the dissociation and plasma density of the process gas. For example, impedance matching circuit 16 may include one or more capacitors, inducers, and other circuit components. The first RF power source 15 supplies RF power to the RF coil assembly 14 at a frequency of about 2 MHz or above, but the present disclosure is not limited thereto. In some embodiments, the bias voltage of the first RF power source 15 is about -30K to +30K volts, and the pulse width during operation thereof is about 5 to 300 microseconds, but is not limited thereto.

As shown in FIG. 2 , the wafer holder 20 is located on the reaction chamber bottom 112 of the reaction chamber 11 , and is configured to carry the semiconductor wafer 5 . In some embodiments, the ring electrode 122 and the RF coil assembly 14 are used as the top electrode of the processing tool 10, and the wafer holder 20 is used as the lower electrode. The wafer holder 20 may be of any configuration suitable for supporting wafers, such as an electrostatic chuck or a vacuum chuck.

According to some embodiments of the present disclosure, the wafer holder 20 includes a body 21 and a support member 22 . The body 21 includes a top surface 211 as a support surface for the semiconductor wafer 5 , the shape of which generally conforms to the shape of the semiconductor wafer 5 to be supported above it. For example, the top surface 211 of the wafer holder 20 is generally circular and is used to support the substantially circular semiconductor wafer 5 . In some embodiments, the top surface 211 of the wafer seat 20 has a larger area than the semiconductor wafer 5 . In one embodiment, the surface of the body 21 is connected to a wafer temperature control system (not shown), such as resistive heating coils and/or fluid channels connected to a heating or cooling fluid system. The body 21 may comprise any material used in the machining tool 10 . For example, the material of the body 21 includes steel, other conductive metals or alloys. In some embodiments, the body 21 includes a vacuum system for holding the semiconductor wafer 5 in place. In some embodiments, the body 21 is an electrostatic wafer holder (Electrostatic. Chuck, ESC).

The support assembly 22 is used to support the semiconductor wafer 5 when the semiconductor wafer 5 is fed over the body 21 . In some embodiments, the support assembly 22 includes a rod 221 , an extension portion 222 and a plurality of lift pins 223 . When the semiconductor wafer 5 is transported above the body 21, the support assembly 22 moves to a raised position (as shown in FIG. 9) to support the semiconductor wafer 5 above the body 21, and then descends to a lowered position (as shown in FIG. 9). 4 ), the semiconductor wafer is placed on the upper surface 211 of the body 21 . The position manipulation of the support assembly 22 will be described in further detail in the description of the method S100 later.

In some embodiments, the rod member 221 is located below the body 21 and extends in a vertical direction (eg, the Z-axis direction), and the extension portion 222 is connected to one end of the rod member 221 . The number of the extension parts 222 may correspond to the number of the lift pins 223 and each extends radially outward from one end of the rod 221 . The lift pin 223 is connected to the extension portion 222 and extends vertically upward to be inserted into the body 21 . In other embodiments, the number of the segments of the extension portion 222 and the lift pins 223 are both three, but the present disclosure is not limited thereto. In other embodiments, the extension portion 222 is omitted, and the rod member 221 and the lift pin 223 extend vertically on a straight line.

Please refer to Figure 3 and Figure 4 at the same time. FIG. 3 shows a top view of the wafer seat 20 with the semiconductor wafer 5 placed thereon according to some embodiments of the present disclosure, and FIG. 4 shows a cross-sectional view of the wafer seat 20 of FIG. 3 along the line A-A. In some embodiments, the body 21 has a plurality of perforations 210 . The through holes 210 penetrate through the upper surface 211 and the lower surface 212 of the main body 21 , and the lift pins 223 are movably disposed in the through holes 210 . It should be understood that, in the embodiment shown in FIG. 3 , the body 21 has three through holes 210 for accommodating three lift pins 223 , but the present disclosure is not limited thereto. It is within the scope of the present disclosure that the body 21 has more or less through holes to accommodate different numbers of lift pins 223 . In one embodiment, the ratio of the width W1 of each lift pin 223 to the width W2 of the corresponding through hole 210 is between 0.25 and 0.75. Since the above ratio is smaller than the ratio of the lift pin to the through hole in the conventional wafer holder, Therefore, the displacement of the lift pins 223 in the through holes 210 can be increased.

In some embodiments, as shown in FIG. 4 , the support assembly 22 further includes a plurality of actuators, such as a first actuator 224 and a plurality of second actuators 225 . The first actuator 224 is configured to drive the movement of the support assembly 22 in the vertical direction (Z-axis direction), and the plurality of second actuators 225 are each configured to drive the lift pins 223 in the horizontal direction relative to the extension 222 move on. In some embodiments, the first actuator 224 includes a rotary motor and is coupled to the bottom end of the rod 221 . The outer surface of the rod 221 is provided with threads. When the first actuator 224 drives the rod 221 to rotate, the rod 221 moves in the vertical direction (Z-axis direction). In one embodiment, the first actuator 224 is driven according to the control signal from the control module 90 to control the vertical movement distance of the rod 221 .

In some embodiments, the plurality of second actuators 225 are respectively disposed at the connection between the extension portion 222 and the lift pin 223 . The second actuators 225 may each include one or more micromotors. For example, the second actuator 225 includes a ball motor to drive the displacement of the lift pin 223 . Alternatively, the second actuator 225 includes two micro linear motors stacked alternately, one of which is used to drive the displacement of the lift pin 223 in the X-axis direction, and the other is used to drive the lift pin 223 to move along the Y-axis. displacement. In one embodiment, the second actuator 225 is driven according to the control signal from the control module 90 to control the horizontal movement distance of the lift pin 223 .

In one embodiment, the surface of the lift pins 223 in contact with the semiconductor wafer 5 includes a rough surface, so as to increase the frictional force between the lift pins 223 and the semiconductor wafer 5 . For example, as shown in FIG. 5A , the lift pin 223 includes a column 226 , and a rough structure 227 is formed on the top 2261 of the column 226 . Roughness 227 may be imprinted on top 2261 . Alternatively, the rough structure 227 is fixed to the top 2261 by means of sticking. In another example, the entire outer surface of the lift pins 223 a has a rough structure, and is not limited to the surface in contact with the semiconductor wafer 5 .

Referring again to FIG. 1 , in some embodiments, the second RF power source 17 is coupled to the body 21 of the wafer seat 20 . The second radio frequency power supply 17 is a low frequency radio frequency power supply, which supplies radio frequency power to the wafer seat 20 at a frequency of about 0.5 to 10 KHz, but is not limited thereto. In some embodiments, the bias voltage of the second RF power source 17 is about -0.2 to 10 kV, and the pulse width during operation thereof is about 20 to 100 microseconds, but not limited thereto. In one embodiment, ions of the plasma 18 are guided to impact the surface of the semiconductor wafer 5 by a bias voltage between the top electrode (ring electrode 122 and the RF coil assembly 14 ) and the lower electrode (wafer holder 20 ). , but this disclosure is not limited to this. In some embodiments, the second RF power source 17 can also be a DC bias voltage source.

In some embodiments, the camera assembly 40 is positioned anywhere above the wafer seat 20 and is used to generate images about the wafer seat 20 . In one embodiment, the camera assembly 40 includes a camera for generating a still image or a moving image of the wafer seat 20 . The photographing unit 40 transmits the image data about the wafer seat 20 to the control module 90 for image analysis, so as to determine the displacement distance of the lift pins 223 .

FIG. 6 shows a block diagram of some components of the semiconductor wafer fabrication system 1 of the present disclosure. In some embodiments, the control module 90 includes a processor 91 and a memory 92 . Processor 91 is configured to execute and/or interpret one or more sets of instructions stored in memory 92 . In some embodiments, processor 91 is a microprocessor (MCP) central processing unit (CPU), a multiprocessor, a distributed processing system, an application specific integrated circuit (ASIC), and/or a suitable processor.

Memory 92 includes random access memory or other dynamic storage devices for storing data and/or instructions for execution by processor 91 . In some embodiments, the memory 92 is used to store process values, temporary variables, or other intermediate information during the execution of the manufacturing process. For example, the memory 92 is configured to store image information generated by the camera element 40 and/or the memory 92 is configured to store image data regarding the proper placement of the semiconductor wafer 5 in the wafer seat 20 .

In some embodiments, memory 92 includes read-only memory or other static storage device for storing static information and instructions for processor 91 . In some embodiments, the memory 92 stores the position information of the center of the semiconductor wafer 5 disposed above the wafer holder 20 . In some embodiments, memory 92 is an electronic, magnetic, optical, electromagnetic, infrared and/or semiconductor system (or device or device). For example, memory 92 includes semiconductor or solid state memory, magnetic tape, removable computer hard disks, random access memory (RAM), read only memory (ROM), optical disks, and/or memory.

In some embodiments, as shown in FIG. 6 , the image data 95 from the camera unit 40 is output to the control module 90 for analysis to determine the offset of the semiconductor wafer 5 relative to the wafer seat 20 . Then, the control module 90 sends a control signal 96 to the actuators of the support assembly 22 , such as the first actuator 224 ( FIG. 4 ) or the second actuator, according to the offset of the semiconductor wafer 5 relative to the wafer holder 20 . An actuator 225 (FIG. 4) controls the displacement of the support assembly 22. In other embodiments, the camera unit 40 includes a dedicated processor or hardware for performing calculations, and outputs an analysis signal about the offset of the semiconductor wafer 5 relative to the wafer seat 20 to the control module 90, and then , the control module 90 sends a control signal 96 to the actuator of the support assembly 22 according to the analysis signal.

FIG. 7 shows a flowchart of a method S100 of fabricating a semiconductor wafer according to some embodiments of the present disclosure. For the sake of example, the flow is illustrated with the schematic diagrams in Figs. 1 and 8-13. In different embodiments, some stages may be replaced or eliminated. The following description is exemplary only and is not intended to limit what is described in the scope of the following claims. It will be appreciated that additional steps are provided before, during, and after the steps illustrated by Figure 7, and that additional embodiments of the method may replace or reduce some of the operations described below, and the order of operations described below Interchangeable.

The method S100 of manufacturing a semiconductor wafer includes operation S110 , moving the lift pins 223 of the wafer holder 20 to a lift position. In one embodiment, before the semiconductor wafer 5 is moved into the processing tool 10 , no semiconductor wafer is placed over the wafer seat 20 . In addition, the first brake 224 of the wafer holder 20 moves the height of the support assembly 22 from the lowered position shown in FIG. 4 to the raised position shown in FIG. 8 to the support assembly 22 according to the control signal of the control module 90 . In the lowered position, the top end 2230 of the lift pin 223 of the support assembly 22 is located below the upper surface 211 of the body 21 . In the raised position, the top end 2230 of the lift pin 223 of the support assembly 22 is located above the upper surface 211 of the main body 21 and is spaced apart from the upper surface 211 of the main body 21 by a distance.

The method S100 for manufacturing a semiconductor wafer further includes operation S120 , moving the semiconductor wafer 5 to the top of the wafer seat 20 and placing the semiconductor wafer 5 on the lift pins 223 . In one embodiment, as shown in FIG. 9 , after the lift pins 223 of the wafer holder 20 are located at the raised position, the semiconductor wafer 5 can be moved into the processing tool 10 by the robot arm 6 and located above the wafer holder 20 . Location. Next, the robot arm 6 lowers the height of the semiconductor wafer 5 to make the semiconductor wafer 5 contact the top ends 2230 of the lift pins 223 . The descending action of the robot arm 6 keeps all the lift pins 223 in contact with the semiconductor wafer 5 , and stops after the semiconductor wafer 5 is separated from the robot arm 6 . In this way, as shown in FIG. 10 , the semiconductor wafer 5 is placed on the lift pins 223 and supported by the lift pins 223 . Next, the robot arm 6 exits the processing tool 10 to transport other semiconductor wafers 5 into or out of the other processing tool 10 .

The method S100 of fabricating a semiconductor wafer further includes operation S130 , generating an image of the semiconductor wafer 5 and the wafer seat 20 by using the photographing device 40 . In one embodiment, the photographing unit 40 is to photograph the semiconductor wafer 5 and the wafer holder 20 when the lift pins 223 of the wafer holder 20 are at the raised position, and generate images of the semiconductor wafer 5 and the wafer holder 20 News. FIG. 11 shows an image M of the semiconductor wafer 5 and the wafer seat 20 generated by the camera unit 40 in one embodiment.

In some embodiments, the semiconductor wafer 5 is placed in an orientation controller (orienter, not shown) for positioning after being fed into the processing tool 10 , and then is fed into the processing tool 10 by the robotic arm 6 . When an error occurs in the adjustment of the direction controller, the semiconductor wafer 5 fed into the processing tool 10 by the robot arm 6 will not be positioned above the wafer holder 20 in the center. Then, as shown in the image M of FIG. 9 , the center C1 of the wafer holder 20 and the center C2 of the semiconductor wafer 5 are displaced. If the semiconductor wafer 5 is directly processed without correcting the offset, the problem of lowering the processing uniformity may occur. Therefore, in order to avoid this problem, the method S100 for manufacturing a semiconductor wafer according to an embodiment of the present disclosure further includes the following steps to correct the position of the semiconductor wafer 5 .

In operation S140, the offset information of the semiconductor wafer 5 is calculated. In one embodiment, the offset information of the semiconductor wafer 5 is obtained by analyzing the images of the semiconductor wafer 5 and the wafer seat 20 generated by the camera unit 40 . For example, as shown in FIG. 11 , after the camera element 40 generates the image M about the semiconductor wafer 5 and the wafer seat 20 , the processor of the camera element 40 itself or the processor of the control module 90 will analyze the image M Offset information of the edge 51 of the middle semiconductor wafer 5 and the edge 213 of the wafer seat 20 at multiple positions.

In one embodiment, the offset information generated by the processor of the camera unit 40 or the processor of the control module 90 includes the position offsets D1 , D2 , D3 , and D4 of the four semiconductor wafers. The position offset D1 represents the offset of the edge 51 of the semiconductor wafer 5 with respect to the reference point P1 on the edge 213 of the body 21 . The positional offset D2 represents the offset of the edge 51 of the semiconductor wafer 5 with respect to the reference point P2 on the edge 213 of the body 21 . The position offset D3 represents the offset of the edge 51 of the semiconductor wafer 5 relative to the reference point P3 on the edge 213 of the body 21 . The position offset D4 represents the offset of the edge 51 of the semiconductor wafer 5 with respect to the reference point P4 on the edge 213 of the body 21 . The reference point P1 and the reference point P3 are respectively located in the positive X direction and the negative X direction of the center C1 of the wafer seat 20 , and the reference point P2 and the reference point P4 are respectively located in the negative Y direction and the positive Y direction of the center C1 of the wafer seat 20 . The above-mentioned X direction and Y direction may be parallel to the X direction and the Y direction of the control operand of the second actuator 225 .

It can be understood that, although the position offsets D1 , D2 , D3 , and D4 of the four semiconductor wafers are generated in the above embodiments, the embodiments of the present disclosure are not limited thereto. In other embodiments, the processor of the camera assembly 40 itself or the processor of the control module 90 may generate more or less information about the offset of the semiconductor wafer. In another embodiment, the processor of the photographing component 40 itself or the processor of the control module 90 only generates the position offset D1 and the position offset D2, but does not generate the position offset D3 and the position offset D4 . In yet another embodiment, the processor of the camera element 40 itself or the processor of the control module 90 does not generate the position offsets D1 , D2 , D3 , D4 , but compares the image information of the edge 51 of the semiconductor wafer 5 with the image information of the edge 51 of the semiconductor wafer 5 . Compare the location information stored in the database. The above position information represents the position when the edge 51 of the semiconductor wafer 5 is placed on the wafer holder 20 in the center.

In operation S150, it is determined whether the positional offset of the semiconductor wafer is within an acceptable range. In one embodiment, the positional offsets D1, D2, D3, and D4 of the four semiconductor wafers are respectively compared with the predetermined parameters stored in the database, and when the comparison result shows the positional offsets D1, D2, Whether the difference between D3, D4 and the predetermined parameter is greater than a threshold. The threshold value may represent the distance between the lift pin 223 and the edge of the through hole 210 in all directions. If the difference between the position offsets D1 , D2 , D3 , D4 and the predetermined parameters is greater than the above-mentioned threshold, it means that the offset of the semiconductor wafer 5 is too large and cannot be corrected by adjusting the position of the lift pins 223 . On the contrary, the correction can be performed by the position of the lift pin 223 .

If the position shift information (or the position shift amount) of the semiconductor wafer 5 exceeds the acceptable range, the method S100 of manufacturing the semiconductor wafer proceeds to operation S180 to issue an alarm. After the control module 90 receives the alarm notification, the control module 90 can drive the robot arm 6 to enter the processing tool 10 again, and remove the semiconductor wafer 5 from the lift pins 223 and send it to the direction controller for positioning. The method S100 of manufacturing a semiconductor wafer repeats to step S120.

If the position shift information (or the position shift amount) of the semiconductor wafer 5 is out of the acceptable range, the method S100 for manufacturing a semiconductor wafer proceeds to operation S160 , and a driving signal is sent according to the position shift amounts D1 , D2 , D3 , and D4 To the second actuator 225 connected to the lift pins 223 , the second actuator 225 drives the displacement of the semiconductor wafer 5 relative to the wafer holder 20 . In one embodiment, the control parameters of the second actuator 225 include the displacement amount in the X direction and the displacement amount in the Y direction.

In some embodiments, the calculation method of the displacement of the second actuator 225 in the X direction includes numerically comparing the position offset D1 with the position offset D3, so as to determine that the second actuator 225 faces the positive X direction. moving in the direction or in the negative X direction; and subtracting a reference distance from the larger value of the position offset D1 and the position offset D3 to determine the displacement in this direction. For example, the position offset D1 is 3mm, the position offset D3 is 1mm, and the reference spacing is 2mm. Since the position shift amount D1 is greater than the position shift amount D3, it is determined that the second actuator 225 moves in the positive X direction, and the displacement amount is 1 mm (ie, 3 mm-2 mm).

In some embodiments, the calculation method of the displacement amount of the second actuator 225 in the Y direction includes comparing the position offset D2 and the position offset D4 numerically, so as to determine that the second actuator 225 is facing the positive Y direction. moving in the direction or in the negative Y direction; and subtracting a reference distance from the larger value of the position offset D2 and the position offset D4 to determine the displacement in the direction. For example, the position offset D2 is 3mm, the position offset D4 is 1mm, and the reference spacing is 2mm. Since the position shift amount D2 is greater than the position shift amount D4, it is determined that the second actuator 225 moves in the negative Y direction, and the displacement amount is 1 mm (ie, 3 mm-2 mm).

After the lift pin 223 is displaced according to the positional offset, as shown in FIG. 12 , the lift pin 223 is displaced relative to the center of the hole 210 . In one embodiment, after the lift pin 223 moves, the lift pin 223 is in close contact with the side wall of the through hole 210 . In addition, the distances D5 and D6 of the semiconductor wafer 5 relative to the edge 21 of the wafer seat 20 in different directions are adjusted to be the same.

In some embodiments, as shown in FIGS. 5A and 5B , the surface of the lift pins 223 or the lift pins 223 a in contact with the semiconductor wafer 5 has a rough structure, so when the lift pins 223 or the lift pins 223 a are displaced, the lift pins 223 or 223 a are lifted The pins 223 or the lift pins 223 a and the semiconductor wafer 5 have high frictional force, so that the lift pins 223 or the lift pins 223 a can be prevented from sliding relative to the semiconductor wafer 5 .

After the operation S160 is completed, the method of manufacturing a semiconductor wafer S100 continues to the operation S170, in which the lift pins 223 of the wafer holder 20 are moved from the raised position to the lowered position. In one embodiment, the photographing assembly 40 is further configured to confirm whether the distance D5 and the distance D6 are the same after the operation S160 is completed. If it is determined to be different, the method S100 for manufacturing a semiconductor wafer may repeatedly perform operations S140-S160. If it is determined to be the same, the control module 90 sends a control signal to the first driver 224 to move the position of the support assembly 22 from the raised position shown in FIG. 12 to the lowered position shown in FIG. 13 .

After the operation S170 is completed, the processing tool 10 can start processing the semiconductor wafer 5 . In one embodiment, the processing of the semiconductor wafer 5 by the processing tool 10 is a plasma etching process. Since the semiconductor wafer 5 is disposed above the wafer holder 20 in the center, the parameters such as the temperature and the bias voltage of the semiconductor wafer 5 can be determined by the wafer. The round seat 20 is adjusted correctly, so that the uniformity of the plasma etching process can be improved accordingly. On the other hand, since the semiconductor wafer 5 is centrally disposed above the wafer seat 20, the plasma erosion efficiency of surrounding elements (eg, focusing rings) can be maintained uniformly, thereby prolonging the service life of these elements.

FIG. 14 shows a schematic diagram of some elements of the processing element 10b according to some embodiments of the present disclosure. Elements in the embodiment shown in FIG. 14 that are the same as those in the embodiment shown in FIG. 3 will be given the same reference numerals, and their features will not be repeated to simplify the description. In one embodiment, processing element 10b differs from processing element 10 in that processing element 10b includes a plurality of photographic assemblies, such as photographic assemblies 41b, 42b, 43b, 44b. The photographing components 41b, 42b, 43b, and 44b can each be used to generate images about the reference points P1, P2, P3, and P4 on the edge 213 of the body 21 of the wafer seat 20, and transmit the generated image data to the control module. Group 90. The images of the semiconductor wafer 5 and the wafer seat 20 are generated by the plurality of photographing elements 41b, 42b, 43b, 44b, so that the above-mentioned method S100 for manufacturing a semiconductor wafer can be applied to a processing tool for large-sized semiconductor wafers without It will be limited by the shooting angle of the camera unit.

The semiconductor wafer manufacturing system of the present disclosure generates images about the semiconductor wafer and the wafer seat by means of a camera, and determines the displacement of the lift pins for supporting the semiconductor wafer based on the images, thereby improving the relative relationship between the semiconductor wafer and the wafer. Offset problem of wafer seat body. In this way, the processing uniformity subsequently applied to the semiconductor wafer will be improved.

The foregoing outlines features or examples of several embodiments so that those skilled in the art may better understand aspects of the present disclosure. Those skilled in the art should appreciate that the present disclosure may be readily used as a basis for designing or modifying other processes and structures for carrying out the same purposes and/or achieving the same advantages of the embodiments or examples described herein. Those skilled in the art should also realize that such equivalent structures do not depart from the spirit and scope of the present disclosure, and that various changes, substitutions and alterations herein can be made without departing from the spirit and scope of the present disclosure .

1: Semiconductor Wafer Manufacturing System 2: Load port 3: Load Lock Chamber 4: Wafer carrier 5: Semiconductor wafers 51: Edge 6: Robot arm 8: Measuring room 10: Machining tools 10b: Machining tools 11: Reaction chamber 111: reaction chamber wall 112: Bottom of the reaction chamber 12: Upper electrode assembly 120: Nozzle 121: Flat electrode 122: Ring electrode 14: RF coil set 15: The first RF power supply 16: Impedance matching circuit 17: Second RF power supply 18: Plasma 20: Wafer holder 21: Ontology 211: Upper surface 212: Lower Surface 213: Edge 210: Perforation 22: Support components 221: Rod 222: Extensions 223: Lifting pin 223a: Lifting pins 2230: Top 224: Actuator (First Actuator) 225: Actuator (Second Actuator) 226: Cylinder 2261: top 227: Rough Structure 40: Photography Components 41b: Photographic Components 42b: Photographic Components 43b: Photographic Components 44b: Photographic Components 90: Control Module 91: Processor 92: memory S100: Method of Manufacturing Semiconductor Wafers S110: Operation S120: Operation S130: Operation S140: Operation S150: Operation S160: Operation S170: Operation S180: Operation C1: Center C2: Center D1: Position offset D2: Position offset D3: Position offset D4: Position offset D5: Distance D6: Distance M: video P1: Reference point P2: Reference point P3: Reference point P4: Reference point

Aspects of the present disclosure may be better understood from the following detailed description when read in conjunction with the accompanying drawings. It should be noted that in accordance with industry standard practice, various features are not drawn to scale. In fact, the dimensions of the various features may be arbitrarily increased or decreased for clarity of discussion. FIG. 1 shows a schematic diagram of a semiconductor wafer fabrication system for processing a semiconductor wafer in accordance with some embodiments of the present disclosure. FIG. 2 shows a schematic diagram of partial elements of a machining tool according to some embodiments of the present disclosure. FIG. 3 shows a top view of a wafer carrier with a semiconductor wafer placed thereon in accordance with some embodiments of the present disclosure. FIG. 4 shows a cross-sectional view of the wafer holder of FIG. 3 along the line A-A. FIG. 5A shows a schematic diagram of a lift pin according to some embodiments of the present disclosure. FIG. 5B shows a schematic diagram of a lift pin according to other embodiments of the present disclosure. FIG. 6 shows a block diagram of some components of a semiconductor wafer fabrication system in accordance with some embodiments of the present disclosure. FIG. 7 shows a flowchart of a method of fabricating a semiconductor wafer according to some embodiments of the present disclosure. FIG. 8 shows a schematic diagram of a portion of the operation of a method of fabricating a semiconductor wafer according to some embodiments of the present disclosure, wherein the lift pins are in a raised position. FIG. 9 shows a schematic diagram of part of operations of a method of fabricating a semiconductor wafer according to some embodiments of the present disclosure, wherein the semiconductor wafer is placed on lift pins by a robotic arm. FIG. 10 shows a schematic diagram of a portion of the operation of a method of fabricating a semiconductor wafer according to some embodiments of the present disclosure, wherein the semiconductor wafer is placed on the lift pins and offset from the wafer seat. FIG. 11 shows an image produced by a camera assembly according to some embodiments of the present disclosure. 12 is a schematic diagram illustrating part of operations of a method of fabricating a semiconductor wafer according to some embodiments of the present disclosure, wherein the semiconductor wafer is placed on the lift pins and centered relative to the wafer holder. FIG. 13 is a schematic diagram illustrating a portion of operations of a method of fabricating a semiconductor wafer, wherein the semiconductor wafer is placed on the upper surface of the body of the wafer holder, according to some embodiments of the present disclosure. FIG. 14 shows a schematic diagram of some elements of a processing element according to some embodiments of the present disclosure.

Domestic storage information (please note in the order of storage institution, date and number) none Foreign deposit information (please note in the order of deposit country, institution, date and number) none

S100: Method of Manufacturing Semiconductor Wafers

S110: Operation

S120: Operation

S130: Operation

S140: Operation

S150: Operation

S160: Operation

S170: Operation

S180: Operation

Claims (9)

A method of manufacturing a semiconductor wafer, comprising: moving a plurality of lift pins of a wafer holder from a lowered position to a raised position; moving a semiconductor wafer over the wafer holder and placing the semiconductor wafer on a On the lift pins at the elevated position; use a camera to generate an image of the semiconductor wafer and the wafer seat; calculate a position offset information of the semiconductor wafer according to the image, wherein the semiconductor wafer The position offset information includes a first offset between a first reference point of the wafer seat and an edge of the semiconductor wafer, a second reference point of the wafer seat and the semiconductor wafer a second offset between the edges of the wafer seat, a third offset between a third reference point of the wafer seat and the edge of the semiconductor wafer, and a fourth offset of the wafer seat a fourth offset between the reference point and the edge of the semiconductor wafer; determining whether the position offset information of the semiconductor wafer is within an acceptable range; and when the position offset information does not fall within the acceptable range When it is within the acceptance range, compare the first offset with the third offset to obtain a first reference distance, and compare the second offset with the fourth offset numerically to obtain A second reference pitch, according to the first reference pitch and the second reference pitch, a driving signal is sent to an actuator connected to the lift pin, so that the actuator drives the displacement of the lift pin, thereby changing the semiconductor chip The position of the circle relative to this wafer holder. The method for manufacturing a semiconductor wafer as claimed in claim 1, further comprising: after the actuator moves the lift pins, moving the lift pins from the lift position to the lower position; wherein in the lift position, A top end of the lift pin is located above an upper surface of a body of the wafer holder; in the descending position, the top end of the lift pin is located below the upper surface of the body. The method for manufacturing a semiconductor wafer as claimed in claim 1, further comprising: when the position offset information of the semiconductor wafer does not fall within the acceptable range, sending an alarm. The method of manufacturing a semiconductor wafer as claimed in claim 1, wherein the actuator can be displaced in at least two different directions. A semiconductor wafer manufacturing system, comprising: a body configured to carry a semiconductor wafer and having a plurality of through holes, an edge of the body has a first reference point, a second reference point, and a third reference point , and a fourth reference point, wherein the first reference point and the third reference point are the intersections from a center of the body along a first direction and the edge of the body, the second reference point and the first The four reference points are the intersections from the center of the body along a second direction and the edge of the body, the first The direction is perpendicular to the second direction; a rod is located below the main body; a plurality of lifting pins are connected to the rod and are movably arranged in the through holes; a plurality of photographic components are arranged in the main body and is configured to generate images of the first reference point, the second reference point, the third reference point, and the fourth reference point on the edge of the body, respectively, wherein the photographic elements do not overlap the a body, wherein the photographing components are configured to: calculate a first offset between the first reference point of the body and an edge of the semiconductor wafer, the second reference point of the body and the semiconductor wafer a second offset between the edges of the body, a third offset between the third reference point of the body and the edge of the semiconductor wafer, and the fourth reference point of the body and the a fourth offset between the edges of the semiconductor wafer; the first offset and the third offset are numerically compared to obtain a first reference spacing, and the second offset and The fourth offset is numerically compared to obtain a second reference distance; a first actuator is connected to the rod and configured to control the displacement of the rod in a vertical direction; a plurality of second coincidences actuators, respectively connected to the lift pins and configured to control the displacement of the lift pins in a horizontal direction; and a control module, electrically connected to the photography components and the second actuator, wherein The control module sends a control signal to the second actuator according to the first reference distance and the second reference distance generated by the photographing elements, and The second actuator controls the displacement of the lift pins in the horizontal direction according to the control signal. The semiconductor wafer manufacturing system of claim 5, wherein a top of the lift pin has a rough structure, and the rough structure is in direct contact with the semiconductor wafer. The semiconductor wafer fabrication system of claim 5, wherein the second actuators are used to control displacements of the lift pins in two vertical components in the horizontal direction. The semiconductor wafer fabrication system as claimed in claim 5, wherein the control module is electrically connected to each of the camera elements, and sends the control signal to the second actuation according to the images generated by the camera elements device. The semiconductor wafer manufacturing system of claim 5, wherein a ratio of the width of the lift pin to the width of the through hole is between 0.25 and 0.75.

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