TWI768377B - Method of generating packing solution of printed circuit board - Google Patents

Abstract

A method of generating packing solution of printed circuit board (PCB) comprises: obtaining a plurality of component files, a first constraint file, and a second constraint file, wherein each of the component files corresponds to a electrical component, the first constraint file corresponds to a signal-PCB, and the second constraint file corresponds to a multiple-PCB; performing a genetic algorithm to generate a plurality of single-PCB solutions according to the plurality of component files and the first constraint files, wherein each of the single-PCB solutions comprises a shape description, selectively performing a concave hull algorithm to update the shape description, after updating the shape description, performing the genetic algorithm to generate a multiple-PCB solution according to the plurality of single-PCB solutions and the second constraint file.

Description

Method of producing a printed circuit board assembly scheme

The present invention relates to a printed circuit board, in particular to a method for combining components and boards of a printed circuit board.

In the Printed Circuit Board (PCB) manufacturing industry, independent electronic components and substrates are assembled into multiple single-PCBs (single-PCBs), and then these PCBs are assembled into a larger PCB Composite board (multiple-PCB). Minimizing the area of the PCB is critical to manufacturing costs.

However, minimizing the PCB area in the prior art requires a lot of manpower. Testers first try different PCB layout combinations, export the PCB layout results, and then verify whether the results are smaller, which will take a lot of time and labor costs.

In view of this, the present invention proposes a method for generating a printed circuit board assembly solution, thereby solving the above problems.

A method for generating a printed circuit board assembly solution according to an embodiment of the present invention includes: obtaining a plurality of component files, a first constraint file and a second constraint file, wherein each component file corresponds to an electronic component, and the first constraint file Corresponding to a single printed circuit board, the second constraint file corresponds to a printed circuit composite board; according to these component files and the first constraint file, a genetic algorithm is performed to generate a plurality of single board feasible solutions, each single board feasible solution has a shape description; selectively execute the concave hull algorithm to update the shape description according to each veneer feasible scheme; after executing the concave hull algorithm according to each veneer feasible scheme to update the shape description, The constraint file executes a genetic algorithm to generate a composite panel assembly plan.

The method of generating a printed circuit board assembly scheme proposed by the present invention can handle combinations with arbitrary component shapes and conform to physical constraints such as board-level, copper wire, and the like. The invention can encapsulate the components into the PCB, and make the PCB area as small as possible or the utilization rate of the PCB area as large as possible. The present invention proposes to use a bottom-up approach and genetic algorithm based optimization to reduce the effort and time required to produce good PCB packaging results. The present invention not only reduces the search space of feasible assembly solutions, but also greatly reduces the computation time. Therefore, the present invention can achieve a near-optimal solution in a short time.

The above description of the present disclosure and the following description of the embodiments are used to demonstrate and explain the spirit and principle of the present invention, and provide further explanation of the scope of the patent application of the present invention.

The detailed features and advantages of the present invention are described in detail below in the embodiments, and the content is sufficient to enable any person skilled in the relevant art to understand the technical content of the present invention and implement it accordingly, and according to the content disclosed in this specification, the scope of the patent application and the drawings , any person skilled in the related art can easily understand the related objects and advantages of the present invention. The following examples further illustrate the viewpoints of the present invention in detail, but do not limit the scope of the present invention in any viewpoint.

The method for generating a printed circuit board assembly scheme proposed by the present invention is used to assemble a plurality of electronic components into one or more printed circuit single boards, and then assemble the one or more printed circuit single boards into a printed circuit composite board. Electronic components may be non-convex and have holes. Electronic components can be rotated when assembled, but only in a limited set of directions, such as 90 degrees.

Please refer to FIG. 1 , which is a flowchart according to an embodiment of the present invention.

Step S1 is "acquiring the component file, the first constraint file and the second constraint file". Each component file corresponds to an electronic component (hereinafter referred to as component). "Getting multiple component files" is equivalent to determining the set of components that can be assembled.

The first constraint file corresponds to a single printed circuit board, and the second constraint file corresponds to a printed circuit composite board. For example: the first constraint file includes the maximum dimension of the printed circuit board. If the size of the printed circuit board is rectangular, the maximum dimension includes the length or width of the printed circuit board. The second constraint file includes the minimum side length of the printed circuit composite board and the maximum number of printed circuit single boards that can be arranged on a printed circuit composite board, that is, the number of panels. It should be noted that the contents of the first and second constraint files are not limited to the above examples. For example, the break-away size or the number of tooling holes can be defined in the first and second constraint files.

Please refer to FIG. 2 , which is a detailed flowchart shown in step S1 of FIG. 1 according to "acquiring a component file".

Step S11 is "obtaining boundary data and constraint data". For example, boundary data and constraint data are stored in Drawing Exchange Format (DXF) files. A DXF file records the appearance information of a component (ie boundary data) and assembly constraints (ie constraint data).

Step S13 is "update the boundary data as the component file according to the constraint data". Please refer to FIG. 3 , which is a schematic diagram of a plurality of components C1 ˜ C10 . As shown in Figure 3, the components are not necessarily simple polygons because they contain additional constraint data, such as PCB labels or copper conductors. If the original boundary data of the component, such as the outer frame B1 of the component C1 in FIG. 3 , is directly used as the input of the subsequent steps, the result of the assembly will not be available.

Therefore, for the DXF file obtained in step S11, step S13 performs preprocessing, and after extracting the original boundary data from the DXF file, the dxf2svg program is used to convert the boundary data into a Scalable Vector Graphics (SVG) file. Then use Javascript to read the boundary data in the document object model (Document Object Model, DOM) in the SVG file, and generate the layout boundary as the component file according to the constraint data related to the size of the component. The layout boundary is the boundary data updated according to the constraint data of the component. As shown in FIG. 3 , the boundary data of the DXF file of the component C1 corresponds to the outer frame B1 , and the boundary data updated in the SVG file (component file) according to the constraint data corresponds to the outer frame B2 .

Referring back to FIG. 1 , step S3 is “execute the genetic algorithm according to the component file and the first constraint file to generate a feasible solution for the single board”. In an embodiment of the present invention, a bottom-up two-stage genetic algorithm is used. Step S3 is the genetic algorithm of the first stage. For example, a chromosome is a number of randomly encoded elements, the population size is the output number of a single-PCB feasible solution, and the mutation rate is the bits in the encoding that are replaced probability. Single-board options represent possible options for assembling multiple components into a single printed circuit board.

In the process of executing the genetic algorithm, each element is sequentially assembled according to its coded value to generate a preliminary assembly plan of the single board. The parameters of each progeny (preliminary assembly scheme of veneer) are calculated with the fitness function. According to the calculation results and the preset threshold values of these parameters, a better offspring is selected as a feasible solution for the single board, and the next iteration is performed, and a new assembly sequence or a new assembly rule is generated. Between each iteration, the genetic algorithm adjusts the conditions for component assembly, such as the order of assembly or the angle of rotation for placement on the substrate. The conditions for the termination of the genetic algorithm are, for example, reaching a specified number of iterations, convergence of the fitness value output by the fitness function, or reaching a specified threshold value. The dimensions of the fitness function (evaluation parameters) include: the minimum space between elements; the curve tolerance, that is, the maximum error allowed by the linear approximation of the Bézier curve to the arc, in SVG units or in pixels, Decrease this value if the curved sections appear to overlap slightly; and the number of rotations of the element, which may be evaluated for each element, e.g. 4 rotations when taking a 90-degree rotation of the element, larger values improve results but converge slower.

Please refer to FIG. 4 , which is a schematic diagram according to step S3 of FIG. 1 . On the left of FIG. 4 are elements C11 , C12 and C13 . The right side of FIG. 4 is the single-board feasible solutions Q1 , Q2 and Q3 generated after step S3 is executed. In the example of FIG. 4 , the available number of each element C11 - C13 is one, but the present invention is not limited to this.

Please refer to FIG. 5 , which is a detailed flowchart shown in step S3 of FIG. 1 . For example, start with the component with the smallest code value, assemble it on the substrate, and then assemble the component with the second smallest code value next to the component with the smallest code value. In the assembling process, step S31 and step S33 are further included.

Step S31 is "generate the first shape with the NFP algorithm according to the component file". For example, component files corresponding to two components are selected, and an NFP (no-fit polygon) algorithm is run to generate the first shape according to the layout boundaries described by the two component files as input data. The first shape is a non-overlapping possible assembled shape containing the two elements. In detail, given two convex polygons A and B and their respective reference vertices _RA and _RB , the NFP algorithm can output a polygon NFP _{A, B} . To be more specific, _RA is fixed at the origin, and a point on the outer circumference of B is in contact with and goes around the circumference of A. At this time, the shape drawn by RB is NFP _{A, B .} The present invention does not limit the NFP algorithm used to generate the first shape.

Step S33 is "generate a first arrangement scheme according to the first shape". Since NFP _{A, B} includes multiple arrangement candidates of element A and element B, one or more of these arrangement candidates will be selected as the first arrangement scheme in a random manner, for example, when the genetic algorithm is executed. Applying the NFP algorithm can quickly generate a first arrangement in which the two elements are closely connected to each other.

Step S35 is "selectively keep the first arrangement scheme as one of the feasible schemes for the single board according to the first constraint file". In detail, according to a plurality of rules defined in the first constraint file, the genetic algorithm retains the first permutation scheme after evaluation. Each time an iteration is completed, the adaptation function of the genetic algorithm will evaluate whether to retain the first arrangement scheme generated this time as a feasible scheme for the single board according to the aforementioned multiple parameters. According to a preset number of generations, the genetic algorithm can generate multiple feasible solutions for a single board.

Step S5 is "execute the concave hull algorithm to update the feasible solution of the single board". When the feasible solution of the single board generated in step S3 has a non-convex shape, this step S5 will be selectively executed.

In detail, each veneer possible solution has a shape description. According to the feasible solutions of each single board generated in step S3, this step S5 executes a concave hull algorithm to update the shape description. The shape description records the way each component is spliced together in the veneer's possible solutions and the shape of the printed circuit veneer. Please refer to FIG. 6 , which is a schematic diagram of the input shape before the execution of step S5 and the output of the input shape after the execution. As shown in FIG. 5 , D1 is the shape of the printed circuit board, and D2 is the shape of the printed circuit board updated after executing the concave shell algorithm according to D1. As a control, D3 is the shape obtained by performing a convex hull algorithm on D1.

As shown in FIG. 6 , the shape of D1 is relatively irregular. If D1 is used as a unit for assembling the printed circuit composite board, it may increase the difficulty of executing the genetic algorithm in the second stage. Therefore, the present invention performs a concave hull algorithm to generate a shape D2 that contains D1 and is easy to assemble. Compared with D3, which directly converts D1 into a convex polygon, D2 can save the area without components on the substrate, that is, improve the utilization rate of the substrate and avoid the waste of space. It should be noted that the present invention does not specifically limit which concave hull algorithm is adopted.

In one embodiment, the radius parameter of the concave hull algorithm is twice the length of all short sides in the shape description. In general, any concave hull algorithm requires a radius parameter. The smaller the radius parameter, the closer the resulting concave hull is to the original shape. However, the smaller the radius parameter, the more difficult the subsequent assembly will be. To overcome this problem, the present invention uses a linear approximation to generate a representative long side L0 from the shape description. The long side L0 corresponds to the skeleton of the shape D1. The long side L0 will be forced to be cut into multiple short sides that are connected to each other (L1~L5 in Figure 6). The radius parameter to be set in the concave shell algorithm is set to the length of these short sides L1~L5. double. However, the present invention is not limited to the figures exemplified above. In practice, considering the utilization rate of the substrate or the degree of influence when the electronic components are arranged in the central part of the concave shell, the size of the radius parameter or its ratio relative to the short side can be adjusted adaptively.

In one embodiment, after the above-mentioned plurality of short sides L1 to L5 are obtained, step S3 may be returned to modify the rules for arranging elements in step S3 by the genetic algorithm. For example, if the elements C14 - C18 (not shown) are included on the short side L1 , in the iteration of step S3 , the arrangement scheme formed by the elements C14 - C18 can be fixed. Through the above correction steps, after the genetic algorithm of the first stage is completed, the number of feasible solutions for the veneer with the concave shell shape can be reduced. Generally speaking, convex polygons are easier to assemble than concave polygons. Therefore, returning to step S3 for correction according to the result of the concave hull algorithm in step S5 is expected to improve the execution efficiency of the genetic algorithm in the second stage.

Step S7 is "execute the genetic algorithm according to the feasible plan of the single board and the second constraint file to generate the assembly plan of the composite board". After step S5 "execute the concave hull algorithm to update the shape description according to each veneer feasible solution". Step S7 is the second-stage genetic algorithm. The operation of this step S7 is similar to that of step S3, the difference is that the input data of step S7 is a feasible solution for a single board, and the output data is a composite board assembly solution.

Please refer to FIG. 6 , which is a schematic diagram according to step S7 of FIG. 1 . On the left side of Figure 6, there are single-board feasible solutions Q1 and Q2. On the right side of FIG. 6 , the first two composite board assembly schemes R1 and R2 generated after the execution of step S7 are included.

In the second constraint file, the maximum number of PCB single boards that can be accommodated in the PCB composite board can be set. In the example shown in FIG. 6 , the maximum number is set to 4. Thus, the Genetic Algorithm can generate three combinations: Q1 uses 1 and Q2 uses 3, Q1 uses 3 and Q2 uses 1, or Q2 uses 4. The foregoing numbers are illustrative only and not intended to limit the present invention.

Please refer to FIG. 8 , which is a detailed flowchart shown in step S7 of FIG. 1 . Step S71 is "generate the second shape according to the component file using the NFP algorithm", step S73 is "generate the second arrangement scheme according to the second shape", and step S75 is "selectively retain the second scheme according to the second constraint file" or composite panel assembly plan”. Steps S71 to S75 can be implemented by adaptive modification with reference to steps S31 to S35, and the description is not repeated here in the present invention.

Please refer to FIG. 9 , which is a flowchart according to another embodiment of the present invention. Steps S1 to S7 in this other embodiment are basically the same as those in the previous embodiment, and are not repeated here.

In another embodiment, the method for generating a printed circuit board assembly scheme further includes steps S8 and S9 after step S7.

Step S8 is "acquiring corresponding constraint data according to the component file in the composite board assembly plan". Specifically, in the printed circuit board layout stage, in addition to using the composite board assembly scheme generated in step S7, it is also necessary to refer to the constraint data of each component. Therefore, when the SVG component file is output and the constraint data is deleted in step S13, the deleted content needs to be additionally recorded, and then when this step S8 is executed, the deleted content is restored to the corresponding component.

Step S9 is "outputting the drawing interchange format file". Export the DXF file after restoring the deleted constraint data for each component in the composite board assembly scheme for use in the layout stage.

Please refer to FIG. 10 , which is a flowchart according to another embodiment of the present invention. Steps S1 ˜ S3 and S5 ˜ S9 in this other embodiment are basically the same as those in the previous embodiment, and will not be repeated here. In yet another embodiment, the method for generating a printed circuit board assembly scheme further includes: step S4 after step S3 and before step S5.

Step S4 is "selectively delete the feasible solution of the board according to the third constraint file". In detail, in order to speed up the subsequent encapsulation process and reduce the solution space for finding feasible solutions, the present invention allows to be interrupted at the end of the first stage, and to load the specified third constraint file, delete the third A single-board feasible solution to the rules defined in the constraint file. For example, the number of resistors on a single board defined in the third constraint file should be less than 100. Therefore, feasible solutions for boards with a total number of resistors that violate this constraint will be removed. This step S4 can speed up the execution speed of step S7. For another example, the upper limit of the weight of components on a single board is defined in the third constraint file. This constraint can avoid the risk of excessively heavy components falling off due to re-melting of solder paste when passing through a reflow oven. The heat absorption coefficient of the element can also be defined in the third constraint file. Generally speaking, the constraint rules defined in the third constraint file are related to the non-shape-related parameters that the component needs to consider during the actual assembly.

The method of generating a printed circuit board assembly scheme proposed by the present invention can handle combinations with arbitrary component shapes and conform to physical constraints such as board-level, copper wire, and the like. The invention can encapsulate the components into the PCB, and make the PCB area as small as possible or the utilization rate of the PCB area as large as possible. The present invention proposes to use a bottom-up approach and genetic algorithm based optimization to reduce the effort and time required to produce good PCB packaging results. The present invention not only reduces the search space of feasible assembly solutions, but also greatly reduces the computation time. Therefore, the present invention can achieve a near-optimal solution in a short time.

Although the present invention is disclosed in the foregoing embodiments, it is not intended to limit the present invention. Changes and modifications made without departing from the spirit and scope of the present invention belong to the scope of patent protection of the present invention. For the protection scope defined by the present invention, please refer to the attached patent application scope.

S1~S9: Steps S11~S13: Steps S31~S35: Steps S71~S75: Steps C1~C10: Electronic components Q1~Q3 Board Feasible Solutions L0: Long side L1~L5: Short side B1: Boundary information of DXF file B2: Boundary information of SVG file R1, R2: Composite board assembly scheme

FIG. 1 is a flowchart according to an embodiment of the present invention; FIG. 2 is a detailed flow chart according to step S1 of FIG. 1 ; Figure 3 is a schematic diagram of a plurality of electronic components FIG. 4 is a schematic diagram according to step S3 of FIG. 1 ; FIG. 5 is a detailed flow chart according to step S3 of FIG. 1 ; FIG. 6 is a schematic diagram according to step S5 of FIG. 1 ; FIG. 7 is a schematic diagram according to step S7 of FIG. 1 ; FIG. 8 is a detailed flow chart according to step S7 of FIG. 1 ; FIG. 9 is a flowchart according to another embodiment of the present invention; and FIG. 10 is a flowchart according to another embodiment of the present invention.

S1~S7: Steps

Claims (10)

A method for generating a printed circuit board assembly scheme, comprising: obtaining a plurality of component files, a first constraint file and a second constraint file, wherein each component file corresponds to an electronic component, and the first constraint file corresponds to a printed circuit board a circuit board, the second constraint file corresponds to a printed circuit composite board; a genetic algorithm is executed according to the component files and the first constraint file to generate a plurality of single-board feasible solutions, each of the single-board feasible solutions has a shape description; selectively executing a concave hull algorithm to update the shape description according to each of the veneer feasible solutions; and executing the concave hull algorithm to update the shape description according to each of the veneer feasible solutions Then, the genetic algorithm is executed according to the feasible solutions of the single board and the second constraint file to generate a composite board assembly solution. The method for generating a printed circuit board assembly plan as claimed in claim 1, wherein executing the genetic algorithm to generate the single-board feasible plans according to the component files and the first constraint file comprises: according to the component files, to An NFP (no-fit polygon) algorithm generates a first shape of one of the component files; generates a first arrangement scheme according to the first shape with the genetic algorithm; and according to the first constraint file, to The genetic algorithm selectively retains the first arrangement plan shape as one of the veneer feasible plans. The method for generating a printed circuit board assembly plan according to claim 2, wherein executing the genetic algorithm to generate the composite board assembly plan according to each of the single-board feasible plans and the second constraint file comprises: according to each of the some single-board feasible solutions, using the NFP algorithm to generate one of the second shapes of the single-board feasible solutions; using the genetic algorithm to generate a second arrangement plan according to the second shape; and according to the second constraint file, and the second arrangement scheme is selectively reserved as the composite board assembly scheme by the genetic algorithm. The method for generating a printed circuit board assembly plan as claimed in claim 1, wherein obtaining the component files, the first constraint file and the second constraint file comprises: obtaining a boundary data and a constraint data, wherein the boundary data and The constraint data all correspond to the electronic component; and according to the constraint data, the boundary data is updated as one of the component files. The method of generating a printed circuit board assembly scheme of claim 4, wherein the boundary data and the constraint data are stored in a drawing interchange format file, and each of the component files is a scalable vector graphics file. The method for generating a printed circuit board assembly plan according to claim 4, wherein after executing the genetic algorithm to generate the composite board assembly plan according to the single-board feasible plans and the second constraint file, further comprising: according to the For the component files in the composite board assembly plan, obtain the constraint data corresponding to each of the component files; and A drawing exchange format file is output, the drawing exchange format file includes the constraint data and the assembly plan of the composite board. The method of generating a printed circuit board assembly scheme of claim 4, wherein the constraint data includes printed circuit board labels and copper conductors. The method for generating a printed circuit board assembly solution as claimed in claim 1, wherein the first constraint file includes the maximum dimension and quantity of the printed circuit single board, and the second constraint file includes the minimum side length of the printed circuit composite board. The method for generating a printed circuit board assembly solution as claimed in claim 1, wherein the shape description has a long side for representing a shape of a possible solution of the single board, the long side includes a plurality of short sides, and the concave shell is calculated The method has a plurality of radius parameters, and each of the radius parameters is associated with each of the short side lengths. The method for generating a printed circuit board assembly solution as claimed in claim 1, wherein after executing the genetic algorithm according to the component files and the first constraint file to generate a feasible solution including the single boards, and according to each Before executing the concave hull algorithm to update the shape description for the single-board feasible solutions, the method further includes: selectively deleting one of the single-board feasible solutions according to a third constraint file.

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