TWI767793B - Glitch filtering circuit and microcontroller circuit - Google Patents

Abstract

A glitch filtering circuit including a comparing circuit and a signal processing circuit is provided. The comparing circuit compares a specific signal and a reference signal to generate an output signal. The signal processing circuit detects a control signal. When the level of the control signal is a turn-on level, the signal processing circuit enters a monitoring mode. In the monitoring mode, the signal processing circuit serves the output signal as a trigger signal. When the level of the control signal is not the turn-on level, the signal processing circuit exits the monitoring mode and stops serving the output signal as the trigger signal.

Description

Surge filter circuit and micro-control circuit

The present invention relates to a surge filtering circuit, in particular to a circuit for filtering surges according to an internal control signal.

With the advancement of technology, there are more and more types and functions of electronic devices. In electronic devices, there are usually many MOS switches. When the MOS switch is turned on instantaneously, it may cause a large current, which will cause a surge and cause the circuit to malfunction.

An embodiment of the present invention provides a surge filtering circuit, which includes a comparison circuit and a signal processing circuit. The comparison circuit compares a specific signal with a reference signal to generate an output signal. The signal processing circuit detects the level of a control signal. When the level of the control signal is equal to a turn-on level, the signal processing circuit enters a monitoring mode. In the monitoring mode, the signal processing circuit uses the output signal as a trigger signal. When the level of the control signal is not equal to the turn-on level, the signal processing circuit leaves the monitoring mode and stops using the output signal as a trigger signal.

The present invention further provides a micro-control circuit, which includes a surge filtering circuit and a control circuit. The surge filtering circuit includes a comparison circuit and a signal processing circuit. The comparison circuit compares a signal with a reference signal to generate an output signal. The signal processing circuit detects the level of a control signal. When the level of the control signal is equal to a turn-on level, the signal processing circuit enters a monitoring mode. In the monitoring mode, the signal processing circuit uses the output signal as a trigger signal. When the level of the control signal is not equal to the turn-on level, the signal processing circuit leaves the monitoring mode and stops using the output signal as a trigger signal. The control circuit generates a driving signal for driving a load. When the level of the trigger signal changes, the control circuit performs a specific action until a release event occurs.

In order to make the objects, features and advantages of the present invention more obvious and easy to understand, the following specific embodiments are given and described in detail in conjunction with the accompanying drawings. The present specification provides different embodiments to illustrate the technical features of different embodiments of the present invention. Wherein, the configuration of each element in the embodiment is for illustration, and not for limiting the present invention. In addition, parts of the reference numerals in the drawings in the embodiments are repeated for the purpose of simplifying the description, and do not mean the correlation between different embodiments.

FIG. 1A is a schematic diagram of the surge filtering circuit of the present invention. As shown in the figure, the surge filtering circuit 100 includes a comparison circuit 110 and a signal processing circuit 120 . The comparison circuit 110 compares a signal SP with a reference signal SN to generate an output signal SO. In a possible embodiment, both the signal SP and the reference signal SN are voltage signals. In a possible embodiment, the level change of the signal SP is related to the sensing result of a temperature sensor (not shown). In other embodiments, at least one of the signal SP and the reference signal SN is generated by a signal generating circuit (not shown). The signal generating circuit may be integrated into or outside the surge filtering circuit 100 . In some embodiments, the reference signal SN is continuously maintained at a fixed level. In this example, when the level of the signal SP changes, the level of the reference signal SN is fixed. The present invention does not limit the structure of the comparison circuit 110 . In a possible embodiment, the comparison circuit 110 is an analog comparator 111 .

The signal processing circuit 120 receives a control signal SC, and provides a trigger signal ST according to the control signal SC. For example, when the level of the control signal SC is equal to a turn-on level (eg, a high level), the signal processing circuit 120 enters a monitoring mode. In the monitoring mode, the signal processing circuit 120 uses the output signal SO as the trigger signal ST. When the level of the control signal SC is not equal to the turn-on level, the signal processing circuit 120 leaves the monitoring mode and stops using the output signal SO as the trigger signal ST. In a possible embodiment, the signal processing circuit 120 sets the trigger signal ST to a low level. The present invention does not limit the type of the control signal SC. In some embodiments, the control signal SC may be a pulse width modulation (PWM) signal.

FIG. 1B is an operation timing chart of the surge filtering circuit of the present invention. When the level of the signal SP is greater than that of the reference signal SN, the output signal SO is at a high level. When the level of the signal SP is lower than that of the reference signal SN, the output signal SO is at a low level. In this embodiment, when the control signal SC is at an on level (eg, a high level), the level of the trigger signal ST is equal to the level of the output signal SO. When the control signal SC is not at the turn-on level, the trigger signal ST is at a low level. At this time, even if the level of the output signal SO greatly changes and causes a surge due to the level of the signal SP, the trigger signal ST is still at a low level and will not be affected by the boosting or decreasing of the signal SP.

FIG. 1C is another schematic diagram of the surge filtering circuit of the present invention. FIG. 1C is similar to FIG. 1A except that the surge filtering circuit 100 of FIG. 1C further includes a selection circuit 130 . The selection circuit 130 selectively uses one of the external signal EXT1 and the signal EXT2 as the control signal SC. The present invention does not limit the structure of the selection circuit 130 . In a possible embodiment, the selection circuit 130 is a multiplexer 131 . When the enable signal en1 is at a specific level (eg, a low level), the multiplexer 131 provides the external signal EXT1 to the signal processing circuit 120 . When the enable signal en1 is not at a specific level, the multiplexer 131 provides the signal EXT2 to the signal processing circuit 120 . In some embodiments, at least one of the external signal EXT1 and the signal EXT2 is a pulse width modulated signal.

The present invention does not limit the application field of the surge filtering circuit 100 . Since the trigger signal ST provided by the surge filtering circuit 100 is not affected by the sudden rise or fall of the signal SP, a stable trigger signal ST can be provided to any control circuit. In a possible embodiment, the surge filtering circuit 100 may be integrated into a microcontroller circuit, such as a microcontroller unit (MCU), together with at least one control circuit.

FIG. 2A is a schematic diagram of the micro-control circuit of the present invention. As shown in the figure, the micro-control circuit 200A includes a surge filtering circuit 210A and a control circuit 220A. The surge filtering circuit 210A compares the signal SP with the reference signal SN, and sets the level of the trigger signal ST according to the control signal SC. In this embodiment, the control signal SC is provided by the control circuit 220A. Since the micro-control circuit 200A does not need to receive control signals from the outside through the input and output pins, the number of pins of the micro-control circuit 200A can be reduced.

In another possible embodiment, the microcontroller circuit 200A further includes an input and output pin P1. The input/output pin P1 is used for receiving the signal SP. In this example, the signal SP is an external signal generated by a circuit outside the microcontroller circuit 200A. In other embodiments, the microcontroller circuit 200A further includes an input and output pin N1. The input and output pin N1 is used for receiving the reference signal SN. In this example, the reference signal SN is generated by a circuit outside the microcontroller 200A. In some embodiments, the microcontroller circuit 200A has a signal generating circuit (not shown) for providing the reference signal SN. In this example, the microcontroller circuit 200A does not need to use the input/output pin N1 to receive the reference signal SN.

The surge filtering circuit 210A includes a comparison circuit 211 and a signal processing circuit 212 . The comparison circuit 211 compares the signal SP and the reference signal SN to generate the output signal SO. Since the characteristics of the comparison circuit 211 are similar to those of the comparison circuit 110 in FIG. 1A , detailed descriptions are omitted. In this embodiment, the signal processing circuit 212 generates the trigger signal ST according to the control signal SC and the output signal SO. Since the characteristics of the signal processing circuit 212 are similar to those of the signal processing circuit 120 in FIG. 1A , detailed descriptions are omitted.

The control circuit 220A provides the control signal SC, and determines whether to execute a specific action according to the trigger signal ST. For example, when the level of the trigger signal ST does not change (eg, it is maintained at a specific level, such as a low level), the control circuit 220A does not perform a specific action. In a possible embodiment, the control circuit 220A generates the driving signal SD for driving a load 202 . However, when the level of the trigger signal ST changes, the control circuit 220A performs a specific action. At this time, the control circuit 220A may stop generating the driving signal SD. Therefore, the load 202 stops operating. In a possible embodiment, when a release event occurs, the control circuit 220A stops performing the specific action. Therefore, the control circuit 220A may provide the driving signal SD again. Therefore, the load 202 operates again. In this example, the duty cycle of the new drive signal may be different from the duty cycle of the previous drive signal. The present invention does not limit the type of the load 202 . In one possible embodiment, the load 202 is a motor.

The present invention does not limit the kind of specific actions. In a possible embodiment, the specific action refers to that the control circuit 220A stops generating the driving signal SD. Therefore, the load 202 stops operating. In this example, when the control circuit 220A does not perform a specific action, the control circuit 220A generates the driving signal SD for driving the load 202 . In another possible embodiment, the specific action refers to that the control circuit 220A generates the driving signal SD for driving the load 202 . In this example, when the control circuit 220A does not perform a specific action, the control circuit 220A stops generating the driving signal SD. Therefore, the load 202 stops operating.

The present invention does not limit the type of the cancellation event. In a possible embodiment, the user can know whether the control circuit 220A performs a specific action according to the operation of the load 202 . In this example, the user may instruct the control circuit 220A to stop executing a specific action through software or hardware. For example, assume that a particular action means that the control circuit 220A stops driving the load. In this example, when the user finds that the load 202 stops operating, the user may start a software to instruct the control circuit 220A to stop executing a specific action. Therefore, the control circuit 220A regenerates the drive signal SD. In another possible embodiment, the control circuit 220A detects the level of a specific signal (not shown). When the level of the specific signal is equal to a specific level, it indicates that a release event occurs. Therefore, the control circuit 220A stops performing the specific action, and generates the drive signal SD again. In some embodiments, the microcontroller circuit 200A further includes an input and output pin (not shown) for receiving the specific signal.

The present invention does not limit the structure of the control circuit 220A. In a possible embodiment, the control circuit 220A is a pulse width modulation circuit. In this example, the PWM circuit generates a first PWM signal and a second PWM signal. The pulse width modulation circuit uses the first pulse width modulation signal as the control signal SC, and the second pulse width modulation signal as the driving signal SD. In other embodiments, the control circuit 220A may be an analog-to-digital converter (ADC) or a direct memory access circuit (DMA). In this example, when the level of the trigger signal ST does not change (eg, it is maintained at a specific level, eg, a low level), the control circuit 220A does not operate. However, when the level of the trigger signal ST changes, the control circuit 220A performs a specific action. For example, if the control circuit 220A is an analog-to-digital converter, when the level of the trigger signal ST changes, the control circuit 220A converts the analog-to-digital signal into a digital signal. If the control circuit 220A is a direct memory access circuit, when the level of the trigger signal ST changes, the control circuit 220A performs a data transfer operation. Since the trigger signal ST is not affected by the instantaneous rise or fall of the level of the signal SP, the control circuit 220A drives the load 202 stably.

FIG. 2B is another schematic diagram of the micro-control circuit of the present invention. As shown in the figure, the micro-control circuit 200B includes input and output pins P1, N1, and PIN, a surge filtering circuit 210B, and a control circuit 220B. The input/output pin P1 is used for receiving the signal SP. The input and output pin N1 is used for receiving the reference signal SN. The input/output pin PIN is used to receive an external signal EXT1. In some embodiments, at least one of the signal SP and the reference signal SN is generated by other circuits (not shown) within the microcontroller circuit 200B. In this example, the microcontroller 200B does not need to set at least one of the input and output pins P1 and N1.

In this embodiment, the surge filtering circuit 210A includes a comparison circuit 211 , a signal processing circuit 212 and a selection circuit 213 . The comparison circuit 211 compares the signal SP with the reference signal SN to generate an output signal SO. The signal processing circuit 212 receives the output signal SO, and determines whether to use the output signal SO as the trigger signal ST according to the control signal SC. The selection circuit 213 uses the external signal EXT1 or the signal EXT2 as the control signal SC according to an enable signal en1.

Since the characteristics of the comparison circuit 211 , the signal processing circuit 212 and the selection circuit 213 are similar to those of the comparison circuit 211 , the signal processing circuit 212 of FIG. 1A and the selection circuit 130 of FIG. 1C , they will not be described again. Since the selection circuit 130 selects the signal EXT1 outside the microcontroller circuit 200B or the signal EXT2 in the microcontroller circuit 200B according to the enable signal en1, the design flexibility of the surge filtering circuit 210B can be improved. In this embodiment, the signal EXT2 is provided by the control circuit 220B. Since the characteristics of the control circuit 220B are similar to the characteristics of the control circuit 220A in FIG. 2A , detailed descriptions are omitted.

FIG. 2C is a timing control diagram of the control circuit of the present invention. The symbol SD_ori represents a preset drive signal SD. When the level of the trigger signal ST does not change, the level of the driving signal SD is the same as the preset signal SD_ori. In the period T211, since the level of the trigger signal ST does not change, the level of the driving signal SD is the same as the preset signal SD_ori. In the period T212, the level of the trigger signal ST changes. At this time, since the control circuit 220A stops providing the driving signal SD, the level of the driving signal SD is different from the preset signal SD_ori. At this time, the driving signal SD may be maintained at a specific level (eg, a low level). At the time point T213, since a release event occurs, the control circuit 220A provides the driving signal SD again. Therefore, the level of the driving signal SD is the same as the preset signal SD_ori. During the period T214, since the level of the trigger signal ST does not change, the level of the drive signal SD of the control circuit 220A is the same as the preset signal SD_ori.

FIG. 3 is another schematic diagram of the micro-control circuit of the present invention. As shown in the figure, the micro-control circuit 300 includes input and output pins P1 and N1 , a surge filtering circuit 310 , a selection circuit 320 , and control circuits 330 and 340 . The surge filtering circuit 310 generates the trigger signal ST according to the voltage levels on the input and output pins P1 and N1 and the control signal SC. In other embodiments, the surge filtering circuit 310 compares the voltage levels of two signals inside the microcontroller circuit 300 to generate an output signal, and determines whether to use the output signal as the trigger signal ST according to the control signal SC. Since the characteristics of the surge filtering circuit 310 are similar to the characteristics of the surge filtering circuit 100 in FIG. 1A , the details are not repeated here.

The selection circuit 320 provides the trigger signal ST to the control circuit 330 or 340 according to an enable signal en2. The present invention does not limit the structure of the selection circuit 320 . In a possible embodiment, the selection circuit 320 is a multiplexer. In this example, when the enable signal en2 has a specific level (eg, a low level), the selection circuit 320 outputs the trigger signal ST to the control circuit 330 . However, when the enable signal en2 does not have a specific level, the selection circuit 320 outputs the trigger signal ST to the control circuit 340 .

In this embodiment, the control circuit 330 performs a first specific action, such as driving the load 302, according to the trigger signal ST, and the control circuit 340 performs a second specific action, such as driving the load 304, according to the trigger signal ST. The present invention does not limit the types of the control circuits 330 and 340 . The control circuits 330 and 340 may be the same type of circuits, such as pulse width modulation circuits. In other embodiments, the type of control circuit 330 is different from the type of control circuit 340 . For example, the control circuit 330 is a pulse width modulation circuit, and the control circuit 340 is an analog-to-digital converter.

In this embodiment, the control signal SC is provided by the control circuit 330 . In this example, even if the control circuit 330 does not receive the trigger signal ST, the control circuit 330 continues to generate the control signal SC. The present invention does not limit the number of control circuits. In other embodiments, the microcontroller circuit 300 has more control circuits. In this example, the selection circuit 320 may provide the trigger signal ST to one of the plurality of control circuits according to more enable signals.

FIG. 4 is another schematic diagram of the micro-control circuit of the present invention. The micro-control circuit 400 includes input and output pins P1 ˜ P3 , N1 ˜ N3 , surge filtering circuits 410 , 430 , and 450 , and control circuits 420 , 440 , and 460 . The surge filtering circuits 410 , 430 and 450 are coupled to corresponding input and output pins. Since the operations of the surge filtering circuits 410 , 430 and 450 are similar, only the surge filtering circuit 410 will be described below. In this embodiment, the surge filtering circuit 410 compares the levels of the input and output pins P1 and N1, and provides the trigger signal ST1 according to the comparison result and the control signal SC1. In other embodiments, the surge filtering circuit 410 compares the voltage levels of the two signals inside the microcontroller 400 to generate an output signal, and determines whether to use the output signal as the trigger signal ST1 according to the control signal SC1. Since the characteristics of the surge filtering circuit 410 are similar to the characteristics of the surge filtering circuit 100 in FIG. 1A , detailed descriptions are omitted.

The control circuits 420, 440, and 460 are coupled to the surge filtering circuits 410, 430, and 450, respectively. Since the operations of the control circuits 420, 440, and 460 are similar, only the operation of the control circuit 420 will be described below. The control circuit 420 provides the control signal SC1 and performs a specific action, such as driving the load 402 or stopping the driving of the load 402, according to the level of the trigger signal ST1. Since the characteristics of the control circuit 420 are similar to the characteristics of the control circuit 220A in FIG. 2A , detailed descriptions are omitted.

The present invention does not limit the number of surge filtering circuits and control circuits. In a possible embodiment, the number of surge filtering circuits is the same or less than the number of control circuits. In other embodiments, the micro-control circuit 400 has more surge filtering circuits and control circuits.

In this embodiment, since the loads 402, 404 and 406 are controlled by different control circuits, the function of multi-stage control can be achieved. Assume that loads 402, 404 and 406 are all three independent motors. During an initial period, loads 402, 404 and 406 operate simultaneously and have different rotational speeds to achieve rapid cooling of the environment. When the ambient temperature is lower than the preset first temperature value, the level of the trigger signal ST1 changes. Therefore, the control circuit 420 stops driving the load 402 . When the ambient temperature rises and exceeds the first temperature value, it indicates that a release event occurs. Therefore, the control circuit 420 drives the load 402 again.

FIG. 5 is another schematic diagram of the micro-control circuit of the present invention. The micro-control circuit 500 includes input and output pins PIN1 - PIN3 , P1 - P3 , N1 - N3 , surge filtering circuits 510 , 520 , 530 and a control circuit 540 . In this embodiment, the micro-control circuit 500 provides driving signals SD1 to SD3 for driving different loads (not shown).

The surge filtering circuits 510 , 520 and 530 are coupled to corresponding input and output pins. Since the operations of the surge filter circuits 510 , 520 and 530 are the same, only the operation of the surge filter circuit 510 will be described below. The surge filtering circuit 510 has a comparison circuit 511 , a signal processing circuit 512 and a selection circuit 513 . The comparison circuit 511 compares the levels of the input and output pins P1 and N1 to generate the output signal SO1. The signal processing circuit 512 sets the trigger signal ST1 based on the control signal SC1 and the output signal SO1. The selection circuit 513 uses the external signal EXT1 or the signal EXT2 as the control signal SC1 according to the enable signal en1. Since the characteristics of the comparison circuit 511 , the signal processing circuit 512 and the selection circuit 513 are similar to those of the comparison circuit 110 , the signal processing circuit 120 and the selection circuit 130 in FIG. 1C , they are not described again. In other embodiments, the comparison circuit 511 does not compare the levels of the two input and output pins from the microcontroller circuit 500 . In this example, at least one input signal of the comparison circuit 511 comes from other circuits (not shown) inside the microcontroller circuit 500 .

Control circuit 540 provides signals EXT2, EXT4, and EXT6. Since the signals EXT2 , EXT4 and EXT6 are generated by the circuits inside the microcontroller circuit 500 (eg, the control circuit 540 ), the signals EXT2 , EXT4 and EXT6 can be called internal signals. In a possible embodiment, the control circuit 540 is a multi-channel PWM circuit. In this example, the PWM signals output by different channels are signals EXT2, EXT4 and EXT6. In this embodiment, the control circuit 540 includes control setting circuits CS1 ˜ CS3 , blocking circuits BF1 ˜BF3 , waveform generating circuits PG1 ˜PG3 , and adjusting circuits ODA1 ˜ODA3 .

The control setting circuits CS1 to CS3 respectively provide signals EXT2, EXT4 and EXT6. Since the operations of the control setting circuits CS1 to CS3 are the same, only the operation of the control setting circuit CS1 will be described below. The control setting circuit CS1 is used for providing the signal EXT2. In a possible embodiment, the control setting circuit CS1 is a waveform generating circuit, such as a pulse width modulation circuit.

The blocking circuits BF1 ˜ BF3 respectively receive the trigger signals ST1 ˜ ST3 provided from the surge filtering circuits 510 , 520 and 530 . Since the operations of the barrier circuits BF1 to BF3 are the same, only the operation of the barrier circuit BF1 will be described below. The blocking circuit BF1 determines whether to execute a specific action according to the level of the trigger signal ST1. In this example, the specific action is to instruct the waveform generating circuit PG1 to stop generating the driving signal SD1.

For example, when the level of the trigger signal ST1 changes, the blocking circuit BF1 performs a specific action. Therefore, the waveform generating circuit PG1 stops supplying the drive signal SD1. When a release event occurs, the blocking circuit BF1 stops performing certain actions. Therefore, the waveform generating circuit PG1 supplies the drive signal SD1 again. In other embodiments, when the level of the trigger signal ST1 does not change (eg, remains at a specific level), the blocking circuit BF1 does not perform a specific action. Therefore, the waveform generation circuit PG1 generates the drive signal SD1. The present invention does not limit the structure of the waveform generating circuit PG1. In a possible embodiment, the waveform generating circuit PG1 is a pulse width adjusting circuit. Since the actions of the waveform generating circuits PG1 to PG3 are the same, they will not be described again.

The adjustment circuits ODA1 to ODA3 respectively provide the adjustment signals SA1 to SA3 to the waveform generation circuits PG1 to PG3 for adjusting the duty ratios of the corresponding driving signals. Since the operations of the adjustment circuits ODA1 to ODA3 are the same, only the operation of the adjustment circuit ODA1 will be described below. In a possible embodiment, when the waveform generating circuit PG1 stops generating the driving signal SD1, the waveform generating circuit PG1 adjusts the duty cycle of the driving signal SD1 according to the adjusting signal SA1. When the release event occurs, the waveform generating circuit PG1 outputs the adjusted driving signal.

In some embodiments, the micro-control circuit 500 further includes switches SW1 ˜ SW3 . The switches SW1 ˜ SW3 are respectively coupled between the surge filtering circuits 510 , 520 , and 530 and the control circuit 540 . Since the operations of the switches SW1 to SW3 are the same, only the operation of the switch SW1 will be described below. When the switch SW1 is turned on, the switch SW1 transmits the trigger signal ST1 to the control circuit 540 . When the switch SW1 is not turned on, the switch SW1 stops transmitting the trigger signal ST1 to the control circuit 540 . In some embodiments, the micro-control circuit 500 has another control circuit (not shown) for turning on or off the switches SW1 ˜ SW3 . In other embodiments, the surge filtering circuit 510 may be coupled to other control circuits through other switches to trigger other control circuits.

FIG. 6 is a schematic flowchart of the control method of the present invention. The control method of the present invention is applicable to a microcontroller circuit (eg, microcontrollers 200A, 200B, 300, 400 and 500). First, a signal is received (step S611). In a possible embodiment, the present invention does not limit the source of the signal. In a possible embodiment, the signal is received by an input and output pin of the microcontroller. In another possible embodiment, the reference signal is generated by a circuit inside the microcontroller.

The comparison signal and a reference signal are used to generate an output signal (step S612). In a possible embodiment, the reference signal is received by an input and output pin of the microcontroller. In another possible embodiment, the reference signal is generated by a circuit inside the microcontroller.

It is judged whether the level of a control signal is equal to a turn-on level (step S613). In a possible embodiment, the control signal is received by another input and output pin of the microcontroller. In another possible embodiment, the control signal is generated by a circuit inside the microcontroller.

When the level of the control signal is equal to the turn-on level, the output signal is used as a trigger signal (step S614). When the level of the control signal is not equal to the turn-on level, stop using the output signal as the trigger signal (step S615). Therefore, even if the level of the signal received in step S611 (eg, SP in FIG. 2A ) changes greatly, the output signal (eg, SO in FIG. 2A ) will not be affected. In a possible embodiment, step S615 is to set the trigger signal to a predetermined level. In some embodiments, the turn-on level is a high level. In this example, the preset level is lower than the turn-on level.

Next, it is determined whether the trigger signal has changed (step S616). When the trigger signal changes, a specific action is performed (step S617). When the trigger signal does not change, no specific action is performed (step S618). In a possible embodiment, the specific action generates a driving signal for driving a load. In this example, step S618 is to stop generating the driving signal to suspend driving the load. In another possible embodiment, the specific action is to stop generating a driving signal to stop driving a load. In this example, step S618 generates a driving signal for driving a load.

The control method of the present invention, or a specific form or part thereof, may exist in the form of code. The code can be stored on physical media, such as floppy disks, optical discs, hard disks, or any other machine-readable (such as computer-readable) storage media, or not limited to external forms of computer program products, where, When the code is loaded and executed by a machine, such as a computer, the machine becomes a micro-control circuit or a surge filtering circuit for participating in the present invention. The code may also be transmitted through some transmission medium, such as wire or cable, optical fiber, or any type of transmission, wherein when the code is received, loaded, and executed by a machine, such as a computer, the machine becomes used to participate in this document. The invented micro-control circuit or the surge filtering circuit. When implemented on a general-purpose processing unit, the code combines with the processing unit to provide a unique device that operates similarly to application-specific logic circuits.

Unless otherwise defined, all terms (including technical and scientific terms) herein are commonly understood by those of ordinary skill in the art to which this invention belongs. Furthermore, unless expressly stated otherwise, the definitions of words in general dictionaries should be construed as consistent with their meanings in articles in the related technical field, and should not be construed as ideal states or overly formal voices. Although the terms "first", "second", etc. may be used to describe various elements, these elements should not be limited by these terms. These terms are only used to distinguish one element from another.

Although the present invention has been disclosed above with preferred embodiments, it is not intended to limit the present invention. Anyone with ordinary knowledge in the technical field can make some changes and modifications without departing from the spirit and scope of the present invention. . For example, the system, apparatus, or method described in the embodiments of the present invention may be implemented in a physical embodiment of hardware, software, or a combination of hardware and software. Therefore, the protection scope of the present invention should be determined by the scope of the appended patent application.

100, 210A, 210B, 310, 410, 430, 450, 510, 520, 530: Surge filter circuit 110, 211, 511, 521, 531: Comparison circuit 120, 212, 512, 522, 532: Signal processing circuit SP, EXT1~EXT6: Signal SN: Reference Signal SO, SO1~SO3: output signal 111: Analog Comparators SC, SC1~SC3: control signal ST, ST1~ST3: trigger signal 130, 213, 320, 513, 523, 533: Selection circuit 131: Multiplexer en1~en3: enable signal 200A, 200B, 300, 400, 500: Micro-control circuit P1~P3, N1~N3, PIN1~PIN3: Input and output pins 220A, 220B, 330, 340, 420, 440, 460, 540: Control circuit 202, 302, 304, 402, 404, 406: Load T211, T212, T214: Period T213: Time point S611~S618: Steps CS1~CS3: Control setting circuit BF1~BF3: blocking circuit PG1~PG3: Waveform generation circuit ODA1~ODA3: Adjustment circuit SA1~SA3: Adjust signal SD, SD1~SD3: drive signal

FIG. 1A is a schematic diagram of the surge filtering circuit of the present invention. FIG. 1B is an operation timing chart of the surge filtering circuit of the present invention. FIG. 1C is another schematic diagram of the surge filtering circuit of the present invention. FIG. 2A is a schematic diagram of the micro-control circuit of the present invention. FIG. 2B is another schematic diagram of the micro-control circuit of the present invention. FIG. 2C is a timing control diagram of the control circuit of the present invention. FIG. 3 is another schematic diagram of the micro-control circuit of the present invention. FIG. 4 is another schematic diagram of the micro-control circuit of the present invention. FIG. 5 is another schematic diagram of the micro-control circuit of the present invention. FIG. 6 is a schematic flowchart of the control method of the present invention.

100: Surge filter circuit

110: Comparison circuit

120: Signal processing circuit

SP:Signal

SN: Reference Signal

SO: output signal

111: Analog Comparators

SC: control signal

ST: trigger signal

Claims (10)

A surge filtering circuit, comprising: a comparison circuit for comparing a specific signal and a reference signal to generate an output signal; and a signal processing circuit for detecting the level of a control signal, when the level of the control signal is When the level is equal to a turn-on level, the signal processing circuit enters a monitoring mode. In the monitoring mode, the signal processing circuit uses the output signal as a trigger signal. When the level of the control signal is not equal to the turn-on level, the signal processing circuit The signal processing circuit leaves the monitoring mode and stops using the output signal as the trigger signal; wherein the control signal is a pulse width modulation signal. The surge filtering circuit of claim 1, wherein the comparison circuit is an analog comparator. The surge filtering circuit of claim 2, further comprising: a selection circuit that selectively uses one of an external signal and the PWM signal as the control signal. A micro-control circuit includes: a first surge filtering circuit, including: a first comparison circuit for comparing a first signal and a first reference signal to generate a first output signal; and a first signal The processing circuit detects the level of a first control signal. When the level of the first control signal is equal to a conduction level, the first signal processing circuit enters a first monitoring mode. In the first monitoring mode, The first signal processing circuit uses the first output signal as a first trigger signal, when the first control When the level of the control signal is not equal to the turn-on level, the first signal processing circuit leaves the first monitoring mode and stops using the first output signal as the first trigger signal; and a first control circuit generates a first a driving signal for driving a first load; wherein: when the level of the first trigger signal changes, the first control circuit performs a specific action until a release event occurs; the first control signal is A pulse width modulated signal. The micro-control circuit of claim 4, wherein the specific action is to stop generating the first drive signal, and when the release event occurs, the first control circuit generates the first drive signal. The micro-control circuit of claim 4 further comprises: a first input-output pin for receiving the first signal; and a second input-output pin for receiving the first reference signal. The micro-control circuit of claim 4, further comprising: a third input and output pin for receiving an external signal; a selection circuit for selectively using one of the external signal and a second signal as the first A control signal, the second signal is generated by the first control circuit. The micro-control circuit of claim 4, further comprising: a second control circuit operating according to the first trigger signal; and a selection circuit selectively providing the first trigger signal to the first or second control circuit. The micro-control circuit of claim 4, further comprising: an adjustment circuit, when the first control circuit stops generating the first driving signal, An adjustment signal is supplied to the first control circuit for changing the duty ratio of the first driving signal; wherein the first control circuit is a pulse width modulation circuit, and the pulse width modulation circuit generates a first a pulse width modulation signal and a second pulse width modulation signal, the pulse width modulation circuit uses the first pulse width modulation signal as a second signal, and uses the second pulse width modulation signal as the the first drive signal. The micro-control circuit of claim 4, further comprising: a second surge filtering circuit, comprising: a second comparison circuit for comparing a second signal with a second reference signal to generate a second output signal; and a second signal processing circuit for detecting the level of a second control signal, when the level of the second control signal is equal to the conduction level, the second signal processing circuit enters a second monitoring mode, and the In the second monitoring mode, the second signal processing circuit uses the second output signal as a second trigger signal, and when the level of the second control signal is not equal to the turn-on level, the second signal processing circuit leaves the the second monitoring mode, and stop using the second output signal as the second trigger signal; wherein: when the level of the second trigger signal does not change, the first control circuit generates a second drive signal for Driving a second load, when the level of the second trigger signal changes, the first control circuit stops generating the second drive signal until the release event occurs; the first and second control signals are determined by the first control circuit is generated by a control circuit, and the duty cycle of the first control signal is different from the duty cycle of the second control signal.

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