TWI767175B - 用於處理輸入輸出儲存指令之資料處理系統、方法及電腦程式產品 - Google Patents

用於處理輸入輸出儲存指令之資料處理系統、方法及電腦程式產品 Download PDF

Info

Publication number
TWI767175B
TWI767175B TW109101030A TW109101030A TWI767175B TW I767175 B TWI767175 B TW I767175B TW 109101030 A TW109101030 A TW 109101030A TW 109101030 A TW109101030 A TW 109101030A TW I767175 B TWI767175 B TW I767175B
Authority
TW
Taiwan
Prior art keywords
data
data processing
buffer
asynchronous
message
Prior art date
Application number
TW109101030A
Other languages
English (en)
Chinese (zh)
Other versions
TW202046094A (zh
Inventor
克里斯多夫 拉奇
馬可 克雷莫
法蘭克 樂娜特
馬提爾斯 克藍
強納森 布瑞布里
克理斯俊 傑可比
布藍頓 貝爾瑪
彼得 杜魯威
Original Assignee
美商萬國商業機器公司
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by 美商萬國商業機器公司 filed Critical 美商萬國商業機器公司
Publication of TW202046094A publication Critical patent/TW202046094A/zh
Application granted granted Critical
Publication of TWI767175B publication Critical patent/TWI767175B/zh

Links

Images

Classifications

    • GPHYSICS
    • G06COMPUTING OR CALCULATING; COUNTING
    • G06FELECTRIC DIGITAL DATA PROCESSING
    • G06F13/00Interconnection of, or transfer of information or other signals between, memories, input/output devices or central processing units
    • G06F13/14Handling requests for interconnection or transfer
    • G06F13/16Handling requests for interconnection or transfer for access to memory bus
    • G06F13/1668Details of memory controller
    • GPHYSICS
    • G06COMPUTING OR CALCULATING; COUNTING
    • G06FELECTRIC DIGITAL DATA PROCESSING
    • G06F13/00Interconnection of, or transfer of information or other signals between, memories, input/output devices or central processing units
    • G06F13/38Information transfer, e.g. on bus
    • G06F13/42Bus transfer protocol, e.g. handshake; Synchronisation
    • G06F13/4282Bus transfer protocol, e.g. handshake; Synchronisation on a serial bus, e.g. I2C bus, SPI bus
    • GPHYSICS
    • G06COMPUTING OR CALCULATING; COUNTING
    • G06FELECTRIC DIGITAL DATA PROCESSING
    • G06F9/00Arrangements for program control, e.g. control units
    • G06F9/06Arrangements for program control, e.g. control units using stored programs, i.e. using an internal store of processing equipment to receive or retain programs
    • G06F9/30Arrangements for executing machine instructions, e.g. instruction decode
    • G06F9/30003Arrangements for executing specific machine instructions
    • G06F9/3004Arrangements for executing specific machine instructions to perform operations on memory
    • G06F9/30043LOAD or STORE instructions; Clear instruction
    • GPHYSICS
    • G06COMPUTING OR CALCULATING; COUNTING
    • G06FELECTRIC DIGITAL DATA PROCESSING
    • G06F9/00Arrangements for program control, e.g. control units
    • G06F9/06Arrangements for program control, e.g. control units using stored programs, i.e. using an internal store of processing equipment to receive or retain programs
    • G06F9/30Arrangements for executing machine instructions, e.g. instruction decode
    • G06F9/30003Arrangements for executing specific machine instructions
    • G06F9/30076Arrangements for executing specific machine instructions to perform miscellaneous control operations, e.g. NOP
    • G06F9/30087Synchronisation or serialisation instructions

Landscapes

  • Engineering & Computer Science (AREA)
  • Theoretical Computer Science (AREA)
  • Physics & Mathematics (AREA)
  • General Engineering & Computer Science (AREA)
  • General Physics & Mathematics (AREA)
  • Software Systems (AREA)
  • Information Transfer Systems (AREA)
  • Input From Keyboards Or The Like (AREA)
TW109101030A 2019-01-31 2020-01-13 用於處理輸入輸出儲存指令之資料處理系統、方法及電腦程式產品 TWI767175B (zh)

Applications Claiming Priority (2)

Application Number Priority Date Filing Date Title
EP19154737.1 2019-01-31
EP19154737 2019-01-31

Publications (2)

Publication Number Publication Date
TW202046094A TW202046094A (zh) 2020-12-16
TWI767175B true TWI767175B (zh) 2022-06-11

Family

ID=65275984

Family Applications (1)

Application Number Title Priority Date Filing Date
TW109101030A TWI767175B (zh) 2019-01-31 2020-01-13 用於處理輸入輸出儲存指令之資料處理系統、方法及電腦程式產品

Country Status (10)

Country Link
US (1) US11334503B2 (https=)
EP (1) EP3918468B1 (https=)
JP (1) JP7479373B2 (https=)
CN (1) CN113366434B (https=)
AU (1) AU2020213829B2 (https=)
CA (1) CA3127840A1 (https=)
IL (1) IL283865B2 (https=)
MX (1) MX2021009159A (https=)
TW (1) TWI767175B (https=)
WO (1) WO2020156798A1 (https=)

Families Citing this family (8)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
ES3015283T3 (en) 2019-01-31 2025-04-30 Ibm Handling an input/output store instruction
TWI767175B (zh) 2019-01-31 2022-06-11 美商萬國商業機器公司 用於處理輸入輸出儲存指令之資料處理系統、方法及電腦程式產品
TWI773959B (zh) * 2019-01-31 2022-08-11 美商萬國商業機器公司 用於處理輸入輸出儲存指令之資料處理系統、方法及電腦程式產品
DE112020000146B4 (de) 2019-01-31 2025-01-16 International Business Machines Corporation Verfahren, datenverarbeitungssystem und computerprogrammprodukt zur handhabung einer eingabe-/ausgabe-speicheranweisung
US11893407B2 (en) * 2020-09-24 2024-02-06 Red Hat, Inc. Overlay container storage driver for microservice workloads
US11522883B2 (en) * 2020-12-18 2022-12-06 Dell Products, L.P. Creating and handling workspace indicators of compromise (IOC) based upon configuration drift
CN115422099B (zh) * 2022-08-30 2026-02-17 深圳市国微电子有限公司 一种通信信息发送方法、装置、电子设备及存储介质
CN116319303A (zh) * 2023-02-22 2023-06-23 中科驭数(北京)科技有限公司 基于dpu跨卡链路聚合的网卡虚拟化方法

Citations (5)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US6490647B1 (en) * 2000-04-04 2002-12-03 International Business Machines Corporation Flushing stale data from a PCI bus system read prefetch buffer
US20110320643A1 (en) * 2010-06-23 2011-12-29 International Business Machines Corporation Measurement facility for adapter functions
US20150106567A1 (en) * 2013-10-15 2015-04-16 Mill Computing, Inc. Computer Processor Employing Cache Memory With Per-Byte Valid Bits
TW201826122A (zh) * 2016-12-31 2018-07-16 美商英特爾股份有限公司 用於異質計算之系統,方法,及設備
US20180341410A1 (en) * 2017-03-24 2018-11-29 Western Digital Technologies, Inc. System and method for adaptive early completion posting using controller memory buffer

Family Cites Families (38)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
FR2273317B1 (https=) * 1974-05-28 1976-10-15 Philips Electrologica
US4947316A (en) * 1983-12-29 1990-08-07 International Business Machines Corporation Internal bus architecture employing a simplified rapidly executable instruction set
US5131081A (en) 1989-03-23 1992-07-14 North American Philips Corp., Signetics Div. System having a host independent input/output processor for controlling data transfer between a memory and a plurality of i/o controllers
US5548735A (en) 1993-09-15 1996-08-20 International Business Machines Corporation System and method for asynchronously processing store instructions to I/O space
US5553302A (en) * 1993-12-30 1996-09-03 Unisys Corporation Serial I/O channel having independent and asynchronous facilities with sequence recognition, frame recognition, and frame receiving mechanism for receiving control and user defined data
JPH07302200A (ja) * 1994-04-28 1995-11-14 Hewlett Packard Co <Hp> 順次付けロード動作および順序付け記憶動作を強制する命令を有するコンピュータのロード命令方法。
US5548788A (en) * 1994-10-27 1996-08-20 Emc Corporation Disk controller having host processor controls the time for transferring data to disk drive by modifying contents of the memory to indicate data is stored in the memory
US6038646A (en) 1998-01-23 2000-03-14 Sun Microsystems, Inc. Method and apparatus for enforcing ordered execution of reads and writes across a memory interface
US6247097B1 (en) 1999-01-22 2001-06-12 International Business Machines Corporation Aligned instruction cache handling of instruction fetches across multiple predicted branch instructions
US6189088B1 (en) 1999-02-03 2001-02-13 International Business Machines Corporation Forwarding stored dara fetched for out-of-order load/read operation to over-taken operation read-accessing same memory location
US6725348B1 (en) * 1999-10-13 2004-04-20 International Business Machines Corporation Data storage device and method for reducing write misses by completing transfer to a dual-port cache before initiating a disk write of the data from the cache
US7042881B1 (en) * 2001-06-29 2006-05-09 Cisco Technology, Inc. Asynchronous transfer mode system and method to verify a connection
US8037224B2 (en) * 2002-10-08 2011-10-11 Netlogic Microsystems, Inc. Delegating network processor operations to star topology serial bus interfaces
US7178019B2 (en) 2003-11-13 2007-02-13 Hewlett-Packard Development Company, L.P. Networked basic input output system read only memory
US7234004B2 (en) 2003-12-19 2007-06-19 International Business Machines Corporation Method, apparatus and program product for low latency I/O adapter queuing in a computer system
US7200626B1 (en) * 2004-01-22 2007-04-03 Unisys Corporation System and method for verification of a quiesced database copy
US7079978B2 (en) * 2004-05-24 2006-07-18 International Business Machines Corporation Apparatus, system, and method for abbreviated library calibration
US7467325B2 (en) * 2005-02-10 2008-12-16 International Business Machines Corporation Processor instruction retry recovery
US7631097B2 (en) 2005-07-21 2009-12-08 National Instruments Corporation Method and apparatus for optimizing the responsiveness and throughput of a system performing packetized data transfers using a transfer count mark
US7827433B1 (en) 2007-05-16 2010-11-02 Altera Corporation Time-multiplexed routing for reducing pipelining registers
US7870351B2 (en) * 2007-11-15 2011-01-11 Micron Technology, Inc. System, apparatus, and method for modifying the order of memory accesses
US7991981B2 (en) * 2008-02-01 2011-08-02 International Business Machines Corporation Completion of asynchronous memory move in the presence of a barrier operation
US7941627B2 (en) * 2008-02-01 2011-05-10 International Business Machines Corporation Specialized memory move barrier operations
JP4623126B2 (ja) 2008-04-14 2011-02-02 株式会社日立製作所 データ処理システム
US8121032B2 (en) 2008-05-30 2012-02-21 Cisco Technology, Inc. Efficient convergence of grouped VPN prefixes
US8867344B2 (en) 2008-07-21 2014-10-21 Mediatek Inc. Methods for bus data transmission and systems utilizing the same
US8566480B2 (en) 2010-06-23 2013-10-22 International Business Machines Corporation Load instruction for communicating with adapters
US10120681B2 (en) * 2014-03-14 2018-11-06 International Business Machines Corporation Compare and delay instructions
US9460019B2 (en) 2014-06-26 2016-10-04 Intel Corporation Sending packets using optimized PIO write sequences without SFENCEs
US9477481B2 (en) 2014-06-27 2016-10-25 International Business Machines Corporation Accurate tracking of transactional read and write sets with speculation
US10489158B2 (en) 2014-09-26 2019-11-26 Intel Corporation Processors, methods, systems, and instructions to selectively fence only persistent storage of given data relative to subsequent stores
GB2531011A (en) * 2014-10-07 2016-04-13 Ibm Initializing I/O Devices
US9542201B2 (en) 2015-02-25 2017-01-10 Quanta Computer, Inc. Network bios management
US10606591B2 (en) 2017-10-06 2020-03-31 International Business Machines Corporation Handling effective address synonyms in a load-store unit that operates without address translation
DE112020000146B4 (de) 2019-01-31 2025-01-16 International Business Machines Corporation Verfahren, datenverarbeitungssystem und computerprogrammprodukt zur handhabung einer eingabe-/ausgabe-speicheranweisung
TWI773959B (zh) 2019-01-31 2022-08-11 美商萬國商業機器公司 用於處理輸入輸出儲存指令之資料處理系統、方法及電腦程式產品
TWI767175B (zh) 2019-01-31 2022-06-11 美商萬國商業機器公司 用於處理輸入輸出儲存指令之資料處理系統、方法及電腦程式產品
ES3015283T3 (en) 2019-01-31 2025-04-30 Ibm Handling an input/output store instruction

Patent Citations (5)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US6490647B1 (en) * 2000-04-04 2002-12-03 International Business Machines Corporation Flushing stale data from a PCI bus system read prefetch buffer
US20110320643A1 (en) * 2010-06-23 2011-12-29 International Business Machines Corporation Measurement facility for adapter functions
US20150106567A1 (en) * 2013-10-15 2015-04-16 Mill Computing, Inc. Computer Processor Employing Cache Memory With Per-Byte Valid Bits
TW201826122A (zh) * 2016-12-31 2018-07-16 美商英特爾股份有限公司 用於異質計算之系統,方法,及設備
US20180341410A1 (en) * 2017-03-24 2018-11-29 Western Digital Technologies, Inc. System and method for adaptive early completion posting using controller memory buffer

Also Published As

Publication number Publication date
TW202046094A (zh) 2020-12-16
IL283865A (en) 2021-07-29
AU2020213829A1 (en) 2021-05-20
IL283865B2 (en) 2024-07-01
US11334503B2 (en) 2022-05-17
CA3127840A1 (en) 2020-08-06
EP3918468C0 (en) 2025-04-30
MX2021009159A (es) 2021-09-10
AU2020213829B2 (en) 2022-09-15
JP7479373B2 (ja) 2024-05-08
US20200250112A1 (en) 2020-08-06
EP3918468B1 (en) 2025-04-30
CN113366434A (zh) 2021-09-07
JP2022518351A (ja) 2022-03-15
CN113366434B (zh) 2026-03-24
WO2020156798A1 (en) 2020-08-06
IL283865B1 (en) 2024-03-01
EP3918468A1 (en) 2021-12-08

Similar Documents

Publication Publication Date Title
TWI767175B (zh) 用於處理輸入輸出儲存指令之資料處理系統、方法及電腦程式產品
TWI773959B (zh) 用於處理輸入輸出儲存指令之資料處理系統、方法及電腦程式產品
CN113366457B (zh) 处理输入/输出存储指令
US11579874B2 (en) Handling an input/output store instruction
HK40057632A (en) Handling an input/output store instruction
HK40057233A (en) Handling an input/output store instruction