TWI766497B - Data access method and system - Google Patents

Abstract

A method of data access includes a processor sending request information. When the request information is local access, the processor reads or writes to the storage medium through its corresponding arbitrator and memory controller. When the request information is non-local During memory access, the processor reads or writes to the storage medium through its corresponding arbiter, memory controller, and DMA controller. A data access system is also disclosed.

Description

Data access method and system

The present application relates to a data access method and system.

System-on-a-Chip (SoC) is an integrated circuit chip, SoC package One or more processor units, which may include internal memory (eg, static random access memory (SRAM)), or may be combined with external memory devices (eg, dynamic random access memory) with a capacity greater than that of the internal memory memory (DRAM) communication.

At present, the access to the memory by the multiprocessors on the SoC is the bus way, through a single memory The memory controller accesses the memory of the dynamic random access memory. Multiple processor units on the SoC share a large memory pool. When multiple processors need to transmit data, the data transmission efficiency is low. Extend high.

In view of this, it is necessary to provide a data access method and system, which can improve the data According to the transmission efficiency, the delay is reduced.

An embodiment of the present application provides a data access method. The data access method should Used in a data access system, the data access system includes a system-on-chip and a storage medium, the system-on-chip and the storage medium communicate through a bus, the system-on-chip includes at least two processors and each Each handling module of the processor, the handling module includes a DMA controller, an arbiter and a memory controller, the data access method includes: the processor sends request information, wherein the request information includes an operation type and address, the operation type includes read operation or write operation; when the request information is local access, based on the address, the processor uses its corresponding arbiter and memory controller to The storage medium performs a read operation or a write operation to complete the local memory access of the processor; and, when the requested information is a non-local memory access, based on the address, the processor passes The corresponding arbiter, memory controller and DMA controller perform read operation or write operation on the storage medium, so as to complete the non-local memory access of the processor.

According to some embodiments of the present application, when the requested information is local access , based on the address, the processor performs a read operation or a write operation on the storage medium through its corresponding arbiter and memory controller, so as to complete the local memory access of the processor, including: When the request information is local access, the working mode of the processor is the memory control mode, the processor sends a first control command to the corresponding memory controller, and the first control command uses instructing the memory controller to obtain the request information; the memory controller sends a bus request signal to the arbiter according to the request information, and the arbiter sends the bus usage right to the memory a memory controller; the memory controller performs a read operation or a write operation on the storage medium according to the address.

According to some embodiments of the present application, the memory controller according to the address pair Performing a read operation or a write operation on the storage medium includes: during the read operation, the memory controller reads the first data according to the address, and the processor receives the data sent by the memory controller. or, during the writing operation, the memory controller writes the second data sent by the processor to the storage medium according to the address.

According to some embodiments of the present application, when the requested information is a non-local memory When the memory is accessed, based on the address, the processor performs a read operation or a write operation on the storage medium through its corresponding arbiter, memory controller and DMA controller to complete the processor's The non-local memory access includes: when the request information is a non-local memory access, the working mode of the processor is a DMA control mode, and the processor sends a second control command to the corresponding DMA controller , the second control command is used to instruct the DMA controller to obtain the request information; the DMA controller sends a bus request signal to the corresponding arbiter according to the request information, and the arbiter sends the bus The row usage right is sent to the DMA controller; the DMA controller performs a read operation or a write operation on the storage medium through the corresponding memory controller according to the address.

According to some embodiments of the present application, the DMA controller communicates according to the address Performing a read operation or a write operation on the storage medium through the corresponding memory controller includes: the DMA controller sends the address to the memory controller, and the memory controller according to The address performs a read operation or a write operation on the storage medium.

According to some embodiments of the present application, the DMA controller sends the address To the memory controller, the memory controller performing a read operation or a write operation on the storage medium according to the address includes: when the write operation is performed, the DMA controller receives the process The DMA controller sends the third data to the arbiter corresponding to the destination address in the address, and sends the bus request signal to the arbiter. After obtaining the right to use the bus, the DMA controller sends the third data to the the first memory controller corresponding to the destination address, so that the first memory controller writes the third data to the storage medium; or, during the read operation, the DMA controller according to the The source address in the address sends a bus request signal to the corresponding arbiter, and after obtaining the right to use the bus, the DMA controller sends the source address to the second corresponding to the source address. A memory controller, the second memory controller reads the fourth data according to the source address, the DMA controller receives the fourth data, and the processor reads all the data through the DMA controller. the fourth data.

According to some embodiments of the present application, the processor includes one or more of the following: Central processing unit, graphics processing unit, digital signal processor.

An embodiment of the present application provides a data access system, the data access system includes including a system-on-chip and a storage medium, the system-on-chip and the storage medium communicate via bus bars, the system-on-chip includes at least two processors and a respective handling module for each processor, and the handling module includes a DMA controller, an arbiter, and a memory controller; the processor sends request information, wherein the request information includes an operation type and an address, and the operation type includes a read operation or a write operation; the processor, for performing a read operation or a write operation on the storage medium through its corresponding arbiter and memory controller based on the address when the request information is local access, so as to complete the local memory access, When the request information is a non-local memory access, based on the address, a read operation or a write operation is performed on the storage medium through its corresponding arbiter, memory controller and DMA controller to complete Non-local memory access.

According to some embodiments of the present application, between the system on chip and the storage medium Connected by wafer stacking.

According to some embodiments of the present application, the storage medium is a dynamic random access memory live.

The data access method and system provided by the embodiments of the present application, when accessed locally, Data access is performed through the memory controller, and during non-local access, data access is performed through the DMA controller. In this way, the data access method and system provided by the embodiments of the present application do not need to wait for the bus to be idle, which can shorten the data transfer time and improve the data access efficiency.

In the following, with reference to the accompanying drawings in the embodiments of the present application, the techniques in the embodiments of the present application will be discussed. The technical solution is clearly and completely described, and obviously, the described embodiments are a part of the embodiments of the present application, but not all of the embodiments.

Based on the embodiments in this application, those of ordinary skill in the art will All other implementations obtained under the premise of sexual labor fall within the scope of protection of this application.

Please refer to FIG. 1, which is a data access system according to an embodiment of the present application 100 structure diagram, as shown in FIG. 1 , the data access system 100 includes a system-on-a-chip (SoC, SoC) and a storage medium 20 , between the system-on-a-chip 10 and the storage medium 20 The communication is performed through a bus bar, which is a Peripheral Component Interconnect express (PCIe) bus bar.

In the embodiment of the present application, the data access system 100 is controlled by a single memory The problem that the bandwidth of the controller 43 accessing the dynamic random access memory is insufficient and the processing efficiency is lowered, which can improve the access speed of the processor 30 on the system-on-chip 10 to the storage medium 20 .

In this embodiment of the present application, on the storage medium 20, each processor 30 is allocated its The corresponding memory address space.

In the embodiment of the present application, the system-on-chip 10 integrates a complete The system includes a central processing unit 30 (central processing unit, CPU), a memory, and peripheral circuits. The system-on-chip 10 includes at least two processors 30 and a respective handling module 40 for each processor 30 . The handling module 40 includes a DMA controller 41 , an arbiter 42 and a memory controller 43 .

In this embodiment of the present application, the processor 30 includes a central processing unit, a graphics processing unit or digital signal processor.

In the implementation of this application, the storage medium 20 may be a non-volatile high-speed transmission bus A non-volatile memory express (NVMe) solid state disk (solid state disk, SSD) can also be other types of storage media 20 . In one possible implementation manner, the storage medium 20 is a dynamic random access memory (Dynamic Random Access Memory, DRAM).

In this embodiment of the present application, each storage medium 20 runs direct memory access control A controller (direct memory access, DMA), that is, the DMA controller 41, the DMA controller 41 is used to directly migrate the data to be read from the storage medium to the memory corresponding to the processor, such as double-rate synchronous dynamic random access memory .

In the embodiment of the present application, the memory controller 43 is an internal control unit of the computer system. It is an important part of memory and is responsible for data exchange between the memory and the central processing unit 30 . Data is transmitted from the memory controller 43 to the central processing unit 30 .

In this embodiment of the present application, multiple devices or modules in the system-on-chip 10 may be applied for at the same time For the right to use the bus, in order to avoid the conflict of the bus, the arbiter 42 reasonably controls and manages the applicants who need to occupy the bus in the system. The processor 30, which arbitrates the right to use the bus, arbitrates.

The processor 30 sends request information, wherein the request information includes the operation type and Address, the operation type includes read operation or write operation.

The processor 30 is configured to, when the request information is local access, address, and perform a read operation or a write operation on the storage medium 20 through its corresponding arbiter 42 and memory controller 43 to complete local memory access. When the request information is a non-local memory access, Based on the address, a read operation or a write operation is performed on the storage medium 20 through the corresponding arbiter 42 , the memory controller 43 and the DMA controller 41 to complete the non-local memory access.

Please refer to FIG. 2 and FIG. 3 together. FIG. 2 and FIG. 3 illustrate the transportation according to an embodiment of the present application. A schematic diagram of the workflow of the module 40 . When the request information is accessed locally, based on the address, the processor 30 performs a read operation or a write operation on the storage medium 20 through its corresponding arbiter 42 and memory controller 43 to The local memory access of the processor 30 is completed. When the request information is a non-local memory access, based on the address, the processor 30 reads the storage medium 20 through its corresponding arbiter 42 , memory controller 43 and DMA controller 41 A fetch operation or a write operation is performed to complete the non-local memory access of the processor 30 .

As shown in FIG. 2 , taking the processor 30 as the central processing unit 30 as an example, the central processing unit CUP1 The corresponding transport module 40 includes an arbiter A1, a memory controller B1, and a DMA controller C1. The transport module 40 of the CPU2 includes an arbiter A2, a memory controller B2, and a DMA controller C2. The central processing unit 30CPU3 and its corresponding transport module 40 include an arbiter A3, a memory controller B3, and a DMA controller C3. The central processing unit 30CPU4 and its corresponding transport module 40 include an arbiter A4, a memory controller B4, and a DMA controller C4. Each central processing unit has its corresponding storage space address. When the central processing unit accesses its own memory space, it is a local access, and when the central processing unit accesses the memory space of other central processing units, it is a non-local access.

Please refer to FIG. 3 together. The workflow of the handling module 40 corresponding to each processor 30 is as follows Down:

When CPU1 wants to perform local access, the working mode of CPU1 is memory control In the memory controller mode, the CPU1 sends a first control command to the memory controller B1, and the first control command is used to instruct the memory controller B1 to obtain the request information. The memory controller B1 sends a bus request signal to the arbiter A1 according to the request information, and the arbiter A1 sends the bus usage right to the memory controller B1, and the memory controller B1 performs a read operation or a write operation on the storage medium 20 according to the address in the request information.

During the read operation, the memory controller B1 reads the first A data, the CPU1 receives the first data sent by the memory controller B1. During the writing operation, the memory controller B1 writes the second data sent by the CPU1 to the storage medium 20 according to the address.

When CPU1 wants to perform non-local access, data transfer between CPU1 and CPU2 When inputting, the CPU1 working mode is the DMA control mode, and the CPU1 sends a second control command to its corresponding DMA controller C1, the second control command is used to instruct the DMA controller C1 to obtain the request information, the DMA controller C1 The controller C1 sends a bus request signal to the corresponding arbiter A1 according to the request information, and the arbiter A1 sends the bus use right to the DMA controller C1, and the DMA controller C1 according to the The address is read or written to the storage medium 20 through the corresponding memory controller 43 .

During the writing operation, the DMA controller C1 receives the first data sent by the CPU1 three data, and send a bus request signal to the arbiter A2 corresponding to the destination address in the address, after obtaining the right to use the bus, the DMA controller C1 sends the third data to the destination address The corresponding first memory controller B2, so that the first memory controller B2 writes the third data to the storage medium 20 corresponding to the CPU2, that is, the destination address in the address.

When performing a read operation, the DMA controller C1 according to the source in the address The DMA controller C1 sends the source address to the second memory controller B2 corresponding to the source address after obtaining the right to use the bus. The second memory controller B2 reads the fourth data according to the source address, that is, the memory corresponding to the CPU2, the DMA controller C1 receives the fourth data, and the CPU1 passes the DMA controller C1 Read the fourth data.

In this embodiment of the present application, when performing local access, each processor 30 uses its The corresponding memory controller 43 directly accesses the storage medium 20. When performing non-local access, each processor 30 uses its corresponding DMA controller 41 to move data between the processors 30, which shortens data transmission. time and improve efficiency.

In one possible implementation manner, the system-on-chip 10 and the storage medium 20 connected by wafer stacking.

In the embodiments of the present application, the wafers are stacked in a wafer on wafer manner (Wafer on Wafer) The IO signal lines of the wafer of the upper system 10 and the wafer of the storage medium 20 are connected together, which simplifies the number of IO pins, and the IO ports of the storage medium 20 do not need to lead out pins, thereby reducing the delay and power consumption, and because the system on a chip 10 The chip of the storage medium 20 is integrated with the chip of the storage medium 20, and the printed circuit board reduces the layout and area of the storage medium 20, and reduces the production cost and wiring difficulty of the circuit board.

Please refer to FIG. 4 , which is a flow of a data access method according to an embodiment of the present application Schematic diagram of the process. The method is applied to a data access system 100, the data access system 100 includes a system-on-chip 10 and a storage medium 20, the system-on-chip 10 and the storage medium 20 communicate through a bus, and the system-on-chip 10 Including at least two processors 30 and a respective handling module 40 for each processor 30, the handling module 40 includes a DMA controller 41, an arbiter 42 and a memory controller 43, as shown in FIG. The data access method includes the following steps:

Step S10: the processor sends request information, wherein the request information includes Operation type and address, the operation type includes read operation or write operation.

Step S20: When the request information is local access, based on the address, the The processor performs a read operation or a write operation on the storage medium through its corresponding arbiter and a memory controller, so as to complete the local memory access of the processor.

In this embodiment of the present application, when the processor 30 performs local access, When the allocated memory performs data access, the corresponding memory controller 43 performs data movement, which can improve data access efficiency.

Please also refer to FIG. 5 , which is a schematic diagram of the refinement process of step S20 . at least the present invention In one embodiment, when the request information is local access, based on the address, the processor 30 reads the storage medium 20 through its corresponding arbiter 42 and memory controller 43 Operations or write operations to accomplish local memory access by the processor 30 include:

Step S201: When the request information is local access, the processor works in a mode In the memory control mode, the processor sends a first control command to the corresponding memory controller, and the first control command is used to instruct the memory controller to obtain the request information.

Step S202 : the memory controller sends the request to the arbiter according to the request information A bus request signal is sent, and the arbiter sends the bus use right to the memory controller.

Step S203 : the memory controller performs the processing on the storage medium according to the address read operation or write operation.

In this embodiment of the present application, the processor 30 needs to control the memory address allocated to it When the space performs data access and local access, the processor 30 performs local access, and the memory controller 43 corresponding to the processor 30 performs data movement to realize the read operation or write operation to its own memory.

In one of the possible implementations, the IMC Bus is used for communication during local access. letter.

Further, when performing a read operation, the memory controller 43 according to the bit The first data is read from the address, and the processor 30 receives the first data sent by the memory controller 43 .

Or, when performing a write operation, the memory controller 43 assigns the address according to the address The second data sent by the processor 30 is written into the storage medium 20 .

Step S30: When the request information is a non-local memory access, based on the bit address, the processor performs a read operation or a write operation on the storage medium through its corresponding arbiter, memory controller and DMA controller, so as to complete the non-local memory access of the processor.

In one of the possible implementations, non-local access uses a fast-lane interconnect bus platoon (Quick Path Interconnect, QPI) to communicate.

Please also refer to FIG. 6 , which is a schematic diagram of the refinement process of step S30 . at least the present invention In one embodiment, when the request information is a non-local memory access, based on the address, the processor 30 , through its corresponding arbiter 42 , memory controller 43 and DMA controller 41 The storage medium 20 performs a read operation or a write operation to complete the non-local memory access of the processor 30 including:

Step S301: When the request information is a non-local memory access, the processor The working mode is a DMA control mode, and the processor sends a second control command to the corresponding DMA controller, where the second control command is used to instruct the DMA controller to acquire the request information.

Step S302 : the DMA controller sends the request to the corresponding secondary server according to the request information. The arbiter sends a bus request signal, and the arbiter sends the bus use right to the DMA controller, and the DMA controller performs processing on the storage medium through the corresponding memory controller according to the address. read operation or write operation.

In one possible implementation manner, the DMA controller 41 sends the address to It is sent to the memory controller 43, and the memory controller 43 performs a read operation or a write operation on the storage medium 20 according to the address.

Further, when performing a write operation, the DMA controller 41 receives the address the third data sent by the processor 30, and send a bus request signal to the arbiter 42 corresponding to the destination address in the address. After obtaining the right to use the bus, the DMA controller 41 sends the third data to the arbiter 42. sending to the first memory controller corresponding to the destination address, so that the first memory controller writes the third data to the storage medium 20;

Or, when the read operation is performed, the DMA controller 41 according to the address in the The source address sends a bus request signal to the corresponding arbiter 42. After obtaining the right to use the bus, the DMA controller 41 sends the source address to the second memory controller corresponding to the source address. , the second memory controller reads the fourth data according to the source address, the DMA controller 41 receives the fourth data, and the processor 30 reads the fourth data through the DMA controller 41 Fourth information.

In this embodiment of the present application, the processor 30 needs to access the memory of other processors 30 In the address space, that is, non-local access is performed, and data is moved through the DMA controller 41 corresponding to the processor 30 to improve the speed of the processor accessing the memory of other processors.

For those skilled in the art, it is obvious that the present application is not limited to the above-mentioned exemplary embodiments details, and the present application may be embodied in other specific forms without departing from the spirit or essential characteristics of the present application. Therefore, the above-described embodiments of the present application should be regarded as exemplary from any point of view.

100: Data Access System 10: System-on-Chip 20: Storage medium 30: Processor 40: Handling module 41: DMA controller 42: Arbiter 43: Memory Controller

FIG. 1 is a structural diagram of a data access system according to an embodiment of the present application. FIG. 2 and FIG. 3 are schematic diagrams of the work flow of a transport module according to an embodiment of the present application. FIG. 4 is a schematic flowchart of a data access method according to an embodiment of the present application. FIG. 5 is a schematic diagram of a refinement flow of step S20 in FIG. 4 . FIG. 6 is a schematic diagram of the refinement flow of step S30 in FIG. 4 .

none

S10~S30: Steps

Claims (10)

A data access method, which is improved in that the data access method is applied to a data access system, the data access system includes an on-chip system and a storage medium, and a bus is used between the on-chip system and the storage medium Queue communication, the system-on-chip includes at least two processors and a respective handling module for each processor, the handling module includes a DMA controller, an arbiter and a memory controller, and the data access method includes: The processor sends request information, wherein the request information includes an operation type and an address, and the operation type includes a read operation or a write operation; When the request information is local access, based on the address, the processor performs a read operation or a write operation on the storage medium through its corresponding arbiter and memory controller to complete the processing local memory access to the server; and, When the request information is a non-local memory access, based on the address, the processor reads or writes to the storage medium through its corresponding arbiter, memory controller and DMA controller operations to complete non-local memory accesses by the processor. The data access method according to claim 1, wherein when the requested information is local access, based on the address, the processor uses its corresponding arbiter and memory controller to access the data. The storage medium performs a read operation or a write operation to complete the local memory access of the processor, including: When the request information is local access, the working mode of the processor is the memory control mode, the processor sends a first control command to the corresponding memory controller, and the first control command uses instructing the memory controller to obtain the request information; The memory controller sends a bus request signal to the arbiter according to the request information, and the arbiter sends the bus use right to the memory controller; The memory controller performs a read operation or a write operation on the storage medium according to the address. The data access method according to claim 2, wherein the memory controller performing a read operation or a write operation on the storage medium according to the address comprises: During the read operation, the memory controller reads the first data according to the address, and the processor receives the first data sent by the memory controller; Or, during the writing operation, the memory controller writes the second data sent by the processor to the storage medium according to the address. The data access method according to claim 1, wherein when the requested information is a non-local memory access, based on the address, the processor uses its corresponding arbiter, memory controller And the DMA controller performs a read operation or a write operation on the storage medium, so as to complete the non-local memory access of the processor, including: When the request information is a non-local memory access, the working mode of the processor is a DMA control mode, and the processor sends a second control command to the corresponding DMA controller, the second control command for instructing the DMA controller to obtain the request information; The DMA controller sends a bus request signal to the corresponding arbiter according to the request information, and the arbiter sends the bus use right to the DMA controller; The DMA controller performs a read operation or a write operation on the storage medium through the corresponding memory controller according to the address. The data access method according to claim 4, wherein the DMA controller performs a read operation or a write operation on the storage medium through the corresponding memory controller according to the address, comprising: The DMA controller sends the address to the memory controller, and the memory controller performs a read operation or a write operation on the storage medium according to the address. The data access method according to claim 5, wherein the DMA controller sends the address to the memory controller, and the memory controller performs the processing on the storage medium according to the address. Read or write operations include: When performing a write operation, the DMA controller receives the third data sent by the processor, and sends a bus request signal to the arbiter corresponding to the destination address in the address. After obtaining the right to use the bus , the DMA controller sends the third data to the first memory controller corresponding to the destination address, so that the first memory controller writes the third data to the storage medium ; Or, when the read operation is performed, the DMA controller sends a bus request signal to the corresponding arbiter according to the source address in the address, and after obtaining the right to use the bus, the DMA controller sends the bus request signal to the corresponding arbiter. The source address is sent to the second memory controller corresponding to the source address, the second memory controller reads the fourth data according to the source address, and the DMA controller receives the fourth data data, the processor reads the fourth data through the DMA controller. The data access method according to any one of claims 1 to 6, wherein the processor includes one or more of the following: a central processing unit, a graphics processing unit, and a digital signal processor. A data access system is improved in that the data access system includes a system on chip and a storage medium, the system on chip and the storage medium communicate through a bus, the system on chip includes at least two processors and A respective handling module of each processor, the handling module includes a DMA controller, an arbiter and a memory controller; The processor sends request information, wherein the request information includes an operation type and an address, and the operation type includes a read operation or a write operation; The processor is configured to perform a read operation or a write operation on the storage medium through its corresponding arbiter and memory controller based on the address when the request information is locally accessed to complete Local memory access, when the request information is a non-local memory access, based on the address, read or write to the storage medium through its corresponding arbiter, memory controller and DMA controller input operation to complete non-local memory accesses. The data access system according to claim 8, wherein the system-on-chip and the storage medium are connected by way of wafer stacking. The data access system according to claim 8, wherein the storage medium is a dynamic random access memory.

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