TWI765812B - Ferroelectric capacitor, ferroelectric memory and method for manufacturing same - Google Patents

Abstract

A ferroelectric capacitor, a ferroelectric memory, and a method for manufacturing the same. The ferroelectric memory includes a plurality of memory units arranged in an array. Each of the memory units includes a transistor and the ferroelectric capacitor connected to the transistor. The ferroelectric capacitor includes a first electrode, a second electrode, and a ferroelectric material layer located between the first electrode and the second electrode. At least one of the first electrode or the second electrode is doped with at least one of group V metal elements.

Description

Ferroelectric capacitor, ferroelectric memory and manufacturing method thereof

The present invention relates to the technical field of ferroelectric memory, in particular to a ferroelectric capacitor, a ferroelectric memory and a manufacturing method thereof.

Ferroelectric memory utilizes layers of ferroelectric material to achieve non-volatility. There is a nonlinear relationship between the electric field applied by the ferroelectric material layer and the stored apparent charge, so the ferroelectric material layer can switch polarity under the electric field. The advantages of ferroelectric memory include low power consumption, fast write performance, and high maximum read/write endurance.

In the existing ferroelectric memory, the ferroelectric capacitor of the memory cell usually adopts the structure of electrode-ferroelectric material layer-electrode. In the existing ferroelectric memory, electrode oxidation occurs during the manufacturing process, which is likely to cause the imprinting effect of the ferroelectric material, which affects the performance of the ferroelectric memory. Furthermore, ferroelectric memories made of existing electrode materials have various problems, such as low breakdown voltage and limitation of queue time (Q-Time) in the process.

The purpose of the present invention is to provide a ferroelectric capacitor, a ferroelectric memory and a manufacturing method thereof, which can improve the breakdown voltage of the ferroelectric capacitor of the ferroelectric memory, avoid the problem of uncontrolled electrode oxidation, and make the waiting time in the process. The limitation of time (queue time, Q-time) is solved.

In order to solve the above technical problems, the present invention provides a ferroelectric capacitor, which includes a first electrode, a second electrode and a ferroelectric material layer between the first electrode and the second electrode, wherein the ferroelectric capacitor is At least one of the first electrode and the second electrode is doped with at least one of the fifth group metal elements.

According to one embodiment of the present invention, the Group V metal elements include vanadium, niobium and tantalum.

According to an embodiment of the present invention, the doped Group V metal element is a metal oxide of the Group V metal element.

According to an embodiment of the present invention, the Group V metal element is uniformly distributed in the first electrode or the second electrode.

According to an embodiment of the present invention, the concentration of the fifth group metal element is higher in the region of the first electrode or the second electrode close to the ferroelectric material layer than in other regions.

According to one embodiment of the present invention, the ferroelectric capacitor is a planar capacitor.

According to an embodiment of the present invention, the ferroelectric capacitor is a cylindrical capacitor in which the inner layer is the first electrode, the middle layer is the ferroelectric material layer, and the outermost layer is the second electrode.

According to an embodiment of the present invention, the materials of the first electrode and the second electrode are one or more of the following materials: titanium (Ti), titanium nitride (TiN), titanium silicon nitride (TiSiNx), nitride Titanium aluminum (TiAlNx), titanium carbonitride (TiCNx), tantalum nitride (TaNx), tantalum silicon nitride (TaSiNx), tantalum aluminum nitride (TaAlNx), tungsten nitride (WNx), tungsten silicide (WSix), Tungsten Carbonitride (WCNx), Ruthenium (Ru), Ruthenium Oxide (RuOx), Iridium (Ir), Doped Polysilicon, Transparent Conductive Oxide (TCO), Iridium Oxide (IrOx) and the like the complex.

According to one embodiment of the present invention, the ferroelectric material includes oxygen and one or more of the following materials: a ferroelectric metal, the ferroelectric metal doped with calcium (Ca), strontium (Sr), or barium (Ba), The ferroelectric metal doped with scandium (Sc), yttrium (Y), aluminum (Al), gallium (Ga) or indium (In), and doped with lanthanum (La), cerium (Ce), pyridine (Pr) ), neodymium (Nd), strontium (Pm), samarium (Sm), europium (Eu), gadolinium (Gd), abium (Tb), dysprosium (Dy), γ (Ho), erbium (Er), tin (Tm) ), ytterbium (Yb), or the ferroelectric metal of ytterbium (Lu), and the ferroelectric metal includes zirconium (Zr), hafnium (Hf), titanium (Ti), aluminum (Al), nickel (Ni), and iron ( one or more of Fe).

In order to achieve the aforementioned object, the present invention also provides a ferroelectric memory, which includes a plurality of memory cells arranged in an array, and each memory cell includes a transistor and the aforementioned ferroelectric capacitor connected to the transistor.

In order to achieve the foregoing object, the present invention also provides a method for manufacturing a ferroelectric memory, comprising: Provide semiconductor substrates; forming a transistor on the semiconductor substrate, wherein the transistor includes a gate electrode, a source electrode and a drain electrode; forming a metal interconnection connected to the source or drain of the transistor on the semiconductor substrate; and The aforementioned ferroelectric capacitor is formed over the transistor, and the first electrode or the second electrode of the ferroelectric capacitor is connected to the source or drain of the transistor through the metal interconnection.

At least one of the first electrode and the second electrode of the ferroelectric memory ferroelectric capacitor of the present invention is doped with at least one of the fifth group metal elements, which can effectively improve the breakdown voltage and avoid uncontrolled electrode oxidation problem, and the limitation of the waiting time (queue time, Q-time) in the process is solved.

The content of the present invention will be further described in detail below with reference to the accompanying drawings and specific embodiments.

Please refer to FIG. 1 , which is a schematic diagram of the circuit structure of the ferroelectric memory of the present invention. The ferroelectric memory of the present invention includes several memory cells arranged in an array, and each memory cell includes a transistor T and a ferroelectric capacitor C connected to the transistor T. In one embodiment of the present invention, the transistor T is a CMOS transistor, which includes a gate electrode, a source electrode and a drain electrode. The gate of the transistor T of the ferroelectric memory cell is connected to the word line WL of the ferroelectric memory through a wire. The word line WL is used to control the turn-on or turn-off of the transistor T. The source or drain of the transistor T is connected to one electrode of the ferroelectric capacitor C. The drain or source of the transistor T is connected to the bit line BL of the ferroelectric memory. The other electrode of the ferroelectric capacitor C is connected to the plate line PL of the ferroelectric memory. The turn-on and turn-off of the transistor T is controlled by the word line WL, data is written to the ferroelectric memory by applying different voltages to the ferroelectric capacitor C through the bit line BL and the plate line PL, and the ferroelectric capacitor C is detected by the bit line BL. Stored data to achieve data reading.

In the ferroelectric memory of the present invention, each memory cell may be a 2T2C structure including two transistors T and two ferroelectric capacitors C, and data is realized by comparing the two transistors T of each memory cell with each other read. Each memory cell can also be a 1T1C structure including a transistor T and a ferroelectric capacitor C, and is compared through an additionally set reference cell to achieve data reading.

Please refer to FIG. 2 , which is a schematic structural diagram of the memory unit of the present invention. The memory cell of the present invention includes a transistor 1 , a ferroelectric capacitor 2 , and a metal interconnection 3 connecting the ferroelectric capacitor 2 and the transistor 1 . The ferroelectric capacitor 2 is a planar capacitor.

As shown in FIG. 2 , the transistor 1 of the present invention includes a gate electrode 11 , and a source electrode 12 and a drain electrode 13 formed by doping on a semiconductor substrate. The ferroelectric capacitor 2 includes an upper electrode 21 , a lower electrode 22 , and a ferroelectric material layer 23 between the upper electrode 21 and the lower electrode 22 .

In one embodiment of the present invention, the material of the upper electrode 21 and the lower electrode 22 of the ferroelectric capacitor 2 may be one or more of the following materials: titanium (Ti), titanium nitride (TiN), titanium silicon nitride ( TiSiNx), Titanium Aluminum Nitride (TiAlNx), Titanium Carbonitride (TiCNx), Tantalum Nitride (TaNx), Tantalum Silicon Nitride (TaSiNx), Tantalum Aluminum Nitride (TaAlNx), Tungsten Nitride (WNx), Silicide Tungsten (WSix), Tungsten Carbonitride (WCNx), Ruthenium (Ru), Ruthenium Oxide (RuOx), Iridium (Ir), Doped Polysilicon, Transparent Conductive Oxide (TCO), Iridium Oxide ( IrOx) and its complexes.

In one embodiment of the present invention, the ferroelectric material layer 23 of the ferroelectric capacitor 2 includes a ferroelectric material composed of oxygen and one or more ferroelectric metals. The ferroelectric metal includes one or more of zirconium (Zr), hafnium (Hf), titanium (Ti), aluminum (Al), nickel (Ni) and iron (Fe). The ferroelectric material may be doped with Group II elements such as calcium (Ca), strontium (Sr) or barium (Ba); or doped with Group III elements such as scandium (Sc), yttrium (Y), aluminum (Al), Gallium (Ga) or indium (In); or doped lanthanides such as lanthanum (La), cerium (Ce), pyridine (Pr), neodymium (Nd), samarium (Pm), samarium (Sm), europium (Eu) ), Gd (Gd), Ytterbium (Tb), Dysprosium (Dy), Y (Ho), Erbium (Er), Ytterbium (Tm), Ytterbium (Yb) or Xium (Lu).

Referring to FIG. 3 , in an embodiment of the present invention, the lower electrode 22 of the ferroelectric capacitor 2 is doped with a fifth group metal element 24 in the periodic table, and the fifth group metal element 24 includes vanadium, niobium, tantalum, etc. at least one of the metals.

In this embodiment, the region doped with the fifth group metal element 24 is the region of the lower electrode 22 close to the ferroelectric material layer 23 , or the surface of the lower electrode 22 in contact with the ferroelectric material layer 23 .

In one embodiment, the doping of the fifth group metal element is achieved by doping the oxide of the fifth group metal element, for example, by doping vanadium oxide (VOx) or niobium oxide (Nb2O5) or tantalum oxide (Ta2O5) )to fulfill.

Referring to FIG. 4, in another embodiment of the present invention, the upper electrode 21 and the lower electrode 22 of the ferroelectric capacitor 2 are both doped with the fifth group metal element 24, such as vanadium, niobium, tantalum and other metals. at least one of. Similarly, oxides of the fifth group metal element 24 can also be doped, such as vanadium oxide (VOx), niobium oxide (Nb2O5) or tantalum oxide (Ta2O5). In this embodiment, the fifth group metal element 24 is non-uniformly distributed within the upper electrode 21 and the lower electrode 22 , wherein the upper electrode 21 and the lower electrode 22 are close to the fifth group metal element 24 in the region of the ferroelectric material layer 23 The concentration is higher than the concentration of the fifth group metal element 24 in the regions of the upper electrode 21 and the lower electrode 22 away from the ferroelectric material layer 23 .

Referring to FIG. 5, in yet another embodiment of the present invention, both the upper electrode 21 and the lower electrode 22 of the ferroelectric capacitor 2 are doped with a fifth group metal element 24, such as vanadium, niobium, tantalum and other metals. at least one of. Similarly, oxides of the fifth group metal element 24 can also be doped, such as vanadium oxide (VOx), niobium oxide (Nb2O5) or tantalum oxide (Ta2O5). In this embodiment, the Group V metal element 24 is uniformly distributed in the upper electrode 21 and the lower electrode 22 .

Please refer to FIG. 6 , which is a schematic structural diagram of a ferroelectric memory cell according to another embodiment of the present invention. The memory cell includes a transistor 1 and a ferroelectric capacitor 5 connected to the transistor 1 by a conductive interconnect 4 . In this embodiment, the ferroelectric capacitor 5 is a three-dimensional cylindrical capacitor. Please refer to FIGS. 7 and 8 , wherein FIG. 7 is a three-dimensional schematic diagram of the ferroelectric capacitor 5 shown in FIG. 6 , and FIG. 8 is a cross-sectional schematic diagram of the ferroelectric capacitor 5 shown in FIG. 7 . As shown in FIG. 7 and FIG. 8 , the ferroelectric capacitor 5 includes a first electrode 51 (upper electrode) in an inner layer, a second electrode 52 (lower electrode) in an outer layer, and a first electrode 51 and a second electrode 52 located between the first electrode 51 and the second electrode 52 . The ferroelectric material layer 53 in between. Similarly, the materials of the first electrode 51 and the second electrode 52 of the ferroelectric capacitor 5 can be one or more of the following materials: titanium (Ti), titanium nitride (TiN), titanium silicon nitride (TiSiNx), Titanium Aluminum Nitride (TiAlNx), Titanium Carbonitride (TiCNx), Tantalum Nitride (TaNx), Tantalum Silicon Nitride (TaSiNx), Tantalum Aluminum Nitride (TaAlNx), Tungsten Nitride (WNx), Tungsten Silicon Nitride (WSix) ), tungsten carbonitride (WCNx), ruthenium (Ru), ruthenium oxide (RuOx), iridium (Ir), doped polysilicon, Transparent Conductive Oxide (TCO), iridium oxide (IrOx) and its complexes.

Likewise, the ferroelectric material layer of the ferroelectric capacitor 5 of this embodiment includes a ferroelectric material composed of oxygen and one or more ferroelectric metals, the ferroelectric metals include zirconium (Zr), hafnium (Hf), titanium One or more of (Ti), aluminum (Al), nickel (Ni) and iron (Fe). The ferroelectric material may be doped with Group II elements such as calcium (Ca), strontium (Sr) or barium (Ba); or doped with Group III elements such as scandium (Sc), yttrium (Y), aluminum (Al), Gallium (Ga) or indium (In); or doped lanthanides such as lanthanum (La), cerium (Ce), pyridine (Pr), neodymium (Nd), samarium (Pm), samarium (Sm), europium (Eu) ), Gd (Gd), Ytterbium (Tb), Dysprosium (Dy), Y (Ho), Erbium (Er), Ytterbium (Tm), Ytterbium (Yb) or Xium (Lu).

Referring to the embodiments shown in FIGS. 3 to 5 , at least one of the first electrode 51 and the second electrode 52 of the three-dimensional ferroelectric capacitor 5 shown in FIG. 6 is doped with the first electrode in the periodic table of elements. Group 5 metal elements, such as at least one of metals such as vanadium, niobium and tantalum. Likewise, oxides of the Group V metal elements such as vanadium oxide (VOx), niobium oxide (Nb2O5) or tantalum oxide (Ta2O5) can also be doped. Only one of the first electrode 51 and the second electrode 52 may be doped, or both the first electrode 51 and the second electrode 52 may be doped. The Group V metal element may be uniformly distributed in the first electrode 51 and/or the second electrode 52 , or may be non-uniformly distributed in the first electrode 51 and/or the second electrode 52 . For example, the doping concentration of the region of the first electrode 51 and/or the second electrode 52 close to the ferroelectric material layer 53 or the surface in contact with the ferroelectric material layer 53 is higher than that of the first electrode 51 and/or the second electrode 52 Doping concentrations in other regions.

The present invention also provides a method for manufacturing the ferroelectric memory, comprising: Provide semiconductor substrates; forming a transistor on the semiconductor substrate, wherein the transistor includes a gate electrode, a source electrode and a drain electrode; A step of forming a metal interconnection connected to the source or drain of the transistor on the semiconductor substrate; specifically, this step may include depositing a dielectric layer over the transistor on the semiconductor substrate, forming a via in the dielectric layer a hole, and forming the metal interconnect within the via; and The ferroelectric capacitor is formed over the transistor, and an electrode of the ferroelectric capacitor is connected to the source or drain of the transistor through the metal interconnect; specifically, this step includes at least one electrode of the ferroelectric capacitor. One electrode is doped with at least one of Group V metal elements.

The method of forming the ferroelectric capacitor differs depending on whether the ferroelectric capacitor is a planar capacitor or a three-dimensional three-dimensional capacitor. The method for forming a planar ferroelectric capacitor may specifically include: forming the metal interconnection portion on the semiconductor substrate, depositing a lower electrode of the ferroelectric capacitor on the dielectric layer formed with the metal interconnection portion, and performing a process on the lower electrode. doping of a Group 5 metal element, forming a ferroelectric material layer on the lower electrode, and forming an upper electrode on the ferroelectric material layer. If necessary, the method may further include: doping the upper electrode with a Group V metal element, and forming individual ferroelectric capacitors separated from each other by means of chemical mechanical polishing or photomask etching.

The method for forming a three-dimensional ferroelectric capacitor may specifically include: forming the metal interconnection on the semiconductor substrate, depositing a second dielectric layer on the dielectric layer formed with the metal interconnection, and depositing a second dielectric layer on the second dielectric layer. A cylindrical deep hole is formed by intra-layer etching, and the lower electrode of the ferroelectric capacitor, the ferroelectric material layer and the upper electrode are sequentially deposited in the cylindrical deep hole (refer to FIG. 8 ). When the lower electrode is used, the lower electrode and the lower electrode are doped with metal elements of Group V, and a single ferroelectric capacitor separated from each other is formed by means of chemical mechanical polishing or photomask etching.

The above description is only a description of the preferred embodiments of the present invention, and does not limit the scope of the present invention. Any changes and modifications made by those with ordinary knowledge in the technical field of the present invention according to the above disclosure belong to the scope of the patent application of the present invention.

1: Transistor 11: Gate 12: Source 13: Drain 2: Ferroelectric capacitors 21: Upper electrode 22: Lower electrode 23: Ferroelectric material layer 24: Group V metal elements 3: Metal Interconnects 4: Conductive Interconnects 5: Ferroelectric capacitors 51: The first electrode 52: Second electrode 53: Ferroelectric material layer BL: bit line C: capacitor PL: Board Line T: Transistor WL: word line

1 is a schematic diagram of a circuit structure of a ferroelectric memory according to an embodiment of the present invention. [ FIG. 2 ] is a schematic structural diagram of a ferroelectric memory cell according to an embodiment of the present invention, wherein the ferroelectric capacitor of the ferroelectric memory cell is a planar capacitor. [ Fig. 3 ] is a first schematic diagram of the electrode doping concentration distribution of the ferroelectric capacitor of Fig. 2 . FIG. 4 is a second schematic diagram of the electrode doping concentration distribution of the ferroelectric capacitor of FIG. 2 . FIG. 5 is a third schematic diagram of the electrode doping concentration distribution of the ferroelectric capacitor of FIG. 2 . 6 is a schematic structural diagram of a ferroelectric memory cell according to another embodiment of the present invention, wherein the ferroelectric capacitor of the ferroelectric memory cell is a cylindrical three-dimensional capacitor. [ Fig. 7] Fig. 7 is a schematic perspective view of the ferroelectric capacitor of Fig. 6 . [ Fig. 8] Fig. 8 is a schematic cross-sectional view of the ferroelectric capacitor of Fig. 7 .

21: Upper electrode 22: Lower electrode 23: Ferroelectric material layer 24: Group V metal elements

Claims (9)

A ferroelectric capacitor comprising a first electrode, a second electrode and a ferroelectric material layer between the first electrode and the second electrode, wherein at least one of the first electrode and the second electrode of the ferroelectric capacitor One is doped with at least one of Group 5 metal elements, and the Group 5 metal elements include vanadium, niobium, tantalum, vanadium oxide, niobium oxide, and tantalum oxide. The ferroelectric capacitor of claim 1, wherein the Group V metal element is uniformly distributed in the first electrode or the second electrode. The ferroelectric capacitor of claim 1, wherein the concentration of the fifth group metal element in a region of the first electrode or the second electrode close to the ferroelectric material layer is higher than that of other regions. The ferroelectric capacitor of claim 1, wherein the ferroelectric capacitor is a planar capacitor. The ferroelectric capacitor of claim 1, wherein the ferroelectric capacitor is a cylindrical capacitor whose inner layer is the first electrode, the middle layer is a ferroelectric material layer, and the outermost layer is the second electrode. The ferroelectric capacitor of claim 1, wherein the materials of the first electrode and the second electrode are one or more of the following materials: titanium (Ti), titanium nitride (TiN), titanium silicon nitride (TiSiNx), Titanium Aluminum Nitride (TiAlNx), Titanium Carbonitride (TiCNx), Tantalum Nitride (TaNx), Tantalum Silicon Nitride (TaSiNx), Tantalum Aluminum Nitride (TaAlNx), Tungsten Nitride (WNx), Tungsten Silicon Nitride (WSix) ), tungsten carbonitride (WCNx), ruthenium (Ru), ruthenium oxide (RuOx), iridium (Ir), doped polysilicon, Transparent Conductive Oxide (TCO), iridium oxide (IrOx) and its complexes. The ferroelectric capacitor of claim 1, wherein the layer of ferroelectric material comprises oxygen and one or more of the following materials: a ferroelectric metal, the iron doped with calcium (Ca), strontium (Sr), or barium (Ba). Electric metals, the ferroelectric metals doped with scandium (Sc), yttrium (Y), aluminum (Al), gallium (Ga), or indium (In), and the ferroelectric metals doped with lanthanum (La), cerium (Ce), Sodium (Pr), Neodymium (Nd), Sodium (Pm), Samarium (Sm), the ferroelectric metal of europium (Eu), gadolinium (Gd), abium (Tb), dysprosium (Dy), γ (Ho), erbium (Er), tin (Tm), ytterbium (Yb) or ytterbium (Lu), And the ferroelectric metal includes one or more of zirconium (Zr), hafnium (Hf), titanium (Ti), aluminum (Al), nickel (Ni) and iron (Fe). A ferroelectric memory, comprising a plurality of memory cells arranged in an array, each memory cell comprising a transistor and a ferroelectric capacitor according to any one of claims 1-7 connected to the transistor. A method of manufacturing a ferroelectric memory, comprising: providing a semiconductor substrate; forming a transistor on the semiconductor substrate, wherein the transistor includes a gate electrode, a source electrode and a drain electrode; forming a connection with the transistor on the semiconductor substrate and a ferroelectric capacitor as claimed in any one of claims 1-7 is formed over the transistor, the first electrode or the second electrode of the ferroelectric capacitor passing through the metal The interconnect is connected to the source or drain of the transistor.

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