TWI765529B - semiconductor memory device - Google Patents

Abstract

Embodiments provide a semiconductor memory device capable of setting a select gate line to a desired voltage at high speed. The semiconductor memory device of the embodiment includes: a plurality of memory cells; word lines connected to gates of the plurality of memory cells; and bit lines connected to one end of the plurality of memory cells through a plurality of selection gates respectively The pole transistor is electrically connected to one end of the above-mentioned plural memory cells; 2 external selection gate lines are respectively connected to the gates of the 2 above-mentioned selective gate transistors at both ends of the block; more than one An internal selection gate line, which is connected to the gates of one or more of the selection gate transistors other than the two ends of the block; and a voltage generating circuit, which reads out the data recorded in the plurality of memory cells. , the voltage supply to the external selection gate line and the internal selection gate line can be individually controlled.

Description

semiconductor memory device

Embodiments of the present invention relate to a semiconductor memory device.

In recent years, semiconductor memory devices such as NAND (Not And) type flash memory tend to realize three-dimensional structure due to the requirements of miniaturization and large capacity. In addition, in NAND-type flash memory, the memory cell transistor is sometimes used as an SLC (Single Level Cell) capable of holding 1-bit (two-value) data. Cell transistors are composed of MLC (Multi Level Cell) that can hold 2-bit (4-value) data, TLC (Triple Level Cell, triple-level cell) that can hold 3-bit (8-value) data, or QLC (Quad Level Cell) capable of holding 4-bit (16-value) data.

When reading data from such a memory cell transistor, a plurality of voltages must be prepared and the voltage supplied to the memory cell transistor must be switched. Therefore, in order to increase the readout speed, it is necessary to speed up the transition to the desired target voltage.

This embodiment provides a semiconductor memory device capable of setting a select gate line to a desired voltage at high speed.

The semiconductor memory device of the embodiment includes: a plurality of memory cells; word lines connected to gates of the plurality of memory cells; and bit lines connected to one end of the plurality of memory cells through a plurality of selection gates respectively The pole transistor is electrically connected to one end of the plurality of memory cells; 2 external selection gate lines, which are respectively connected to the gates of the 2 above-mentioned selection gate transistors at both ends of the block; more than one an internal selection gate line, which is connected to the gates of one or more of the selection gate transistors other than the two ends of the block; and a voltage generating circuit, which is read and recorded in the plurality of memory cells. The voltage supply to the above-mentioned external selection gate lines and internal selection gate lines can be individually controlled during data recording.

Hereinafter, embodiments of the present invention will be described in detail with reference to the drawings. (first embodiment)

In this embodiment, the resistance value of the supply circuit for the overdrive voltage can be changed according to the type of the gate line selected by supplying an overdrive voltage higher than the target voltage to be targeted in the voltage generation circuit, regardless of the gate selection. Regardless of the type of line, the variation of the voltage applied to the selected gate line can be uniformized, and the target voltage can be reached in a short time. (The composition of the memory system)

FIG. 1 is a block diagram showing an example of the configuration of the memory system according to the embodiment. The memory system of this embodiment includes a memory controller 1 and a non-volatile memory 2 . The memory system can be connected to the host computer. The host is, for example, an electronic device such as a personal computer and a mobile terminal.

The non-volatile memory 2 is a semiconductor memory device that non-volatilely stores data, and includes, for example, a NAND flash memory. In this embodiment, the non-volatile memory 2 is used as a NAND memory having a memory cell transistor capable of storing 3 bits per memory cell transistor, that is, a 3 bit/Cell (TLC: Triple Level Cell) NAND memory body is described, but it is not limited to this. The nonvolatile memory 2 is three-dimensionalized.

The memory controller 1 controls the writing of data to the non-volatile memory 2 according to the write request from the host. In addition, the memory controller 1 controls the readout of data from the non-volatile memory 2 according to the readout request from the host. The memory controller 1 includes a random access memory (RAM) 11 , a processor 12 , a host interface 13 , an Error Check and Correct (ECC) circuit 14 and a memory interface 15 . The RAM 11 , the processor 12 , the host interface 13 , the ECC circuit 14 and the memory interface 15 are connected to each other by the internal bus bar 16 .

The host interface 13 outputs requests received from the host, write data as user data, and the like to the internal bus 16 . In addition, the host interface 13 sends the user data read from the non-volatile memory 2, the response from the processor 12, and the like to the host.

The memory interface 15 controls the process of writing user data to the non-volatile memory 2 and the process of reading from the non-volatile memory 2 based on the instructions of the processor 12 .

The processor 12 collectively controls the memory controller 1 . The processor 12 is, for example, a CPU (Central Processing Unit, central processing unit), an MPU (Micro Processing Unit, microprocessor) or the like. When the processor 12 receives a request from the host via the host interface 13, it performs control according to the request. For example, the processor 12 instructs the memory interface 15 to write user data and parity to the non-volatile memory 2 according to a request from the host. In addition, the processor 12 instructs the memory interface 15 to read the user data and the parity from the non-volatile memory 2 according to the request from the host.

The processor 12 determines a memory area (hereinafter, referred to as a memory area) on the non-volatile memory 2 for the user data stored in the RAM 11 . User data is stored in the RAM 11 via the internal bus 16 . The processor 12 implements the determination of the memory area for data in units of pages, ie, page data, which is the unit of writing. In this specification, the user data stored in one page of the non-volatile memory 2 is defined as unit data. The unit data are, for example, encoded as code words and stored in the non-volatile memory 2 .

Again, coding is not necessary. The memory controller 1 may store the unit data in the non-volatile memory 2 without encoding, but FIG. 1 shows a configuration in which encoding is performed as an example of the configuration. When the memory controller 1 does not perform encoding, the page data is consistent with the unit data. In addition, one codeword may be generated based on one unit data, or one codeword may be generated based on divided data obtained by dividing the unit data. Alternatively, one codeword may be generated using a plurality of unit data.

The processor 12 determines, for each unit of data, a memory area of the non-volatile memory 2 to be a write target. Physical addresses are allocated to the memory area of the non-volatile memory 2 . The processor 12 uses the physical address to manage the memory area to which the unit data is written. The processor 12 specifies the physical address of the determined memory area and instructs the memory interface 15 to write user data to the non-volatile memory 2 . The processor 12 manages the correspondence between the logical addresses of the user data (the logical addresses managed by the host) and the physical addresses. When receiving a read request including a logical address from the host, the processor 12 specifies a physical address corresponding to the logical address, specifies the physical address, and instructs the memory interface 15 to read user data.

The ECC circuit 14 encodes the user data stored in the RAM 11 to generate a codeword. Also, the ECC circuit 14 decodes the codeword read from the non-volatile memory 2 .

The RAM 11 temporarily stores the user data received from the host until it is stored in the non-volatile memory 2, or temporarily stores the data read from the non-volatile memory 2 until it is sent to the host. The RAM 11 is, for example, a general-purpose memory such as SRAM (Static Random Access Memory, static random access memory) or DRAM (Dynamic Random Access Memory, dynamic random access memory).

FIG. 1 shows a configuration example in which the memory controller 1 includes the ECC circuit 14 and the memory interface 15, respectively. However, the ECC circuit 14 can also be built into the memory interface 15 . In addition, the ECC circuit 14 may also be built in the non-volatile memory 2 .

When a write request is received from the host, the memory controller 1 operates as follows. The processor 12 temporarily stores the written data in the RAM 11 . The processor 12 reads out the data stored in the RAM 11 and inputs it to the ECC circuit 14 . The ECC circuit 14 encodes the input data and assigns the code word to the memory interface 15 . The memory interface 15 writes the input code word to the non-volatile memory 2 .

When a read request is received from the host, the memory controller 1 operates as follows. The memory interface 15 assigns the codeword read from the non-volatile memory 2 to the ECC circuit 14 . The ECC circuit 14 decodes the input codeword, and stores the decoded data in the RAM 11 . The processor 12 sends the data stored in the RAM 11 to the host through the host interface 13 . (Constitution of non-volatile memory)

FIG. 2 is a block diagram showing a configuration example of the nonvolatile memory of the present embodiment. The non-volatile memory 2 includes a logic control circuit 21 , an input/output circuit 22 , a memory cell array 23 , a sense amplifier 24 , a column decoder 25 , a register 26 , a sequencer 27 , a voltage generation circuit 28 , and an input/output circuit. A pad group 32 , a logic control pad group 34 , and a power input terminal group 35 .

The memory cell array 23 includes a plurality of blocks. Each of the plurality of blocks BLK includes a plurality of memory cell transistors (memory cells). The memory cell array 23 is provided with a plurality of bit lines, a plurality of word lines, and source lines in order to control the voltage applied to the memory cell transistors. The specific structure of the block BLK will be described below.

The I/O pad group 32 includes a plurality of terminals corresponding to the signal DQ<7:0> and the data strobe signals DQS and /DQS in order to transmit and receive signals including data to and from the memory controller 1 . (solder pads).

The logic control pad group 34 is provided with the chip enable signal /CE, the command latch enable signal CLE, the address latch enable signal ALE, the write enable signal, and the A plurality of terminals (pads) corresponding to the input enable signal /WE, the read enable signal RE, /RE, and the write protection signal /WP.

Signal /CE enables the selection of non-volatile memory 2. Signal CLE enables latching of the command sent in the form of signal DQ in the command register. Signal ALE enables latching of the address sent as signal DQ in the address register. Signal WE enables writing. Signal RE enables readout. Signal WP inhibits writing and erasing. The signal R/B indicates whether the non-volatile memory 2 is in a ready state (a state in which an external command can be accepted) or a busy state (a state in which it cannot accept an external command). The memory controller 1 can know the state of the non-volatile memory 2 by receiving the signal R/B.

The power input terminal group 35 includes a plurality of terminals for inputting power supply voltages Vcc, VccQ, Vpp, and ground voltage Vss in order to supply various operating power sources to the nonvolatile memory 2 from the outside. The power supply voltage Vcc is a circuit power supply voltage generally given from the outside as an operating power supply, for example, an input voltage of about 3.3 V. The power supply voltage VccQ is input with a voltage of, for example, 1.2 V. The power supply voltage VccQ is used for transmitting and receiving signals between the memory controller 1 and the non-volatile memory 2 . The power supply voltage Vpp is a power supply voltage higher than the power supply voltage Vcc, such as an input voltage of 12 V.

The logic control circuit 21 and the input/output circuit 22 are connected to the memory controller 1 via the NAND bus. The input-output circuit 22 transmits and receives signals DQ (eg, DQ0 to DQ7 ) with the memory controller 1 via the NAND bus.

The logic control circuit 21 receives external control signals (eg, chip enable signal /CE, command latch enable signal CLE, address latch enable signal ALE, write enable signal) from the memory controller 1 via the NAND bus. signal /WE, read enable signal RE, /RE, and write protect signal /WP). The "/" appended to the signal name indicates that the low level is valid. In addition, the logic control circuit 21 transmits the ready/busy signal/RB to the memory controller 1 via the NAND bus.

The register 26 includes an instruction register, an address register, a status register, and the like. The instruction scratchpad temporarily holds instructions. The address scratchpad holds addresses temporarily. The state register temporarily holds the data required for the operation of the non-volatile memory 2 . The temporary memory 26 is constituted by, for example, SRAM.

The sequencer 27 receives commands from the register 26 and controls the non-volatile memory 2 according to the sequence based on the commands.

The voltage generation circuit 28 receives a power supply voltage from the outside of the non-volatile memory 2, and uses the power supply voltage to generate a plurality of voltages required for a write operation, a read operation, and an erase operation. The voltage generation circuit 28 supplies the generated voltage to the memory cell array 23, the sense amplifier 24, the column decoder 25, and the like.

The column decoder 25 receives the column address from the register 26 and decodes the column address. The column decoder 25 performs a word line selection operation based on the decoded column address. Furthermore, the selected block of the column decoder 25 transmits a plurality of voltages required for the write operation, the read operation, and the erase operation.

The sense amplifier 24 receives the row address from the register 26 and decodes the row address. The sense amplifier 24 has a group of sense amplifier cells 24A connected to the bit lines, and the group of sense amplifier cells 24A selects any one of the bit lines based on the decoded row address. In addition, the sense amplifier unit group 24A detects and amplifies the data read from the memory cell transistor to the bit line when reading data. In addition, the sense amplifier unit group 24A transmits the written data to the bit line when data is written.

The sense amplifier 24 has a data register 24B. When the data is read out, the data register 24B temporarily holds the data detected by the sense amplifier unit group 24A and transmits the data to the input/output circuit 22 in series. In addition, when writing data, the data register 24B temporarily holds the data serially transmitted from the I/O circuit 22 and transmits it to the sense amplifier unit group 24A. The data register 24B is composed of SRAM or the like. (Block composition of memory cell array)

FIG. 3 is a diagram showing a configuration example of a block of a NAND memory cell array 23 having a three-dimensional structure. FIG. 3 shows one block BLK among a plurality of blocks constituting the memory cell array 23 . Other blocks of the memory cell array also have the same structure as that shown in FIG. 3 . Furthermore, the present embodiment can also be applied to a memory cell array having a two-dimensional structure.

As shown in the figure, the block BLK includes, for example, five string units (SU0 to SU4). Also, each string unit SU includes a plurality of NAND strings NS. Each of the NAND strings NS here includes eight memory cell transistors MT (MT0-MT7), and select gate transistors ST1, ST2. Furthermore, the number of memory cell transistors MT included in the NAND string NS is 8 here, but is not limited to 8, for example, it can also be 32, 48, 64, 96, etc. . The selection gate transistors ST1 and ST2 are represented as one transistor on the electrical circuit, but the structure can also be the same as that of the memory cell transistor. Also, for example, in order to improve the off characteristic, a plurality of selection gate transistors may be used as the selection gate transistors ST1 and ST2, respectively. Furthermore, a dummy cell transistor may also be provided between the memory cell transistor MT and the selection gate transistors ST1 and ST2.

The memory cell transistor MT is arranged in series connection between the selection gate transistors ST1 and ST2. The memory cell transistor MT7 at one end is connected to the selection gate transistor ST1, and the memory cell transistor MT0 at the other end is connected to the selection gate transistor ST2.

The gates of the selection gate transistors ST1 of the string units SU0 to SU4 are respectively connected to the selection gate lines SGD0 to SGD4 (hereinafter, referred to as selection gate lines SGD when there is no need to distinguish them). On the other hand, the gate of the selection gate transistor ST2 is commonly connected to the same selection gate line SGS among the plurality of string units SU in the same block BLK. In addition, the gates of the memory cell transistors MT0 to MT7 in the same block BLK are respectively connected to the word lines WL0 to WL7 in common. That is, the word lines WL0 to WL7 and the selection gate line SGS are connected in common among the plurality of string units SU0 to SU4 in the same block BLK. On the other hand, the selection gate line SGD is still in the same block BLK even if it is in the same block BLK. It is independent for each string unit SU0 to SU4.

The gate electrodes of the memory cell transistors MT0 ˜ MT7 constituting the NAND string NS are respectively connected with the word lines WL0 ˜ WL7 . The gates of the memory cell transistors MTi in the same row in the block BLK are connected to the same word line WLi. In addition, in the following description, the NAND string NS may be abbreviated as "string" in some cases.

Each NAND string NS is connected to a corresponding bit line. Therefore, each memory cell transistor MT is connected to the bit line via the select gate transistor ST or other memory cell transistors MT included in the NAND string NS. As described above, the data of the memory cell transistors MT in the same block BLK are erased together. On the other hand, the reading and writing of data are performed in units of memory cell groups MG (or in units of pages). In this specification, a plurality of memory cell transistors MT connected to one word line WLi and belonging to one string unit SU are defined as a memory cell group MG. In this embodiment, the non-volatile memory 2 is a TLC NAND memory capable of holding 3-bit (8-value) data. Therefore, one memory cell group MG can hold 3 pages of data. The 3 bits that each memory cell transistor MT can hold correspond to the 3 pages respectively. (write action)

In the case of writing multi-value data to the memory cell transistor MT, the threshold voltage of the memory cell transistor MT is set to a value corresponding to the data value. When the programming voltage VPGM and the bit line voltage Vbl are applied to the memory cell transistor MT, electrons are injected into the charge storage film of the memory cell transistor MT, thereby increasing the threshold voltage. By increasing the programming voltage VPGM, the injection amount of electrons can be increased, thereby increasing the threshold voltage of the memory cell transistor MT. However, due to the difference of the memory cell transistors MT, even if the same programming voltage VPGM is applied, the injection amount of electrons is still different for each memory cell transistor MT. The injected electrons are held until the erase action is performed. Therefore, while gradually increasing the programming voltage VPGM, a plurality of programming operations and verifications are performed so as not to exceed the allowable threshold voltage range (hereinafter, referred to as the target region) for the threshold voltage set for each memory cell transistor MT. Action (loop).

The verification operation is a read operation performed as a part of the write operation. FIG. 4 is a diagram showing a potential change of each wiring in a writing operation (programming operation). Furthermore, the voltages shown in FIG. 4 are also generated by the voltage generating circuit 28 controlled by the sequencer 27 .

The programming action is performed according to the programming voltages and bit line voltages applied to the word lines and bit lines. The block BLK to which a voltage is not applied to the word lines (selected WL and non-selected WL in FIG. 4 ) is a non-selected BLK (lower row in FIG. 4 ) that is not the target of writing. In addition, since the bit line voltage is applied to the memory cell transistor MT by turning on the selection gate transistor ST1 connected to the bit line BL, it is not applied to the block BLK (selection BLK) to be written. The string unit SU of the selected gate line SGD is a non-selected SU that is not the target of writing (the middle section of FIG. 4 ). Furthermore, regarding the non-selection SU of the selection BLK (the middle part of FIG. 4 ), before the programming voltage VPGM is applied, the selection gate line SGD may be set to, for example, 5 V, and the selection gate transistor ST1 may be turned on.

Regarding the write target block BLK (select BLK) of the write target string unit SU (select SU) (the upper part of FIG. 4 ), before applying the programming voltage VPGM, as shown on the left side of the upper part of FIG. 4 , the select gate The pole line SGD is, for example, 5 V, and turns on the selection gate transistor ST1. In addition, during the programming operation, the gate line SGS is selected to be, for example, 0 V. Therefore, the selection gate transistor ST2 is turned off. On the other hand, as shown on the right side of the upper section of FIG. 4 , when the programming voltage VPGM is applied, the selection gate line SGD is set to be, for example, 2.5 V. Thereby, the conduction and non-conduction states of the selection gate transistor ST1 are determined by the bit line voltage of the bit line BL connected to the selection gate transistor ST1.

As described above, the sense amplifier 24 transmits data to the bit line BL. The ground voltage Vss, eg, 0 V, is applied as the bit line voltage Vbl_L to the bit line BL to which the "0" data is assigned. A write-inhibit voltage Vinhibit (eg, 2.5 V) is applied to the bit line to which "1" data is assigned as the BL bit line voltage Vbl_H. Therefore, when the programming voltage VPGM is applied, the select gate transistor ST1 connected to the bit line BL assigned with "0" data is turned on, and the select gate transistor ST1 connected to the bit line BL assigned "1" data ST1 ends. The memory cell transistor MT connected to the OFF selection gate transistor ST1 becomes write inhibited.

The memory cell transistor MT connected to the selection gate transistor ST1 in an on state performs injection of electrons into the charge storage film according to the voltage applied to the word line WL. The memory cell transistor MT connected to the word line WL to which the voltage VPASS is applied as the word line voltage is turned on regardless of the threshold voltage, but the injection of electrons into the charge storage film is not performed. On the other hand, the memory cell transistor MT connected to the word line WL to which the program voltage VPGM is applied as the word line voltage performs injection of electrons into the charge storage film according to the program voltage VPGM.

That is, the column decoder 25 selects any word line WL in the selected block BLK, applies the programming voltage VPGM to the selected word line, and applies the voltage VPASS to the other word lines (unselected word lines) WL. The programming voltage VPGM is a high voltage for injecting electrons into the charge storage film by the tunneling phenomenon, VPGM>VPASS. By using the column decoder 25 to control the voltage of the word line WL, and using the sense amplifier 24 to supply data to the bit line BL, the writing operation (programming) to each cell transistor MT of the memory cell array 23 is performed. action). (read action)

The readout of data from the multi-valued memory cell transistors is performed by applying a readout voltage to the selected word line WL using the column decoder 25, and using the sense amplifier 24 to read out bits to bits. The data sensing of the element line BL determines whether the read data is "0" or "1". Furthermore, in order to turn on the cell transistors connected to the unselected word lines WL, the column decoder 25 applies a voltage VREAD that is sufficiently high to turn on the respective memory cell transistors to the unselected word lines WL. Furthermore, regarding the adjacent word lines, in order to facilitate the conduction of the memory cell transistors connected to the adjacent word lines, a slightly higher voltage VREADK may be applied than the voltage VREAD.

Further, the column decoder 25 applies a voltage for turning on the selection gate transistor ST1 to the selection gate line SGD (hereinafter, referred to as SGD_sel) of the string unit (selection string unit) constituting the read target in the string unit SU VSG_sel applies a voltage VSG_usel for turning off the selection gate transistor ST1 to the selection gate line SGD (hereinafter, referred to as SGD_usel) constituting a string cell (unselected string cell) that is not a read target.

The column decoder 25 applies the read voltage to the selected word line, and applies the voltage VREAD or VEREDK to the unselected word line. During the readout operation, the sense amplifier 24 fixes the bit line BL to a fixed voltage (eg, 0.5 V), and charges the unillustrated sense node SEN inside the sense amplifier unit group 24A as a bit cell. The voltage of the line BL is high at the prescribed precharge voltage Vpre. In this state, the logic control circuit 21 connects the sensing node SEN to the bit line BL. Therefore, a current flows from the sensing node SEN to the bit line BL, and the voltage of the sensing node SEN gradually decreases.

The voltage of the sense node SEN varies according to the state of the threshold voltage of the memory cell transistor connected to the corresponding bit line BL. That is, when the threshold voltage of the memory cell transistor is lower than the readout voltage, the memory cell transistor is turned on, a larger cell current flows to the memory cell transistor, and the voltage of the sensing node SEN decreases faster. In addition, when the threshold voltage of the memory cell transistor is higher than the readout voltage, the memory cell transistor is in an off state, and the cell current flowing to the memory cell transistor is small, or no cell current flows to the memory cell transistor to sense. The speed at which the voltage of the node SEN decreases becomes slower.

The speed difference of the voltage drop of the sensing node SEN is used to determine the writing state of the memory cell transistor, and the result is stored in the data latch circuit. For example, it is determined whether the voltage of the sensing node SEN is a low level (hereinafter, "L") or a high level at the first time point when the discharge starts to discharge the electric charge of the sensing node SEN after a predetermined first period. (hereinafter, "H"). For example, when the threshold voltage of the memory cell transistor is lower than the readout voltage, the memory cell transistor is completely turned on, and a relatively large cell current flows to the memory cell transistor. Therefore, the voltage of the sensing node SEN drops rapidly, and the voltage drop amount is relatively large, and at the first time point, the sensing node SEN becomes "L".

Furthermore, when the threshold voltage of the memory cell transistor is higher than the readout voltage, the memory cell transistor is in an off state, and the cell current flowing to the memory cell transistor is very small, or no cell current flows to the memory cell transistor. Therefore, the voltage of the sensing node SEN decreases very slowly, and the voltage drop is relatively small. At the first time point, the sensing node SEN is maintained at "H".

In this way, by using the column decoder 25 to apply the readout voltage to the selected word line, while monitoring the state of the sense node SEN by the sense amplifier circuit 32, it is determined that the threshold voltage of the cell transistor is higher than the readout voltage still lower than the readout voltage. Therefore, by setting the voltage between the respective levels as the read voltage and applying it to the selected word line WL, the level of each memory cell transistor can be determined, and the data allocated to each level can be read out.

For example, by allocating data to 8 target areas of the TLC, 3-bit data can be stored in each memory cell transistor in the TLC. Write to each memory cell transistor at any level of Er, A, B, . Cell transistor data values. (Select gate line SGD)

FIG. 5 is an explanatory diagram for explaining each selection gate line SGD in one block BLK. FIG. 5 shows the planar shape of a part of the block BLK on the left side of the paper, and the cross-sectional shape cut along the line A-A is shown on the right side of the paper. The circles in FIG. 5 represent the memory holes 334 that form the NAND strings. The insulating layer 351 separates one block BLK shown in FIG. 5 from the other blocks BLK. The example of FIG. 5 shows an example in which five string units SU0 to SU4 each including five selection gate lines SGD0 to SGD4 separated by an insulating layer 352 are formed in one block BLK. In the example on the right side of FIG. 5 , the insulating layer 352 is extended to the selection gate lines SGD of the three layers and separates the selection gate lines SGD0 to SGD4 from each other.

A plurality of memory holes 334 constituting NAND strings are arranged in one string unit. The number of NAND strings (the number of memory holes) in one string unit is extremely large (only 16 are shown in FIG. 5 ). On the other hand, the memory holes 334 are arranged in a zigzag manner. Each memory hole 334 in a string unit is connected to the bit lines BL0, BL1, . . Furthermore, in the left side of FIG. 5, considering the easy-to-see diagram, only a part of the bit line BL and a part of the contact plug 339 are shown.

As shown in FIG. 5 , the bit lines BL0 , BL1 , . . . are respectively connected to one memory hole 334 for each string through the contact plugs 339 . Furthermore, in order to connect the bit line BL to one memory hole 334 of each string, the positions of the contact plugs 339 are staggered in a direction orthogonal to the extending direction of the bit line BL.

On the substrate 330, a plurality of NAND strings NS are formed. That is, on the substrate 330, a selection gate line SGS, a plurality of word lines WL, and a plurality of selection gate lines SGD are laminated through an insulating film. Furthermore, a memory hole 334 is formed through the selection gate line SGS, the word line WL, and the selection gate line SGD to reach the substrate 330 . On the side of the memory hole 334 , a blocking insulating film (not shown), a charge storage film (charge holding region), and a gate insulating film are sequentially formed, and then a conductor not shown is filled in the memory hole 334 column. The conductor pillars include, for example, polysilicon, and function as regions for forming channels when the memory cell transistors MT and the select gate transistors ST1 and ST2 included in the NAND string NS operate. That is, the selection gate line SGD, the conductor pillars, and the insulating films between them function as the selection gate transistor ST1, respectively, and the insulating films between the word lines WL, the conductor pillars, and the like function as the selection gate transistors ST1, respectively. The memory cell transistor MT functions as the selection gate transistor ST2, and the selection gate line SGS, the respective conductor posts, and the insulating film between them, etc., function.

Furthermore, in FIG. 5 , the memory holes 334 are shown as having a cylindrical shape with the same diameter, but actually have a tapered shape with a narrow diameter toward the substrate 330 . In addition, depending on the manufacturing process, the memory hole 334 and the conductor post may have a tapered shape in which the diameter is expanded in the middle of the tapered shape and then becomes a tapered shape of a plurality of stages with a narrow diameter toward the substrate 330 .

However, it is not necessary to form the memory hole 334 in dividing the formation area of the insulating layer 352 of each select gate line SGD. However, due to manufacturing reasons, the memory holes 334 are formed in a state where the arrangement positions are uniform. For this reason, the memory hole 334 is also formed in the formation region of the insulating layer 352 . Therefore, as shown in FIG. 5 , each selection gate line SGD has a cutout portion 340 that cuts through the area where the memory hole 334 is formed in the boundary portion with the adjacent selection gate line SGD. On the other hand, the selection gate lines SGD at both ends of each block BLK do not generate the cutout portion 340 in the formation region of the memory hole 334 at the end portion of the block BLK.

The two selection gate lines SGD0 and SGD4 (hereinafter, also referred to as external selection gate lines SGD(outer)) at both ends of each block BLK have cutout portions 340 only at one end side, and the other three selection gate lines in each block BLK are selected The gate lines SGD1 to SGD3 (hereinafter, also referred to as the inner selection gate line SGD(inner)) have cutout portions 340 at both ends. Therefore, the inner selection gate line SGD(inner) is narrower than the outer selection gate line SGD(outer), and accordingly the resistance value is larger than that of the outer selection gate line SGD(outer).

Furthermore, in the following description, the external selection gate line SGD(outer) of the selected string unit is referred to as SGD_sel(outer), and the external selection gate line SGD(outer) of the non-selected string unit is referred to as SGD_usel(outer). ). In addition, the internal selection gate line SGD(inner) of the selected string unit is called SGD_sel(inner), and the internal selection gate line SGD(inner) of the non-selected string unit is called SGD_usel(inner). (USTRDIS (non-selective string discharge))

FIG. 6 is a diagram illustrating the USTRDIS with time on the horizontal axis and voltage on the vertical axis. FIG. 6 shows an example when the outer selection gate line SGD(outer) is selected and the inner selection gate line SGD(inner) is not selected. The single-dotted chain line in FIG. 6 represents the voltage change of SGD_sel(outer), and the dotted line represents the voltage change of SGD_usel(inner).

As described above, during readout, the voltage VSG_sel for turning on the selection gate transistor ST1 is applied to SGD_sel constituting the selected string unit, and the voltage VSG_sel for turning the selection gate transistor ST1 off is applied to SGD_usel constituting the non-selected string unit On voltage VSG_usel (eg, 0 V). Before the readout operation, both SGD_sel and SGD_usel are executed by USTRDIS (unselected string discharge).

In order to prevent interference (miswriting caused by an unexpected rise in threshold voltage), USTRDIS conducts full channel conduction before operation. That is, the readout operation includes a USTRDIS period and an actual readout period (hereinafter, referred to as an actual readout period). During the USTRDIS period, SGD_sel and SGD_usel are set to the voltage VSG_sel that turns on the selection gate transistor ST1.

As shown in FIG. 6 , the USTRDIS period is first set before the actual reading period. The voltage VSG_sel is applied to SGD_sel(outer) and SGD_usel(inner). SGD_sel(outer) is maintained at the voltage VSG_sel during the readout period. SGD_usel(inner) is lowered to the voltage VSG_usel (eg, 0 V) for turning off the select gate transistor ST1.

Furthermore, FIG. 6 shows an example in which the unselected word line WL_usel is set to the voltage Vread, and the selected word line WL_sel is changed to the voltage for reading the A level and the F level during the actual reading period. .

FIG. 7 and FIG. 8 are diagrams for explaining the problem during the USTRDIS period using the same expression as that of FIG. 6 . In FIGS. 7 and 8 , the voltage change of SGD_sel(outer) is represented by the single-dotted chain line, the voltage change of SGD_usel(outer) is represented by the solid line, and the voltage change of SGD_usel(inner) is represented by the dotted line.

In USTRDIS, it takes a relatively long time for SGD_sel and SGD_usel to transition from 0 V to the target voltage VSG_sel. Therefore, in order to shorten the time, the voltage generating circuit 28 generates an overdrive voltage exceeding the level of the target voltage, ie, the voltage VSG_sel, at the transition timing.

The overdrive voltage is larger than the target voltage VSG_sel in the positive direction. As a result of applying the overdrive voltage, SGD_sel and SGD_usel reach the target voltage VSG_sel in a relatively short time.

However, as described above, the internal selection gate line SGD(inner) has a higher resistance value than the external selection gate line SGD(outer). Therefore, even if the overdrive voltage is applied to the internal selection gate line SGD(inner), the time until the internal selection gate line SGD(inner) reaches the target voltage VSG is longer than the external selection gate line SGD(outer) reaches the target voltage VSG The time up to this point is long (the inclination of FIG. 7 decreases). As a result, as shown in FIG. 7 , if the internal selection gate line SGD(inner) is to reach the target voltage, SGD_sel(outer) and SGD_usel(outer) which are the external selection gate line SGD(outer) exceed the target voltage voltage VSG_sel resulting in overshoot.

FIG. 8 shows an example of the case where the overdrive time is shortened or the kick amount is reduced (overdrive voltage is reduced) in order to suppress such overshoot. In this case, although SGD_sel(outer) and SGD_usel(outer) will not generate overshoot, SGD_usel(inner) will not reach the target voltage VSG_sel during the USTRDIS period. As a result, it is considered that the release of electrons does not proceed sufficiently. In the case of any one of FIG. 7 and FIG. 8 , there is a possibility of interference as a result. (overdrive control)

Therefore, in this embodiment, the supply overdrive is changed according to whether the supply target of the overdrive voltage for obtaining the target voltage VGS_sel is the external selection gate line SGD(outer) or the internal selection gate line SGD(inner). The resistance value of the voltage supply circuit.

FIG. 9 is a block diagram showing a partial configuration of the voltage generating circuit 28. As shown in FIG. 10 is a block diagram showing an example of the configuration of the column decoder 25. As shown in FIG. In addition, in FIG. 10, only the partial structure of the voltage generation circuit 28 is shown.

In FIG. 10 , the voltage generating circuit 28 generates various voltages including voltages required for the programming operation and the reading operation of the memory cell transistor MT. The voltage generation circuit 28 includes a supply circuit 41 that supplies voltages to the signal lines SG0 to SG4 ; an SG driver 28A that supplies voltages to the signal lines SG5 ; and a plurality of CG drivers 28B that supply voltages to the signal lines CG0 to CG7 , respectively . The signal lines SG0 to SG5 and CG0 to CG7 are branched by the column decoder 25 and connected to the wiring of each block BLK. That is, the signal lines SG0 to SG4 function as global drain-side selective gate lines, and are connected to the selective gate lines SGD0 to SGD4 serving as local selective gate lines in each block BLK via the column decoder 25 . The signal lines CG0 to CG7 function as global word lines, and are connected to word lines WL0 to WL7 that are local word lines in each block BLK via the column decoder 25 . The signal line SG5 functions as a global source-side selection gate line, and is connected to a selection gate line SGS serving as a local selection gate line in each block BLK via the column decoder 25 .

The voltage generation circuit 28 is controlled by the sequencer 27 and generates various voltages. The SG driver (select gate line driver) 28A and the CG driver (word line driver) 28B supply various generated voltages to the corresponding signal lines SG5 and CG0 to CG7, respectively.

The column decoder 25 includes a plurality of switch circuit groups 25A corresponding to the respective blocks, and a plurality of block decoders 25B provided respectively corresponding to the plurality of switch circuit groups 25A. Each switch circuit group 25A includes a plurality of transistors TR_SG0 to TR_SG4 that connect the signal lines SG0 to SG4 and the selection gate lines SGD0 to SGD4, respectively, and a plurality of transistors that connect the signal lines CG0 to CG7 to the word lines WL0 to WL7, respectively. The transistors TR_CG0 to TR_CG7, and the transistor TR_SG5 connecting the signal line SG5 and the selection gate line SGS. The transistors TR_SG0 to TR_SG5 and the transistors TR_CG0 to TR_CG7 are respectively high withstand voltage crystals.

Each block decoder 25B supplies the block selection signal BLKSEL to the gates of the transistors TR_SG0 to TR_SG5 and the gates of the transistors TR_CG0 to TR_CG7 when it is designated by the column address. As a result, in the switch circuit group 25A that supplies the block selection signal BLKSEL to the block decoder 25B designated by the free column address, since the transistors TR_SG0 to TR_SG5 and the transistors TR_CG0 to TR_CG7 are turned on and are turned on, the power is generated from the power source. The voltages supplied by the circuit 28 to the signal lines SG0 to SG5 and the signal lines CG0 to CG7 are supplied to the selection gate lines SGD0 to SGD4 and SGS and the word lines WL0 to WL7 included in the block BLK to be operated.

That is, by the voltage generation circuit 28 and the column decoder 25, the read voltage VCGRV is supplied to the selected word line WL, and the voltage VREAD or VREADK is supplied to the unselected word line WL. Also, for example, the voltage VSG_sel is supplied to the selection gate line SGD (SGD_sel) connected to the selection gate transistor ST1 belonging to the string unit SU that is the target of operation, and the voltage VSG_sel is supplied to the selection gate line SGD (SGD_sel) that is connected to the string unit SU that is not the target of operation. The selection gate line SGD (SGD_usel) of the pole transistor ST1 supplies a voltage VSG_usel such as 0 V.

In FIG. 9 , the voltage generation circuit 28 includes a voltage generation circuit 40 and a supply circuit 41 . In addition, in FIG. 9, only the circuit for supplying a voltage to the selection gate line SGD is shown. The voltage generating circuit 40 is constituted by a charge pump circuit or the like, and generates various voltages. The supply circuit 41 includes an SGD_sel(inner) driver 42 , a SGD_usel(inner) driver 43 , a SGD_sel(outer) driver 44 , a SGD_usel(outer) driver 45 , a MUX(Multiplexer)(inner) 46 and a MUX(outer) 47 .

FIG. 11 is a circuit diagram showing an example of a specific configuration of the drivers 42 to 44 in FIG. 9 .

The drivers 42 to 44 each have a plurality of input terminals for inputting a plurality of input voltages, and can input a plurality of voltages from the voltage generating circuit 40 through the input terminals. Each of the input terminals of the drivers 42 to 44 is connected to one output terminal through switches T1 , T2 , . . . arranged on respective supply paths of a plurality of voltages. By selecting any one of the switches T1, T2, .

Drivers 42 and 43 are drivers corresponding to SGD_inner. The driver 42 outputs the voltage VSG_sel assigned to the selected selection gate line SGD_sel from the output terminal, and the driver 43 outputs the voltage VSG_usel assigned to the non-selected selection gate line SGD_usel from the output terminal.

The drivers 44 and 45 are drivers corresponding to the external selection gate line SGD(outer). The driver 44 outputs the voltage VSG_sel assigned to the selected selection gate line SGD_sel from the output terminal, and the driver 45 outputs the voltage VSG_usel assigned to the unselected selection gate line SGD_usel from the output terminal.

In this embodiment, the drivers 44 and 45 corresponding to the external selection gate lines SGD (outer) among the drivers 42 to 44 are provided with resistors R1 on the voltage supply paths. The resistance R1 is used to suppress the slope (voltage rise rate) of the voltage applied to the external selection gate line SGD(outer). Furthermore, metal wiring is used as the resistor R1, and the effective resistance value can also be increased by pulling the metal wiring thinly.

The self-voltage generation circuit 40 applies the overdrive voltage to the drivers 42 and 44 to obtain the target voltage VSG_sel in the USTRDIS period, and applies the voltage VSG_sel when the gate line SGD is selected in the actual readout period. In addition, the target voltage VSG_sel is applied to the drivers 43 and 45 in the USTRDIS period, and the voltage VSG_usel when the selected gate line SGD is not selected in the actual read period is applied. Furthermore, the overdrive voltage output from the voltage generating circuit 40 during the USTRDIS period is higher than the voltage of the voltage VSG_sel.

FIG. 12 and FIG. 13 are circuit diagrams respectively showing an example of a specific configuration of MUX(inner) 46 and MUX(outer) 47 in FIG. 9 .

In FIG. 12, the MUX(inner) 46 has six switches T11-T16 on the voltage supply path. The voltage VSG_sel from the SGD_sel(inner) driver 42 is applied to the input terminals of the switches T11 , T13 and T15 , and the voltage VSG_usel from the SGD_usel(inner) driver 43 is applied to the input terminals of the switches T12 , T14 and T16 . The output terminals of the switches T15 and T16 are commonly connected to the selection gate line SGD1 (inner). In addition, the output terminals of the switches T13 and T14 are commonly connected to the selection gate line SGD2(inner), and the output terminals of the switches T11 and T12 are commonly connected to the selection gate line SGD3(inner).

By selecting one of the switches T15 and T16 and then turning on, the voltage supplied to the selected switch is supplied to SDG1 (inner). Similarly, one of the switches T13 and T14 is selected to be turned on, and the voltage supplied to the selected switch is supplied to SDG2 (inner), and one of the switches T11 and T12 is selected to be turned on, and The voltage supplied to the selected switch is supplied to SDG1(inner).

In FIG. 13, the MUX (outer) 47 has four switches T17-T20 on the voltage supply path. The voltage VSG_sel from the SGD_sel(outer) driver 44 is applied to the input terminals of the switches T17 and T19, and the voltage VSG_usel from the SGD_usel(outer) driver 45 is applied to the input terminals of the switches T18 and T19. The output terminals of the switches T19 and T20 are commonly connected to the selection gate line SGD0 (outer). In addition, the output terminals of the switches T17 and T18 are commonly connected to the selection gate line SGD4 (outer).

By selecting one of the switches T19 and T20 and then turning on, the voltage supplied to the selected switch is supplied to SDG0 (outer). Similarly, by selecting one of the switches T17 and T18 and then turning on, the voltage supplied to the selected switch is supplied to SDG4 (outer).

Next, the operation of the thus-configured embodiment will be described with reference to FIG. 14 . FIG. 14 is a diagram for explaining the effect of the embodiment in the USTRDIS period using the same expression as FIG. 6 . In FIG. 14 , the voltage change of SGD_sel(outer) is represented by the single-dotted chain line, the voltage change of SGD_usel(outer) is represented by the solid line, and the voltage change of SGD_usel(inner) is represented by the dotted line.

Now, data is read from the memory cell transistors that are written with the prescribed codes. In the memory (not shown) of the sequencer 27, information of various voltages required for reading the data is stored. Based on the information, the sequencer 27 causes the voltage generating circuit 28 to generate the voltage required for reading.

That is, the voltage generating circuit 28 is controlled by the sequencer 27 to generate an overdrive voltage during the USTRDIS period and apply it to the drivers 42 to 45 . The drivers 42 to 45 turn on the switch T1 to select and output the overdrive voltage. The selection gate lines SGD1 to SGD3 to which the overdrive voltages are supplied by the drivers 42 and 43 , respectively, have larger resistance values than the selection gate lines SGD0 and SGD4 of the drivers 44 and 45 to supply the overdrive voltages, respectively. However, since the resistors R1 are provided on the voltage supply paths of the drivers 44 and 45, the voltage rise rates of the selection gate lines SGD0 and SGD4 are suppressed. Therefore, the voltage change of the internal selection gate line SGD(inner) and the voltage change of the external selection gate line SGD(outer) can be made approximately the same, and the voltage rise rates of the selection gate lines SGD0 to SGD4 can be fixed to each other.

As shown in FIG. 14 , the voltages of SGD(inner) and SGD(outer) in the USTRDIS period change at approximately the same voltage rise rate. As a result, SGD(outer) does not generate overshoot, and SGD(outer) and SGD(inner) use the same voltage change to reach the target voltage VSG_sel in a short time.

In this way, in the present embodiment, by changing the resistance value of the supply circuit of the overdrive voltage according to the type of the selected gate line, the voltage applied to the selected gate line can be made uniform regardless of the type of the selected gate line , reach the target voltage in a short time. (Second embodiment)

FIG. 15 is a circuit diagram showing an SGD_usel(outer) driver used in the second embodiment of the present invention. FIG. 15 is adopted instead of the SGD_usel (outer) driver 45 of FIG. 11 , and other hardware configurations in this embodiment are the same as those in the first embodiment.

When the outer selection gate line SGD(outer) in the block BLK is selected, other outer selection gate lines SGD(outer) in the block BLK are not selected. On the other hand, when the inner selection gate line SGD(inner) in the block BLK is selected, neither of the two outer selection gate lines SGD(outer) in the block BLK is selected. Therefore, the non-selection voltage VSG_usel from the voltage generating circuit 40 may be supplied to one external selection gate line SGD(outer) or two external selection gate lines SGD(outer) depending on the selection state.

That is, the output of the SGD_usel(outer) driver 45 in FIG. 11 is supplied to an external selection gate line SGD(outer) via only one of the switches T18 and T20 of the MUX(outer) 47, and the case where the output is supplied to an external selection gate line SGD(outer) via the MUX(outer) 47 )47 switches T18 and T20 are supplied to two external selection gate lines SGD(outer). That is, the load of the driver 45 changes according to the selection state SGD_usel(outer), and the voltage rise rate of the external selection gate line SGD(outer) cannot be made uniform. Therefore, in this embodiment, the SGD_usel(outer) driver 50 is used instead of the SGD_usel(outer) driver 45 .

The SGD_usel(outer) driver 50 adds the NOR circuit 51 and the switch TO to the SGD_usel(outer) driver 45 of FIG. 11, and uses the resistors R2 and R3 instead of the resistor R1. A signal String Add[0] indicating whether or not to apply the voltage VSG_usel to the selection gate line SGD0 and a signal String Add[4] indicating whether or not to apply the voltage VSG_usel to the selection gate line SGD5 are input to the NOR circuit 51 . The NOR circuit 51 performs NOR operation of two inputs, and outputs the operation result to the switch TO.

On the supply path of the voltage between the output end of the voltage generating circuit 40 and the switch T1, a series circuit of resistors R3 and R2 is provided. The switch TO is connected to both ends of the resistor R3. When the operation result of the NOR circuit 51 is a logic "1", the switch TO is turned on and the resistor R3 is short-circuited. When the operation result of the NOR circuit 51 is logic "0", the switch circuit TO is turned off.

Next, the operation of the thus-configured embodiment will be described with reference to FIGS. 16 and 17 . 16 and 17 are explanatory diagrams for explaining the operation of the embodiment.

Now, it is assumed that the selection gate line SGD0 is selected and the selection gate line SGD4 is not selected. That is, in this case, the SGD_usel(outer) driver 50 only needs to supply the voltage VSG_usel to only one external selection gate line SGD(outer). As shown in FIG. 16, in this case, the signal String Add[0] is "H" and the signal String Add[4] is "L". The output of the NOR circuit 51 is "L" (logical value "0"), the switch circuit TO is disconnected, and the resistor R3 is not short-circuited. That is, as shown by the arrow in FIG. 16 , a series circuit of resistors R3 and R2 is connected to the supply path of the voltage between the output terminal of the voltage generating circuit 40 and the switch T1 . The two resistors R3 and R2 are used to suppress the voltage change rate of the external selection gate line SGD(outer).

In addition, it is assumed that neither the selection gate line SGD0 nor the selection gate line SGD4 is selected. That is, in this case, the SGD_usel(outer) driver 50 supplies the voltage VSG_usel to the two external selection gate lines SGD(outer). As shown in FIG. 17, in this case, the signal String Add is [0], and String Add[4] is both "L". The output of the NOR circuit 51 becomes "H" (logical value "1"), the switch circuit TO is turned on, and the resistor R3 is short-circuited. That is, as shown by the arrow in FIG. 17 , only the resistor R2 is connected to the supply path of the voltage between the output terminal of the voltage generating circuit 40 and the switch T1 . As a result, the voltage change rate of the external selection gate line SGD(outer) tends to increase.

As described above, in the present embodiment, the SGD_usel is switched according to whether the SGD_usel(outer) driver supplies the voltage VSG_usel to one external selection gate line SGD(outer) or the two external selection gate lines SGD(outer). The resistance value of the (outer) driver can make the voltage change rate of the non-selected external selection gate line SGD(outer) constant even when any one of the selection gate lines SGD is selected.

Furthermore, the resistance values of the resistors R2 and R3 may be configured to be able to be set and changed. (variation example)

FIG. 18 is a circuit diagram showing the SGD_usel(inner) driver. FIG. 18 is adopted instead of the SGD_usel (inner) driver 43 of FIG. 11 , and other hardware configurations in this embodiment are the same as those in the first embodiment or the second embodiment.

When the outer selection gate line SGD(outer) in the block BLK is selected, none of the three inner selection gate lines SGD(inner) in the block BLK is selected. On the other hand, when the inner selection gate line SGD(inner) in the block BLK is selected, the two inner selection gate lines SGD(inner) in the block BLK are not selected. Therefore, the non-selection voltage VSG_usel from the voltage generating circuit 40 is supplied to two internal selection gate lines SGD(inner) and three internal selection gate lines SGD(inner) depending on the selection state.

That is, the output of the SGD_usel(inner) driver 43 in FIG. 11 is supplied to the two internal selection gate lines SGD(inner) through two switches of the switches T12 , T14 and T16 of the MUX(inner) 46 , and the case where the output is supplied to the two internal selection gate lines SGD(inner) through the MUX(inner) 46 The case where all the switches T12, T14, and T16 of (inner) 46 are supplied to the three internal selection gate lines SGD(inner). That is, the load of the SGD_usel(inner) driver 43 varies according to the selection state, so that the voltage rise rate of the inner selection gate line SGD(inner) cannot be made uniform. Therefore, in the present embodiment, the SGD_usel(inner) driver 60 is used instead of the SGD_usel(inner) driver 43 .

The SGD_usel(inner) driver 60 is formed by adding a NOR circuit 61 , a switch TO, a resistor R4 and a resistor R5 to the SGD_usel(inner) driver 43 of FIG. 11 . A signal String Add[1] indicating whether to apply the voltage VSG_usel to the selection gate line SGD1, a signal String Add[2] indicating whether to apply the voltage VSG_usel to the selection gate line SGD2, and a signal String Add[2] indicating whether or not to apply the voltage VSG_usel to the selection gate line SGD2 are input to the NOR circuit 61 SGD3 applies the signal String Add[3] of the voltage VSG_usel. The NOR circuit 61 performs 3-input NOR operation, and outputs the operation result to the switch TO.

On the supply path of the voltage between the output end of the voltage generating circuit 40 and the switch T1, a series circuit of resistors R5 and R4 is arranged. The switch TO is connected to both ends of the resistor R5, and when the operation result of the NOR circuit 61 is a logic "1", the switch TO is turned on and the resistor R5 is short-circuited. When the operation result of the NOR circuit 61 is logic "0", the switch circuit TO is turned off. Furthermore, the resistance ratio of the resistors R5 and R4 is set to, for example, 1:2. Furthermore, the resistance ratio of the resistors R5 and R4 can consider all the resistance values from the rear section of the driver to the internal selection gate line SGD (inner), but the resistance values of the resistors R5 and R4 are dominant, and only the resistor R5 can be considered. , The resistance value of R4. In addition, the resistance values of the resistors R5 and R4 may be configured to be able to be set and changed.

Furthermore, as a driver for the external selection gate line SGD(outer), the SGD_usel(outer) driver 50 of FIG. 15 can also be used.

Next, the operation of the thus-configured embodiment will be described.

Now, it is assumed that one of the internal selection gate lines SGD(inner) is selected, and the other two internal selection gate lines SGD(inner) are not selected. That is, in this case, the SGD_usel(inner) driver 60 only needs to supply the voltage VSG_usel to the two internal selection gate lines SGD(inner). In this case, any one of the signals String Add[1] to String Add[3] is "H", and the output of the NOR circuit 61 is "L" (logical value "0"). The switch circuit TO is disconnected, and the resistor R5 is not short-circuited. That is, a series circuit of resistors R5 and R4 is connected to the supply path of the voltage between the output end of the voltage generating circuit 40 and the switch T1. The two resistors R5 and R4 are used to suppress the voltage change rate of the internal selection gate line SGD(inner).

In addition, it is assumed that none of the selected gate lines SGD0 to SGD3 are selected. That is, in this case, the SGD_usel(inner) driver 60 supplies the voltage VSG_usel to the three internal selection gate lines SGD(inner). In this case, the signals String Add[1] to String Add[3] are all "L", and the output of the NOR circuit 61 becomes "H" (logical value "1"). Thereby, the switch circuit TO is turned on, and the resistor R5 is short-circuited. That is, only the resistor R4 is connected to the supply path of the voltage between the output terminal of the voltage generating circuit 40 and the switch T1. As a result, the voltage change rate of the internal selection gate line SGD(inner) tends to increase.

In this way, in this embodiment, the SGD_usel(inner) driver switches SGD_usel according to whether the voltage VSG_usel is supplied to the two internal selection gate lines SGD(inner) or the voltage VSG_usel is supplied to the three internal selection gate lines SGD(inner). The resistance value of the (inner) driver can make the voltage change rates of the non-selected internal selection gate lines SGD(inner) fixed to each other even when any one of the selection gate lines SGD is selected. (third embodiment)

FIG. 19 is a block diagram showing a third embodiment of the present invention. The present embodiment differs from the first embodiment in that voltage generation circuits 71 and 72 are used instead of the voltage generation circuit 40 of FIG. 11 , and drivers 73 and 74 are used instead of the drivers 44 and 45 , and other structures are the same as those of the first embodiment.

In this embodiment, in the USTRDIS period, the overdrive period (overdrive period) for the external selection gate line SGD(outer) and the overdrive period for the internal selection gate line SGD(inner) are Differently, the generation of overshoot can be suppressed, and the voltage applied to the selected gate line can be made to reach the target voltage in a short time regardless of the type of the selected gate line.

The SGD_sel(outer) driver 73 has the same configuration as the SGD_sel(inner) driver 42 , and the SGD_usel(outer) driver 74 has the same configuration as the SGD_usel(inner) driver 43 . The voltage generating circuits 71 and 72 have the same configuration as the voltage generating circuit 40, respectively.

Next, the operation of the thus-configured embodiment will be described with reference to FIG. 20 . Fig. 20 is a graph showing the voltage change of the external selection gate line SGD(outer) and the internal selection gate line SGD(inner) in the USTRDIS period with time on the horizontal axis and voltage on the vertical axis, and the left side shows the characteristics in the comparative example , and the right side shows the characteristics in this embodiment.

The comparative example of FIG. 20 shows an example in which the same overdrive voltage is applied to the external selection gate line SGD(outer) and the internal selection gate line SGD(inner) in the USTRDIS period. As described above, in this case, since the resistance value of the internal selection gate line SGD(inner) is larger than the resistance value of the external selection gate line SGD(outer), in order to make the internal selection gate line SGD(inner) ) reaches the target voltage, and the external select gate line SGD(outer) produces an overshoot.

On the other hand, in this embodiment, the voltage generating circuit 71 and the voltage generating circuit 72 generate the overdrive voltage of the same voltage level, and the overdrive periods are different from each other. That is, the voltage generation circuit 71 generates the overdrive voltage for a relatively long period, and the voltage generation circuit 72 generates the overdrive voltage for a shorter period than the voltage generation circuit 71 .

The output of the voltage generating circuit 71 is supplied to the SGD_sel(inner) drivers 42 and 43 , and the output of the voltage generating circuit 72 is supplied to the SGD_sel(outer) drivers 73 and 74 . The SGD_sel(inner) driver 42 and the driver 73 have the same structure. The output of the SGD_sel(inner) driver 42 and the output of the SGD_sel(outer) driver 73 are different only during the overdrive period, and overdrive is applied to the external selection gate line SGD(outer) The voltage is only for a relatively short period, and the overdrive voltage is applied to the internal selection gate line SGD(inner) for a relatively long period.

Similarly, the outputs of the SGD_usel(inner) driver 43 and the SGD_usel(outer) driver 74 differ only in the overdrive period, and the overdrive voltage is applied to the external selection gate line SGD(outer) during a relatively short period, and the internal selection gate The pole line SGD(inner) applies the overdrive voltage for a longer period.

As shown in FIG. 20 , the overdrive voltage is applied to the external selection gate line SGD(outer) for a relatively short period, and the overdrive voltage is applied to the internal selection gate line SGD(inner) for a relatively long period. As a result, the external selection gate line SGD(outer) reaches the target voltage relatively quickly because the resistance value is small, and the overdrive period is short so that no overshoot occurs. In addition, the overdrive voltage is applied to the internal selection gate line SGD(inner) for a long period of time, and as a result, the target voltage is reached in a relatively short period of time.

In this way, in the present embodiment, the overdrive period of the external selection gate line SGD(outer) and the internal selection gate line SGD(inner) are different to prevent overshooting of the external selection gate line SGD(outer), and The external selection gate line SGD(outer) and the internal selection gate line SGD(inner) can reach the target voltage relatively quickly.

In this embodiment mode, an example in which the overdrive period is made different has been described, but the overdrive voltage may be changed between the external selection gate SGD(outer) and the internal selection gate SGD(inner). The voltage values are different.

The present invention is not limited to the above-described embodiment, and various changes can be made in the implementation stage within a range that does not deviate from the gist. In addition, the above-mentioned embodiment includes inventions of various stages, and various inventions can be extracted by appropriate combination of a plurality of constituent elements disclosed. For example, even if some constituent elements are deleted from all the constituent elements shown in the embodiments, the above-mentioned problems in the column of the problem to be solved by the invention can be solved and the above-mentioned effects in the column of the effect of the invention can be obtained. The constitution from which the constituent elements are deleted is extracted as the invention. [Related applications]

This application enjoys the priority of the basic application based on Japanese Patent Application No. 2020-156299 (filing date: September 17, 2020). This application contains all the contents of the basic application by reference to the basic application.

1: Memory controller 2: Non-volatile memory 11: RAM 12: Processor 13: Host interface 14: ECC circuit 15: Memory interface 16: Internal bus 21: Logic control circuit 22: Input and output circuit 23: Memory Cell Array 24: Sense Amplifier 24A: Sense Amplifier Cell Group 24B: Data Register 25: Column Decoder 25A: Switch Circuit Group 25B: Block Decoder 26: Register 27: Sequencer 28: Voltage Generation circuit 28A: SG driver 28B: CG driver 32: Pad group for input and output 34: Pad group for logic control 35: Terminal group for power input 40: Voltage generation circuit 41: Supply circuit 42: SGD_sel(inner) driver 43 : SGD_usel(inner) driver 44: SGD_sel(outer) driver 45: SGD_usel(outer) driver 46: MUX(inner) 47: MUX(outer) 50: SGD_usel(outer) driver 51: NOR circuit 60: SGD_usel(inner) driver 61: NOR circuit 71: Voltage generating circuit 72: Voltage generating circuit 73: SGD_sel(outer) driver 74: SGD_usel(outer) driver 330: Substrate 334: Memory hole 339: Contact plug 340: Cutout 351: Insulating layer 352 : Insulating layer BL, BL0～BL(m-1): Bit line BLK: Block MG: Memory cell group MT(MT0～MT7): Memory cell transistor R2: Resistor R3: Resistor R4: Resistor R5: Resistor SGD0~SGD4: select gate line SU(SU0~SU4): string unit ST1: select gate transistor ST2: select gate transistor T1: switch T2: switch T11: switch T12: switch T13: switch T14: switch T15 : switch T16: switch T17: switch T18: switch T19: switch T20: switch TO: switch WL0～WL7: word line

FIG. 1 is a block diagram showing an example of the configuration of the memory system according to the embodiment. FIG. 2 is a block diagram showing a configuration example of the nonvolatile memory of the embodiment. FIG. 3 is a diagram showing a configuration example of a block of the NAND memory cell array 23 having a three-dimensional structure. Fig. 4 is a diagram showing the potential change of each wiring in the write operation (program operation). FIG. 5 is an explanatory diagram for explaining each selection gate line SGD in one block BLK. Figure 6 is a diagram illustrating the USTRDIS with time on the horizontal axis and voltage on the vertical axis. Fig. 7 is a diagram showing the potential change of each wiring in the write operation (program operation). Figure 8 is a diagram illustrating the problem during USTRDIS using the same expression as Figure 6 . FIG. 9 is a block diagram showing a partial configuration of the voltage generating circuit 28. FIG. 10 is a block diagram showing an example of the configuration of the column decoder 25. FIG. 11 is a circuit diagram showing an example of a specific configuration of the drivers 42 to 44 in FIG. 9 . FIG. 12 is a circuit diagram showing an example of a specific configuration of the MUX(inner) 46 in FIG. 9 . FIG. 13 is a circuit diagram showing an example of a specific configuration of the MUX(outer) 47 in FIG. 9 . FIG. 14 is a diagram for explaining the effect of the embodiment. FIG. 15 is a circuit diagram showing the SGD_usel(outer) driver used in the second embodiment of the present invention. FIG. 16 is an explanatory diagram for explaining the operation of the embodiment. FIG. 17 is an explanatory diagram for explaining the operation of the embodiment. Figure 18 shows the circuit diagram of the SGD_usel(inner) driver. Fig. 19 is a block diagram showing a third embodiment of the present invention. Fig. 20 is a graph showing the voltage change of the external selection gate line SGD(outer) and the internal selection gate line SGD(inner) during the USTRDIS period with time on the horizontal axis and voltage on the vertical axis.

25: Column decoder 25A: Switch circuit group 25B: Block decoder 27: Sequencer 28: Voltage generation circuit 28A: SG driver 28B: CG driver 41: Supply circuit

Claims (9)

A semiconductor memory device, comprising: a plurality of memory cells; a word line, which is connected to the gates of the plurality of memory cells; a bit line, which is connected to one end of the plurality of memory cells through a plurality of selection gates respectively A pole transistor, electrically connected to one end of the above-mentioned plural memory cells; Two external selection gate lines, which are respectively connected to the gates of the two above-mentioned selection gate transistors at both ends of the block; More than 1 line The internal selection gate line, which is connected to the gates of one or more of the selection gate transistors other than the two ends of the block; and a voltage generation circuit, which is recorded in the plurality of memory cells when reading During data acquisition, the voltage supply to the external selection gate line and the internal selection gate line can be individually controlled. The semiconductor memory device of claim 1, wherein the voltage generating circuit individually controls the voltage rise rate of the voltage supplied to the external selection gate line and the internal selection gate line. The semiconductor memory device of claim 2, wherein the voltage generating circuit includes: a driver for an external selective gate line, which supplies a voltage to the external selective gate line; and a driver for an internal selective gate line, which is used for the internal selective gate line. Pole line supply voltage; The resistance value on the voltage supply path of the driver for the external selection gate line is greater than the resistance value on the voltage supply path of the driver for the internal selection gate line. The semiconductor memory device of claim 1, wherein the voltage generating circuit individually controls the application period of the overdrive voltage supplied to the external selection gate line and the internal selection gate line. The semiconductor memory device of claim 4, wherein the voltage generating circuit includes: a voltage generating circuit for an external selective gate line, which generates a voltage supplied to the external selective gate line; and a voltage generating circuit for an internal selective gate line, It generates the voltage supplied to the internal selective gate line; the application period of the overdrive voltage of the external selective gate line voltage generating circuit is shorter than that of the internal selective gate line voltage generating circuit. The semiconductor memory device of claim 1, wherein the voltage generating circuit has a driver for an external selection gate line that generates a voltage supplied to the external selection gate line, and the driver for the external selection gate line is based on the plurality of memory cells. Voltage supply is controlled by externally selecting the number of gate lines corresponding to the memory cells not to be read out. The semiconductor memory device of claim 6, wherein the driver for the external selection gate lines makes the voltage The resistance value on the supply path changes. The semiconductor memory device of claim 1, wherein the voltage generation circuit has a driver for an internal selection gate line that generates a voltage supplied to the internal selection gate line, and the driver for the internal selection gate line is based on the plurality of memory cells. The number of gate lines corresponding to the memory cells not to be read is internally selected to control the voltage supply. The semiconductor memory device of claim 8, wherein in the above-mentioned driver for internal selection gate lines, the greater the number of internal selection gate lines corresponding to the memory cells not targeted for reading, the higher the resistance value on the voltage supply path. Small.

Images