TWI764050B - Semiconductor devices and methods for forming the same - Google Patents

Abstract

A method for forming a semiconductor device includes patterning a substrate to form a strip including a first semiconductor material, forming an isolation region along a sidewall of the strip, an upper portion of the strip extending above the isolation region, forming a dummy structure along sidewalls and a top surface of the upper portion of the strip, performing a first etching process on an exposed portion of the upper portion of the strip to form a first recess, the exposed portion of the strip being exposed by the dummy structure, after performing the first etching process, reshaping the first recess to have a V-shaped bottom surface using a second etching process, wherein the second etching process is selective to first crystalline planes having a first orientation relative to second crystalline planes having a second orientation, and epitaxially growing a source/drain region in the reshaped first recess.

Description

Semiconductor device and method of forming the same

Embodiments of the invention relate to semiconductor technology, and more particularly, to semiconductor devices and methods of forming the same.

Semiconductor devices are used in a wide variety of electronic applications, such as personal computers, cell phones, digital cameras, and other electronic equipment. Semiconductor devices generally form circuit components and components thereon by sequentially depositing insulating or dielectric layers, conductive layers, and semiconductor layer materials on a semiconductor substrate, and patterning the various material layers using lithography techniques.

The semiconductor industry continues to improve the integration density of various electronic components (such as transistors, diodes, resistors, capacitors, etc.) by continuously reducing the size of the smallest features, so that more components are integrated into a given area. However, when reducing the size of the smallest components, additional problems arise that should be addressed.

In some embodiments, a method of forming a semiconductor device is provided, the method comprising forming a fin on a substrate; forming an isolation region adjacent to the fin; forming a dummy structure over the fin; Recessing to form a first notch; using a second etching process to reshape the first notch to form a reshaped first notch, wherein the bottom of the reshaped first notch is formed by the crystal plane of the first sidewall surface Defined by intersection with a crystal plane of the second sidewall surface, wherein the first sidewall surface faces the second sidewall surface; and source/drain regions are epitaxially grown in the reshaped first recess.

In some other embodiments, a method of forming a semiconductor device is provided, the method comprising patterning a substrate to form strips, the strips comprising a first semiconductor material; forming isolation regions along sidewalls of the strips, upper portions of the strips extending from the isolation above the top surface of the region; forming a dummy structure along the sidewall and top surface of the upper part of the strip; performing a first etching process on the exposed part of the upper part of the strip to form a first recess, the exposed part of the strip is exposed by the dummy structure out; after the first etching process is performed, the first recess is reshaped to have a V-shaped bottom surface using a second etching process, wherein the second etching process pair has the first notch with respect to the second crystal plane having the second crystal orientation The first crystal plane of the crystal orientation is selective; and the source/drain regions are epitaxially grown in the reshaped first recess.

In other embodiments, a semiconductor device is provided, the semiconductor device comprising a fin located over a substrate, wherein a first sidewall surface of a bottom of the fin extends along a crystal plane of a first crystallographic direction; an isolation region adjacent to the fin; and a gate structure , extending along the sidewalls of the fin and over the top surface of the fin; a gate spacer, laterally adjacent to the gate structure; and an epitaxial region adjacent to the fin, wherein the bottom of the epitaxial region tapers to a point.

It is to be understood that the following disclosure provides many different embodiments or examples for implementing different components of the provided subject matter. Specific examples of various components and their arrangements are described below in order to simplify the description of the disclosure. Of course, these are only examples and are not intended to limit the present invention. For example, the following disclosure describes that a first part is formed on or over a second part, which means that it includes embodiments in which the formed first part and the second part are in direct contact, and also includes For example, an additional component may be formed between the first component and the second component, and the first component and the second component may not be in direct contact with each other. In addition, different examples in the disclosure may use repeated reference symbols and/or words. These repeated symbols or words are used for the purpose of simplicity and clarity, and are not used to limit the relationship between the various embodiments and/or the appearance structures.

Furthermore, for convenience in describing the relationship of one element or component to another (plural) element or (plural) component in the drawings, spatially relative terms such as "under", "under", "under" may be used. ”, “above”, “upper” and similar terms. In addition to the orientation depicted in the drawings, spatially relative terms also encompass different orientations of the device in use or operation. The device may also be otherwise oriented (eg, rotated 90 degrees or at other orientations) and the description of the spatially relative terms used interpreted accordingly.

Embodiments of the present invention will be discussed below for a specific case, ie, a fin field effect transistor device and a method of forming the same. Various embodiments discussed herein allow the shape of the epitaxial source/drain regions of the FinFET device to be controlled such that the bottoms of the epitaxial source/drain regions have a pointed shape defined by the crystal planes. By controlling the shape of the epitaxial source/drain regions of the finFET in this way, the performance of the finFET device can be improved. Various embodiments presented herein are discussed in the context of fin field effect transistors formed using post-gate processing. In other embodiments, a gate-first process may be used. Some embodiments contemplate aspects for planar devices, such as planar field effect transistors. Some embodiments may also be used in semiconductor devices that are not field effect transistors.

FIG. 1 shows a three-dimensional view of an example of a fin field effect transistor (FinFET) 30 in accordance with some embodiments. FinFET 30 includes fins 36 on substrate 32 . The isolation regions 34 are disposed on the substrate 32 around the fins 36 , and the fins 36 protrude above the adjacent isolation regions 34 . Gate dielectric 38 is along the sidewalls and top surface of fin 36 , and gate electrode 40 is above gate dielectric 38 . Source/drain regions 42 and 44 are disposed on both sides of fin 36 relative to gate dielectric 38 and gate electrode 40 . Figure 1 further shows a reference section for subsequent drawings. Section A-A spans the channel region of finFET 30 , gate dielectric 38 and gate electrode 40 . Section C-C is in a plane parallel to section A-A and spans the fins 36 outside the channel region. Section B-B is perpendicular to section A-A and along the longitudinal axis of fin 36 , and in the direction of current flow, eg, between source/drain regions 42 and 44 . For clarity, subsequent figures refer to these reference sections.

FIGS. 2A-22 are schematic cross-sectional views of intermediate stages of fabricating a finFET in accordance with some embodiments. In Figures 2A to 11A-11C and Figures 16A-16C to 21A-21C, the figures ending with the "A" mark are shown along the reference section A-A in Figure 1, except that the above figures have multiple fin fields effect transistors and each fin field effect transistor has a plurality of fins. Figures ending with a "B" mark are shown along reference section B-B in Figure 1. Figures ending with a "C" mark are shown along reference section C-C in Figure 1. Figures 12-15C and 22 are shown along reference section B-B in Figure 1.

In Figure 2, a substrate 50 is provided. The substrate 50 may be a semiconductor substrate, such as a bulk semiconductor, a semiconductor-on-insulator (SOI) substrate, or the like, and the substrate 50 may be doped (eg, doped p-type or n-type doped). impurities) or undoped. The substrate 50 can be a wafer, such as a silicon wafer, and can have a specific crystal orientation, such as (100), (111), or (110). Generally, a semiconductor-on-insulator substrate includes a layer of semiconductor material formed on the insulating layer. The insulating layer may be, for example, a buried oxide (BOX) layer, a silicon oxide layer, or the like. The insulating layer is provided on a substrate, typically a silicon substrate or a glass substrate. Other substrates can also be used, such as multilayer or gradient substrates. In some embodiments, the semiconductor material of the substrate 50 may include silicon, germanium, compound semiconductors (including silicon carbide, gallium arsenide, gallium phosphide, indium phosphide, indium arsenide and/or indium antimonide), alloy semiconductors ( Including SiGe, GaAsP, AlInAs, AlGaAs, GaInAs, GaInP, and/or GaInAsP) or a combination of the foregoing.

The substrate 50 may further include integrated circuit elements (not shown). Those of ordinary skill in the art to which this invention pertains will understand that a wide variety of integrated circuit elements (eg, transistors, diodes, capacitors, resistors, the like, or combinations of the foregoing) may be formed in the substrate 50 and/or substrate 50 to generate the structural and functional requirements for the final FinFET design. Integrated circuit elements may be formed using any suitable method.

In some embodiments, the substrate 50 may include a first region 100A and a second region 100B. The first region 100A may be used to form n-type devices, such as n-type metal oxide semiconductor (NMOS) transistors, such as n-type fin field effect transistors. The second region 100B may be used to form a p-type device, such as a p-type metal oxide semiconductor (PMOS) transistor, such as a p-type FinFET. Therefore, the first region 100A may also be referred to as an N-type metal oxide semiconductor region, and the second region 100B may also be referred to as a P-type metal oxide semiconductor region. In some embodiments, the first region 100A may be physically separated from the second region 100B. The first region 100A may be separated from the second region 100B by any number of components.

FIG. 2A further shows that the mask 53 is formed over the substrate 50 . In some embodiments, the mask 53 can be used in a subsequent etching step to pattern the substrate 50 (please refer to FIG. 3A). As shown in FIG. 2A , the mask 53 may include a first mask layer 53A and a second mask layer 53B. The first mask layer 53A may be a hard mask layer, and may include silicon nitride (SiN), silicon oxynitride (SiON), silicon carbide (SiC), silicon carbide nitride (SiCN), a combination of the foregoing, or the like, And can be formed by using any suitable process, such as atomic layer deposition (ALD), physical vapor deposition (PVD), chemical vapor deposition (chemical vapor deposition, CVD), a combination of the foregoing or similar method. The first mask layer 53A may also include multiple layers, and the multiple layers may be of different materials. For example, the first mask layer 53A may comprise a silicon nitride layer over the silicon oxide layer, although other materials and combinations of materials may also be used. The second mask layer 53B may include photoresist, and in some embodiments, the second mask layer 53B may be used in the subsequent etching steps described above to pattern the first mask layer 53A. The second mask layer 53B can be formed by using a spin coating technique, and can be patterned by using a suitable photolithography technique. In some embodiments, mask 53 may include three or more mask layers.

FIG. 3A shows semiconductor strips 52 formed in substrate 50 . First, first mask layer 53A and second mask layer 53B may be patterned, wherein openings in first mask layer 53A and second mask layer 53B exposing substrate 50 will form isolation regions 54 (sometimes The region 55 is called Shallow Trench Isolation (STI) region. Next, an etching process may be performed, wherein the etching process forms the trenches 55 in the substrate 50 through the openings in the mask 53 . The remainder of the substrate 50 below the patterned mask 53 forms a plurality of semiconductor strips 52 . The etching can be any suitable etching process, such as reactive ion etch (RIE), neutral beam etch (NBE), the like, or a combination of the foregoing. The etching process may be anisotropic. In some embodiments, the semiconductor strips 52 may have a height H ₁ between about 200 nm and about 400 nm, and may have a width W ₁ between about 10 nm and about 40 nm.

The semiconductor strips 52 may be patterned by any suitable method. For example, the semiconductor strips 52 may be patterned using one or more photolithography processes, including double-patterning or multi-patterning processes. In general, double-patterning or multi-patterning processes combine photolithography and self-alignment processes to create patterns with smaller pitches that, for example, have a Patterns with smaller spacing. For example, in one embodiment, a sacrificial layer is formed over substrate 50 and patterned by using a photolithography process. Spacers are formed beside the patterned sacrificial layer by using a self-aligned process. Next, the sacrificial layer is removed, and the semiconductor strips 52 can then be patterned using the remaining spacers or mandrels as masks.

FIG. 4A shows insulating material formed in trenches 55 (see FIG. 3A ) between adjacent semiconductor strips 52 to form isolation regions 54 . The insulating material can be oxide (such as silicon oxide), nitride, the like, or a combination of the foregoing, and can be processed by high-density plasma chemical vapor deposition (HDP-CVD), flowable chemical vapor deposition Flowable CVD (FCVD) (eg, chemical vapor deposition-based material deposition in a remote plasma system, and post-curing to convert it to another material, such as an oxide), similar methods, or a combination of the foregoing . Other insulating materials formed by any suitable process may also be used.

Furthermore, in some embodiments, isolation regions 54 may include compliant liners formed on the sidewalls and bottom surfaces of trenches 55 (see FIG. 3A ) prior to filling trenches 55 with the insulating material of isolation regions 54 pad (not shown). In some embodiments, the liner may include semiconductor (eg, silicon), nitride, semiconductor (eg, silicon) oxide, thermal semiconductor (eg, silicon) oxide, semiconductor (eg, silicon) oxynitride, polymer dielectrics , a combination of the foregoing, or the like. Formation of the liner may comprise any suitable method, such as atomic layer deposition, chemical vapor deposition, high density plasma chemical vapor deposition, physical vapor deposition, combinations of the foregoing, or the like. In these embodiments, the liner may prevent (or at least reduce) diffusion of semiconductor material from semiconductor strips 52 (eg, Si and/or Ge) into surrounding isolation regions 54 during subsequent annealing of isolation regions 54 . For example, after the insulating material of the isolation regions 54 is deposited, an annealing process may be performed on the insulating material of the isolation regions 54 .

In FIG. 4A, a planarization process (eg, chemical mechanical polishing (CMP)) may remove excess insulating material from the isolation regions 54 so that the top surfaces of the isolation regions 54 and the top surfaces of the semiconductor strips 52 are coplanar . In some embodiments, chemical mechanical polishing may also remove mask 53 . In other embodiments, mask 53 may be removed by using a wet etch process separate from chemical mechanical polishing.

FIG. 5A shows that isolation regions 54 are recessed to form fins 56 . The isolation regions 54 are recessed so that the fins 56 in the first and second regions 100A and 100B protrude from between adjacent isolation regions 54 . In some embodiments, semiconductor strips 52 may be considered part of fins 56 . Furthermore, the top surface of the isolation region 54 may have a flat surface as shown, a convex surface, a concave surface (eg, a depression), or a combination of the foregoing. The top surface of the isolation region 54 may be flat, convex and/or concave by suitable processes. The isolation regions 54 can be recessed by using a suitable etching process, such as an etching process that is selective to the material of the isolation regions 54 .

Those of ordinary skill in the art to which this invention pertains will readily appreciate that the process described with respect to FIGS. 2A-5A is only one example of how fins 56 may be formed. In other embodiments, a dielectric layer may be formed over the top surface of substrate 50, trenches may be etched through the dielectric layer, a homo-epitaxial structure may be epitaxially grown in the trenches, and the dielectric layer may be recessed such that The epitaxial structure protrudes from the dielectric layer to form fins 56 . In other embodiments, hetero-epitaxial structures may be used for the fins. For example, the semiconductor strips 52 in FIG. 4A may be recessed, and a material different from the semiconductor strips 52 may be epitaxially grown in the recesses. In other embodiments, a dielectric layer may be formed over the top surface of substrate 50, trenches may be etched through the dielectric layer, hetero-epitaxial structures may be epitaxially grown in the trenches by using a different material than substrate 50, and The dielectric layer is recessed so that the hetero epitaxial structure protrudes from the dielectric layer to form fins 56 . In some embodiments of epitaxially grown homo-epitaxial or hetero-epitaxial structures, the growth material may be doped in situ during growth. In other embodiments, the homo-epitaxial or hetero-epitaxial structure may be doped by using ion implantation, eg, after epitaxial growth of the homo-epitaxial or hetero-epitaxial structure. Furthermore, it may be advantageous for the epitaxially grown material in the N-type metal oxide semiconductor region to be different from the material epitaxially grown in the P-type metal oxide semiconductor region. In various embodiments, the fins 56 may comprise silicon germanium (S _x Ge _1-x , where x may be between about 0 and 1), silicon carbide, pure or substantially pure germanium, Group III-V compound semiconductors, Group II-VI compound semiconductors or the like. Materials that can be used to form Group III-V compound semiconductors include, but are not limited to, InAs, AlAs, GaAs, InP, GaN, InGaAs, InAlAs, GaSb, AlSb, AlP, GaP, and the like, for example.

In FIGS. 6A-6B , a dummy dielectric layer 58 is formed on the fins 56 . The dummy dielectric layer 58 may be, for example, silicon oxide, silicon nitride, combinations of the foregoing, or the like, and may be deposited by a suitable technique (eg, chemical vapor deposition, physical vapor deposition, combinations of the foregoing, or the like) or Thermal growth (eg using thermal oxidation or similar). The dummy gate layer 60 is formed over the dummy dielectric layer 58 , and the mask 62 is formed over the dummy gate layer 60 . In some embodiments, dummy gate layer 60 may be deposited over dummy dielectric layer 58 and then planarized by fabrication using, for example, chemical mechanical polishing. Mask 62 may be deposited over dummy gate layer 60 . The dummy gate layer 6 may be made of polysilicon, for example, but other materials with high etch selectivity relative to the material of the isolation regions 54 may also be used. Mask 62 may comprise one or more layers such as silicon nitride, silicon oxynitride, silicon carbide, silicon nitride carbide, the like, or a combination of the foregoing.

6A-6B, in the embodiment shown, a single dummy dielectric layer 58, a single dummy gate layer 60, and a single mask 62 are formed across the first region 100A and the second region 100B. In other embodiments, individual dummy dielectric layers, individual dummy gate layers, and individual masks may be formed in the first region 100A and the second region 100B. In some embodiments, dummy dielectric layer 58 may have a thickness between about 0.8 nm and about 2.0 nm, and dummy gate layer 60 may have a thickness between about 50 nm and about 100 nm.

In Figures 7A-7C, mask 62 (please refer to Figures 6A and 6B) may be formed by using suitable photolithography and etching techniques to form mask 72 in first region 100A and second region 100B. The mask 72 may be a hard mask, and the pattern of the mask 72 in the first region 100A and the second region 100B may be different. Next, the pattern of the mask 72 in the first region 100A and the second region 100B may be transferred to the dummy gate layer 60 by a suitable etching technique. For convenience, the dummy gate layer 60 and the mask 72 may be collectively referred to as a dummy structure 70 . In some embodiments, the dummy gate layer 60 and the mask 72 are formed in the first region 100A and the second region 100B in separate processes, and may be formed of different materials in the first region 100A and the second region 100B. Alternatively, the pattern of mask 72 can be similarly transferred to dummy dielectric layer 58 . The patterns of the dummy structures 70 cover the individual channel regions of the fins 56 , and the patterns of the dummy structures 70 expose the source/drain regions of the fins 56 at the same time. The dummy structures 70 may also have a length direction substantially perpendicular to the length direction of the individual fins 56 . The size of the dummy structures 70 or the spacing between the dummy structures 70 may depend on the area of the die on which the dummy gates are formed. In some embodiments, the dummy structures 70 located in the input/output regions of the die (eg, the regions where the input/output circuits are located) are compared to the dummy structures 70 located in the logic regions of the die (eg, the regions where the input/output circuits are located) Structures 70 may have larger dimensions or larger spacing. In some embodiments, the dummy structures 70 may have a width between about 15 nm and about 40 nm.

Referring to FIGS. 7A-7C , suitable well regions (not shown) may be formed in fins 56 , semiconductor strips 52 and/or substrate 50 . For example, P-type wells can be formed in the first region 100A, and N-type wells can be formed in the second region 100B. The different implantation steps for the first region 100A and the second region 100B can be achieved through the use of a photoresist or other mask (not shown). For example, photoresist may be formed over the fins 56 and the isolation regions 54 in the first region 100A and the second region 100B. The photoresist is patterned to expose the second region 100B (eg, the P-type metal oxide semiconductor region) of the substrate 50 while protecting the first region 100A (eg, the N-type metal oxide semiconductor region). The photoresist can be formed by using spin coating techniques and can be patterned by using suitable photolithography techniques. After the photoresist is patterned, n-type impurities are implanted in the second region 100B, and the photoresist can be used as a mask to substantially prevent the implantation of the n-type impurities in the first region 100A. The n-type impurity may be phosphorus, arsenic, or the like, and may be implanted in the second region 100B to a concentration equal to or less than 10 ¹⁸ cm ^-3 , eg, between about 10 ¹⁷ cm ^-3 to about 10 ¹⁸ cm ^-3 in the range. After the implantation process, the photoresist is removed, for example, by using a suitable ashing process followed by a wet cleaning process.

After implantation of the second region 100B, a second photoresist (not shown) is formed over the fins 56 and isolation regions 54 in the first and second regions 100A and 100B. The second photoresist is patterned to expose the first region 100A of the substrate 50 while protecting the second region 100B. The photoresist can be formed by using spin coating techniques and can be patterned by using suitable photolithography techniques. The second photoresist can be formed by using spin coating techniques and can be patterned by using suitable photolithography techniques. After the second photoresist is patterned, p-type impurities are implanted in the first region 100A, and the second photoresist can be used as a mask to substantially prevent the p-type impurities from being implanted in the second region 100B. The p-type impurity may be boron, BF ₂ or the like, and may be implanted in the first region 100A to a concentration equal to or less than 10 ¹⁸ cm ^-3 , eg, between about 10 ¹⁷ cm ^-3 to about 10 ¹⁸ cm ^-3 in the range. After the implantation process, the photoresist is removed, for example, by using a suitable ashing process followed by a wet cleaning process.

After the implantation of the first region 100A and the second region 100B, annealing may be performed to activate the implanted p-type and/or n-type impurities. The implantation process may form P-type wells in the first region 100A and N-type wells in the second region 100B. In some embodiments of epitaxially grown fins, the growth material of fins 56 may be doped in-situ during the growth process.

In FIGS. 8A-8C , a first spacer layer 80A is formed on the exposed surface of the dummy structure 70 (see FIGS. 8A and 8B ) and/or the dummy dielectric layer 58 (see FIG. 8C ) over the fins 56 . The first spacer layer 80A may be formed using any suitable method. In some embodiments, deposition (eg, chemical vapor deposition, atomic layer deposition, or the like) may be used to form the first spacer layer 80A. In some embodiments, the first spacer layer 80A may comprise one or more layers such as silicon nitride (SiN), silicon oxynitride, silicon nitride carbide, silicon oxynitride (SiOCN), combinations of the foregoing, or the like.

Referring to FIGS. 8A-8C, lightly doped source/drain (LDD) regions 75 and 79 may be formed in the substrate 50 in the first region 100A and the second region 100B, respectively. Similar to the implantation process discussed above with reference to FIGS. 7A-7C, a mask (not shown), such as a photoresist, may be formed over the first region 100A (eg, an NMOS region) while exposing the second region 100A. region 100B (eg, a p-type metal oxide semiconductor region), and p-type impurities may be implanted into the exposed fins 56 in the second region 100B to form lightly doped source/drain regions 79 . During implantation of the lightly doped source/drain regions 79 , the dummy structures 70 may act as a mask to prevent (or at least reduce) dopant implantation in the channel regions of the exposed fins 56 . Thus, lightly doped source/drain regions 79 may be formed substantially in the source/drain regions of exposed fins 56 . Next, the mask can be removed. Thereafter, a second mask (not shown), such as a photoresist, may be formed over the second region 100B while exposing the first region 100A, and n-type impurities may be implanted into the exposed fins 56 in the first region 100A , to form lightly doped source/drain regions 75 . During implantation of the lightly doped source/drain regions 75 , the dummy structures 70 may act as a mask to prevent (or at least reduce) dopant implantation in the channel regions of the exposed fins 56 . Accordingly, lightly doped source/drain regions 75 may be formed substantially in the source/drain regions of exposed fins 56 . Next, the second mask can be removed. The n-type impurities may be any of the aforementioned n-type impurities, and the p-type impurities may be any of the aforementioned p-type impurities. Lightly doped source/drain regions 75 and 79 each have an impurity concentration in the range of about 10 ¹⁵ cm ^-3 to about 10 ¹⁶ cm ^-3 . An annealing process may be performed to activate the implanted impurities.

Referring to FIGS. 9A-9C, an etching process is performed on a portion of the first spacer layer 80A. The etching process may be a dry etching process, and may be anisotropic. After the etching process, lateral portions of the first spacer layer 80A over the lightly doped source/drain regions 75/79 and isolation regions 54 may be removed to expose the fins 56 and the mask 72 of the dummy structure 70 top surface. Portions of the first spacer layer 80A along the sidewalls of the dummy structures 70 and the fins 56 may remain, and the offset spacers 120 may be formed. In other embodiments, the first spacer layer 80A may also be removed from the sidewalls of the fins 56 . In some embodiments, the offset spacers 120 in the first region 100A and the offset spacers 120 in the second region 100B are formed simultaneously, while in other embodiments, the offset spacers 120 in the first region 100A and the second region 100B are formed simultaneously. The offset spacers 120 are formed in a separate process. In some embodiments, lateral portions of dummy dielectric layer 58 over lightly doped source/drain regions 75/79 and isolation regions 54 may also be removed.

In FIGS. 10A-10C, the second spacer layer 80B and the third spacer layer 80C are formed over the first region 100A and the second region 100B. Any suitable method of forming the first spacer layer 80A may be used. In some embodiments, deposition (eg, chemical vapor deposition, atomic layer deposition, or the like) may be used to form the second spacer layer 80B and the third spacer layer 80C. In some embodiments, the second spacer layer 80B and the third spacer layer 80C may include one or more layers such as oxide materials, silicon nitride, silicon oxynitride, silicon nitride carbide, silicon oxynitride, combinations of the foregoing, or the like . In some embodiments, one of the second spacer layer 80B or the third spacer layer 80C may be omitted.

Referring to FIGS. 11A-11C , a patterning process is performed to remove the second spacer layer 80B and the third spacer layer 80C in the first region 100A. Any acceptable patterning process can be used. In some embodiments, the mask 118 is formed over the first region 100A and the second region 100B. The mask 118 may be a single layer or may include multiple layers, such as a three-layer mask structure or other types of mask structures. In some cases, mask 118 may include photoresist, although mask 118 may include other materials. The mask 118 is patterned to expose the first region 100A. Mask 118 can be patterned using suitable photolithography techniques.

Referring to FIGS. 11A-11C , an etching process is performed on a part of the second spacer layer 80B and a part of the third spacer layer 80C using the mask 118 as a mask. The etching process may be a dry etching process, and may be anisotropic. After the etching process, lateral portions of the second spacer layer 80B and the third spacer layer 80C over the lightly doped source/drain regions 75/79 and isolation regions 54 may be removed to expose the fins 56 and the mask 72 top surface. Portions of the second spacer layer 80B and the third spacer layer 80C along the sidewalls of the dummy structures 70 and fins 56 may remain and form gate spacers 122 and fin spacers 130 . In some embodiments, gate spacers 122 and fin spacers 130 in the first region 100A and gate spacers 122 and fin spacers 130 in the second region 100B are formed simultaneously, while in other embodiments, Before forming the gate spacers 122 and fin spacers 130 in the first region 100A, the gate spacers 122 and the fin spacers 130 in the second region 100B are formed. In some embodiments, prior to forming the third spacer layer 80C, the second spacer layer 80B may be etched as described above, and then the third spacer layer 80C may be etched to form the gate spacers 122 and the fin spacers 130 .

Figures 12-16C show the formation of epitaxial source/drain regions 82 between adjacent fins 56 in the first region 100A. Figures 12-15C are all shown along the reference section B-B of Figure 1 . During formation of the epitaxial source/drain regions 82 in the first region 100A, the second region 100B may be masked (eg, through the mask 118 ). In some embodiments, the epitaxial source/drain regions 82 may be formed in the first region 100A before the epitaxial source/drain regions 84 are formed in the second region 100B. In other embodiments, the epitaxial source/drain regions 84 may be formed in the second region 100B before the epitaxial source/drain regions 82 are formed in the first region 100A.

Referring to FIG. 12 , a first patterning process is performed on the fins 56 to form notches 124 in the source/drain regions of the fins 56 . The first patterning may be performed in such a way that notches 124 are formed between adjacent dummy structures 70 (in the inner region of fins 56 ) or between isolation regions 54 and adjacent dummy structures 70 (in the end regions of fins 56 ) chemical process. In some embodiments, the first patterning process may include a suitable anisotropic dry etch process while using dummy structures 70, gate spacers 122, fin spacers 130, and/or isolation regions 54 as merging masks. Suitable anisotropic dry etching processes may include reactive ion etching, neutron beam etching, the like, or a combination of the foregoing. In some embodiments in which the first patterning process uses reactive ion etching, process parameters such as process gas mixture, voltage bias, and RF power may be selected such that etching occurs primarily through the use of physical etching, such as ion bombardment. In some embodiments, the voltage bias can be increased to increase the energy of the ions used in the ion bombardment process, and thus increase the rate of physical etch. Since physical etching is anisotropic in nature and chemical etching is isotropic in nature, the etching rate of this etching process is higher in the vertical direction than in the lateral direction. In some embodiments, the anisotropic etch process can be accomplished by using process gases including BF2, Cl2, _CH3F , _CH4 , _HBr , _O2 , Ar, other etchant gases, combinations _of the foregoing, or the like mixture to proceed. In some embodiments, the first patterning process forms the notch 124 having a U-shaped bottom surface. The notch 124 may also be referred to as a U-shaped notch, such as the exemplary notch 124 shown in FIG. 12 . FIG. 12 also shows that the notch 124 has a top access distance TP0, a middle access distance MP0, and a bottom access distance BP0, each of the top access distance TP0, the middle access distance MP0 and the bottom access distance BP0 from the adjacent dummy gate layers. Measured laterally from the edge to the sidewall of the notch 124 . The top proximity distance TP0 is measured at the top of the fin 56, and the top proximity distance TP0 may be between about 1 nm and about 30 nm. The bottom proximity distance BP0 is measured at the bottom of the notch 124, and the bottom proximity distance BP0 may be between about 1 nm and about 30 nm. The intermediate proximity distance MP0 is measured approximately halfway between the top of the fin 56 and the bottom of the notch 124, and may be between about 1 nm and about 30 nm. As shown in FIG. 12, the notch 124 has a notch depth D0, measured from the top surface of the fin 56 to the bottom of the notch 124, which may be between about 40 nm and about 100 nm. In some embodiments, the etch process that forms the recesses 124 may also etch the isolation regions 54 . In some cases, after the etching process, a cleaning process may be performed, such as a dry cleaning process (eg, an ashing process), a wet cleaning process, the like, or a combination of the foregoing. In some cases, native oxide (not shown) may be formed on the exposed surface of the U-shaped notch 124 .

Referring to FIG. 13 , a second patterning process is performed on the fin 56 to reshape the U-shaped notch 124 and form the reshaped notch 126 . As shown in FIG. 13 , the second patterning process expands the U-shaped notch 124 (shown in phantom in FIG. 13 for comparison) to form a reshaped notch 126 . In Figures 13-15C, the sidewall area of the notch 126 at or near the bottom of the notch 126 is labeled lower sidewall 125, and the sidewall area of the notch 126 at or near the top of the notch 126 is labeled upper side wall 127 . The sidewall regions labeled lower sidewall 125 and upper sidewall 127 in Figure 13 are exemplary and may differ from those shown. The lower sidewall 125 may be separated from the upper sidewall 127 by other sidewall regions, or the lower sidewall 125 may be adjacent to the upper sidewall 127 . In some embodiments, upper sidewall 127 may extend between about 10 nm and about 90 nm from the top surface of fin 56 . In some embodiments, the lower sidewall 125 may extend between about 10 nm and about 90 nm from the bottom surface of the recess 126 . In some embodiments, upper sidewall 127 may extend between about 10% and about 90%, eg, about 50%, of the depth of the sidewall of recess 126 . In some embodiments, the lower sidewall 125 may extend between about 10% and about 90%, such as about 50%, of the sidewall depth of the recess 126 . In some cases, the lower sidewall 125 is defined as the sidewall region of the notch 126 having a surface along the crystal plane, as described in more detail below. In some embodiments, the second patterning process causes the bottom approach distance BP1 of the reshaped notch 126 to be greater than the bottom approach distance BP0 of the notch 124 . In some embodiments, the second patterning process may include an anisotropic dry etching process while using the dummy structures 70, gate spacers 122, and/or isolation regions 54 as merging masks. In some cases, the second patterning process may have a slower etch rate than the first patterning process.

In some embodiments, the second patterning process includes a plasma etch process performed in a process chamber, wherein process gases are supplied to the process chamber. In some embodiments, the plasma is direct plasma. In other embodiments, the plasma is remote plasma generated in another plasma generation chamber connected to the process chamber. Process gases can be activated to plasma by any suitable method for generating plasma, such as transformer coupled plasma (TCP) systems, inductively coupled plasma (ICP) systems, magnetically assisted reactive ion techniques, Electron cyclotron resonance technique or similar method.

In some embodiments, the process gas used for the plasma etch process includes an etchant gas such as _H2 , Ar, other gases, or combinations of gases. In some embodiments, a carrier gas, such as _N2 , Ar, He, Xe, or the like, may be used to carry the process gas to the process chamber. The process gas may flow into the process chamber at a rate between about 10 seem and about 3000 seem. For example, the etchant gas may flow into the process chamber or plasma generation chamber at a rate between about 10 seem and about 1000 seem, eg, about 70 seem. The carrier gas may flow into the process chamber at a rate between about 10 seem and about 3000 seem, eg, about 130 seem. In some cases, the lower flow of process gases can reduce the etch rate of the second patterning process and reduce damage to the fins 56 during the second patterning process. In some embodiments, the plasma etch process is performed at a temperature between about 200°C and about 400°C, eg, about 330°C. In some cases, higher process temperatures can reduce the etch rate of the second patterning process and reduce damage to the fins 56 during the second patterning process. The pressure in the process chamber may be between about 60 mTorr and about 120 mTorr, eg, about 100 mTorr. In some cases, higher process pressures can make the plasma more stable or reproducible. The higher process pressure may also reduce damage to the fins 56 during the second patterning process. In some embodiments, the plasma etch process is performed for between about 10 seconds and about 1000 seconds. In some embodiments, the plasma etch process includes multiple steps.

In some embodiments, the second patterning process includes a plasma etching process using hydrogen (H) radicals. Hydrogen radicals can be formed by flowing _H2 gas into the plasma generation chamber and igniting the plasma in the plasma generation chamber. In some embodiments, an additional gas, such as Ar, may be ignited into plasma in the plasma generating chamber. The fins 56 are exposed to hydrogen radicals, and the hydrogen radicals etch the sidewalls of the U-shaped notch 124 laterally and vertically, forming the reshaped notch 126 . In some cases, hydrogen radicals may preferentially etch certain crystal planes of the semiconductor material of fin 56 . For example, for embodiments in which the material of fin 56 is silicon, hydrogen radicals can selectively etch facet (100) as compared to facet (111) or facet (110). Although examples of crystal planes (100) and (111) are shown in Figure 13, there may also be crystal planes (100), (111) or (110) that are not shown. In some cases, the etch rate of crystal plane (100) may be about 3 times greater than the etch rate of crystal plane (111). Due to selectivity, the etching of hydrogen radicals along the crystal planes (111) or (110) of the silicon may tend to be slower or stop during the second patterning process.

In some embodiments, the selective etching of hydrogen radicals may result in some sidewalls of the reshaped recess 126 having a surface that maintains the crystal plane ( 111 ) or the crystal plane ( 110 ) after the second patterning process. As shown in FIG. 13, some or all of the lower sidewalls 125 of the notch 126 have surfaces along the crystal plane. The lower sidewall 125 may have a surface comprising crystal plane (111), crystal plane (110), or a combination of crystal plane (111) or crystal plane (110). In some cases, the crystal plane ( 111 ) to crystal plane ( 110 ) ratio in lower sidewall 125 may depend on the crystallographic orientation of the material of fin 56 or substrate 50 . In some cases, the lower sidewall 125 having a surface along the crystal plane can cause the reshaped notch 126 to have a tapered, pointed or V-shape at the bottom as shown in FIG. 13 . For example, at the bottom of the reshaped recess 126, the lower sidewalls 125 on both sides may have surfaces along crystal planes that meet at angles defined by the intersection of the crystal planes of the surfaces. For example, in some cases, the bottom of the reshaped notch 126 may be defined by the intersection of the crystallographic plane of the first sidewall surface and the crystallographic plane of the second sidewall surface. Figure 13 shows the reshaped notch 126 having a pointed tip shape at the bottom laterally centered between the gate spacers 122 on either side, but in other cases the bottom of the notch 126 may have a laterally offset tip head shape. In some cases, some, none, or all of the upper sidewalls 127 of the reshaped recesses 126 have flat surfaces (eg, crystal planes (111) or (110)). In some cases, the reshaped notch 126 may have a plane that is flat or straight but not along a crystal plane. For example, the reshaped notch may have vertical, lateral, or slanted surfaces that are not along the crystal planes. In some cases, as shown in FIG. 13, the upper sidewall 127 may have a curved or convex surface.

In some cases, the bottom access distance (eg, bottom access distance BP1 shown in FIG. 13 ) can be increased by having the bottom of the reshaped notch 126 defined by the described crystal plane intersection. For example, a reshaped notch 126 with a V-shaped bottom may be further away from an adjacent fin than a notch with a U-shaped bottom or a more horizontal bottom surface, such as the notch 124 shown in FIG. 12 . In some cases, the larger bottom approach distance reduces the amount of dopant diffusion in the epitaxial source/drain regions into or under the channel of the finFET. Dopants that reduce diffusion can improve device performance. For example, reducing the diffusion of dopants can reduce the undesired Drain-Induced Barrier Lowering (DIBL) effect or can reduce the off-state leakage current of the FinFET.

Figure 14 shows another embodiment of the reshaped notch 126 after the second patterning process has been performed. The reshaped notch 126 shown in FIG. 14 is similar to the reshaped notch 126 shown in FIG. 13 except that a portion 128 of the fin 56 remains under the gate spacer 122 after the second patterning process. In some embodiments, the second patterning process with the remaining portion 128 may have a shorter duration than the second patterning process without the remaining portion 128 (as shown in FIG. 13 ). For example, in some embodiments, the second patterning process of retaining portion 128 may be performed for a first duration that is less than half the second duration of the second patterning process of removing portion 128, but In other embodiments, the first duration may be another fraction of the second duration. In some embodiments, portion 128 may extend from gate spacer 122 toward fin 56 a distance between about 0.1 nm and about 10 nm, and may extend downward from gate spacer 122 a distance between about 0.1 nm and about 10 nm between. In some embodiments, the portion 128 has a sidewall surface that is remote from the center of the recess 126 (ie, toward the fin 56 ), denoted by the symbol "S" in the example of FIG. 14 . In some embodiments, surface S comprises one or more crystalline planar surfaces. For example, surface S may have crystal planes (111) or (110) due to the above-mentioned selective etching of hydrogen radicals. In some embodiments, the angle A2 between the sidewall of the notch 126 and the surface S may be between about 35° and about 125°. In some cases, portions 128 of fins 56 remain below gate spacers 122 as additional highly doped regions that can effectively extend lightly doped source/drain regions 75/79 to the gate below the spacer 122 . In this manner, portion 128 may provide additional device performance improvement similar to that provided by lightly doped source/drain regions 75/79. In some cases, after the second patterning process, retaining the portion 128 of the fin 56 under the gate spacer 122 may protect the replacement gate (see FIGS. 20A-20C ) from dopants from the epitaxial source The /drain region (see Figures 16A-16C) diffuses into the replacement gate and thus improves device performance. In some embodiments, the shape (eg, angle A2) or size of portion 128 can be controlled by controlling parameters of the second patterning process, such as process duration, process temperature, process pressure, process gas flow (eg, _H2 flow) or other parameters.

Figures 15A-15C show other embodiments in which reshaped notches 126 having different shapes may be formed by using the second patterning process described herein. The reshaped notch 126 shown in Figures 15A-15C is similar to the reshaped notch 126 shown in Figures 13-14. For example, a second patterning process with hydrogen radicals used in a plasma etch process can be used to form the recesses 126 shown in FIGS. 15A-15C. In addition, the reshaped notch 126 shown in FIGS. 13-15C is for illustration purposes, and the reshaped notch 126 may have a different shape or size than the shown reshaped notch 126, or may have the shown reshape combination of the shapes or dimensions of the notches 126 . In some embodiments, the shape or size of the reshaped recesses 126 can be controlled by controlling parameters of the second patterning process, such as process duration, process temperature, process pressure, process gas flow, or other parameters. In some embodiments, the parameters of the second patterning process can be controlled to form reshaped recesses 126 having a desired shape or having a desired size. In some cases, by controlling the shape of the reshaped notch 126, the shape of the channel region of the adjacent finFET is also controlled. In this manner, channel regions can be formed with desired characteristics, such as specific top access distances, intermediate access distances, and bottom access distances. The sidewall profile of the channel region can also be controlled to have specific features, such as uniform sidewalls, vertical sidewalls, tapered sidewalls, and the like. In some cases, the particular shape of the reshaped recess 126 (eg, having a V-shaped bottom or having vertical sidewalls, etc.) may be more suitable for a particular source/drain epitaxial material or for use in the reshaped recess 126 The epitaxial material forming process for forming the epitaxial source/drain regions. In this manner, the embodiments shown herein present illustrative examples of some shapes of the reshaped notches 126 that can be controlled to produce a second patterning process as described herein. As such, the second patterning process described herein allows for greater flexibility in controlling the shape of the notch or the shape of the channel region of the FFET.

FIG. 15A shows another example of the shape of the reshaped notch 126 that is similar to the shape of the reshaped notch 126 shown in FIG. 13 . The lower sidewalls 125 of the notch 126 may include surfaces along crystal planes (eg, crystal planes (111) or (110)), and the upper sidewalls 127 may include surfaces that are not along crystal planes (eg, curved surfaces). The reshaped notch 126 may have a notch depth D1 of between about 40 nm and about 100 nm measured perpendicularly from the top surface of the fin 56 to the bottom of the notch 126 . The reshaped notch 126 may have a top width W1 of between about 15 nm and about 60 nm measured across the notch 126 from the top of one fin 56 to the top of the opposing fin 56 . The reshaped notch 126 may have an intermediate width W2 of between about 15 nm and about 80 nm, measured from one fin 56 to the opposite fin 56 across the notch 126 at about half the notch depth D1. The ratio of widths W1:W2 may be between about 0.5:1 and about 1:1. The reshaped notch 126 may have a width W3 of between about 5 nm and about 50 nm measured from one fin 56 to the opposite fin 56 across the notch 126 at about halfway between the intermediate width W2 and the bottom of the notch 126 . The ratio of widths W3:W2 may be between about 0.5:1 and about 1:1. The reshaped notch may have a top access distance TP1 between about 1 nm and about 15 nm, a middle access distance MP1 between about 1 nm and about 10 nm, and a bottom access distance BP1 between about 1 nm and about 25 nm. The second patterning process described herein may allow for a smaller intermediate proximity distance MP1, which in some cases may result in reduced drain induced barrier reduction effects in finFETs. In some cases, the second patterning process may be able to decrease the middle proximity distance MP1 with less increased depth D1 or with less decreased top proximity distance TP1 than other techniques. The lower sidewall 125 of the notch 126 may have an angle A1 defined by a crystal plane (eg, crystal plane (111) or (110)) with the horizontal plane. The angle A1 may be between about 20° and about 80°.

FIG. 15B shows another embodiment of a reshaped notch 126 with a straight upper side wall 127 . In some cases, the upper sidewall 127 may be substantially vertical (as shown in Figure 15B) or may be angled. The lower sidewall 125 may include surfaces along a crystal plane (eg, crystal plane (111) or (110)). The reshaped notch 126 may have a notch depth D1 of between about 40 nm and about 100 nm measured perpendicularly from the top surface of the fin 56 to the bottom of the notch 126 . The reshaped notch 126 may have a depth D2 of between about 30 nm and about 100 nm, measured vertically from the top surface of the fin 56 to the lower sidewall 125 . The reshaped notch 126 may have a top width W1 of between about 10 nm and about 60 nm measured across the notch 126 from the top of one fin 56 to the top of the opposite fin 56 . The reshaped notch 126 may have an intermediate width W2 of between about 10 nm and about 80 nm measured across the notch 126 from one fin 56 to the opposite fin 56 at about half the notch depth D1. The ratio of widths W1:W2 may be between about 0.5:1 and about 1:1. The reshaped notch 126 may have a width W3 of between about 5 nm and about 60 nm measured across the notch 126 from one fin 56 to the opposite fin 56 at about halfway between the intermediate width W2 and the bottom of the notch 126 . The ratio of widths W3:W2 may be between about 0.5:1 and about 1:1. The reshaped notch may have a top access distance TP1 between about 1 nm and about 15 nm, a middle access distance MP1 between about 1 nm and about 15 nm, and a bottom access distance BP1 between about 1 nm and about 30 nm. The lower sidewall 125 of the notch 126 may have an angle A1 defined by a crystal plane (eg, crystal plane (111) or (110)) with the horizontal plane. The angle A1 may be between about 20° and about 80°. In some cases, forming the reshaped notch 126 with more vertical sidewalls may allow for a more uniform profile of the channel region under the gate stack of the finFET. By improving the uniformity of the channel region profile, finFETs can turn on and off more uniformly across the channel region, which can improve device speed, current uniformity, and efficiency.

FIG. 15C shows another embodiment of a reshaped notch 126 having an upper side wall 127 , an intermediate side wall 129 and a lower side wall 125 . In the example recess 126 shown in Figure 15C, the upper sidewall 127 and the lower sidewall 125 include surfaces along a crystal plane (eg, crystal plane (111) or (110)). The intermediate sidewall 129 may be vertical (as shown in Figure 15C) or may have a curved or sloped profile. The reshaped notch 126 may have a notch depth D1 of between about 40 nm and about 100 nm measured perpendicularly from the top surface of the fin 56 to the bottom of the notch 126 . The reshaped notch 126 may have a depth D3 of between about 1 nm and about 30 nm, measured vertically from the top surface of the fin 56 to the intermediate sidewall 129 . The intermediate sidewalls 129 may extend between about 10 nm and about 50 nm by a vertical depth D4. The reshaped notch 126 may have a top width W1 of between about 10 nm and about 60 nm measured across the notch 126 from the top of one fin 56 to the top of the opposite fin 56 . The reshaped notch 126 may have a width W4 of between about 10 nm and about 70 nm measured across the notch 126 from one fin 56 to the opposite fin 56 at the top of the intermediate sidewall 129 . The reshaped notch 126 may have a width W5 of between about 10 nm and about 80 nm measured across the notch 126 from one fin 56 to the opposite fin 56 at the bottom of the intermediate sidewall 129 . The ratio of widths W5:W4 may be between about 0.5:1 and about 1:1. The reshaped notch 126 may have a width W3 of between about 1 nm and about 40 nm, measured from one fin 56 to the opposite fin 56 across the notch 126 at about halfway between the width W5 and the bottom of the notch 126 . The reshaped notch may have a top access distance TP1 between about 1 nm and about 20 nm, a middle access distance MP1 between about 1 nm and about 15 nm, and a bottom access distance BP1 between about 2 nm and about 30 nm. The lower sidewall 125 of the notch 126 may have an angle A1 defined by a crystal plane of the lower sidewall 125 (eg, crystal plane (111) or (110)) with the horizontal plane. The angle A1 may be between about 20° and about 80°. The upper sidewall 127 of the notch 126 may have an angle A3 defined by a crystal plane (eg, crystal plane (111) or (110)) with the horizontal plane. Angle A3 may be between about 45° and about 90°. In some cases, forming a reshaped notch 126 with relatively vertical sidewalls (eg, middle sidewall 129 ) may allow for a more uniform profile of the channel region under the gate stack of the finFET. By improving the uniformity of the channel region profile, finFETs can turn on and off more uniformly across the channel region, which can improve device speed, current uniformity, and efficiency.

Figures 16A-16C show the formation of epitaxial source/drain regions 82 in the first region 100A. The epitaxial source/drain regions 82 may be a single layer or comprise two or more layers of material. For example, the epitaxial source/drain region 82 shown in FIG. 16B includes a plurality of epitaxial layers 82A-82C. For clarity, the other figures do not show multiple epitaxial layers. In some embodiments, the epitaxial source/drain regions 82 are formed by using metal-organic chemical vapor deposition (MOCVD), molecular beam epitaxy (MBE), liquid phase epitaxy (liquid phase epitaxy) phase epitaxy (LPE), vapor phase epitaxy (VPE), selective epitaxial growth (SEG), a combination of the foregoing, or similar methods are epitaxially grown in the recess 126 . In some embodiments, epitaxial source/drain regions 82 are grown in the same process chamber as the second patterning process is performed. In some cases, prior to forming epitaxial source/drain regions 82, fins 56 may be subjected to a cleaning process, such as a dry cleaning process (eg, an ashing process), a wet cleaning process (eg, using Caro's Strip or HF), the like method or a combination of the foregoing. Epitaxial source/drain regions 82 may have surfaces that are raised from corresponding surfaces of fins 56 and may have facets. Epitaxial source/drain regions 82 are formed in the fins 56 such that each dummy structure 70 is disposed between corresponding adjacent pairs of epitaxial source/drain regions 82 . The epitaxial source/drain regions 82 may comprise any suitable material, such as any material suitable for n-type fin field effect transistors. For example, if fin 56 is silicon, epitaxial source/drain regions 82 may comprise silicon, SiC, SiCP, SiP, SiGeB, the like, or a combination of the foregoing. The different layers of epitaxial source/drain regions 82 may be of different materials or may be of the same material, and may be grown in separate steps. For example, epitaxial layer 82A (sometimes referred to as the first epitaxial layer) may be deposited in the recess 126 first, and then epitaxial layer 82B (sometimes referred to as the second epitaxial layer) may be deposited in the epitaxial layer Over epitaxial layer 82A, then epitaxial layer 82C (sometimes referred to as a third epitaxial layer) may be deposited over epitaxial layer 82B. In some embodiments, epitaxial layer 82A may comprise materials such as silicon, SiC, SiP, the like, or a combination of the foregoing. The epitaxial layer 82A may be undoped or doped. For example, in some embodiments, epitaxial layer 82A may be doped with phosphorus to a concentration between about 5x10 ¹⁹ cm ^-3 and about 5x10 ²⁰ cm ^-3 , although other dopants or concentrations may be used. In some embodiments, epitaxial layer 82A may be formed to have a thickness between about 5 nm and about 20 nm. In some embodiments, epitaxial layer 82A may include a stressor material that stresses the channel regions of fins 56 . For example, the stress may be tensile stress for n-type finfield effect transistors. In some embodiments, epitaxial layer 82B may include materials such as silicon, SiP, the like, or a combination of the foregoing. The epitaxial layer 82B may be undoped or doped. For example, in some embodiments, epitaxial layer 82B may be doped with phosphorus to a concentration between about 5x10 ²⁰ cm ^-3 and about 4x10 ²¹ cm ^-3 , although other dopants or concentrations may be used. In some embodiments, epitaxial layer 82B may be formed to have a thickness between about 15 nm and about 60 nm. In some embodiments, epitaxial layer 82C may include materials such as silicon, SiP, SiGe, SiGe:P, the like, or a combination of the foregoing. The epitaxial layer 82C may be undoped or doped. For example, in some embodiments, epitaxial layer 82C may be doped with phosphorus to a concentration of between about 1 x 10 ²¹ cm ^-3 and about 3 x 10 ²¹ cm ^-3 , although other dopants or concentrations may be used. In some embodiments, epitaxial layer 82C may be formed to have a thickness between about 5 nm and about 20 nm. In some cases, the tapered shape of the reshaped notch 126 may allow for improved filling efficiency of the epitaxial source/drain regions 82 during formation of the epitaxial source/drain regions 82 .

In some embodiments, the epitaxial source/drain regions 82 in the first region 100A may be implanted with dopants, similar to the aforementioned process for forming the lightly doped source/drain regions 75/79, and then Perform annealing (see Figures 8A, 8B and 8C). The epitaxial source/drain regions 82 may have an impurity concentration in a range between about 10 ¹⁹ cm ⁻³ and about 10 ²¹ cm ⁻³ . The n-type impurities used for the source/drain regions in the first region 100A (eg, the n-type metal oxide semiconductor region) may be any of the aforementioned n-type impurities. In other embodiments, the material of epitaxial source/drain regions 82 may be doped in-situ during growth. In the embodiment shown, each epitaxial source/drain region 82 is physically separated from other epitaxial source/drain regions 82 . In other embodiments, two or more adjacent epitaxial source/drain regions 82 may be merged. An embodiment of this, shown in FIG. 22, combines two adjacent epitaxial source/drain regions 82 to form a common source/drain region. In some embodiments, more than two adjacent epitaxial source/drain regions 82 may be merged.

Referring to FIGS. 17A-17C, after the epitaxial source/drain regions 82 in the first region 100A are formed, the epitaxial source/drain regions 84 are formed in the second region 100B. In some embodiments, epitaxial source/drain regions 84 are formed in second region 100B using a similar formation method for epitaxial source/drain regions 82 described above with reference to FIGS. 12-15C, and in order to For brevity, detailed descriptions are not repeated. In some embodiments, during formation of the epitaxial source/drain regions 84 in the second region 100 (eg, p-type metal oxide semiconductor region), the first region 100A (eg, n-type metal oxide semiconductor region) may be masked (not shown) material semiconductor region). Afterwards, the source/drain regions of the fins 56 in the second region 100B are etched to form a notch similar to the reshaped notch 126 (please refer to FIGS. 13-15C ) (as shown in FIGS. 17B-17C to fill the epitaxy) crystal source/drain regions 84). For example, a first patterning process can be used to form a U-shaped notch similar to U-shaped notch 124 (see FIG. 12), followed by a second patterning process to reshape the notch. The second patterning process may include, for example, a plasma etching process using hydrogen radicals or may include other techniques described above. The reshaped notch in the second region 100B may be formed by using a formation method similar to that of the reshaped notch 126 in the first region 100A above with reference to FIGS. 12-15C. For the sake of brevity, it is not repeated here.

Next, the epitaxial source/drain regions 84 in the second region 100B are formed by using metal organic chemical vapor deposition, molecular beam epitaxy, liquid phase epitaxy, vapor phase epitaxy, selective epitaxial growth, or a combination of the foregoing. or a similar method for epitaxial growth in the notch. In some embodiments, epitaxial source/drain regions 84 are grown in the same process chamber as the second patterning process. In some cases, prior to forming epitaxial source/drain regions 84, fins 56 may be subjected to a cleaning process, such as a dry cleaning process (eg, an ashing process), a wet cleaning process (eg, using Caro's Strip or HF), the like method or a combination of the foregoing. The epitaxial source/drain regions 84 may be a single layer or comprise two or more layers of material. Epitaxial source/drain regions 84 may comprise any suitable material, such as any material suitable for use in p-type fin field effect transistors. For example, if fin 56 is silicon, epitaxial source/drain regions 84 may comprise SiGe, SiGeB, Ge, GeSn, the like, or a combination of the foregoing. The different layers of epitaxial source/drain regions 84 may be of different materials or may be of the same material, and may be grown in separate steps. For example, a first epitaxial layer can be deposited in the recess first, then a second epitaxial layer can be deposited over the first epitaxial layer, and then a third epitaxial layer can be deposited over the second epitaxial layer. In some embodiments, the first epitaxial layer may include materials such as silicon, SiGe, SiGe:B, the like, or a combination of the foregoing. The first epitaxial layer may be undoped or doped. For example, in some embodiments, the first epitaxial layer may be SiGe having between about 1% and about 25% Ge atomic percent, or may be doped with boron concentration between about 5× ^{10 19} cm ⁻³ and about Material between 1x10 ²⁰ cm ^-3 , but other dopants or concentrations can be used. In some embodiments, the first epitaxial layer may be formed to have a thickness between about 5 nm and about 20 nm. In some embodiments, the first epitaxial layer may include a stressor material that stresses the channel regions of the fins 56 . For example, the stress may be a compressive stress for a p-type FinFET. In some embodiments, the second epitaxial layer may include materials such as silicon, SiGe, SiGe:B, the like, or a combination of the foregoing. The second epitaxial layer may be undoped or doped. For example, in some embodiments, the second epitaxial layer may be SiGe having between about 25 and about 55% Ge atomic percent, or may be doped with boron at a concentration between about 1×10 ²⁰ cm ⁻³ and about Material between 2x10 ²¹ cm ^-3 , but other dopants or concentrations can be used. In some embodiments, the second epitaxial layer may be formed to have a thickness between about 20 nm and about 60 nm. In some embodiments, the third epitaxial layer may include materials such as silicon, SiGe, SiGe:B, the like, or a combination of the foregoing. The third epitaxial layer may be undoped or doped. For example, in some embodiments, the third epitaxial layer may be SiGe having between about 45% and about 60% Ge atomic percent, or may be doped with boron at a concentration between about 5x10 ²⁰ cm ^-3 and about Material between 2x10 ²¹ cm ^-3 , but other dopants or concentrations can be used. In some embodiments, the third epitaxial layer may be formed to have a thickness between about 10 nm and about 20 nm. Epitaxial source/drain regions 84 may have surfaces that are raised from corresponding surfaces of fins 56 and may have facets. In the second region 100B, epitaxial source/drain regions 84 are formed in the fins 56 such that each dummy structure 70 is disposed between a corresponding adjacent pair of epitaxial source/drain regions 84 . In some embodiments, epitaxial source/drain regions 84 may extend through fins 56 and into semiconductor strips 52 .

In some embodiments, the epitaxial source/drain regions 84 in the second region 100B may be implanted with dopants, similar to the processes previously described for forming the lightly doped source/drain regions 75/79, and then Perform annealing (see Figures 8A, 8B and 8C). The epitaxial source/drain regions 84 may have an impurity concentration in a range between about 10 ¹⁹ cm ⁻³ and about 10 ²¹ cm ⁻³ . The p-type impurities used for the epitaxial source/drain regions 84 in the second region 100B (eg, the p-type metal oxide semiconductor region) may be any of the aforementioned p-type impurities. In other embodiments, the material of epitaxial source/drain regions 84 may be doped in-situ during growth. A portion of epitaxial source/drain regions 82 and 84 may have curved sidewalls or substantially straight sidewalls depending on the shape of the corresponding reshaped notch. In the embodiment shown, each epitaxial source/drain region 84 is physically separated from other epitaxial source/drain regions 84 . In other embodiments, two or more adjacent epitaxial source/drain regions 84 may be merged. An embodiment of this, shown in FIG. 22, combines two adjacent epitaxial source/drain regions 84 to form a common source/drain region. In some embodiments, more than two adjacent epitaxial source/drain regions 84 may be merged.

Referring to FIGS. 17A-17C , an etch stop layer 87 and an interlayer dielectric (ILD) 88 are deposited over the dummy structure 70 and over the epitaxial source/drain regions 82 and 84 . In some embodiments, the interlayer dielectric 88 is a flowable film formed by flowable chemical vapor deposition. In some embodiments, the interlayer dielectric 88 is formed of a dielectric material, such as Phospho-Silicate Glass (PSG), Boro-Silicate Glass (BSG), boron-doped phosphorus Silicate glass (Boron-Doped Phospho-Silicate Glass, BPSG), undoped silicate glass (undoped Silicate Glass, USG) or the like, and can be deposited by any suitable method, such as chemical vapor deposition, electroplating Slurry assisted chemical vapor deposition, combinations of the foregoing, or similar methods. In some embodiments, etch stop layer 87 is used as a stop layer when interlayer dielectric 88 is patterned to form openings for forming contacts. Accordingly, the material of the etch stop layer 87 may be selected such that the material of the etch stop layer 87 has a lower etch rate than the material of the interlayer dielectric 88 .

Referring to FIGS. 18A-18C , a planarization process (eg, a chemical mechanical polishing process) may be performed to make the top surface of the interlayer dielectric 88 flush with the top surface of the dummy structure 70 . After the planarization process, the top surface of the dummy structure 70 is exposed from the interlayer dielectric 88 . In some embodiments, chemical mechanical polishing may also remove mask 72 or a portion of mask 72 on dummy structure 70 .

Referring to FIGS. 19A-19C, the mask 72 and a portion of the dummy structure 70 are removed in the etching step, so that the notch 90 is formed. Each notch 90 exposes a channel region of the corresponding fin 56 . Each channel region is disposed between each pair of adjacent epitaxial source/drain regions 82 in the first region 100A or between each pair of adjacent epitaxial source/drain regions 84 in the second region 100B between. During the removal process, the dummy dielectric layer 58 may serve as an etch stop layer when the dummy structure 70 is etched. After removing dummy structure 70, dummy dielectric layer 58 may then be removed.

Referring to FIGS. 20A-20C, gate dielectric layers 92 and 96 for replacing gate electrodes and gate electrodes 94 and 98 are formed in the first region 100A and the second region 100B, respectively. Gate dielectric layers 92 and 96 are compliantly deposited in recess 90 , eg, on the top surface and sidewalls of fin 56 , on the sidewalls of gate spacers 122 and fin spacers 130 , and on the sidewalls of interlayer dielectric 88 , respectively. on the top surface. In some embodiments, gate dielectric layers 92 and 96 comprise silicon oxide, silicon nitride, or multiple layers of the foregoing. In other embodiments, gate dielectric layers 92 and 96 comprise high-k dielectric materials, and in these embodiments, gate dielectric layers 92 and 96 may have dielectric constant values greater than about 7.0, and may include metal oxides or silicates of Hf, Al, Zr, La, Mg, Ba, Ti, Pb and combinations of the foregoing. The methods of forming the gate dielectric layers 92 and 96 may include molecular beam deposition (MBD), atomic layer deposition, plasma assisted chemical vapor deposition, combinations of the foregoing, or the like.

Next, gate electrodes 94 and 98 are deposited over gate dielectric layers 92 and 96 , respectively, and fill the remainder of recess 90 . Gate electrodes 94 and 98 may be made of metal-containing materials such as TiN, TaN, TaC, Co, Ru, Al, Ag, Au, W, Ni, Ti, Cu, combinations of the foregoing, or multiple layers of the foregoing. After the gate electrodes 94 and 98 are filled, a planarization process (eg, a chemical mechanical polishing process) may be performed to remove the gate dielectric layers 92 and 96 and the excess portions of the gate electrodes 94 and 98, where the excess portion is in the interlayer dielectric Above the top surface of the electrical substance 88 . The final remaining portions of the gate electrodes 94 and 98 and the material of the gate dielectric layers 92 and 96 thus form the replacement gates of the final finFET.

In some embodiments, the formation of gate dielectric layers 92 and 96 may occur simultaneously, such that gate dielectric layers 92 and 96 are made of the same material, and the formation of gate electrodes 94 and 98 may occur simultaneously, such that gate dielectric layers 92 and 96 are formed of the same material The pole electrodes 94 and 98 are made of the same material. However, gate dielectric layers 92 and 96 may be formed by different processes, such that gate dielectric layers 92 and 96 are made of different materials, and gate electrodes 94 and 98 may be formed by different processes, such that gate electrodes 94 and 98 are formed by different processes. 98 is made of different materials. When using different processes, various masking steps can be used to mask and expose suitable areas.

Referring to FIGS. 21A-21C, ILD 102 is deposited over ILD 88, contacts 104 are formed through ILD 102 and ILD 88, and contacts 110 are formed through ILD 102 . In one embodiment, the interlayer dielectric 102 is formed using materials and formation methods similar to those of the interlayer dielectric 88 described above with reference to Figures 17A-17C. For the sake of brevity, it is not repeated here. In some embodiments, interlayer dielectric 102 and interlayer dielectric 88 are formed of the same material. In other embodiments, interlayer dielectric 102 and interlayer dielectric 88 are formed of different materials.

Openings for contacts 104 are formed through interlayer dielectrics 88 and 102 and etch stop layer 87 . Openings for contacts 110 are formed through interlayer dielectric 102 and etch stop layer 87 . These openings may all be formed simultaneously in the same process, or may be formed in separate processes. The openings can be formed by using suitable photolithography and etching techniques. A liner (eg, a diffusion barrier layer, adhesive layer, or the like) and conductive material are formed in the opening. The liner may contain titanium, titanium nitride, tantalum, tantalum nitride, or the like. The conductive material may be copper, copper alloys, silver, gold, tungsten, cobalt, aluminum, nickel, or the like. A planarization process, such as chemical mechanical polishing, may be performed to remove excess material from the top surface of the interlayer dielectric 102 . The remaining pads and conductive material form contacts 104 and 110 in the openings. Annealing may be performed to form silicide at the interface between epitaxial source/drain regions 82 and 84 and contact 104, respectively. Contact 104 is physically and electrically coupled to epitaxial source/drain regions 82 and 84 , and contact 110 is physically and electrically coupled to gate electrodes 94 and 98 . Although FIG. 21B shows contacts 104 and 110 in the same section, this figure is for illustration purposes, and in some embodiments, contacts 104 and 110 are disposed in different sections.

FIG. 22 shows a schematic cross-sectional view of a finFET device, which is similar to the finFET device shown in FIGS. 21A-21C, wherein the same elements are denoted by the same reference numerals. FIG. 22 is shown along the reference section B-B of FIG. 1 . In some embodiments, the FinFET device of FIG. 22 may be formed using materials and formation methods similar to those of the FinFET device described above with reference to FIGS. 21A-21C. For the sake of brevity, it is not repeated here. In the embodiment shown, two adjacent epitaxial source/drain regions 82 and two adjacent epitaxial source/drain regions 84 are merged to form individual common source/drain regions. In other embodiments, more than two adjacent epitaxial source/drain regions 82 or more than two adjacent epitaxial source/drain regions 84 may be combined.

23 shows a flowchart of a method of forming a FinFET device in accordance with some embodiments. Method 2000 begins at step 2001, wherein a substrate (eg, substrate 50 shown in Figure 2A) is patterned to form strips (eg, semiconductor strips 52 shown in Figure 3A), as described above with reference to Figures 2A and 3A. In step 2003, isolation regions (eg, isolation regions 54 shown in Figure 5A) are formed between adjacent strips, as described above with reference to Figures 4A and 5A. In step 2005, a dummy structure (eg, dummy structure 70 shown in Figures 7A-7B) is formed over the strips, as described above with reference to Figures 6A-6B and 7A-7C. In step 2007, a first etching process is performed on the strip to form a notch (eg, the notch 124 in the strip described above with reference to FIG. 12). In step 2009, a second etching process is performed on the strip to form a reshaped notch (eg, notch 126 described above with reference to Figures 13-15C). In step 2011, source/drain regions (eg, epitaxial source/drain regions 82 shown in FIGS. 16B-16C) are epitaxially grown in the reshaped recesses. In some embodiments, steps 2007, 2009 and 2011 are performed on strips disposed in the first region of the substrate forming the n-type device. In these embodiments, steps 2007, 2009, and 2011 may be repeated to perform these steps on strips disposed in the second region of the substrate forming the p-type device, as described above with reference to Figures 17A-17C. In step 2013, a replacement gate stack is formed over the strips (eg, gate dielectric 92/gate electrode 94 and gate dielectric 96/gate electrode 98 shown in Figures 20A-20C) .

Various embodiments discussed herein result in improved fin field effect transistor performance. For example, there may be advantages to using hydrogen radicals to reshape the notches between the fins during the etch process. By using hydrogen radicals during the etching process, the bottom of the reshaped recess can be formed with a tapered shape or with a pointed bottom. In this manner, the bottom access distance of the reshaped notch can be increased because the pointed bottom of the reshaped notch can be further away from the adjacent fin. In this manner, a notch with a pointed bottom as described herein can have a greater bottom approach distance than a notch with a U-shaped or flatter bottom surface. In some cases, the larger bottom approach distance reduces the amount of dopant diffusion in the epitaxial source/drain regions into or under the channel of the finFET. Diffusion of dopants into or under the channel can reduce device performance. In some cases, drain induced barrier lowering (DIBL) effects or off-state leakage current can also be reduced using the techniques described herein. By controlling the etch parameters, the etching of the reshaped notch can be controlled to produce a desired shape of the reshaped notch (some examples are shown in Figures 13-15C). In this manner, the top, middle, and bottom access distances of the reshaped notch can also be controlled. The techniques described herein are described with reference to FinFETs, but may be used to form other devices, such as planar FETs, semiconductor lasers, or other optical devices or other types of devices.

According to one embodiment, a method includes forming a fin on a substrate, forming an isolation region adjacent to the fin, forming a dummy structure over the fin, and recessing the fin adjacent to the dummy structure using a first etching process to form a first recess , using a second etching process to reshape the first notch to form a reshaped first notch, wherein the bottom of the reshaped first notch consists of the crystal plane of the first sidewall surface and the crystal plane of the second sidewall surface An intersection is defined with the first sidewall surface facing the second sidewall surface, and source/drain regions are epitaxially grown in the reshaped first recess. In one embodiment, the second etching process selectively etches the crystal plane with the first crystal orientation relative to the second crystal plane with the second crystal orientation, wherein the crystal plane of the first sidewall surface has the first crystal orientation, and The first sidewall surface includes a second crystal plane with a second crystal orientation. In one embodiment, the second crystal plane has a (111) orientation. In one embodiment, the second etching process includes a plasma etching process using hydrogen radicals. In one embodiment, the second etching process further includes forming an argon plasma. In one embodiment, the first lateral distance between the bottom of the first notch and the adjacent dummy structure is less than the second lateral distance between the bottom of the reshaped first notch and the adjacent dummy structure. In one embodiment, the step of epitaxially growing the source/drain regions in the reshaped first recess includes epitaxially growing a first semiconductor material in the reshaped first recess, wherein the first semiconductor material covers the reshape at the bottom of the first notch, a second semiconductor material is epitaxially grown over the first semiconductor material, the second semiconductor material has a different composition from the first semiconductor material, and a third semiconductor material is epitaxially grown over the second semiconductor material , the third semiconductor material has a different composition than the second semiconductor material.

According to another embodiment, a method includes patterning a substrate to form strips comprising a first semiconductor material, forming isolation regions along sidewalls of the strips, upper portions of the strips extending over top surfaces of the isolation regions, The sidewalls and the top surface of the upper part of the strip form a dummy structure, the exposed part of the upper part of the strip is subjected to a first etching process to form a first recess, the exposed part of the strip is exposed by the dummy structure, and the first etching process is performed. Then, the first notch is reshaped to have a V-shaped bottom surface using a second etching process, wherein the second etching process has a negative effect on the first crystal plane with the first crystal orientation relative to the second crystal plane with the second crystal orientation Selectivity, and epitaxial growth of source/drain regions in the reshaped first notch. In one embodiment, the second etching process has a lower etching rate than the first etching process. In one embodiment, the V-shaped bottom surface includes intersecting (111) crystal planes. In one embodiment, the first etching process includes a first plasma etching process using a first etching gas, and the second etching process includes a second plasma etching process using a second etching gas different from the first etching gas. In one embodiment, the second etch gas includes H ₂ . In one embodiment, the second plasma etch process forms a plasma containing hydrogen radicals. In one embodiment, after the second etching process is performed, the uppermost surface of the first recess extends along the third crystal plane having the second crystal direction. In one embodiment, the step of epitaxially growing the source/drain regions includes epitaxially growing a first material, epitaxially growing a second material and epitaxially growing a third material, wherein the first material, the second material and the third material are epitaxially grown. Materials are all different materials. In one embodiment, the method further includes forming spacers along sidewalls of the dummy structure, wherein after the second etching process is performed, the second etching process does not remove portions of the first semiconductor material adjacent to the bottom surfaces of the spacers .

According to another embodiment, the device includes a fin over a substrate, wherein a first sidewall surface of the bottom of the fin extends along a crystal plane of a first crystal orientation, an isolation region is adjacent to the fin, and a gate structure is along the sidewall of the fin and the top of the fin Extending above the surface, the gate spacer is laterally adjacent to the gate structure, and the epitaxial region is adjacent to the fin, with the bottom of the epitaxial region tapering to a point. In one embodiment, the bottom of the epitaxial region tapers along the crystal plane of the first crystal direction. In one embodiment, the widest portion of the epitaxial region has a curved profile. In one embodiment, the widest portion of the epitaxial region is between the top surface of the epitaxial region and the bottom of the epitaxial region. In one embodiment, the epitaxial region includes a first material, a second material above the first material, and a third material above the second material, wherein the first material, the second material and the third material are all composed of different materials .

The foregoing context summarizes the features of many embodiments so that those skilled in the art may better understand the embodiments of the invention from various aspects. It should be understood by those skilled in the art that other processes and structures can be easily designed or modified based on the embodiments of the present invention to achieve the same purpose and/or to achieve the embodiments described herein. the same advantages. Those of ordinary skill in the art should also realize that such equivalent structures do not depart from the spirit and scope of the invention. Various changes, substitutions or modifications may be made to the embodiments of the present invention without departing from the spirit and scope of the invention.

30: FinFET 32, 50: Substrate 34, 54: Isolation region 36, 56: Fin 38: Gate dielectric 40, 94, 98: Gate electrode 42, 44: Source/drain region 52 : semiconductor strips 53, 62, 72, 118: mask 53A: first mask layer 53B: second mask layer 55: trench 58: dummy dielectric layer 60: dummy gate layer 70: dummy structure 75, 79: lightly doped source/drain regions 80A: first spacer layer 80B: second spacer layer 80C: third spacer layers 82, 84: epitaxial source/drain regions 82A, 82B, 82C: epitaxial layers 87: etch stop layer 88, 102: interlayer dielectric 90, 124, 126: notches 92, 96: gate dielectric layer 100A: first region 100B: second region (100), (111): crystal plane / Orientation 104, 110: Contact 120: Offset Spacer 122: Gate Spacer 125: Lower Sidewall 127: Upper Sidewall 128: Section 130: Fin Spacer 2000: Methods 2001, 2003, 2005, 2007, 2009, 2011, 2013: Step S: Surface A1, A2, A3: Angle D0, D1, D2, D3, D4: Depth H1 _: Height _W1 , W1, W2, W3, W4, W5: Width BP0: Bottom approach distance MP0 : Middle approach distance TP0: Top approach distance

The embodiments of the present invention can be better understood according to the following detailed description and the accompanying drawings. It should be noted that, in accordance with standard practice in the industry, the various features in the illustrations are not necessarily drawn to scale. In fact, the dimensions of various components may be arbitrarily enlarged or reduced for clarity of illustration. FIG. 1 is a three-dimensional view of a fin field-effect transistor (FinFET) device in accordance with some embodiments. FIG. 2A is a schematic cross-sectional view of an intermediate stage of fabricating a FinFET device in accordance with some embodiments. 3A is a schematic cross-sectional view of an intermediate stage of fabricating a FinFET device in accordance with some embodiments. FIG. 4A is a schematic cross-sectional view of an intermediate stage of fabricating a FinFET device in accordance with some embodiments. 5A is a schematic cross-sectional view of an intermediate stage of fabricating a FinFET device in accordance with some embodiments. 6A-6B are schematic cross-sectional views of intermediate stages of fabricating a finFET device in accordance with some embodiments. 7A-7C are schematic cross-sectional views of intermediate stages of fabricating a finFET device according to some embodiments. 8A-8C are schematic cross-sectional views of intermediate stages of fabricating a finFET device according to some embodiments. FIGS. 9A-9C are schematic cross-sectional views of intermediate stages of fabricating a FinFET device in accordance with some embodiments. FIGS. 10A-10C are schematic cross-sectional views of intermediate stages of fabricating a finFET device according to some embodiments. FIGS. 11A-11C are schematic cross-sectional views of intermediate stages of fabricating a FinFET device in accordance with some embodiments. FIG. 12 is a schematic cross-sectional view of the formation of a first notch in the fabrication of a finFET device according to some embodiments. FIG. 13 is a schematic cross-sectional view of the formation of a reshaped notch in fabricating a finFET device according to an embodiment. FIG. 14 is a schematic cross-sectional view of the formation of the reshaped notch in the manufacture of the fin field effect transistor device according to another embodiment. FIGS. 15A-15C are schematic cross-sectional views illustrating the formation of a reshaped notch for fabricating a finFET device according to other embodiments. 16A-16C are schematic cross-sectional views of intermediate stages of fabricating a finFET device according to some embodiments. 17A-17C are schematic cross-sectional views of intermediate stages of fabricating a finFET device according to some embodiments. 18A-18C are schematic cross-sectional views of intermediate stages of fabricating a finFET device according to some embodiments. FIGS. 19A-19C are schematic cross-sectional views of intermediate stages of fabricating a FinFET device in accordance with some embodiments. 20A-20C are schematic cross-sectional views of intermediate stages of fabricating a finFET device according to some embodiments. FIGS. 21A-21C are schematic cross-sectional views of intermediate stages of fabricating a FinFET device in accordance with some embodiments. 22 is a schematic cross-sectional view of an intermediate stage of fabricating a FinFET device with merged epitaxial regions in accordance with some embodiments. 23 is a flow diagram of a method of forming a FinFET device using a reshaped notch in accordance with some embodiments.

2000: Methods

2001, 2003, 2005, 2007, 2009, 2011, 2013: Steps

Claims (15)

A method for forming a semiconductor device, comprising: forming a fin on a substrate; forming an isolation region adjacent to the fin; forming a dummy structure above the fin; The fin is recessed to form a first recess, wherein the bottom of the first recess is higher than the bottom surface of the isolation region; the first recess is reshaped using a second etching process to form a reshaped a first notch, wherein the bottom of the reshaped first notch is defined by the intersection of a crystal plane of a first sidewall surface with a crystal plane of a second sidewall surface, wherein the first sidewall surface faces the second sidewall surface , and the bottom of the reshaped first recess is lower than the bottom surface of the isolation region; and a source/drain region is epitaxially grown in the reshaped first recess. The method for forming a semiconductor device according to claim 1, wherein the second etching process selectively etches a crystal plane with a first crystal orientation relative to a second crystal plane with a second crystal orientation , wherein the crystal plane of the first sidewall surface has the first crystallographic orientation, and wherein the first sidewall surface includes the second crystallographic plane with the second crystallographic orientation. The method for forming a semiconductor device according to item 2 of the claimed scope, wherein the second crystal surface has a (111) crystal orientation. The method for forming a semiconductor device according to any one of claims 1 to 3 of the claimed scope, wherein the second etching process includes a plasma etching process using hydrogen radicals. The method for forming a semiconductor device according to any one of claims 1 to 3, wherein a first lateral distance between the bottom of the first recess and an adjacent dummy structure is smaller than the A second lateral distance between the bottom of the reshaped first notch and the adjacent dummy structure. The method for forming a semiconductor device as described in any one of claims 1 to 3, wherein the step of epitaxially growing the source/drain region in the reshaped first recess comprises: in the reshaped first recess A first semiconductor material is epitaxially grown in the first recess of the Two semiconductor materials have a different composition from the first semiconductor material; and a third semiconductor material is epitaxially grown over the second semiconductor material, the third semiconductor material has a different composition from the second semiconductor material. A method of forming a semiconductor device, comprising: patterning a substrate to form a strip, the strip comprising a first semiconductor material; forming an isolation region along a sidewall of the strip, an upper portion of the strip extending from the isolation on the top surface of the region; forming a dummy structure along the sidewall and top surface of the upper part of the strip; performing a first etching process on an exposed portion of the upper part of the strip to form a first recess, the The exposed portion of the strip is exposed by the dummy structure, wherein the bottom of the first recess is higher than the bottom surface of the isolation region; after the first etching process, a second etching process is used to reshape the first The recess has a V-shaped bottom surface, wherein the second etching process is selective to a first crystal plane having a first crystal orientation relative to a second crystal plane having a second crystal orientation, and the The V-shaped bottom surface is lower than the bottom surface of the isolation region; and a source/drain region is epitaxially grown in the reshaped first recess. The method for forming a semiconductor device as described in claim 7, wherein the second etching process has a lower etching rate than the first etching process. The method for forming a semiconductor device as described in claim 7 or 8, wherein the V-shaped bottom surface includes intersecting (111) crystal planes. The method for forming a semiconductor device as described in claim 7 or 8, wherein the first etching process includes a first plasma etching process using a first etching gas, and wherein the second etching process includes using a different A second plasma etching process of a second etching gas in the first etching gas. The method for forming a semiconductor device according to claim 7 or 8, wherein after the second etching process is performed, an uppermost surface of the first recess is along a third crystal plane having the second crystal orientation extend. The method for forming a semiconductor device as described in claim 7 or 8 of the claimed scope, further comprising forming a spacer along the sidewall of the dummy structure, wherein after the second etching process is performed, the second etching process is not removed The portion of the first semiconductor material adjacent the bottom surface of the spacer. A semiconductor device, comprising: a fin located above a substrate, wherein a first sidewall surface of the bottom of the fin extends along a crystal plane of a first crystal direction; an isolation region adjacent to the fin; a gate structure , extending along the sidewall of the fin and above the top surface of the fin; a gate spacer, laterally adjacent to the gate structure, wherein a portion of the fin is below the gate spacer, and the portion of the fin is a surface is angularly spaced from a sidewall of the other portion of the fin; and an epitaxial region adjacent to the fin, wherein the bottom of the epitaxial region tapers to a point below the bottom surface of the isolation region. The semiconductor device of claim 13, wherein the bottom of the epitaxial region tapers along the crystal plane of the first crystal direction. The semiconductor device of claim 13 or 14, wherein the widest portion of the epitaxial region is between a top surface of the epitaxial region and a bottom portion of the epitaxial region.

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