TW202029349A - Semiconductor devices and methods forforming the same - Google Patents

Abstract

A method for forming a semiconductor device includes patterning a substrate to form a strip including a first semiconductor material, forming an isolation region along a sidewall of the strip, an upper portion of the strip extending above the isolation region, forming a dummy structure along sidewalls and a top surface of the upper portion of the strip, performing a first etching process on an exposed portion of the upper portion of the strip to form a first recess, the exposed portion of the strip being exposed by the dummy structure, after performing the first etching process, reshaping the first recess to have a V-shaped bottom surface using a second etching process, wherein the second etching process is selective to first crystalline planes having a first orientation relative to second crystalline planes having a second orientation, and epitaxially growing a source/drain region in the reshaped first recess.

Description

Semiconductor device and its forming method

The embodiments of the present invention are related to semiconductor technology, and more particularly to semiconductor devices and methods of forming them.

Semiconductor devices are used in various electronic applications, such as personal computers, mobile phones, digital cameras, and other electronic equipment. Semiconductor devices generally deposit insulating or dielectric layers, conductive layers, and semiconductor layer materials on a semiconductor substrate in sequence, and use lithography technology to pattern various material layers to form circuit components and components thereon.

The semiconductor industry continues to reduce the size of the smallest features, and continues to improve the integration density of various electronic components (such as transistors, diodes, resistors, capacitors, etc.), so that more components are integrated into a given area. However, when the size of the smallest part is reduced, additional problems arise that should be solved.

In some embodiments, a method for forming a semiconductor device is provided. The method includes forming a fin on a substrate; forming an isolation region adjacent to the fin; forming a dummy structure above the fin; and using a first etching process to remove the fin adjacent to the dummy structure Recess to form a first notch; use a second etching process to reshape the first notch to form a reshaped first notch, wherein the bottom of the reshaped first notch is formed by the crystal plane of the first sidewall surface It is defined by intersecting the crystal plane of the second sidewall surface, wherein the first sidewall surface faces the second sidewall surface; and epitaxially grows the source/drain regions in the reshaped first recess.

In some other embodiments, a method for forming a semiconductor device is provided. The method includes patterning a substrate to form a strip. The strip includes a first semiconductor material; an isolation region is formed along the sidewall of the strip, and the upper portion of the strip extends over the isolation. Above the top surface of the zone; forming a dummy structure along the sidewall and top surface of the upper part of the strip; performing a first etching process on the exposed part of the upper part of the strip to form a first notch, and the exposed part of the strip is exposed by the dummy structure Out; after the first etching process, a second etching process is used to reshape the first notch to have a V-shaped bottom surface, wherein the second etching process pair has a first The first crystal plane of the crystal orientation is selective; and the source/drain regions are epitaxially grown in the reshaped first recess.

In other embodiments, a semiconductor device is provided. The semiconductor device includes a fin located above the substrate, wherein the first sidewall surface at the bottom of the fin extends along the crystal plane of the first crystal orientation; the isolation region is adjacent to the fin; and the gate structure , Extending along the sidewalls of the fin and above the top surface of the fin; the gate spacer, which is laterally adjacent to the gate structure; and the epitaxial region, which is adjacent to the fin, wherein the bottom of the epitaxial region is tapered to a point.

It should be understood that the following disclosure provides many different embodiments or examples to implement different components of the main body provided. The following describes specific examples of each component and its arrangement in order to simplify the description of the disclosure. Of course, these are only examples and are not intended to limit the present invention. For example, the following disclosure describes that a first part is formed on or above a second part, which means that it includes an embodiment in which the formed first part is in direct contact with the second part, and also includes It is still possible to form an additional component between the first component and the second component, and the first component and the second component may not be in direct contact. In addition, different examples in the disclosure may use repeated reference symbols and/or words. These repeated symbols or words are for the purpose of simplification and clarity, and are not used to limit the relationship between the various embodiments and/or the appearance structure.

Furthermore, in order to facilitate the description of the relationship between one element or component and another (plural) element or (plural) component in the drawings, space-related terms can be used, such as "under", "below", and "lower" ", "upper", "upper" and similar terms. In addition to the orientation shown in the diagram, space-related terms also cover different orientations of the device in use or operation. The device can also be positioned separately (for example, rotated by 90 degrees or located in another orientation), and correspondingly interpret the description of the used spatially related terms.

The embodiments of the present invention will be discussed below for specific situations, namely, a fin-type field effect transistor device and its forming method. The various embodiments discussed herein allow to control the shape of the epitaxial source/drain region of the fin field effect transistor device so that the bottom of the epitaxial source/drain region has a pointed shape defined by the crystal plane. By controlling the shape of the epitaxial source/drain regions of the fin field effect transistor in this way, the performance of the fin field effect transistor device can be improved. The various embodiments presented herein are discussed in the context of using a fin field effect transistor formed by a post-gate process. In other embodiments, a gate first manufacturing process can be used. Some embodiments consider aspects for planar devices, such as planar field effect transistors. Some embodiments can also be used in non-field effect transistor semiconductor devices.

FIG. 1 shows a three-dimensional view of an example of a FinFET 30 according to some embodiments. The fin field effect transistor 30 includes a fin 36 on a substrate 32. The isolation region 34 is disposed on the substrate 32 around the fin 36, and the fin 36 protrudes above the adjacent isolation region 34. The gate dielectric 38 is along the sidewalls and top surface of the fin 36, and the gate electrode 40 is above the gate dielectric 38. The source/drain regions 42 and 44 are provided on both sides of the fin 36 opposite to the gate dielectric 38 and the gate electrode 40. Figure 1 further shows the reference section used in subsequent figures. Section A-A spans the channel region of the fin field effect transistor 30, the gate dielectric 38 and the gate electrode 40. The section C-C is in a plane parallel to the section A-A and straddles the fin 36 outside the channel area. The cross-section B-B is perpendicular to the cross-section A-A and along the longitudinal axis of the fin 36 and in the direction of current flow between, for example, the source/drain regions 42 and 44. For clarity, the subsequent drawings refer to these reference profiles.

2A-22 is a schematic cross-sectional view of an intermediate stage of manufacturing a fin-type field effect transistor according to some embodiments. In Figures 2A to 11A-11C and Figures 16A-16C to 21A-21C, the figures ending with "A" are shown along the reference section AA in Figure 1, except that the above figures have multiple fin fields Each fin-type field effect transistor has multiple fins. The drawings ending with the "B" mark are shown along the reference section B-B in Figure 1. The drawings ending with the "C" mark are shown along the reference section C-C in Figure 1. Figures 12-15C and 22 are shown along the reference section B-B in Figure 1.

In Figure 2, a substrate 50 is provided. The substrate 50 may be a semiconductor substrate, such as a bulk semiconductor, a semiconductor-on-insulator (SOI) substrate, or the like, and the substrate 50 may be doped (for example, doped p-type or n-type doped). Impurities) or undoped. The substrate 50 may be a wafer, such as a silicon wafer, and may have a specific crystal orientation, such as (100), (111), or (110). Generally, the semiconductor substrate over the insulating layer includes a semiconductor material layer formed on the insulating layer. The insulating layer may be, for example, a buried oxide (BOX) layer, a silicon oxide layer, or the like. The insulating layer is provided on the substrate, which is generally a silicon substrate or a glass substrate. Other substrates can also be used, such as multilayer or gradient substrates. In some embodiments, the semiconductor material of the substrate 50 may include silicon, germanium, compound semiconductors (including silicon carbide, gallium arsenide, gallium phosphide, indium phosphide, indium arsenide and/or indium antimonide), alloy semiconductors ( Including SiGe, GaAsP, AlInAs, AlGaAs, GaInAs, GaInP, and/or GaInAsP) or a combination of the foregoing.

The substrate 50 may further include integrated circuit components (not shown). Those with ordinary knowledge in the technical field to which the present invention pertains will understand that various integrated circuit elements (such as transistors, diodes, capacitors, resistors, the like, or combinations of the foregoing) can be formed in the substrate 50 and/or On the substrate 50, the structural and functional requirements for the final fin field effect transistor design are generated. The integrated circuit element can be formed by using any suitable method.

In some embodiments, the substrate 50 may include a first region 100A and a second region 100B. The first region 100A can be used to form an n-type device, such as an n-type metal oxide semiconductor (NMOS) transistor, such as an n-type fin field effect transistor. The second region 100B can be used to form a p-type device, such as a p-type metal oxide semiconductor (PMOS) transistor, such as a p-type fin field effect transistor. Therefore, the first region 100A may also be referred to as an N-type metal oxide semiconductor region, and the second region 100B may also be referred to as a P-type metal oxide semiconductor region. In some embodiments, the first zone 100A may be physically separated from the second zone 100B. The first zone 100A can be separated from the second zone 100B by any number of components.

FIG. 2A further shows that the mask 53 is formed on the base 50. In some embodiments, the mask 53 can be used in a subsequent etching step to pattern the substrate 50 (please refer to FIG. 3A). As shown in FIG. 2A, the mask 53 may include a first mask layer 53A and a second mask layer 53B. The first mask layer 53A may be a hard mask layer, and may include silicon nitride (SiN), silicon oxynitride (SiON), silicon carbide (SiC), silicon carbide nitride (SiCN), a combination of the foregoing, or the like, And can be formed by using any suitable process, such as atomic layer deposition (ALD), physical vapor deposition (PVD), chemical vapor deposition (chemical vapor deposition, CVD), a combination of the foregoing, or Similar method. The first mask layer 53A may also include multiple layers, and the multiple layers may be of different materials. For example, the first mask layer 53A may include a silicon nitride layer above the silicon oxide layer, but other materials and combinations of materials may also be used. The second mask layer 53B may include a photoresist, and in some embodiments, the second mask layer 53B may be used in the above-mentioned subsequent etching step to pattern the first mask layer 53A. The second mask layer 53B can be formed by using a spin coating technique, and can be patterned by using a suitable photolithography technique. In some embodiments, the mask 53 may include three or more mask layers.

FIG. 3A shows that the semiconductor strip 52 is formed in the substrate 50. First, the first mask layer 53A and the second mask layer 53B can be patterned, wherein the openings in the first mask layer 53A and the second mask layer 53B expose the substrate 50 to form an isolation region 54 (sometimes by An area 55 called Shallow Trench Isolation (STI) area. Next, an etching process may be performed, wherein the etching process forms the trench 55 in the substrate 50 through the opening in the mask 53. The remaining part of the substrate 50 under the patterned mask 53 forms a plurality of semiconductor strips 52. The etching can be any suitable etching process, such as reactive ion etch (RIE), neutral beam etch (NBE), similar methods, or a combination of the foregoing. The etching process can be anisotropic. In some embodiments, the semiconductor strip 52 may have a height H ₁ between about 200 nm and about 400 nm, and may have a width W ₁ between about 10 nm and about 40 nm.

The semiconductor strip 52 can be patterned by any suitable method. For example, the semiconductor strip 52 can be patterned by using one or more photolithography processes (including double patterning or multiple patterning processes). Generally speaking, a double patterning or multiple patterning process combines photolithography and self-alignment processes to create patterns with a smaller pitch. For example, this pattern has a better performance than the single direct photolithography process. Patterns with smaller spacing. For example, in one embodiment, the sacrificial layer is formed on the substrate 50 and patterned by using a photolithography process. The spacer is formed beside the patterned sacrificial layer by using a self-aligning process. Next, the sacrificial layer is removed, and the remaining spacers or mandrels can then be used as a mask to pattern the semiconductor strip 52.

FIG. 4A shows that an insulating material is formed in the trench 55 between adjacent semiconductor strips 52 (please refer to FIG. 3A) to form an isolation region 54. The insulating material can be oxide (such as silicon oxide), nitride, the like, or a combination of the foregoing, and can be passed through high-density plasma chemical vapor deposition (HDP-CVD), flowable chemical vapor Phase deposition (flowable CVD, FCVD) (for example, chemical vapor deposition-based material deposition in a remote plasma system, and post-curing to transform it into another material, such as oxide), similar methods or a combination of the foregoing . Other insulating materials formed by any suitable process can also be used.

Furthermore, in some embodiments, the isolation region 54 may include a compliant liner formed on the sidewall and bottom surface of the trench 55 (please refer to FIG. 3A) before filling the trench 55 with the insulating material of the isolation region 54 Pad (not shown). In some embodiments, the liner may include semiconductor (such as silicon), nitride, semiconductor (such as silicon) oxide, thermal semiconductor (such as silicon) oxide, semiconductor (such as silicon) oxynitride, polymer dielectric , The combination of the foregoing or the like. The formation of the liner may include any suitable method, such as atomic layer deposition, chemical vapor deposition, high density plasma chemical vapor deposition, physical vapor deposition, a combination of the foregoing, or similar methods. In these embodiments, the liner can prevent (or at least reduce) the semiconductor material from diffusing into the surrounding isolation region 54 from the semiconductor strip 52 (eg, Si and/or Ge) during subsequent annealing of the isolation region 54. For example, after the insulating material of the isolation region 54 is deposited, the insulating material of the isolation region 54 may be subjected to an annealing process.

In Figure 4A, a planarization process (such as chemical mechanical polishing (CMP)) can remove excess insulating material in the isolation region 54 so that the top surface of the isolation region 54 and the top surface of the semiconductor strip 52 are coplanar . In some embodiments, the mask 53 can also be removed by chemical mechanical polishing. In other embodiments, the mask 53 can be removed by using a wet etching process separate from chemical mechanical polishing.

FIG. 5A shows that the isolation region 54 is recessed to form a fin 56. The isolation region 54 is recessed so that the fins 56 in the first region 100A and the second region 100B protrude from between adjacent isolation regions 54. In some embodiments, the semiconductor strip 52 may be considered as part of the fin 56. Furthermore, the top surface of the isolation region 54 may have a flat surface, a convex surface, a concave surface (such as a recess) as shown in the figure, or a combination of the foregoing. The top surface of the isolation region 54 can be formed into a flat, convex and/or concave shape through a suitable process. The isolation region 54 can be recessed by using a suitable etching process, for example, an etching process selective to the material of the isolation region 54.

Those skilled in the art to which the present invention pertains will easily understand that the process described in FIGS. 2A-5A is only an example of how the fin 56 can be formed. In other embodiments, the dielectric layer can be formed on the top surface of the substrate 50, the trench can be etched through the dielectric layer, the homoepitaxial structure can be epitaxially grown in the trench, and the dielectric layer can be recessed so that The homoepitaxial structure protrudes from the dielectric layer to form the fin 56. In other embodiments, heteroepitaxial structures can be used for fins. For example, the semiconductor strip 52 in FIG. 4A can be recessed, and the material of the semiconductor strip 52 can be epitaxially grown in the recess. In other embodiments, a dielectric layer can be formed on the top surface of the substrate 50, trenches can be etched through the dielectric layer, the heteroepitaxial structure can be epitaxially grown in the trenches by using a material different from the substrate 50, and The dielectric layer is recessed so that the hetero epitaxial structure protrudes from the dielectric layer to form the fin 56. In some embodiments of epitaxial growth of homoepitaxial or heteroepitaxial structures, the growth material can be doped in situ during the growth. In other embodiments, the homoepitaxial or heteroepitaxial structure may be doped by using ion implantation after the epitaxial growth of the homoepitaxial or heteroepitaxial structure, for example. Furthermore, it may be advantageous that the material epitaxially grown in the N-type metal oxide semiconductor region is different from the material epitaxially grown in the P-type metal oxide semiconductor region. In various embodiments, the fin 56 may include silicon germanium (Si _x Ge _1-x , where x may be between about 0 and 1), silicon carbide, pure germanium or substantially pure germanium, group III-V compound semiconductors, Group II-VI compound semiconductors or the like. For example, materials that can be used to form group III-V compound semiconductors include InAs, AlAs, GaAs, InP, GaN, InGaAs, InAlAs, GaSb, AlSb, AlP, GaP, and the like, but are not limited thereto.

In FIGS. 6A-6B, a dummy dielectric layer 58 is formed on the fin 56. The dummy dielectric layer 58 can be, for example, silicon oxide, silicon nitride, a combination of the foregoing, or the like, and can be deposited by a suitable technique (such as chemical vapor deposition, physical vapor deposition, a combination of the foregoing, or the like) or Thermal growth (for example using thermal oxidation or similar methods). The dummy gate layer 60 is formed on the dummy dielectric layer 58, and the mask 62 is formed on the dummy gate layer 60. In some embodiments, the dummy gate layer 60 may be deposited on the dummy dielectric layer 58, and then the dummy gate layer 60 is planarized by using, for example, chemical mechanical polishing. The mask 62 may be deposited on the dummy gate layer 60. The dummy gate layer 6 may be made of, for example, polysilicon, but other materials having high etching selectivity with respect to the material of the isolation region 54 may also be used. The mask 62 may include one or more layers such as silicon nitride, silicon oxynitride, silicon carbide, silicon carbide nitride, the like, or a combination of the foregoing.

Referring to FIGS. 6A-6B, in the embodiment shown, a single dummy dielectric layer 58, a single dummy gate layer 60, and a single mask 62 are formed across the first region 100A and the second region 100B. In other embodiments, individual dummy dielectric layers, individual dummy gate layers, and individual masks may be formed in the first region 100A and the second region 100B. In some embodiments, the dummy dielectric layer 58 may have a thickness between about 0.8 nm and about 2.0 nm, and the dummy gate layer 60 may have a thickness between about 50 nm and about 100 nm.

In FIGS. 7A-7C, the mask 62 (please refer to FIGS. 6A and 6B) can form the mask 72 in the first region 100A and the second region 100B by using appropriate photolithography and etching techniques. The mask 72 may be a hard mask, and the patterns of the mask 72 in the first area 100A and the second area 100B may be different. Then, the pattern of the mask 72 in the first region 100A and the second region 100B can be transferred to the dummy gate layer 60 through a suitable etching technique. For convenience, the dummy gate layer 60 and the mask 72 may be collectively referred to as a dummy structure 70. In some embodiments, the dummy gate layer 60 and the mask 72 are formed in the first region 100A and the second region 100B in separate processes, and may be formed of different materials in the first region 100A and the second region 100B. Optionally, the pattern of the mask 72 can be similarly transferred to the dummy dielectric layer 58. The pattern of the dummy structure 70 covers the individual channel regions of the fin 56, and the pattern of the dummy structure 70 simultaneously exposes the source/drain regions of the fin 56. The dummy structure 70 may also have a length direction substantially perpendicular to the length direction of the individual fin 56. The size of the dummy structure 70 or the spacing between the dummy structures 70 may depend on the area of the die on which the dummy gate is formed. In some embodiments, compared to the dummy structure 70 located in the logic region of the die (such as the region where the logic circuit is provided), the dummy structure 70 located in the input/output region of the die (such as the region where the input/output circuit is provided) The structure 70 may have a larger size or a larger pitch. In some embodiments, the dummy structure 70 may have a width between about 15 nm and about 40 nm.

Referring to FIGS. 7A-7C, suitable well regions (not shown) can be formed in the fin 56, the semiconductor strip 52, and/or the substrate 50. For example, a P-type well may be formed in the first zone 100A, and an N-type well may be formed in the second zone 100B. The different implantation steps for the first area 100A and the second area 100B can be achieved by using photoresist or other masks (not shown). For example, a photoresist may be formed above the fin 56 and the isolation region 54 in the first region 100A and the second region 100B. The photoresist is patterned to expose the second region 100B (for example, the P-type metal oxide semiconductor region) of the substrate 50, while protecting the first region 100A (for example, the N-type metal oxide semiconductor region). The photoresist can be formed by using spin coating technology and can be patterned by using suitable photolithography technology. After the photoresist is patterned, n-type impurities are implanted in the second region 100B, and the photoresist can be used as a mask to substantially prevent the n-type impurities from being implanted in the first region 100A. The n-type impurity can be phosphorus, arsenic or the like, and can be implanted in the second region 100B to a concentration equal to or less than 10 ¹⁸ cm ^-3 , for example, between about 10 ¹⁷ cm ^-3 and about 10 ¹⁸ cm ^-3 In range. After the planting process, the photoresist is removed, for example, by using a suitable ashing process and then performing a wet cleaning process.

After the implantation of the second region 100B, a second photoresist (not shown) is formed above the fin 56 and the isolation region 54 in the first region 100A and the second region 100B. The second photoresist is patterned to expose the first region 100A of the substrate 50 while protecting the second region 100B. The photoresist can be formed by using spin coating technology and can be patterned by using suitable photolithography technology. The second photoresist can be formed by using a spin coating technology, and can be patterned by using a suitable photolithography technology. After the second photoresist is patterned, p-type impurities are implanted in the first region 100A, and the second photoresist can be used as a mask to substantially prevent the p-type impurities from being implanted in the second region 100B. The p-type impurity can be boron, BF ₂ or the like, and can be implanted in the first region 100A to a concentration equal to or less than 10 ¹⁸ cm ^-3 , for example, between about 10 ¹⁷ cm ^-3 and about 10 ¹⁸ cm ^-3 In the range. After the planting process, the photoresist is removed, for example, by using a suitable ashing process and then performing a wet cleaning process.

After the implantation of the first region 100A and the second region 100B, annealing may be performed to activate the implanted p-type and/or n-type impurities. The implantation process can form a P-type well in the first zone 100A and an N-type well in the second zone 100B. In some embodiments of epitaxial growth fins, the growth material of the fin 56 may be doped in-situ during the growth process.

In Figures 8A-8C, the first spacer layer 80A is formed on the exposed surface of the dummy structure 70 (please refer to Figures 8A and 8B) and/or the dummy dielectric layer 58 (please refer to Figure 8C) above the fin 56 . Any suitable method may be used to form the first spacer layer 80A. In some embodiments, deposition (such as chemical vapor deposition, atomic layer deposition, or the like) may be used to form the first spacer layer 80A. In some embodiments, the first spacer layer 80A may include one or more layers such as silicon nitride (SiN), silicon oxynitride, silicon carbide oxynitride, silicon oxycarbonitride (SiOCN), a combination of the foregoing, or the like.

Referring to FIGS. 8A-8C, lightly doped source/drain (LDD) regions 75 and 79 may be formed in the substrate 50 in the first region 100A and the second region 100B, respectively. Similar to the implantation process discussed above with reference to Figures 7A-7C, a mask (not shown) (such as a photoresist) can be formed on the first region 100A (such as the N-type metal oxide semiconductor region) while exposing the second region. Region 100B (for example, a P-type metal oxide semiconductor region), and p-type impurities can be implanted into the fin 56 exposed in the second region 100B to form a lightly doped source/drain region 79. During the implantation of the lightly doped source/drain regions 79, the dummy structure 70 can serve as a mask to prevent (or at least reduce) implantation of dopants into the channel region of the exposed fin 56. Therefore, the lightly doped source/drain region 79 can be substantially formed in the source/drain region of the exposed fin 56. Then, the mask can be removed. After that, a second mask (not shown) (such as a photoresist) can be formed over the second region 100B while exposing the first region 100A, and n-type impurities can be implanted in the fin 56 exposed in the first region 100A , To form a lightly doped source/drain region 75. During the implantation of the lightly doped source/drain regions 75, the dummy structure 70 can serve as a mask to prevent (or at least reduce) the implantation of dopants into the channel region of the exposed fin 56. Therefore, the lightly doped source/drain region 75 can be substantially formed in the source/drain region of the exposed fin 56. Then, the second mask can be removed. The n-type impurity can be any of the aforementioned n-type impurities, and the p-type impurity can be any of the aforementioned p-type impurities. The lightly doped source/drain regions 75 and 79 each have an impurity concentration of about 10 ¹⁵ cm ^-3 to about 10 ¹⁶ cm ^-3 . An annealing process can be performed to activate implanted impurities.

Please refer to FIGS. 9A-9C to perform an etching process on a part of the first spacer layer 80A. The etching process may be a dry etching process, and may be anisotropic. After the etching process, the lateral portion of the first spacer layer 80A above the lightly doped source/drain regions 75/79 and the isolation region 54 can be removed to expose the fin 56 and the mask 72 of the dummy structure 70 The top surface. A portion of the first spacer layer 80A along the sidewalls of the dummy structure 70 and the fin 56 may be retained, and an offset spacer 120 may be formed. In other embodiments, the first spacer layer 80A can also be removed from the sidewall of the fin 56. In some embodiments, the offset spacer 120 in the first region 100A and the offset spacer 120 in the second region 100B are formed at the same time, while in other embodiments, the offset spacer 120 in the first region 100A and the second region 100B The offset spacer 120 is formed in a separate manufacturing process. In some embodiments, the lateral portion of the dummy dielectric layer 58 above the lightly doped source/drain regions 75/79 and the isolation region 54 may also be removed.

In Figures 10A-10C, the second spacer layer 80B and the third spacer layer 80C are formed above the first region 100A and the second region 100B. Any suitable method of forming the first spacer layer 80A can be used. In some embodiments, deposition (such as chemical vapor deposition, atomic layer deposition, or the like) may be used to form the second spacer layer 80B and the third spacer layer 80C. In some embodiments, the second spacer layer 80B and the third spacer layer 80C may include one or more layers such as oxide materials, silicon nitride, silicon oxynitride, silicon carbide oxynitride, silicon oxynitride, a combination of the foregoing, or the like . In some embodiments, one of the second spacer layer 80B or the third spacer layer 80C may be omitted.

Please refer to FIGS. 11A-11C to perform a patterning process to remove the second spacer layer 80B and the third spacer layer 80C in the first region 100A. Any acceptable patterning process can be used. In some embodiments, the mask 118 is formed over the first area 100A and the second area 100B. The mask 118 may be a single layer or may include multiple layers, such as a three-layer mask structure or other types of mask structures. In some cases, the mask 118 may include photoresist, but the mask 118 may include other materials. The mask 118 is patterned to expose the first region 100A. The mask 118 can be patterned by using a suitable photolithography technique.

Please refer to FIGS. 11A-11C, using the mask 118 as a mask to perform an etching process on a part of the second spacer layer 80B and the third spacer layer 80C. The etching process may be a dry etching process, and may be anisotropic. After the etching process, the lateral portions of the second spacer layer 80B and the third spacer layer 80C above the lightly doped source/drain regions 75/79 and the isolation region 54 can be removed to expose the fin 56 and the mask 72 of the top surface. The portions of the second spacer layer 80B and the third spacer layer 80C along the sidewalls of the dummy structure 70 and the fin 56 may be retained, and the gate spacer 122 and the fin spacer 130 may be formed. In some embodiments, the gate spacer 122 and the fin spacer 130 in the first region 100A and the gate spacer 122 and the fin spacer 130 in the second region 100B are formed at the same time, while in other embodiments, Before forming the gate spacer 122 and the fin spacer 130 in the first region 100A, the gate spacer 122 and the fin spacer 130 in the second region 100B are formed. In some embodiments, before forming the third spacer layer 80C, the second spacer layer 80B may be etched as described above, and then the third spacer layer 80C may be etched to form the gate spacer 122 and the fin spacer 130.

Figures 12-16C show that epitaxial source/drain regions 82 are formed between adjacent fins 56 in the first region 100A. Figures 12-15C are shown along the reference section B-B of Figure 1. During the formation of the epitaxial source/drain region 82 in the first region 100A, the second region 100B may be shielded (for example, through the mask 118). In some embodiments, before forming the epitaxial source/drain region 84 in the second region 100B, the epitaxial source/drain region 82 may be formed in the first region 100A. In other embodiments, before forming the epitaxial source/drain region 82 in the first region 100A, the epitaxial source/drain region 84 may be formed in the second region 100B.

Referring to FIG. 12, a first patterning process is performed on the fin 56 to form a notch 124 in the source/drain region of the fin 56. The first pattern may be performed in a manner that notches 124 are formed between adjacent dummy structures 70 (in the inner region of the fin 56) or between the isolation region 54 and the adjacent dummy structure 70 (in the end region of the fin 56) The process. In some embodiments, the first patterning process may include a suitable anisotropic dry etching process, while using the dummy structure 70, the gate spacer 122, the fin spacer 130, and/or the isolation region 54 as a combined mask. A suitable anisotropic dry etching process can include reactive ion etching, neutron beam etching, similar methods, or a combination of the foregoing. In some embodiments where the first patterning process uses reactive ion etching, process parameters such as process gas mixture, voltage bias, and radio frequency power can be selected so that the etching is mainly performed by using physical etching, such as ion bombardment. In some embodiments, the voltage bias can be increased to increase the energy of the ions used in the ion bombardment process, and thus increase the rate of physical etching. Since physical etching is anisotropic in nature and chemical etching is isotropic in nature, the etching rate in the vertical direction of this etching process is greater than the etching rate in the lateral direction. In some embodiments, the anisotropic etching process can be achieved by using a process gas including BF ₂ , Cl ₂ , CH ₃ F, CH ₄ , HBr, O ₂ , Ar, other etchant gases, combinations of the foregoing, or the like Mix to proceed. In some embodiments, the first patterning process forms the notch 124 with a U-shaped bottom surface. The notch 124 may also be referred to as a U-shaped notch, such as the exemplary notch 124 shown in FIG. 12. Figure 12 also shows that the notch 124 has a top proximity distance TP0, a middle proximity distance MP0, and a bottom proximity distance BP0, the top proximity distance TP0, the middle proximity distance MP0, and the bottom proximity distance BP0 each from the adjacent dummy gate layer. Measure laterally from the edge to the side wall of the notch 124. The top proximity distance TP0 is measured at the top of the fin 56, and the top proximity distance TP0 may be between about 1 nm and about 30 nm. The bottom proximity distance BPO is measured at the bottom of the notch 124, and the bottom proximity distance BPO may be between about 1 nm and about 30 nm. The intermediate proximity distance MP0 is measured approximately halfway between the top of the fin 56 and the bottom of the notch 124, and the intermediate proximity distance MP0 may be between about 1 nm and about 30 nm. As shown in FIG. 12, the notch 124 has a notch depth D0 measured from the top surface of the fin 56 to the bottom of the notch 124, and the depth D0 may be between about 40 nm and about 100 nm. In some embodiments, the etching process for forming the recess 124 may also etch the isolation region 54. In some cases, after the etching process, a cleaning process may be performed, such as a dry cleaning process (such as an ashing process), a wet cleaning process, the like, or a combination of the foregoing. In some cases, native oxide (not shown) may be formed on the exposed surface of the U-shaped recess 124.

Please refer to FIG. 13, a second patterning process is performed on the fin 56 to reshape the U-shaped notch 124 and form the reshaped notch 126. As shown in FIG. 13, the second patterning process expands the U-shaped notch 124 (shown in dotted lines in FIG. 13 for comparison) to form the reshaped notch 126. In Figures 13-15C, the side wall area of the recess 126 at or near the bottom of the recess 126 is marked as the lower side wall 125, and the side wall area of the recess 126 at or near the top of the recess 126 is marked as upper The side wall 127. The sidewall regions labeled as the lower sidewall 125 and the upper sidewall 127 in Figure 13 are examples and may be different from those shown in the figure. The lower side wall 125 may be separated from the upper side wall 127 through other side wall regions, or the lower side wall 125 may be adjacent to the upper side wall 127. In some embodiments, the upper sidewall 127 may extend from the top surface of the fin 56 between about 10 nm and about 90 nm. In some embodiments, the lower sidewall 125 may extend from the bottom surface of the recess 126 between about 10 nm and about 90 nm. In some embodiments, the upper sidewall 127 may extend between about 10% and about 90% of the sidewall depth of the recess 126, for example, about 50%. In some embodiments, the lower sidewall 125 may extend between about 10% and about 90% of the sidewall depth of the recess 126, for example, about 50%. In some cases, the lower sidewall 125 is defined as a sidewall region having a recess 126 along the surface of the crystal plane, as described in more detail below. In some embodiments, the second patterning process causes the bottom proximity distance BP1 of the reshaped recess 126 to be greater than the bottom proximity distance BP0 of the recess 124. In some embodiments, the second patterning process may include an anisotropic dry etching process, while using the dummy structure 70, the gate spacer 122 and/or the isolation region 54 as a combined mask. In some cases, the second patterning process may have a slower etch rate than the first patterning process.

In some embodiments, the second patterning process includes a plasma etching process performed in a process chamber, wherein a process gas is supplied to the process chamber. In some embodiments, the plasma is direct plasma. In other embodiments, the plasma is a remote plasma generated in another plasma generating chamber connected to the process chamber. The process gas can be activated into plasma by any suitable method for generating plasma, such as transformer coupled plasma (TCP) system, inductively coupled plasma (ICP) system, magnetic assisted reactive ion technology, Electron cyclotron resonance technology or similar methods.

In some embodiments, the process gas used in the plasma etching process includes an etchant gas, such as H ₂ , Ar, other gases, or a combination of gases. In some embodiments, a carrier gas, such as N ₂ , Ar, He, Xe, or the like, can be used to carry the process gas to the process chamber. The process gas can flow into the process chamber at a rate between about 10 sccm and about 3000 sccm. For example, the etchant gas may flow into the process chamber or the plasma generation chamber at a rate between about 10 sccm and about 1000 sccm, for example, about 70 sccm. The carrier gas may flow into the process chamber at a rate between about 10 sccm and about 3000 sccm, for example, about 130 sccm. In some cases, the lower flow rate of the process gas can reduce the etching rate of the second patterning process and reduce damage to the fin 56 during the second patterning process. In some embodiments, the plasma etching process is performed at a temperature between about 200°C and about 400°C, such as about 330°C. In some cases, a higher process temperature can reduce the etching rate of the second patterning process and reduce damage to the fin 56 during the second patterning process. The pressure in the process chamber may be between about 60 mTorr and about 120 mTorr, for example, about 100 mTorr. In some cases, higher process pressure can make the plasma more stable or more renewable. The higher process pressure can also reduce damage to the fin 56 during the second patterning process. In some embodiments, the time for performing the plasma etching process is between about 10 seconds and about 1000 seconds. In some embodiments, the plasma etching process includes multiple steps.

In some embodiments, the second patterning process includes a plasma etching process using hydrogen (H) radicals. Hydrogen radicals can be formed by flowing H ₂ gas into the plasma generating cavity and igniting the plasma in the plasma generating cavity. In some embodiments, additional gas may be ignited into plasma, such as Ar, in the plasma generating cavity. The fin 56 is exposed to hydrogen radicals, and the hydrogen radicals etch the sidewalls of the U-shaped recess 124 laterally and vertically to form the reshaped recess 126. In some cases, hydrogen radicals can preferentially etch certain crystal faces of the semiconductor material of the fin 56. For example, for an embodiment where the material of the fin 56 is silicon, hydrogen radicals can selectively etch the crystal plane (100) compared to the crystal plane (111) or the crystal plane (110). Although examples of crystal planes (100) and crystal planes (111) are shown in Figure 13, there may be crystal planes (100), (111) or (110) that are not shown. In some cases, the etching rate of the crystal plane (100) may be greater than the etching rate of the crystal plane (111) by about 3 times. Due to the selectivity, during the second patterning process, the etching of hydrogen radicals along the silicon crystal plane (111) or (110) may tend to be slower or stop.

In some embodiments, the selective etching of hydrogen radicals may cause some sidewalls of the reshaped recess 126 to have surfaces that maintain crystal planes (111) or crystal planes (110) after the second patterning process. As shown in FIG. 13, some or all of the lower sidewall 125 of the recess 126 has a surface along the crystal plane. The lower sidewall 125 may have a surface including a crystal plane (111), a crystal plane (110), or a crystal plane (111) or a combination of crystal planes (110). In some cases, the ratio of the crystal plane (111) to the crystal plane (110) in the lower sidewall 125 may depend on the crystal orientation of the material of the fin 56 or the base 50. In some cases, having the lower sidewall 125 along the surface of the crystal plane may cause the reshaped recess 126 to have a taper, pointed shape, or V shape at the bottom as shown in FIG. 13. For example, at the bottom of the reshaped recess 126, the lower sidewalls 125 on both sides may have surfaces along crystal planes that meet at an angle defined by the intersection of the crystal planes of the surfaces. For example, in some cases, the bottom of the reshaped recess 126 may be defined by the intersection of the crystal plane of the first sidewall surface and the crystal plane of the second sidewall surface. Figure 13 shows that the reshaped recess 126 has a pointed shape with a bottom that is laterally centered between the gate spacers 122 on both sides, but in other cases, the bottom of the recess 126 may have a laterally offset tip. Head shape. In some cases, some, none, or all of the upper sidewall 127 of the reshaped recess 126 has a flat surface (e.g., crystal plane (111) or (110)). In some cases, the reshaped recess 126 may have a plane that is flat or straight but not along the crystal plane. For example, the reshaped notch may have a vertical, lateral, or oblique surface that is not along the crystal plane. In some cases, as shown in FIG. 13, the upper side wall 127 may have a curved surface or a convex surface.

In some cases, the bottom proximity distance can be increased by having the bottom of the reshaped recess 126 defined by the described crystal plane intersection (for example, the bottom proximity distance BP1 shown in Figure 13). For example, a reshaped notch 126 with a V-shaped bottom may be farther from an adjacent fin than a notch with a U-shaped bottom or a more horizontal bottom surface (such as the notch 124 shown in FIG. 12). In some cases, a larger bottom proximity distance reduces the amount of dopants in the epitaxial source/drain region that diffuse into or under the channel of the fin field effect transistor. Reducing diffused dopants can improve device performance. For example, reducing the diffusion of dopants can reduce the unwanted Drain-Induced Barrier Lowering (DIBL) effect or can reduce the off-state leakage current of the fin-type field effect transistor.

Figure 14 shows another embodiment of the reshaped recess 126 after the second patterning process has been performed. The reshaped notch 126 shown in FIG. 14 is similar to the reshaped notch 126 shown in FIG. 13 except that after the second patterning process, a portion 128 of the fin 56 remains under the gate spacer 122. In some embodiments, the second patterning process of the reserved portion 128 may have a shorter duration than the second patterning process without the reserved portion 128 (as shown in FIG. 13). For example, in some embodiments, the second patterning process of the retaining portion 128 may be performed for a first duration, and the first duration is less than half of the second duration of the second patterning process of the removing portion 128, but In other embodiments, the first duration may be another fraction of the second duration. In some embodiments, the portion 128 may extend from the gate spacer 122 toward the fin 56 for a distance between about 0.1 nm and about 10 nm, and may extend downward from the gate spacer 122 for a distance between about 0.1 nm and about 10 nm. between. In some embodiments, the portion 128 has a sidewall surface away from the center of the notch 126 (ie, toward the fin 56), which is marked with the symbol "S" in the example of FIG. 14. In some embodiments, the surface S includes one or more crystalline flat surfaces. For example, due to the above-mentioned selective etching of hydrogen radicals, the surface S may have crystal planes (111) or (110). In some embodiments, the angle A2 between the sidewall of the recess 126 and the surface S may be between about 35° and about 125°. In some cases, the portion 128 of the fin 56 remaining under the gate spacer 122 serves as an additional highly doped region, which can effectively extend the lightly doped source/drain regions 75/79 to the gate. Below the gap 122. In this approach, portion 128 can provide additional device performance improvements similar to those provided by lightly doped source/drain regions 75/79. In some cases, after the second patterning process, the remaining portion 128 of the fin 56 under the gate spacer 122 can protect the replacement gate (please refer to Figures 20A-20C) from dopants from the epitaxial source. /Drain region (please refer to Figures 16A-16C) diffuses into the replacement gate, and therefore can improve device performance. In some embodiments, the shape (for example, angle A2) or size of the portion 128 can be controlled by controlling the parameters of the second patterning process, such as process duration, process temperature, process pressure, process gas flow rate (for example, H ₂ flow rate) Or other parameters.

Figures 15A-15C show other embodiments in which the reshaped recesses 126 with different shapes can be formed by using the second patterning process described herein. The reshaped notch 126 shown in FIGS. 15A-15C is similar to the reshaped notch 126 shown in FIGS. 13-14. For example, a second patterning process with hydrogen radicals used in a plasma etching process can be used to form the notches 126 shown in FIGS. 15A-15C. In addition, the reshaped notch 126 shown in Figures 13-15C is for display purposes, and the reshaped notch 126 may have a different shape or size from the displayed reshaped notch 126, or may have a displayed reshape The combination of the shape or size of the notch 126. In some embodiments, the shape or size of the reshaped recess 126 can be controlled by controlling parameters of the second patterning process, such as process duration, process temperature, process pressure, process gas flow, or other parameters. In some embodiments, the parameters of the second patterning process can be controlled to form the reshaped notch 126 having a desired shape or a desired size. In some cases, by controlling the shape of the reshaped recess 126, the shape of the channel region of the adjacent fin-type field effect transistor is also controlled. In this way, a channel area with desired characteristics can be formed, such as a specific top proximity distance, middle proximity distance, and bottom proximity distance. The sidewall profile of the channel area can also be controlled to have specific features, such as uniform sidewalls, vertical sidewalls, tapered sidewalls, and so on. In some cases, the specific shape of the reshaped recess 126 (for example, with a V-shaped bottom or vertical sidewalls, etc.) may be more suitable for a specific source/drain epitaxial material or used to reshape the recess 126 An epitaxial material formation process for forming epitaxial source/drain regions in the process. In this manner, the embodiment shown herein presents an illustrative example of some shapes of the reshaped notch 126 that can be controlled by the second patterning process as described herein. In this way, the second patterning process described herein can provide greater flexibility in controlling the shape of the notch or the shape of the channel region of the fin-type field effect transistor.

FIG. 15A shows another embodiment of the shape of the reshaped recess 126, which is similar to the shape of the reshaped recess 126 shown in FIG. The lower sidewall 125 of the recess 126 may include a surface along a crystal plane (for example, the crystal plane (111) or (110)), and the upper sidewall 127 may include a surface not along a crystal plane (for example, a curved surface). The reshaped notch 126 may have a notch depth D1 measured vertically from the top surface of the fin 56 to the bottom of the notch 126 between about 40 nm and about 100 nm. The reshaped recess 126 may have a top width W1 measured across the recess 126 from the top of one fin 56 to the top of the opposite fin 56 between about 15 nm and about 60 nm. The reshaped notch 126 may have an intermediate width W2 measured across the notch 126 from one fin 56 to the opposite fin 56 at about half of the notch depth D1 between about 15 nm and about 80 nm. The ratio of width W1:W2 may be between about 0.5:1 and about 1:1. The reshaped notch 126 may have a width W3 measured across the notch 126 from one fin 56 to the opposite fin 56 between about 5 nm and about 50 nm at about half between the intermediate width W2 and the bottom of the notch 126. The ratio of width W3:W2 may be between about 0.5:1 and about 1:1. The reshaped notch may have a top proximity distance TP1 between about 1 nm and about 15 nm, a middle proximity distance MP1 between about 1 nm and about 10 nm, and a bottom proximity distance BP1 between about 1 nm and about 25 nm. The second patterning process described herein may allow a smaller intermediate proximity distance MP1, and in some cases, a smaller intermediate proximity distance MP1 may result in a reduction in the drain-induced energy barrier reduction effect in the fin-type field effect transistor. In some cases, compared to other technologies, the second patterning process may be able to reduce the intermediate proximity distance MP1 with less increase in depth D1 or less decrease in top approach distance TP1. The lower sidewall 125 of the recess 126 may have an angle A1 defined by a crystal plane (for example, a crystal plane (111) or (110)) and a horizontal plane. The angle A1 may be between about 20° and about 80°.

Figure 15B shows another embodiment of a reshaped recess 126 with a straight upper side wall 127. In some cases, the upper side wall 127 may be substantially vertical (as shown in Figure 15B) or may have an angle. The lower sidewall 125 may include a surface along a crystal plane (for example, the crystal plane (111) or (110)). The reshaped notch 126 may have a notch depth D1 measured vertically from the top surface of the fin 56 to the bottom of the notch 126 between about 40 nm and about 100 nm. The reshaped notch 126 may have a depth D2 measured vertically from the top surface of the fin 56 to the lower sidewall 125 between about 30 nm and about 100 nm. The reshaped notch 126 may have a top width W1 measured across the notch 126 from the top of one fin 56 to the top of the opposite fin 56 between about 10 nm and about 60 nm. The reshaped notch 126 may have an intermediate width W2 measured across the notch 126 from one fin 56 to the opposite fin 56 at about half of the notch depth D1 between about 10 nm and about 80 nm. The ratio of width W1:W2 may be between about 0.5:1 and about 1:1. The reshaped notch 126 may have a width W3 measured across the notch 126 from one fin 56 to the opposite fin 56 between about 5 nm and about 60 nm at about half between the intermediate width W2 and the bottom of the notch 126. The ratio of width W3:W2 may be between about 0.5:1 and about 1:1. The reshaped notch may have a top proximity distance TP1 between about 1 nm and about 15 nm, a middle proximity distance MP1 between about 1 nm and about 15 nm, and a bottom proximity distance BP1 between about 1 nm and about 30 nm. The lower sidewall 125 of the recess 126 may have an angle A1 defined by a crystal plane (for example, a crystal plane (111) or (110)) and a horizontal plane. The angle A1 may be between about 20° and about 80°. In some cases, forming the reshaped recess 126 with more vertical sidewalls may allow the channel region under the gate stack of the fin-type field effect transistor to have a more uniform profile. By improving the uniformity of the channel area profile, the fin-type field effect transistor can be turned on and off more uniformly across the channel area, which can improve device speed, current uniformity, and efficiency.

FIG. 15C shows another embodiment of the reshaped recess 126 with the upper side wall 127, the middle side wall 129 and the lower side wall 125. In the exemplary recess 126 shown in FIG. 15C, the upper sidewall 127 and the lower sidewall 125 include surfaces along crystal planes (for example, crystal planes (111) or (110)). The middle side wall 129 may be vertical (as shown in FIG. 15C) or may have a curved or inclined profile. The reshaped notch 126 may have a notch depth D1 measured vertically from the top surface of the fin 56 to the bottom of the notch 126 between about 40 nm and about 100 nm. The reshaped notch 126 may have a depth D3 measured perpendicularly from the top surface of the fin 56 to the middle sidewall 129 of between about 1 nm and about 30 nm. The middle sidewall 129 may extend a vertical depth D4 between about 10 nm and about 50 nm. The reshaped notch 126 may have a top width W1 measured across the notch 126 from the top of one fin 56 to the top of the opposite fin 56 between about 10 nm and about 60 nm. The reshaped notch 126 may have a width W4 measured across the notch 126 from one fin 56 to the opposite fin 56 at the top of the intermediate sidewall 129 between about 10 nm and about 70 nm. The reshaped notch 126 may have a width W5 measured across the notch 126 from one fin 56 to the opposite fin 56 at the bottom of the intermediate sidewall 129 between about 10 nm and about 80 nm. The ratio of width W5:W4 may be between about 0.5:1 and about 1:1. The reshaped notch 126 may have a width W3 between about 1 nm and about 40 nm measured across the notch 126 from one fin 56 to the opposite fin 56 at about half between the width W5 and the bottom of the notch 126. The reshaped notch may have a top proximity distance TP1 between about 1 nm and about 20 nm, a middle proximity distance MP1 between about 1 nm and about 15 nm, and a bottom proximity distance BP1 between about 2 nm and about 30 nm. The lower side wall 125 of the recess 126 may have an angle A1 defined by the crystal plane of the lower side wall 125 (for example, the crystal plane (111) or (110)) and the horizontal plane. The angle A1 may be between about 20° and about 80°. The upper sidewall 127 of the recess 126 may have an angle A3 defined by a crystal plane (for example, a crystal plane (111) or (110)) and a horizontal plane. The angle A3 may be between about 45° and about 90°. In some cases, forming the reshaped recess 126 with more vertical sidewalls (such as the middle sidewall 129) may allow the channel region under the gate stack of the fin-type field effect transistor to have a more uniform profile. By improving the uniformity of the channel area profile, the fin-type field effect transistor can be turned on and off more uniformly across the channel area, which can improve device speed, current uniformity, and efficiency.

Figures 16A-16C show that epitaxial source/drain regions 82 are formed in the first region 100A. The epitaxial source/drain region 82 may be a single layer or include two or more layers of materials. For example, the epitaxial source/drain region 82 shown in FIG. 16B includes a plurality of epitaxial layers 82A-82C. For clarity, other drawings do not show multiple epitaxial layers. In some embodiments, the epitaxy source/drain region 82 uses metal-organic chemical vapor deposition (metal-organic CVD, MOCVD), molecular beam epitaxy (MBE), and liquid epitaxy (liquid epitaxy). Phase epitaxy (LPE), vapor phase epitaxy (VPE), selective epitaxial growth (SEG), a combination of the foregoing, or similar methods are epitaxially grown in the recess 126. In some embodiments, the epitaxial source/drain region 82 is grown in the same process chamber as the second patterning process. In some cases, before forming the epitaxial source/drain region 82, the fin 56 may be cleaned, such as a dry cleaning process (such as an ashing process), a wet cleaning process (such as using Caro's Strip or HF), and the like Method or a combination of the foregoing. The epitaxial source/drain region 82 may have a surface protruding from the corresponding surface of the fin 56 and may have facets. The epitaxial source/drain regions 82 are formed in the fin 56 such that each dummy structure 70 is disposed between corresponding adjacent pairs of epitaxial source/drain regions 82. The epitaxial source/drain region 82 may include any suitable material, such as any material suitable for n-type fin field effect transistors. For example, if the fin 56 is silicon, the epitaxial source/drain region 82 may include silicon, SiC, SiCP, SiP, SiGeB, the like, or a combination of the foregoing. The different layers of the epitaxial source/drain region 82 can be of different materials or can be the same material, and can be grown in separate steps. For example, the epitaxial layer 82A (sometimes referred to as the first epitaxial layer) may be deposited in the recess 126 first, and then the epitaxial layer 82B (sometimes referred to as the second epitaxial layer) may be deposited in the epitaxy Above the epitaxial layer 82A, then an epitaxial layer 82C (sometimes referred to as the third epitaxial layer) may be deposited on the epitaxial layer 82B. In some embodiments, the epitaxial layer 82A may include materials such as silicon, SiC, SiP, the like, or a combination of the foregoing. The epitaxial layer 82A may be undoped or doped. For example, in some embodiments, the epitaxial layer 82A can be doped with a phosphorus concentration between about 5× ^{10 19} cm ⁻³ and about 5× ^{10 20} cm ⁻³ , but other dopants or concentrations may be used. In some embodiments, the epitaxial layer 82A may be formed to have a thickness between about 5 nm and about 20 nm. In some embodiments, the epitaxial layer 82A may include a stressor material that applies stress to the channel region of the fin 56. For example, the stress may be a tensile stress for an n-type fin field effect transistor. In some embodiments, the epitaxial layer 82B may include materials such as silicon, SiP, the like, or a combination of the foregoing. The epitaxial layer 82B may be undoped or doped. For example, in some embodiments, the epitaxial layer 82B may be doped with phosphorus at a concentration between about 5× ^{10 20} cm ⁻³ and about 4× ^{10 21} cm ⁻³ , but other dopants or concentrations may be used. In some embodiments, the epitaxial layer 82B may be formed to have a thickness between about 15 nm and about 60 nm. In some embodiments, the epitaxial layer 82C may include materials such as silicon, SiP, SiGe, SiGe:P, the like, or a combination of the foregoing. The epitaxial layer 82C may be undoped or doped. For example, in some embodiments, the epitaxial layer 82C may be doped with phosphorus at a concentration between about 1×10 ²¹ cm ⁻³ and about 3×10 ²¹ cm ⁻³ , but other dopants or concentrations may be used. In some embodiments, the epitaxial layer 82C can be formed to have a thickness between about 5 nm and about 20 nm. In some cases, the tapered shape of the reshaped recess 126 may allow for improved filling efficiency of the epitaxial source/drain region 82 during the formation of the epitaxial source/drain region 82.

In some embodiments, the epitaxial source/drain regions 82 in the first region 100A may be implanted with dopants, similar to the aforementioned process for forming lightly doped source/drain regions 75/79, and then Perform annealing (please refer to Figures 8A, 8B and 8C). The epitaxial source/drain region 82 may have an impurity concentration in a range between about 10 ¹⁹ cm ^-3 and about 10 ²¹ cm ^-3 . The n-type impurities used in the source/drain regions in the first region 100A (for example, the n-type metal oxide semiconductor region) can be any of the aforementioned n-type impurities. In other embodiments, the material of the epitaxial source/drain region 82 may be doped in-situ during the growth. In the embodiment shown, each epitaxial source/drain region 82 is physically separated from the other epitaxial source/drain regions 82. In other embodiments, two or more adjacent epitaxial source/drain regions 82 may be combined. This embodiment is shown in FIG. 22. Two adjacent epitaxial source/drain regions 82 are merged to form a common source/drain region. In some embodiments, more than two adjacent epitaxial source/drain regions 82 may be merged.

Referring to FIGS. 17A-17C, after forming the epitaxial source/drain region 82 in the first region 100A, the epitaxial source/drain region 84 is formed in the second region 100B. In some embodiments, the epitaxial source/drain region 84 is formed in the second region 100B by using the similar formation method of the epitaxial source/drain region 82 described above with reference to FIGS. 12-15C, and for For brevity, the detailed description will not be repeated. In some embodiments, during the formation of the epitaxial source/drain region 84 in the second region 100 (such as the p-type metal oxide semiconductor region), the first region 100A (such as the n-type metal oxide semiconductor region) may be shielded (not shown).物 Semiconductor area). After that, the source/drain regions of the fin 56 in the second region 100B are etched to form a notch similar to the reshaped notch 126 (please refer to FIGS. 13-15C) (as shown in FIGS. 17B-17C). Crystal source/drain region 84). For example, a first patterning process may be used to form a U-shaped notch similar to the U-shaped notch 124 (please refer to FIG. 12), and then a second patterning process may be performed to reshape the notch. The second patterning process may include, for example, a plasma etching process using hydrogen radicals or may include other techniques described above. The reshaped notch in the second region 100B can be formed by using a method similar to the above-mentioned formation method of the reshaped notch 126 in the first region 100A with reference to FIGS. 12-15C. For the sake of brevity, I will not repeat them here.

Then, the epitaxial source/drain region 84 in the second region 100B is obtained by using metal organic chemical vapor deposition, molecular beam epitaxy, liquid phase epitaxy, vapor phase epitaxy, selective epitaxial growth, and a combination of the foregoing Or similar method epitaxial growth in the notch. In some embodiments, the epitaxial source/drain region 84 is grown in the same process cavity where the second patterning process is performed. In some cases, before forming the epitaxial source/drain region 84, the fin 56 may be cleaned, such as a dry cleaning process (such as an ashing process), a wet cleaning process (such as using Caro's Strip or HF), and the like Method or a combination of the foregoing. The epitaxial source/drain region 84 may be a single layer or include two or more layers of materials. The epitaxial source/drain region 84 may include any suitable material, such as any material suitable for p-type fin field effect transistors. For example, if the fin 56 is silicon, the epitaxial source/drain region 84 may include SiGe, SiGeB, Ge, GeSn, the like, or a combination of the foregoing. The different layers of the epitaxial source/drain region 84 can be of different materials or can be the same material, and can be grown in separate steps. For example, the first epitaxial layer may be deposited in the recess first, then the second epitaxial layer may be deposited on the first epitaxial layer, and then the third epitaxial layer may be deposited on the second epitaxial layer. In some embodiments, the first epitaxial layer may include materials such as silicon, SiGe, SiGe:B, the like, or a combination of the foregoing. The first epitaxial layer may be undoped or doped. For example, in some embodiments, the first epitaxial layer may be SiGe with a Ge atomic percentage between about 1% and about 25%, or may be doped with a boron concentration of about 5× ^{10 19} cm ⁻³ and about Materials between 1x10 ²⁰ cm ^-3 , but other dopants or concentrations can be used. In some embodiments, the first epitaxial layer may be formed to have a thickness between about 5 nm and about 20 nm. In some embodiments, the first epitaxial layer may include a stressor material that applies stress to the channel region of the fin 56. For example, the stress may be the compressive stress used for a p-type fin field effect transistor. In some embodiments, the second epitaxial layer may include materials such as silicon, SiGe, SiGe:B, the like, or a combination of the foregoing. The second epitaxial layer can be undoped or doped. For example, in some embodiments, the second epitaxial layer may be SiGe with a Ge atomic percentage between about 25% and about 55%, or may be doped with a boron concentration of about 1×10 ²⁰ cm ^-3 and about Materials between 2x10 ²¹ cm ^-3 , but other dopants or concentrations can be used. In some embodiments, the second epitaxial layer may be formed to have a thickness between about 20 nm and about 60 nm. In some embodiments, the third epitaxial layer may include materials such as silicon, SiGe, SiGe:B, the like, or a combination of the foregoing. The third epitaxial layer can be undoped or doped. For example, in some embodiments, the third epitaxial layer may be SiGe with a Ge atomic percentage between about 45% and about 60%, or may be doped with a boron concentration of about 5× ^{10 20} cm ^-3 and about Materials between 2x10 ²¹ cm ^-3 , but other dopants or concentrations can be used. In some embodiments, the third epitaxial layer may be formed to have a thickness between about 10 nm and about 20 nm. The epitaxial source/drain region 84 may have a surface protruding from the corresponding surface of the fin 56 and may have facets. In the second region 100B, the epitaxial source/drain region 84 is formed in the fin 56 such that each dummy structure 70 is disposed between the corresponding adjacent pair of epitaxial source/drain regions 84. In some embodiments, the epitaxial source/drain region 84 may extend through the fin 56 and into the semiconductor strip 52.

In some embodiments, the epitaxial source/drain region 84 in the second region 100B may be implanted with dopants, similar to the aforementioned process for forming lightly doped source/drain regions 75/79, and then Perform annealing (please refer to Figures 8A, 8B and 8C). The epitaxial source/drain region 84 may have an impurity concentration in a range between about 10 ¹⁹ cm ^-3 and about 10 ²¹ cm ^-3 . The p-type impurity used in the epitaxial source/drain region 84 in the second region 100B (for example, the p-type metal oxide semiconductor region) can be any of the aforementioned p-type impurities. In other embodiments, the material of the epitaxial source/drain region 84 may be doped in-situ during the growth. Depending on the shape of the corresponding reshaped notch, a portion of the epitaxial source/drain regions 82 and 84 may have curved sidewalls or substantially straight sidewalls. In the embodiment shown, each epitaxial source/drain region 84 is physically separated from the other epitaxial source/drain regions 84. In other embodiments, two or more adjacent epitaxial source/drain regions 84 may be combined. This embodiment is shown in FIG. 22. Two adjacent epitaxial source/drain regions 84 are merged to form a common source/drain region. In some embodiments, more than two adjacent epitaxial source/drain regions 84 may be merged.

Referring to FIGS. 17A-17C, an etch stop layer 87 and an interlayer dielectric (ILD) 88 are deposited above the dummy structure 70 and above the epitaxial source/drain regions 82 and 84. In some embodiments, the interlayer dielectric 88 is a flowable film formed by flowable chemical vapor deposition. In some embodiments, the interlayer dielectric 88 is formed of a dielectric material, such as Phospho-Silicate Glass (PSG), Boro-Silicate Glass (Boro-Silicate Glass, BSG), boron-doped phosphorus Boron-Doped Phospho-Silicate Glass (BPSG), undoped Silicate Glass (USG) or the like, and can be deposited by any suitable method, such as chemical vapor deposition, electrical Slurry assisted chemical vapor deposition, a combination of the foregoing, or similar methods. In some embodiments, when the interlayer dielectric 88 is patterned to form openings for forming contacts, the etch stop layer 87 is used as a stop layer. Therefore, the material of the etch stop layer 87 can be selected so that the material of the etch stop layer 87 has a lower etching rate than the material of the interlayer dielectric 88.

Referring to FIGS. 18A-18C, a planarization process (such as a chemical mechanical polishing process) may be performed to make the top surface of the interlayer dielectric 88 and the top surface of the dummy structure 70 flush. After the planarization process, the top surface of the dummy structure 70 is exposed from the interlayer dielectric 88. In some embodiments, chemical mechanical polishing can also remove the mask 72 or a part of the mask 72 on the dummy structure 70.

Referring to FIGS. 19A-19C, the mask 72 and part of the dummy structure 70 are removed in the etching step, so that the notch 90 is formed. Each notch 90 exposes the channel area of the corresponding fin 56. Each channel region is disposed between each pair of adjacent epitaxial source/drain regions 82 in the first region 100A or between each pair of adjacent epitaxial source/drain regions 84 in the second region 100B between. During the removal process, the dummy dielectric layer 58 can be used as an etch stop layer when the dummy structure 70 is etched. After the dummy structure 70 is removed, the dummy dielectric layer 58 can then be removed.

Referring to FIGS. 20A-20C, gate dielectric layers 92 and 96 and gate electrodes 94 and 98 for replacing the gate are formed in the first region 100A and the second region 100B, respectively. The gate dielectric layers 92 and 96 are compliantly deposited in the recess 90, such as on the top surface and sidewalls of the fin 56, the sidewalls of the gate spacer 122 and the fin spacer 130, and the interlayer dielectric 88 respectively. On the top surface. In some embodiments, the gate dielectric layers 92 and 96 include silicon oxide, silicon nitride, or the foregoing multiple layers. In other embodiments, the gate dielectric layers 92 and 96 comprise high-k dielectric materials, and in these embodiments, the gate dielectric layers 92 and 96 may have a dielectric constant value greater than About 7.0, and may include metal oxides or silicates of Hf, Al, Zr, La, Mg, Ba, Ti, Pb and combinations of the foregoing. The method for forming the gate dielectric layers 92 and 96 may include molecular-beam deposition (MBD), atomic layer deposition, plasma-assisted chemical vapor deposition, a combination of the foregoing, or similar methods.

Next, gate electrodes 94 and 98 are deposited on the gate dielectric layers 92 and 96, respectively, and fill the remaining part of the notch 90. The gate electrodes 94 and 98 may be made of metal-containing materials, such as TiN, TaN, TaC, Co, Ru, Al, Ag, Au, W, Ni, Ti, Cu, a combination of the foregoing, or the foregoing multiple layers. After the gate electrodes 94 and 98 are filled, a planarization process (such as a chemical mechanical polishing process) can be performed to remove the excess parts of the gate dielectric layers 92 and 96 and the gate electrodes 94 and 98, where the excess parts are interlayered Above the top surface of the electric mass 88. The final remaining part of the materials of the gate electrodes 94 and 98 and the gate dielectric layers 92 and 96 thus form the replacement gate of the final fin field effect transistor.

In some embodiments, the formation of gate dielectric layers 92 and 96 can occur simultaneously, so that the gate dielectric layers 92 and 96 are made of the same material, and the formation of gate electrodes 94 and 98 can occur simultaneously, so that the gate The pole electrodes 94 and 98 are made of the same material. However, the gate dielectric layers 92 and 96 can be formed by different processes, so that the gate dielectric layers 92 and 96 are made of different materials, and the gate electrodes 94 and 98 can be formed by different processes, so that the gate electrodes 94 and 98 is made of different materials. When using different processes, various masking steps can be used to mask and expose suitable areas.

Please refer to Figures 21A-21C, the interlayer dielectric 102 is deposited on the interlayer dielectric 88, the contact 104 is formed through the interlayer dielectric 102 and the interlayer dielectric 88, and the contact 110 is formed through the interlayer dielectric 102 . In one embodiment, the interlayer dielectric 102 is formed by using materials and formation methods similar to the interlayer dielectric 88 described above with reference to FIGS. 17A-17C. For the sake of brevity, I will not repeat them here. In some embodiments, the interlayer dielectric 102 and the interlayer dielectric 88 are formed of the same material. In other embodiments, the interlayer dielectric 102 and the interlayer dielectric 88 are formed of different materials.

The opening for the contact 104 is formed through the interlayer dielectrics 88 and 102 and the etch stop layer 87. The opening for the contact 110 is formed through the interlayer dielectric 102 and the etch stop layer 87. These openings can all be formed in the same process at the same time, or formed in separate processes. The opening can be formed by using suitable photolithography and etching techniques. A liner (such as a diffusion barrier layer, an adhesive layer, or the like) and a conductive material are formed in the opening. The liner may include titanium, titanium nitride, tantalum, tantalum nitride, or the like. The conductive material may be copper, copper alloy, silver, gold, tungsten, cobalt, aluminum, nickel, or the like. A planarization process (such as chemical mechanical polishing) may be performed to remove excess material from the top surface of the interlayer dielectric 102. The remaining pads and conductive material form contacts 104 and 110 in the openings. Annealing may be performed to form silicides at the interface between the epitaxial source/drain regions 82 and 84 and the contact 104, respectively. The contact 104 is physically and electrically coupled to the epitaxial source/drain regions 82 and 84, and the contact 110 is physically and electrically coupled to the gate electrodes 94 and 98. Although FIG. 21B shows that the contact 104 and the contact 110 are in the same cross-section, this drawing is for display purposes, and in some embodiments, the contact 104 and the contact 110 are disposed in different cross-sections.

Fig. 22 shows a schematic cross-sectional view of the fin-type field effect transistor device, which is similar to the fin-type field effect transistor device shown in Figs. 21A-21C, wherein the same components are marked with the same reference symbols. Figure 22 is shown along the reference section B-B of Figure 1. In some embodiments, the fin field effect transistor device of FIG. 22 can be formed by using materials and forming methods similar to those of the fin field effect transistor device described above with reference to FIGS. 21A-21C. For the sake of brevity, I will not repeat them here. In the embodiment shown, two adjacent epitaxial source/drain regions 82 and two adjacent epitaxial source/drain regions 84 are merged to form individually shared source/drain regions. In other embodiments, more than two adjacent epitaxial source/drain regions 82 or more than two adjacent epitaxial source/drain regions 84 may be combined.

FIG. 23 shows a flowchart of a method of forming a fin-type field effect transistor device according to some embodiments. The method 2000 begins in step 2001, where a substrate (such as the substrate 50 shown in Figure 2A) is patterned to form a strip (such as the semiconductor strip 52 shown in Figure 3A), as described above with reference to Figures 2A and 3A. In step 2003, an isolation region (for example, isolation region 54 shown in FIG. 5A) is formed between adjacent strips, as described above with reference to FIGS. 4A and 5A. In step 2005, a dummy structure (for example, the dummy structure 70 shown in Figures 7A-7B) is formed above the strips, as described above with reference to Figures 6A-6B and 7A-7C. In step 2007, a first etching process is performed on the strip to form a recess (for example, the recess 124 in the strip described above with reference to FIG. 12). In step 2009, a second etching process is performed on the strip to form a reshaped recess (for example, the recess 126 described above with reference to FIGS. 13-15C). In step 2011, the source/drain regions are epitaxially grown in the reshaped recesses (for example, the epitaxial source/drain regions 82 shown in Figures 16B-16C). In some embodiments, steps 2007, 2009 and 2011 are performed on the strips provided in the first region of the substrate forming the n-type device. In these embodiments, steps 2007, 2009, and 2011 may be repeated to perform these steps on the strips provided in the second region of the substrate forming the p-type device, as described above with reference to Figures 17A-17C. In step 2013, a replacement gate stack (such as gate dielectric layer 92/gate electrode 94 and gate dielectric layer 96/gate electrode 98 shown in Figures 20A-20C) is formed above the strips .

The various embodiments discussed herein lead to improved fin-type field effect transistor performance. For example, the use of hydrogen radicals during the etching process to reshape the notches between the fins can have advantages. By using hydrogen radicals during the etching process, the bottom of the reshaped recess can be formed to have a tapered shape or a pointed bottom. In this manner, since the pointed bottom of the reshaped recess can be farther away from the adjacent fin, the proximity distance of the bottom of the reshaped recess can be increased. In this manner, the bottom approach distance of the notch with a pointed bottom as described herein may be greater than that of the notch with a U-shaped or flatter bottom surface. In some cases, a larger bottom proximity distance reduces the amount of dopants in the epitaxial source/drain region that diffuse into or under the channel of the fin field effect transistor. The diffusion of dopants into or below the channel can reduce device performance. In some cases, using the techniques described herein can also reduce the Drain Induced Barrier Reduction (DIBL) effect or reduce off-state leakage current. By controlling the etching parameters, the etching of the reshaped notch can be controlled to produce the reshaped notch of the desired shape (some examples are shown in Figures 13-15C). In this way, the top approach distance, the middle approach distance, and the bottom approach distance of the reshaped notch can also be controlled. The technology described herein is described with reference to fin field effect transistors, but can be used to form other devices, such as planar field effect transistors, semiconductor lasers, or other optical devices or other types of devices.

According to an embodiment, a method includes forming a fin on a substrate, forming an isolation region adjacent to the fin, forming a dummy structure above the fin, and recessing the fin adjacent to the dummy structure using a first etching process to form a first recess , Using a second etching process to reshape the first notch to form a reshaped first notch, wherein the bottom of the reshaped first notch consists of the crystal plane of the first sidewall surface and the crystal plane of the second sidewall surface It is defined by intersection, where the first sidewall surface faces the second sidewall surface, and the source/drain regions are epitaxially grown in the reshaped first recess. In one embodiment, the second etching process selectively etches the crystal plane with the first crystal orientation relative to the second crystal plane with the second crystal orientation, wherein the crystal plane on the first sidewall surface has the first crystal orientation, and The first sidewall surface includes a second crystal plane with a second crystal orientation. In one embodiment, the second crystal plane has a (111) crystal orientation. In one embodiment, the second etching process includes a plasma etching process using hydrogen radicals. In one embodiment, the second etching process further includes forming argon plasma. In an embodiment, the first lateral distance between the bottom of the first recess and the adjacent dummy structure is smaller than the second lateral distance between the bottom of the reshaped first recess and the adjacent dummy structure. In one embodiment, the step of epitaxially growing the source/drain regions in the reshaped first recess includes epitaxially growing a first semiconductor material in the reshaped first recess, wherein the first semiconductor material covers the reshaped At the bottom of the first recess, a second semiconductor material is epitaxially grown above the first semiconductor material, the second semiconductor material has a different composition from the first semiconductor material, and a third semiconductor material is epitaxially grown above the second semiconductor material , The third semiconductor material has a different composition from the second semiconductor material.

According to another embodiment, a method includes patterning a substrate to form a strip, the strip including a first semiconductor material, and an isolation region is formed along the sidewall of the strip, and the upper part of the strip extends above the top surface of the isolation region along The sidewalls and top surface of the upper part of the strip form a dummy structure, the exposed part of the upper part of the strip is subjected to a first etching process to form a first notch, the exposed part of the strip is exposed by the dummy structure, and the first etching process is performed Afterwards, a second etching process is used to reshape the first notch to have a V-shaped bottom surface, wherein, relative to the second crystal plane with the second crystal orientation, the second etching process has the first crystal plane with the first crystal orientation. Selectivity, and epitaxial growth of the source/drain regions in the reshaped first recess. In one embodiment, the second etching process has a lower etching rate than the first etching process. In one embodiment, the V-shaped bottom surface includes intersecting (111) crystal planes. In one embodiment, the first etching process includes a first plasma etching process using a first etching gas, and the second etching process includes a second plasma etching process using a second etching gas different from the first etching gas. In one embodiment, the second etching gas includes H ₂ . In one embodiment, the second plasma etching process forms a plasma containing hydrogen radicals. In one embodiment, after the second etching process is performed, the uppermost surface of the first recess extends along the third crystal plane having the second crystal orientation. In one embodiment, the step of epitaxially growing the source/drain regions includes epitaxially growing a first material, epitaxially growing a second material, and epitaxially growing a third material, wherein the first material, the second material, and the third material The materials are all different materials. In one embodiment, the method further includes forming spacers along the sidewalls of the dummy structure, wherein after the second etching process, the second etching process does not remove the portion of the first semiconductor material adjacent to the bottom surface of the spacers .

According to another embodiment, the device includes a fin located above the substrate, wherein the first sidewall surface of the bottom of the fin extends along the crystal plane of the first crystal orientation, the isolation region is adjacent to the fin, and the gate structure is along the sidewalls of the fin and the top of the fin. Extending above the surface, the gate spacer is laterally adjacent to the gate structure, and the epitaxial region is adjacent to the fin, wherein the bottom of the epitaxial region is tapered to a point. In one embodiment, the bottom of the epitaxial region is tapered along the crystal plane of the first crystal direction. In one embodiment, the widest part of the epitaxial region has a curved profile. In one embodiment, the widest part of the epitaxial region is between the top surface of the epitaxial region and the bottom of the epitaxial region. In an embodiment, the epitaxial region includes a first material, a second material above the first material, and a third material above the second material, wherein the first material, the second material, and the third material are all composed of different materials .

The foregoing text summarizes the features of many embodiments, so that those skilled in the art can better understand the embodiments of the present invention from various aspects. Those skilled in the art should understand, and can easily design or modify other processes and structures based on the embodiments of the present invention, so as to achieve the same purpose and/or achieve the same purpose as the embodiments described herein. The same advantages. Those skilled in the art should also understand that these equivalent structures do not depart from the spirit and scope of the present invention. Without departing from the spirit and scope of the invention, various changes, substitutions or modifications can be made to the embodiments of the invention.

30: fin field effect transistor 32, 50: substrate 34, 54: isolation region 36, 56: fin 38: gate dielectric 40, 94, 98: gate electrode 42, 44: source/drain region 52 : Semiconductor strips 53, 62, 72, 118: mask 53A: first mask layer 53B: second mask layer 55: trench 58: dummy dielectric layer 60: dummy gate layer 70: dummy structure 75, 79: Lightly doped source/drain regions 80A: first spacer layer 80B: second spacer layer 80C: third spacer layer 82, 84: epitaxial source/drain regions 82A, 82B, 82C: epitaxial layer 87: etch stop layer 88, 102: interlayer dielectric 90, 124, 126: notch 92, 96: gate dielectric layer 100A: first region 100B: second region (100), (111): crystal plane / Crystal orientation 104, 110: contact 120: offset spacer 122: gate spacer 125: lower side wall 127: upper side wall 128: part 130: fin spacer 2000: methods 2001, 2003, 2005, 2007, 2009, 2011, 2013: Step S: Surface A1, A2, A3: Angle D0, D1, D2, D3, D4: Depth H ₁ : Height W ₁ , W1, W2, W3, W4, W5: Width BP0: Bottom Approaching Distance MP0 : Middle approach distance TP0: Top approach distance

The embodiments of the present invention can be better understood according to the following detailed description and the accompanying drawings. It should be noted that, according to the standard practice of this industry, the various features in the illustration are not necessarily drawn to scale. In fact, it is possible to arbitrarily enlarge or reduce the size of various components to make a clear description. Figure 1 is a three-dimensional view of a fin field-effect transistor (FinFET) device according to some embodiments. 2A is a schematic cross-sectional view of an intermediate stage of manufacturing a fin-type field effect transistor device according to some embodiments. 3A is a schematic cross-sectional view of an intermediate stage of manufacturing a fin-type field effect transistor device according to some embodiments. 4A is a schematic cross-sectional view of an intermediate stage of manufacturing a fin-type field effect transistor device according to some embodiments. FIG. 5A is a schematic cross-sectional view of an intermediate stage of manufacturing a fin-type field effect transistor device according to some embodiments. 6A-6B are schematic cross-sectional diagrams of an intermediate stage of manufacturing a fin-type field effect transistor device according to some embodiments. FIGS. 7A-7C are schematic cross-sectional views of an intermediate stage of manufacturing a fin-type field effect transistor device according to some embodiments. 8A-8C are schematic cross-sectional diagrams of an intermediate stage of manufacturing a fin-type field effect transistor device according to some embodiments. 9A-9C are schematic cross-sectional diagrams of intermediate stages of manufacturing a fin-type field effect transistor device according to some embodiments. FIGS. 10A-10C are schematic cross-sectional views of an intermediate stage of manufacturing a fin-type field effect transistor device according to some embodiments. FIGS. 11A-11C are schematic cross-sectional views of an intermediate stage of manufacturing a fin-type field effect transistor device according to some embodiments. FIG. 12 is a schematic cross-sectional view of the formation of the first recess in the fabrication of fin-type field effect transistor devices according to some embodiments. FIG. 13 is a schematic cross-sectional view of the formation of a reshaping recess in a fin-type field effect transistor device according to an embodiment. FIG. 14 is a schematic cross-sectional view of the formation of the reshaping notch in the fin-type field effect transistor device according to another embodiment. FIGS. 15A-15C are schematic cross-sectional views showing the formation of the reshaping notch in the fabrication of fin-type field effect transistor devices according to other embodiments. 16A-16C are schematic cross-sectional diagrams of an intermediate stage of manufacturing a fin-type field effect transistor device according to some embodiments. FIGS. 17A-17C are schematic cross-sectional views of an intermediate stage of manufacturing a fin-type field effect transistor device according to some embodiments. FIGS. 18A-18C are schematic cross-sectional views of an intermediate stage of manufacturing a fin-type field effect transistor device according to some embodiments. FIGS. 19A-19C are schematic cross-sectional views of an intermediate stage of manufacturing a fin-type field effect transistor device according to some embodiments. FIGS. 20A-20C are schematic cross-sectional views of an intermediate stage of manufacturing a fin-type field effect transistor device according to some embodiments. 21A-21C are schematic cross-sectional diagrams of an intermediate stage of manufacturing a fin-type field effect transistor device according to some embodiments. FIG. 22 is a schematic cross-sectional view of an intermediate stage of manufacturing a fin-type field effect transistor device with merged epitaxial regions according to some embodiments. FIG. 23 is a flowchart of a method for forming a fin-type FET device using a reshaping notch according to some embodiments.

2000: method

2001, 2003, 2005, 2007, 2009, 2011, 2013: steps

Claims (20)

A method for forming a semiconductor device includes: A fin is formed on a base; Forming an isolation region adjacent to the fin; Forming a dummy structure above the fin; Using a first etching process to recess the fin adjacent to the dummy structure to form a first recess; A second etching process is used to reshape the first notch to form a reshaped first notch, wherein the bottom of the reshaped first notch consists of a crystal plane of a first sidewall surface and a second The sidewall surface is defined by intersecting crystal planes, wherein the first sidewall surface faces the second sidewall surface; and A source/drain region is epitaxially grown in the reshaped first recess. The method for manufacturing a semiconductor device as described in claim 1, wherein the second etching process selectively etches a crystal plane with a first crystal orientation relative to a second crystal plane with a second crystal orientation , Wherein the crystal plane of the first sidewall surface has the first crystal orientation, and wherein the first sidewall surface includes the second crystal plane having the second crystal orientation. According to the method of manufacturing a semiconductor device described in the second patent application, the second crystal face has a (111) crystal orientation. According to the manufacturing method of the semiconductor device described in the first item of the patent application, the second etching process includes a plasma etching process using hydrogen radicals. According to the method for manufacturing a semiconductor device as described in claim 4, the second etching process further includes forming an argon plasma. The method for manufacturing a semiconductor device as described in claim 1, wherein a first lateral distance between the bottom of the first recess and an adjacent dummy structure is smaller than the bottom of the reshaped first recess A second lateral distance between the adjacent dummy structure. The method for manufacturing a semiconductor device as described in claim 1, wherein the step of epitaxially growing the source/drain region in the reshaped first recess includes: Epitaxially grow a first semiconductor material in the reshaped first recess, wherein the first semiconductor material covers the bottom of the reshaped first recess; Epitaxially growing a second semiconductor material on the first semiconductor material, the second semiconductor material having a different composition from the first semiconductor material; and A third semiconductor material is epitaxially grown on the second semiconductor material, and the third semiconductor material has a different composition from the second semiconductor material. A method for forming a semiconductor device includes: Patterning a substrate to form a strip, the strip including a first semiconductor material; An isolation region is formed along the sidewall of the strip, and an upper portion of the strip extends above the top surface of the isolation region; Forming a dummy structure along the sidewall and top surface of the upper part of the strip; Performing a first etching process on an exposed portion of the upper portion of the strip to form a first notch, and the exposed portion of the strip is exposed by the dummy structure; After performing the first etching process, a second etching process is used to reshape the first notch to have a V-shaped bottom surface, wherein the second etching process is opposite to a second crystal plane having a second crystal orientation The process is selective to a first crystal plane having a first crystal orientation; and A source/drain region is epitaxially grown in the reshaped first recess. According to the manufacturing method of the semiconductor device described in claim 8, wherein the second etching process has a lower etching rate than the first etching process. According to the manufacturing method of the semiconductor device described in claim 8, wherein the V-shaped bottom surface includes intersecting (111) crystal planes. According to the manufacturing method of the semiconductor device described in claim 8, wherein the first etching process includes a first plasma etching process using a first etching gas, and wherein the second etching process includes using a process different from the A second plasma etching process with a first etching gas and a second etching gas. According to the method of manufacturing a semiconductor device as described in claim 11, the second etching gas includes H ₂ . According to the method of manufacturing a semiconductor device described in claim 11, wherein the second plasma etching process forms a plasma including hydrogen radicals. According to the method of manufacturing a semiconductor device described in claim 8, wherein after the second etching process is performed, an uppermost surface of the first recess extends along a third crystal plane having the second crystal orientation. The method for manufacturing a semiconductor device described in claim 8 further includes forming a spacer along the sidewall of the dummy structure, wherein after the second etching process is performed, the second etching process does not remove the second etching process A part of a semiconductor material adjacent to the bottom surface of the spacer. A semiconductor device including: A fin located above a substrate, wherein a first sidewall surface at the bottom of the fin extends along a crystal plane of a first crystal orientation; An isolation area adjacent to the fin; A gate structure extending along the sidewall of the fin and above the top surface of the fin; A gate spacer laterally adjacent to the gate structure; and An epitaxial region is adjacent to the fin, and the bottom of the epitaxial region gradually shrinks to a point. The semiconductor device described in claim 16, wherein the bottom of the epitaxial region is tapered along the crystal plane of the first crystal direction. In the semiconductor device described in claim 16, wherein the widest part of the epitaxial region has a curved profile. According to the semiconductor device described in claim 16, wherein the widest part of the epitaxial region is between the top surface of the epitaxial region and the bottom of the epitaxial region. The semiconductor device described in claim 16, wherein the epitaxial region includes a first material, a second material above the first material, and a third material above the second material, wherein the first material The material, the second material and the third material all have different material compositions.

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