TWI763530B - Probe card testing device - Google Patents

Abstract

A probe card testing device includes a first sub-circuit board, a second sub-circuit board, a connecting structure layer, a fixing plate, a probe head and a plurality of conductive probes. The first sub-circuit board is electrically connected to the second sub-circuit board by the connecting structure layer. The fixing plate is disposed on the second sub-circuit board and includes an opening and a containing groove. The opening penetrates the fixing plate and exposes a plurality of pads on the second sub-circuit board. The containing groove is located on a side of the fixing plate relatively far away from the second sub-circuit board and communicated with the opening. The probe head is disposed in the contacting groove of the fixing plate. The conductive probes are set on the probe head and in the opening of the fixing plate. On end of the conductive probes corresponds to the pads, respectively.

Description

Probe Card Test Device

The present invention relates to a test device, and more particularly, to a probe card test device.

The current probe card testing device includes a test printed circuit board, a space transformer and a test probe head, wherein the space transformer is located between the test printed circuit board and the test probe head, and the space transformer passes through ball grid array to connect to the test printed circuit board. Here, the ball material of the ball grid array is, for example, soft solder. In addition, in order to increase the structural reliability, underfill can also be filled between the space transformer and the test printed circuit board to cover the ball grid array. However, the above-mentioned probe card testing device cannot effectively reduce the cost and simplify the process steps because it needs to use solder and primer, and there is also a problem of alignment accuracy between the test probe head and the test printed circuit board. In addition, as the pitch of the test chip-pads on the wafer is getting smaller and smaller, the pitch of the pads on the space transformer is getting smaller and smaller.

The present invention provides a probe card testing device, which does not need to use solder and primer, can reduce costs, and has better structural reliability.

The probe card testing device of the present invention includes a first sub-circuit board, a second sub-circuit board, a connection structure layer, a fixing plate, a probe head and a plurality of conductive probes. The second sub-circuit board is disposed on one side of the first sub-circuit board. The connection structure layer is disposed between the first sub-circuit board and the second sub-circuit board. The first sub-circuit board is electrically connected with the second sub-circuit board through the connection structure layer. The fixing board is arranged on the second sub-circuit board. The fixing plate includes an opening and an accommodating groove. The opening penetrates through the fixing board and exposes a plurality of contact pads on the second sub-circuit board. The accommodating groove is located on a side of the fixing plate relatively far away from the second sub-circuit board and communicates with the opening. The probe head is arranged in the accommodating groove of the fixing plate. The conductive probes are inserted through the probe head and located in the opening of the fixing plate. One end of the conductive probe corresponds to the contact pad respectively.

In an embodiment of the present invention, the above-mentioned first sub-circuit board includes a base material, multi-layer circuit layers, multi-layer dielectric layers, at least one first conductive via and a plurality of second conductive vias. The circuit layers and the dielectric layers are alternately arranged on opposite sides of the substrate. The first conductive via penetrates the substrate, and the second conductive via penetrates the dielectric layer. The circuit layers are electrically connected to each other through the first conductive via and the second conductive via.

In an embodiment of the present invention, the above-mentioned first sub-circuit board further includes two solder resist layers, which are respectively disposed on the two outermost circuit layers among the circuit layers, and partially expose the two circuit layers.

In an embodiment of the present invention, the above-mentioned second sub-circuit board further includes a multi-layer circuit layer, a multi-layer dielectric layer, and a plurality of conductive vias. The circuit layers and the dielectric layers are arranged alternately. The conductive via penetrates through the dielectric layer and is electrically connected to the circuit layer and the pad. At least one of the wiring layers includes a plurality of thin wirings.

In an embodiment of the present invention, the above-mentioned second sub-circuit board further includes a circuit structure layer, a connection layer, and a reconfiguration circuit layer. The wiring structure layer includes a multi-layer wiring layer, a multi-layer first dielectric layer, and a plurality of first conductive vias. The circuit layers and the first dielectric layers are alternately arranged, and the first conductive vias penetrate through the first dielectric layers and are electrically connected to the circuit layers. The connection layer includes a dielectric body and at least one second conductive through hole, and the second conductive through hole penetrates the dielectric body. The reconfiguration line layer includes multi-layer re-configuration lines, multi-layer second dielectric layers, a plurality of third conductive vias and pads. The reconfiguration lines are alternately arranged with the second dielectric layer. The third conductive via penetrates the second dielectric layer and is electrically connected to the reconfiguration line and the pad. The second conductive via of the connection layer electrically connects the circuit layer of the circuit structure layer and the reconfiguration circuit of the reconfiguration circuit layer.

In an embodiment of the present invention, the metal line width and line spacing of the above-mentioned circuit structure layer are greater than the metal line width and line spacing of the reconfiguration circuit layer.

In an embodiment of the present invention, the above-mentioned connection structure layer includes a plurality of solder balls, which are disposed between the first sub-circuit board and the second sub-circuit board separately from each other.

In an embodiment of the present invention, the above-mentioned connecting structure layer includes a dielectric body and at least one conductive through hole, and the conductive through hole penetrates the dielectric body.

In an embodiment of the present invention, the diameter of the accommodating groove of the fixing plate is larger than the diameter of the opening.

In an embodiment of the present invention, the above-mentioned probe head has a first surface and a second surface opposite to each other. The first surface faces the contact pad, the fixing plate has a configuration surface, and the accommodating groove is located on the configuration surface. There is a height difference between the configuration surface and the second surface.

In an embodiment of the present invention, the edge of the above-mentioned fixing board is cut to be aligned with the edge of the first sub-circuit board, the edge of the second sub-circuit board, and the edge of the connection structure layer.

In an embodiment of the present invention, the above-mentioned first sub-circuit board is a multilayer circuit board, and the second sub-circuit board is a reconfigured circuit substrate.

In an embodiment of the present invention, the metal line width and line spacing of the first sub-circuit board are larger than the metal line width and line spacing of the second sub-circuit board.

Based on the above, in the design of the probe card testing device of the present invention, the fixing board is arranged on the second sub-circuit board, the probe head is arranged in the accommodating groove of the fixing board, and the conductive probes are set at The probe head is located in the opening of the fixing plate, wherein one end of the conductive probe corresponds to the contact pad of the second sub-circuit board respectively. Therefore, the probe card test device of the present invention does not need to use solder and primer, which can effectively reduce the manufacturing cost of the probe card test device, and the probe head is fixed in the accommodating groove without the probe head and the circuit. Alignment accuracy between boards. In addition, since no solder is used, the bonding yield between the first sub-circuit board, the second sub-circuit board and the connection structure layer can be effectively improved, thereby improving the structural reliability of the probe card testing device of the present invention.

In order to make the above-mentioned features and advantages of the present invention more obvious and easy to understand, the following embodiments are given and described in detail with the accompanying drawings as follows.

FIG. 1 is a schematic cross-sectional view of a probe card testing apparatus according to an embodiment of the present invention. Referring to FIG. 1 , in this embodiment, the probe card testing device 10 includes a first sub-circuit board 100 , a second sub-circuit board 200 , a connection structure layer 300 , a fixing board 400 , and a probe head 500 and a plurality of conductive probes 600 . The second sub-circuit board 200 is disposed on one side of the first sub-circuit board 100 . The connection structure layer 300 is disposed between the first sub-circuit board 100 and the second sub-circuit board 200 , and the first sub-circuit board 100 is electrically connected to the second sub-circuit board 200 through the connection structure layer 300 . That is to say, the connection between the first sub-circuit board 100 and the second sub-circuit board 200 does not need to pass through solder and primer, and because no solder is used, the first sub-circuit board 100 and the second sub-circuit board can be effectively improved. Bonding yield between the board 200 and the connection structure layer 300 .

Furthermore, the fixing board 400 of this embodiment is disposed on the second sub-circuit board 200 , wherein the fixing board 400 includes an opening 412 and an accommodating groove 414 . The opening 412 penetrates through the fixing board 400 and exposes the plurality of pads 252 on the second sub-circuit board 200 . The accommodating groove 414 is located on a side of the fixing board 400 relatively far away from the second sub-circuit board 200 and communicates with the opening 412 . The probe head 500 is disposed in the accommodating groove 414 of the fixing plate 400 , and the conductive probe 600 is disposed through the probe head 500 and is located in the opening 412 of the fixing plate 400 , wherein one end of the conductive probe 600 is respectively in contact with the connection. pad 252. In other words, the probe head 500 of this embodiment is positioned on the second sub-circuit board 200 through the accommodating groove 414 of the fixing plate 400 , so no solder and primer are used, and the probe head 500 and the fixing plate can be effectively improved The assembly yield between 400 and the probe head 500 and the second sub-circuit board 200 does not have the problem of alignment accuracy.

Furthermore, in this embodiment, the first sub-circuit board 100 includes a base material 110 , multi-layer circuit layers 120 , 130 , 140 , 150 , 160 , 170 , multi-layer dielectric layers 115 , and at least one first conductive contact holes (a first conductive via 123 is schematically shown) and a plurality of second conductive vias 125 . The circuit layers 120 , 130 , 140 , 150 , 160 , 170 and the dielectric layer 115 are alternately arranged on opposite sides of the substrate 110 . The first conductive via 123 penetrates the substrate 110 , and the second conductive via 125 penetrates the dielectric layer 115 . The circuit layers 120 , 130 , 140 , 150 , 160 , and 170 are electrically connected to each other through the first conductive via 123 and the second conductive via 125 . Here, the wiring layers 120 , 130 are electrically connected to each other through the first conductive via 123 , and the wiring layers 120 , 140 , 160 and the wiring layers 130 , 150 , 170 are electrically connected to each other via the second conductive via 125 . Furthermore, the first sub-circuit board 100 of this embodiment further includes two solder mask layers 180 and 190 , which are respectively disposed on the two outermost circuit layers 160 and 170 of the circuit layers 120 , 130 , 140 , 150 , 160 and 170 , respectively. , and part of the two circuit layers 160 and 170 are exposed. In short, the first sub-circuit board 100 in this embodiment is embodied as a multi-layer circuit board, but not limited thereto.

Referring again to FIG. 1 , the second sub-circuit board 200 of this embodiment further includes multilayer circuit layers 220 , 230 , 240 , a multilayer dielectric layer 210 , and a plurality of conductive vias 225 . The circuit layers 220 , 230 , 240 and the dielectric layer 210 are arranged alternately, and the pads 252 are located on the outermost dielectric layer 210 . The conductive vias 225 penetrate through the dielectric layer 210 and are electrically connected to the circuit layers 220 , 230 , 240 and the pads 252 . At least one of the circuit layers 220 , 230 and 240 (the circuit layers 230 and 240 are schematically shown) includes a plurality of thin circuits 232 and 242 . In short, the second sub-circuit board 200 is embodied as a reconfigured circuit substrate, wherein the metal line width and line spacing of the first sub-circuit board 100 are larger than those of the second sub-circuit board 200 . Furthermore, the distance between the pads 252 on the second sub-circuit board 200 is much smaller than the pads on the first sub-circuit board 100 (ie, where the solder mask layers 180 and 190 are exposed to the circuit layers 160 and 170 respectively). spacing between.

Furthermore, the connection structure layer 300 of this embodiment includes a dielectric body 310 and at least one conductive via (two conductive vias 320 are schematically shown), and the conductive via 320 penetrates the dielectric body 310 . Here, the material of the dielectric body 310 includes a prepreg (PP), and the material of the conductive via 320 is, for example, a conductive metal glue, which has the effect of conducting electricity and heat conduction, and is suitable for bonding with any metal material.

It should be noted that, the first sub-circuit board 100 is electrically connected to the second sub-circuit board 200 through the connection structure layer 300 through a thermocompression bonding process. Specifically, during thermocompression bonding, the circuit layer 170 of the first sub-circuit board 100 and the circuit layer 220 of the second sub-circuit board 200 directly contact the surface of the dielectric body 310 and press the conductive via 320 to deform it. At this time, since the dielectric body 310 is not fully cured and has flexibility and viscosity, the circuit layer 170 and the circuit layer 220 can be bonded together and squeezed into the exposed surface of the solder mask layer 190 . After the lamination and curing, the dielectric body 310 of the connection structure layer 300 changes from the B-stage state to the C-stage state, which means that the connection structure layer 300 is in a fully cured state, and the first sub-circuit board 100 and the second sub-circuit board are in a state of being completely cured. 200 and the connecting structure layer 300 are firmly bonded together. At this stage, the circuit layer 170 of the first sub-circuit board 100 is electrically connected to the circuit layer 220 of the second sub-circuit board 200 through the conductive vias 320 of the connection structure layer 300 . In this way, no solder and primer are used, so the bonding yield between the first sub-circuit board 100 , the second sub-circuit board 200 and the connection structure layer 300 can be effectively improved, thereby improving the probe card test of this embodiment. Structural reliability of the device 10 .

Referring to FIG. 1 again, the probe head 500 of the present embodiment is disposed in the accommodating groove 414 of the fixing plate 400 , and the conductive probes 600 are set through the probe head 500 and located in the opening 412 of the fixing plate 400 . Here, the probe head 500 has a first surface 502 and a second surface 504 opposite to each other. The first surface 502 faces the contact pad 252 , and the fixing plate 400 has a configuration surface 402 , and the accommodating groove 414 is located on the configuration surface 402 . In particular, there is a height difference H between the configuration surface 402 of the fixing plate 400 and the second surface 504 of the probe head 500 , which can prevent the test wafer 20 from directly touching the configuration surface 402 of the fixing plate 400 to affect the electrical test. result. Preferably, the caliber W2 of the accommodating groove 414 of the fixing plate 400 is larger than the caliber W1 of the opening 412, wherein the caliber W2 of the accommodating groove 414 is the length of the probe head 500, and the depth of the accommodating groove 414 is smaller than that of the probe head. 500 , so that the second surface 504 of the probe head 500 is higher than the arrangement surface 402 of the fixing plate 400 . In addition, the edge of the fixing board 400 in this embodiment is substantially aligned with the edge of the first sub-circuit board 100 , the edge of the second sub-circuit board 200 and the edge of the connection structure layer 300 .

It must be noted here that the following embodiments use the element numbers and part of the contents of the previous embodiments, wherein the same numbers are used to represent the same or similar elements, and the description of the same technical contents is omitted. For the description of the omitted part, reference may be made to the foregoing embodiments, and repeated descriptions in the following embodiments will not be repeated.

2 is a schematic cross-sectional view of a probe card testing apparatus according to another embodiment of the present invention. Please refer to FIG. 1 and FIG. 2 at the same time. The probe card testing device 10a of the present embodiment is similar to the probe card testing device 10 described above. The difference between the two is that the second sub-circuit board 700 of the present embodiment is different from the above-mentioned probe card testing device 10. The second sub-circuit board 200 . Specifically, in this embodiment, the second sub-circuit board 700 further includes a circuit structure layer 710 , a connection layer 720 and a reconfiguration circuit layer 730 . The wiring structure layer 710 includes a multi-layer wiring layer 712 , a multi-layer first dielectric layer 714 and a plurality of first conductive vias 716 . The circuit layers 712 and the first dielectric layers 714 are alternately arranged, and the first conductive vias 716 penetrate through the first dielectric layer 714 and are electrically connected to the circuit layers 712 . The connection layer 720 includes a dielectric body 722 and at least one second conductive via 724 , and the second conductive via 724 penetrates the dielectric body 722 . The reconfiguration line layer 730 includes a multi-layer reconfiguration line 732 , a multi-layer second dielectric layer 734 , a plurality of third conductive vias 736 and pads 738 . The reconfiguration lines 732 and the second dielectric layers 734 are alternately arranged. The third conductive vias 736 penetrate through the second dielectric layer 734 and are electrically connected to the reconfiguration lines 732 and the pads 738 . The second conductive vias 724 of the connection layer 720 are electrically connected to the circuit layer 712 of the circuit structure layer 710 and the reconfiguration circuit 732 of the reconfiguration circuit layer 730 , and one end of the conductive probe 600 corresponds to the contact pad 738 respectively.

In other words, the second sub-circuit board 700 of this embodiment is a composite circuit board, which does not use solder and primer, but connects the circuit structure layer 710 and the reconfiguration circuit layer 730 through the connection layer 720 . Therefore, the bonding yield between the circuit structure layer 710 , the connection layer 720 and the reconfigured circuit layer 730 can be effectively improved, thereby improving the structural reliability of the probe card testing apparatus 10 a of the present embodiment. In addition, the spacing between the plurality of pads on the reconfigured circuit layer 730 is much smaller than the spacing between the multiple pads on the circuit structure layer 710, that is, the metal line width and line spacing of the circuit structure layer 710 are larger than those of the reconfigured circuit layer 710. The metal line width and line spacing of the circuit layer 730 .

3 is a schematic cross-sectional view of a probe card testing device according to another embodiment of the present invention. Please refer to FIG. 2 and FIG. 3 at the same time. The probe card testing device 10b of the present embodiment is similar to the probe card testing device 10a described above. The difference between the two is that the structure of the connection structure layer 800 of the present embodiment is different from the above-mentioned probe card testing device 10a. The structure of the connection structure layer 300 . In detail, the connection structure layer 800 includes a plurality of solder balls 810 which are disposed between the first sub-circuit board 100 and the second sub-circuit board 700 separately from each other, wherein the solder balls 810 are electrically connected to the circuits of the first sub-circuit board 100 Layer 170 and the circuit layer 712 of the circuit structure layer 710 of the second sub-circuit board 700 .

To sum up, in the design of the probe card testing device of the present invention, the fixing board is arranged on the second sub-circuit board, the probe head is arranged in the accommodating groove of the fixing board, and the conductive probes pass through it. The probe head is set to be located in the opening of the fixing plate, wherein one end of the conductive probe corresponds to the contact pad of the second sub-circuit board respectively. Therefore, the probe card test device of the present invention does not need to use solder and primer, which can effectively reduce the manufacturing cost of the probe card test device, and the probe head is fixed in the accommodating groove without the probe head and the circuit. Alignment accuracy between boards. In addition, since no solder is used, the bonding yield between the first sub-circuit board, the second sub-circuit board and the connection structure layer can be effectively improved, thereby improving the structural reliability of the probe card testing device of the present invention.

Although the present invention has been disclosed above by the embodiments, it is not intended to limit the present invention. Anyone with ordinary knowledge in the technical field can make some changes and modifications without departing from the spirit and scope of the present invention. Therefore, The protection scope of the present invention shall be determined by the scope of the appended patent application.

10, 10a, 10b: probe card testing device 20: Test Wafer 100: The first sub-circuit board 110: Substrate 115: Dielectric layer 120, 130, 140, 150, 160, 170: circuit layer 123: first conductive via 125: Second conductive via 180, 190: Solder mask 200, 700: Second sub-circuit board 210: Dielectric Layer 220, 230, 240, 712: circuit layer 225: Conductive Vias 232, 242: Thin lines 252, 738: pads 300: Connect Structural Layers 310: Dielectric 320: Conductive Via 400: Fixed plate 402: Configuration plane 412: Opening 414: accommodating slot 500: Probe head 502: First Surface 504: Second Surface 600: Conductive Probe 710: Line structure layer 714: First Dielectric Layer 716: first conductive via 720: Connection Layer 722: Dielectric 724: Second conductive via 730: Reconfigure line layer 732: Reconfiguration line 734: Second Dielectric Layer 736: Third conductive via 810: Solder Ball H: height difference W1, W2: Diameter

FIG. 1 is a schematic cross-sectional view of a probe card testing apparatus according to an embodiment of the present invention. 2 is a schematic cross-sectional view of a probe card testing apparatus according to another embodiment of the present invention. 3 is a schematic cross-sectional view of a probe card testing device according to another embodiment of the present invention.

10: Probe card test device

20: Test Wafer

100: The first sub-circuit board

110: Substrate

115: Dielectric layer

120, 130, 140, 150, 160, 170: circuit layer

123: first conductive via

125: Second conductive via

180, 190: Solder mask

200: Second sub-circuit board

210: Dielectric Layer

220, 230, 240: circuit layer

225: Conductive Vias

232, 242: Thin lines

252: Pad

300: Connect Structural Layers

310: Dielectric

320: Conductive Via

400: Fixed plate

402: Configuration plane

412: Opening

414: accommodating slot

500: Probe head

502: First Surface

504: Second Surface

600: Conductive Probe

H: height difference

W1, W2: Diameter

Claims (13)

A probe card testing device, comprising: a first sub-circuit board; a second sub-circuit board, disposed on one side of the first sub-circuit board; a connection structure layer disposed between the first sub-circuit board and the second sub-circuit board, and the first sub-circuit board is electrically connected to the second sub-circuit board through the connection structure layer; A fixing board is disposed on the second sub-circuit board, and the fixing board includes an opening and an accommodating groove, wherein the opening penetrates the fixing board and exposes a plurality of pads on the second sub-circuit board, and the accommodating groove is located on a side of the fixing plate relatively far away from the second sub-circuit board and communicates with the opening; a probe head disposed in the accommodating groove of the fixing plate; and A plurality of conductive probes are disposed through the probe head and located in the opening of the fixing plate, wherein one end of the conductive probes respectively contacts the pads. The probe card testing device according to claim 1, wherein the first sub-circuit board comprises a base material, a multi-layer circuit layer, a multi-layer dielectric layer, at least one first conductive via and a plurality of second conductive vias, The circuit layers and the dielectric layers are alternately arranged on opposite sides of the substrate, the at least one first conductive via penetrates the substrate, the second conductive vias penetrate the dielectric layers, And the circuit layers are electrically connected to each other through the at least one first conductive via and the second conductive vias. The probe card testing device as claimed in claim 2, wherein the first sub-circuit board further comprises: The two solder resist layers are respectively disposed on the two outermost circuit layers among the circuit layers, and part of the two circuit layers are exposed. The probe card testing device as claimed in claim 1, wherein the second sub-circuit board further comprises a multi-layer circuit layer, a multi-layer dielectric layer and a plurality of conductive vias, the circuit layers and the dielectric layers are arranged alternately , and the conductive vias penetrate through the dielectric layers and are electrically connected to the circuit layers and the pads, and at least one of the circuit layers includes a plurality of thin circuits. The probe card testing device according to claim 1, wherein the second sub-circuit board further comprises: A circuit structure layer includes multilayer circuit layers, multilayer first dielectric layers and a plurality of first conductive vias, the circuit layers and the first dielectric layers are alternately arranged, and the first conductive vias pass through the first dielectric layers are electrically connected to the circuit layers; a connection layer including a dielectric body and at least one second conductive via, and the at least one second conductive via penetrates the dielectric body; and A reconfiguration line layer includes multi-layer re-configuration lines, multi-layer second dielectric layers, a plurality of third conductive vias and the pads, the re-configuration lines and the second dielectric layers are alternately arranged, and the The third conductive vias penetrate through the second dielectric layers and are electrically connected to the reconfiguration lines and the pads, wherein the at least one second conductive via of the connection layer is electrically connected to the circuit structure layer the circuit layers and the reconfiguration circuits of the reconfiguration circuit layer. The probe card testing device according to claim 5, wherein the metal line width and line spacing of the circuit structure layer are greater than the metal line width and line spacing of the reconfiguration circuit layer. The probe card testing device according to claim 1, wherein the connection structure layer includes a plurality of solder balls, which are disposed between the first sub-circuit board and the second sub-circuit board separately from each other. The probe card testing device according to claim 1, wherein the connection structure layer comprises a dielectric body and at least one conductive through hole, and the at least one conductive through hole penetrates the dielectric body. The probe card testing device according to claim 1, wherein the diameter of the accommodating groove of the fixing plate is larger than the diameter of the opening. The probe card testing device as claimed in claim 1, wherein the probe head has a first surface and a second surface opposite to each other, the first surface faces the pads, and the fixing plate has a configuration surface, the accommodating groove is located on the configuration surface, and there is a height difference between the configuration surface and the second surface. The probe card testing device as claimed in claim 1, wherein the edge of the fixing board is aligned with the edge of the first sub-circuit board, the edge of the second sub-circuit board and the edge of the connection structure layer. The probe card testing device of claim 1, wherein the first sub-circuit board is a multilayer circuit board, and the second sub-circuit board is a reconfigured circuit substrate. The probe card testing device according to claim 12, wherein the metal line width and line spacing of the first sub-circuit board are greater than the metal line width and line spacing of the second sub-circuit board.

Images