TWI762932B - Memory management and erasure decoding for a memory device - Google Patents

Abstract

Memory management and erasure decoding for a memory device are described. A memory device may identify charge leakage associated with one or more memory cells, and may determine whether to invert a logic state stored by one or more memory cells to improve the likelihood that the memory cells are read properly. In some examples, the memory device may store an indication that the complement of the detected logic state was written, which may correspond to one memory cell or a set of memory cells. In some examples, a memory device may be configured to identify conditions associated with an erasure, or an otherwise indeterminate logic state, which may be used to enhance aspects of error handling operations, including those that may be performed at the memory device or a host device (e.g., error handling operations performed at a memory controller external to the memory device).

Description

Memory management and delete decoding for memory devices

The technical field relates to memory management and delete decoding for a memory device.

Memory devices are widely used to store information in various electronic devices (eg, computers, wireless communication devices, cameras, digital displays, etc.). Information is stored by programming different states of a memory device. For example, binary devices most commonly store one of two states, usually denoted as a logic 1 or a logic 0. In other devices, more than two states may be stored. To access the stored information, a component of the device can read or sense at least one state stored in the memory device. To store information, a component of the device may write or program state in a memory device.

Various types of memory devices exist, including magnetic disk drives, random access memory (RAM), read only memory (ROM), dynamic RAM (DRAM), synchronous dynamic RAM (SDRAM), ferroelectric RAM (FeRAM), Magnetic RAM (MRAM), Resistive RAM (RRAM), Flash memory, Phase Change Memory (PCM), etc. Memory devices can be volatile or non-volatile. Non-volatile memory (eg, FeRAM) can maintain its stored logic state for extended periods of time even without an external power source. Volatile memory devices (eg, DRAM) can lose their stored state when disconnected from an external power source. FeRAM may be able to achieve a density similar to volatile memory but with non-volatile properties due to the use of a ferroelectric capacitor as a storage device.

This patent application claims U.S. Patent Application Serial No. 16/441,722 to Visconti, filed June 14, 2019, and entitled "MEMORY MANAGEMENT FOR CHARGE LEAKAGE IN A MEMORY DEVICE" and filed April 3, 2020 Priority to US Patent Application Serial No. 16/840,286 to Fackenthal et al. for "ERASURE DECODING FOR A MEMORY DEVICE," each of which is assigned to its assignee and each of which is The entire contents are expressly incorporated into this case for reference.

In some memory devices, charge leakage or other phenomena can negatively affect a memory device's ability to determine a logic state stored by a memory cell. For example, a charge leakage in a memory device can result in the detection or identification of a charge transfer that is larger than a charge transfer originally associated with a particular logic state previously stored in a memory cell, such as detecting A voltage on a signal line is detected to be lower than a corresponding voltage in the absence of charge leakage. In some instances, charge leakage can reduce a read margin of a memory device, or can be associated with reading an incorrect logic state from a memory cell (eg, with a memory cell already stored in a memory cell) is in a different logical state than a logical state). Such effects can be associated, for example, with capacitive memory technology or other charge storage memory technologies in which memory cells can store different amounts of charge or different polarities of polarization to store different logic states.

In one example, the memory cells of a memory device can be configured to store (eg, in a capacitive memory element, in a ferroelectric memory element) associated with a first amount of charge transfer is associated with a first logic state or a second logic state associated with a second charge transfer amount, or both, that is greater than the first charge transfer amount. The first amount of charge transfer may refer to or correspond to a transfer of charge to and from a memory cell storing the first logic state, a first amount of charge stored at a memory cell during a read operation, or A first charge polarity, or first amount of charge transfer, stored at a memory cell may generally correspond to a relatively low current logic state.

The second amount of charge transfer may refer to or correspond to a charge transfer amount to and from a memory cell storing a second logic state, a second amount of charge stored at a memory cell during a read operation Either stored at a memory cell at a second charge polarity, or the second charge transfer amount may generally correspond to a relatively high current logic state. During a read operation on a memory cell storing the first logic state, a sensing element may detect or identify the first charge transfer amount to determine that the memory cell stores the first logic state. During a read operation on a memory cell storing the second logic state, a sensing element may detect or identify the second charge transfer amount to determine that the memory cell stores the second logic state.

In the presence of charge leakage, for example, a memory device (eg, a sensing element within the memory device) may detect a charge higher than the charge transfer normally associated with a particular logic state Transfer, the higher charge transfer may represent in part charge transfer from the memory cell storing the logic state and in part charge leakage. In other words, charge leakage can be superimposed on the charge transfer normally associated with a particular logic state (eg, associated with a read operation of the logic state). In some cases, the superimposed charge leakage may reduce the read margin for reading a memory cell storing the first logic state (eg, normally associated with a relatively low charge transfer), or may Causes the memory device to incorrectly detect the second logic state from a memory cell written with the first logic state (eg, associated with a higher charge transfer during a read operation).

In some cases, a memory device can identify a charge leakage associated with one or more memory cells or access lines, and can determine whether to intentionally store one or more memories in the presence of charge leakage A logic state stored by the voxel is inverted to increase the likelihood of properly detecting the logic state. For example, a memory device may determine the data stored by a memory cell during an access operation (eg, during a read portion of an access operation, during a write portion of an access operation). A logic state and also detects whether a memory cell or associated access line is associated with a charge leak (eg, during a leak detection portion of an access operation).

In some cases, a memory device may determine to determine one's complement of the determined logic state (eg, a read or write with an access operation based in part on detected charge leakage or some other phenomenon) A different logic state, a complementary logic state, an inverted logic state, an inverse logic state) associated with the portion are written to the memory cell. In some examples, determining the complement of the write logic state may be associated with a first amount of charge transfer based on the detected logic state, and the complement of the logic state is associated with a second amount of charge transfer, The second charge transfer amount is greater than the first charge transfer amount. In some cases, the memory device may then write the complement of the logic state to the memory cell (eg, during an overwrite portion of an access operation).

In addition to writing a complementary logic state to a memory cell, the memory device can also store an indication that the complement of the detected logic state was written, such as a bit flip indication, where this indication May correspond to a set of one or more memory cells, the set of one or more memory cells including memory cells for which an associated charge leakage is detected. For example, a memory device may store such an indication to track whether a memory cell or group of memory cells (eg, a row or page) has been programmed with a direct logic state or a complementary logic state (eg, once reversed). This indication can be used in a subsequent read operation to properly interpret the changed logical state of one or more memory cells when reading information from the memory device (eg, directly interpreting the memory cell's storage or invert or otherwise alter the interpretation of the logical state stored by the memory cell).

Thus, a detected charge leakage or other phenomenon in a memory device can be accounted for by changing a logic state stored by a memory cell (eg, during a rewrite operation), which can avoid incorrectly Interpreting the information stored in the memory cells may avoid or reduce the effect of narrowing the read margin. In some instances, this technique can support improved performance of a memory device, such as extended cycling to find fault (CTF) performance, relaxed bit error rate (BER) requirements, and other benefits.

In some memory devices, deletions or other actions can cause an information state (eg, logical state) in which it is written to or stored by a memory cell to be indeterminate (eg, a subsequent storage take a condition during operation). For example, in some cases a memory device may be unable to distinguish between a memory cell storing one logic state or another (eg, a memory cell storing a logic 1 or a logic 0), or A memory device may read one logic state when reading a memory cell, but a different logic state is written to the memory cell (eg, detect during a read operation on a memory cell A logic 0 was detected, but the memory cell was written with a logic 1). In some instances, a memory cell with an indeterminate logic state may cause an error in a corresponding codeword that needs to be corrected (eg, by an error correction code (ECC) or ECC engine), or may The number of errors that cause a corresponding codeword exceeds an error correction capability (eg, the error correction capability of a memory device, the error correction capability of a host device coupled to the memory device). Conditions such as these can degrade the performance of a memory device or a host device that uses the memory device for information storage, or can cause a malfunction in the operation of the memory device or one of the host devices.

In some examples, a memory device may be configured to identify a memory cell, or information location of a corresponding codeword associated with a deletion generated during an access operation, to indicate the condition of a possible deletion, or A condition associated with an indeterminate information state. In some examples, a memory device can be configured to identify information indicative of charge leakage (eg, charge leakage through a memory cell, charge leakage through an access line associated with an access operation) In some cases, charge leakage may be associated with sensing a higher probability of a memory cell storing a particular logic state (eg, degrading or eliminating a read margin associated with reading a logic state). In some examples, a memory device may be configured to recognize that a signal associated with reading a memory cell is at a first threshold corresponding to a first information state (eg, a signal near the limit value indicates a logic 0) and a second threshold value corresponding to a second information state (eg, the signal threshold value indicates a logic 1) within a range, and the signal within this range An uncertainty that may instruct the memory cell to store the first information state or the second information state.

Identifying conditions associated with an indeterminate information state can enhance aspects of error detection or error correction operations, including operations that may be performed at a memory device or a host device (eg, outside a memory device) error correction operation performed at a memory controller). For example, a memory device may identify one or more memory cells, one or more access lines, or one or more information locations of a codeword, all of which are associated with an indeterminate information state. A corresponding codeword (eg, generated during a read operation) may include certain information locations with a detected or determined information state (eg, a logic 0 or logic 1) and with an indeterminate information state or Certain information locations are not assigned information states (eg, a logic X, an empty logic state). An error detection operation or an error correction operation may be performed on one or more codewords (eg, speculative codewords) in which the information location associated with an indeterminate or unassigned logic state is replaced or assigned a The respective assumed information state (eg, a logical 0 for a logical X, a logical 1 for a logical X). By identifying the information location to which this assumed information state will be assigned, an error detection or an error correction can be enhanced to handle indeterminate states or combinations of indeterminate states and other error conditions (eg, in unknown memory cells). or error in the information state sensed at the location of a codeword).

The features of the present invention are first described in the context of a memory device, circuitry, and memory cell characteristics with reference to FIGS. 1 to 3 . Features of the present invention are further described with reference to FIGS. 4-5 in the context of an exemplary circuit and corresponding access operations and with reference to FIG. 6 in the context of a general memory management method for charge leakage in a memory device . Features of the present invention are further described in the context of an example of read characteristics and an erasure decoding method with reference to FIGS. 7-8 . These and other features of the present invention are further illustrated and described with reference to equipment diagrams and flow charts related to memory management and delete decoding of a memory device described with reference to FIGS. 9-13.

1 illustrates one example of a memory device 100 that supports memory management and delete decoding according to the examples disclosed herein. The memory device 100 may also be referred to as an electronic memory device. The memory device 100 may include memory cells 105 that can be programmed to store different logical states. In some cases, a memory cell 105 can be programmed to store two logic states, designated as a logic 0 and a logic 1. In some cases, a memory cell 105 can be programmed to store more than two logic states. In various examples, memory cell 105 may include a capacitive storage element, a ferroelectric storage element, a material memory element, a resistive memory element, a limiting memory element, a phase change memory element, or Other types of storage elements (eg, memory elements, charge storage elements, polarized storage elements).

A set of memory cells 105 may be part of a memory sector 110 of memory device 100 (eg, comprising an array of memory cells 105 ), where in some instances a memory sector 110 may Refers to a contiguous piece of memory cell 105 (eg, a set of contiguous elements of a semiconductor wafer). In some examples, a memory sector 110 may refer to the smallest set of memory cells 105 that can be biased during an access operation, or share a common electrical node (eg, a common plate line, The smallest set of memory cells 105 that are biased to a common voltage (a set of board lines). Although only a single memory sector 110 of memory device 100 is shown, various examples of memory devices supporting one of the techniques described may have a set of one or more memory sectors 110 . In one illustrative example, a memory device 100 may include 32 "banks" and each bank may include 32 sectors. Thus, memory device 100 according to one illustrative example may include 1,024 memory sectors 110 .

In some examples, a memory cell 105 may store an electric charge representing a programmable logic state (eg, in a capacitor, capacitive memory element, capacitive storage element). In one example, the charged and uncharged capacitors may represent two logic states, respectively. In another example, positively charged (eg, a first polarity, a positive polarity) and negatively charged (eg, a second polarity, a negative polarity) capacitors may represent two logic states, respectively. DRAM or FeRAM architectures can use this design, and the capacitors employed can include a dielectric material with linear or parapolar polarization properties as an insulator. In some examples, different charge levels of a capacitor may represent different logic states, and in some examples, different charge levels of a capacitor may support more than two logic states in a respective memory cell 105 . In some examples, such as FeRAM architectures, a memory cell 105 may include a ferroelectric capacitor having a ferroelectric material as an insulating (eg, non-conductive) layer between the terminals of the capacitor. Different levels or different polarization polarities of a ferroelectric capacitor can represent different logic states (eg, supporting two or more logic states in a respective memory cell 105). Ferroelectric materials have nonlinear polarization properties, including those discussed in more detail with reference to Figures 3A and 3B.

In some examples, a memory cell 105 may include or otherwise be associated with a configurable material, which may be referred to as a material memory element, a material storage component, a material part, etc. Configurable materials can have properties or properties (eg, material states) that represent (eg, correspond to) one or more variable and configurable properties of different logical states. For example, a configurable material can take on different forms, different atomic configurations, different degrees of crystallinity, different atomic distributions, or otherwise maintain different properties that can be used to represent one logical state or another. In some examples, these characteristics can be detected or distinguished from a different resistance, a different threshold, and a logical state written to or stored by the configurable material during a read operation to identify voltage or other properties.

In some cases, a configurable material of a memory cell 105 may be associated with a threshold voltage. For example, when a voltage greater than the threshold voltage is applied across the memory cell 105, current can flow through the configurable material, and when a voltage less than the threshold voltage is applied across the memory cell 105 At a voltage, current may not flow through the configurable material or may flow through the configurable material at a rate lower than some level (eg, according to a leakage rate). Thus, a voltage applied to a memory cell 105 can result in a different current flow or a different sensed resistance or a resistance change (eg, a finite event or switching event), depending on which one of the memory cells 105 is configurable It depends on whether the material portion is written in one logical state or the other. Thus, the magnitude of the current or other characteristics associated with the current from applying a read voltage to the memory cell 105 (eg, limit behavior, resistance collapse behavior, snapback behavior) can be used to determine writes to memory The soma cell 105 or memory cell 105 stores a logic state.

A memory device 100 may include a three-dimensional (3D) memory array in which a plurality of two-dimensional (2D) memory arrays (eg, layers, levels) are formed on top of each other. In various examples, these arrays may be divided into a set of memory sectors 110, where each memory sector 110 may be configured within a level or level, distributed across multiple levels or levels, or any combination thereof. Compared to 2D arrays, this configuration can increase the number of memory cells 105 that can be placed or formed on a single die or substrate, which in turn can reduce production costs or improve the performance of a memory device 100, Alternatively, the production cost can be reduced and the performance of a memory device 100 can be improved. The layers or levels may be separated by an electrically insulating material. Each level or level may be aligned or positioned such that the memory cells 105 may be substantially aligned with each other across each level, forming a stack of memory cells 105 . In the example of memory device 100, each column of memory cells 105 of memory sector 110 may be associated with one of a set of first access lines 120 (eg, a word line (WL), such as WL ₁ -WL one of _M , a select line), and each row of memory cells 105 may be coupled with one of a set of second access lines 130 (eg, a digit line (DL), such as among DL ₁ through DL _N ) one) coupling. In some examples, a column of memory cells 105 of a different memory sector 110 (not shown) may be different from one of the plurality of first access lines 120 (eg, different from WL1 _{- WLMM} ) A word line) is coupled, and a row of memory cells 105 of a different memory sector 110 may be connected to one of a different plurality of second access lines 130 (eg, a different digit line than DL1 _{- DLN} ) coupling. In some cases, the first access line 120 and the second access line 130 may be substantially perpendicular to each other in the memory device 100 (eg, when viewing a plane of a level of the memory device 100 as shown in FIG. 1 displayed). References to word lines and bit lines or the like are interchangeable and do not affect understanding or operation.

Typically, a memory cell 105 may be located at the intersection of an access line 120 and an access line 130 (eg, coupled to access line 120 and access line 130 , coupled to access line 120 and access line 130 ) between). This intersection may be referred to as an address of a memory cell 105 . A target or selected memory cell 105 may be a memory cell 105 located at the intersection of a energized or otherwise selected access line 120 and a energized or otherwise selected access line 130 . In other words, an access line 120 and an access line 130 may be energized or otherwise selected to access (eg, read, write, rewrite, refresh) a memory cell 105 at its intersection . Other memory cells 105 that are in electronic communication with the same access line 120 or 130 (eg, connected to the same access line 120 or 130 ) may be referred to as non-target or non-selected memory cells 105 .

In some architectures, logical storage elements (eg, a capacitive storage element, a ferroelectric storage element, a material storage element) of a memory cell 105 may be accessed by a cell selection element and a second Line 130 is electrically isolated (eg, selectively isolated), and in some instances, the cell selection element may be referred to as a switching element or a selector device of memory cell 105 or is otherwise associated with memory cell 105. Element 105 is associated. A first access line 120 may be coupled to the cell selection element (eg, via a control node or terminal of the cell selection element) and may control the cell selection element of the memory cell 105 . For example, the cell select element may be a transistor and the first access line 120 may be coupled to a gate of the transistor (eg, where a gate node of the transistor may be a control node of the transistor) . Activating the first access line 120 of a memory cell 105 can form an electrical connection or closed circuit between the logical storage element of the memory cell 105 and its corresponding second access line 130 . The second access line 130 can then be accessed to read or write to the memory cell 105 .

In some examples, the memory cells 105 of the memory sector 110 may also be connected to one of the plurality of third access lines 140 (eg, a plate line (PL), such as one of PL ₁ to PL _N ) ) coupling. Although illustrated as separate lines, in some instances the plurality of third access lines 140 may represent or be functionally equivalent to a common board line of memory sectors 110, a common board, or Other common nodes (eg, a node common to each of the memory cells 105 in the memory sector 110 ) or other common nodes of the memory device 100 . In some examples, the plurality of third access lines 140 may couple the memory cell 105 with one or more voltage sources for various sensing or writing operations, including the sensing operations described herein or write operations. For example, when a memory cell 105 employs a capacitor to store a logic state, a second access line 130 may provide access to a first terminal or a first plate of the capacitor, and a third Access line 140 may provide access to a second terminal or a second plate of the capacitor (eg, a terminal associated with an opposing plate of the capacitor opposite the first terminal of the capacitor, a second terminal of the capacitor A terminal is located on the opposite side of a capacitor). In some examples, memory cells 105 (not shown) of a different memory sector 110 may be different from one of the plurality of third access lines 140 (eg, different from one of PL ₁ -PL _N ) A group board line, a different common board line, a different common board, a different common node) are coupled.

The plurality of third access lines 140 may be coupled to a board assembly 145, which may control various operations, such as enabling one or more of the plurality of third access lines 140 or the plurality of third access lines 140 One or more of 140 are selectively coupled to a voltage source or other circuit element. Although the plurality of third access lines 140 of the memory device 100 are shown as being substantially parallel to the plurality of second access lines 130, in other examples, the plurality of third access lines 140 may be parallel to the plurality of The first access lines 120 are substantially parallel, or in any other configuration (eg, a common planar conductor, a common plane).

Although the access lines described with reference to FIG. 1 are shown as through lines between the memory cells 105 and coupling components, the access lines may include other circuit elements such as capacitors, resistors, transistors, amplifiers, voltage sources , toggle components, select components, etc., which may be used to support access operations, including those described herein. In some examples, an electrode may be coupled with a memory cell 105 and an access line 120 (eg, between memory cell 105 and an access line 120) or with a memory cell 105 and an access line 120. An access line 130 is coupled (eg, between the memory cell 105 and the access line 130). The term electrode can refer to an electrical conductor or other electrical interface between components, and in some cases can serve as an electrical contact with a memory cell 105 . An electrode may include a trace, wire, conductive line, conductive layer, conductive pad, etc. that provides a conductive path between elements or components of memory device 100 .

An access operation to a memory cell 105 may be performed by activating or selecting a first access line 120, a second access line 130, or a third access line 140 coupled to the memory cell 105 ( For example, read, write, rewrite, and refresh), performing an access operation may include applying a voltage, a charge, or a current to the respective access line. The access lines 120, 130, and 140 may be made of conductive materials such as metals (eg, copper (Cu), silver (Ag), aluminum (Al), gold (Au), tungsten (W), titanium (Ti)), Made of metal alloys, carbon or other conductive or semiconductive materials, alloys or compounds. When a memory cell 105 is selected, a resulting signal can be used to determine the logic state stored by the memory cell 105 . For example, a memory cell 105 having a capacitive memory element storing a logic state can be selected, and the resulting charge flow through an access line or the resulting voltage on an access line can be detected to determine the The programmed logic state stored by memory cell 105 .

Access to memory cells 105 may be controlled by a column of components 125 (eg, a column of decoders), a row of components 135 (eg, a row of decoders), or a board component 145 (eg, a board driver), or a combination thereof. For example, a column of components 125 may receive a column address from the memory controller 170 and enable the appropriate first access line 120 based on the received column address. Similarly, a row of components 135 may receive a row of addresses from memory controller 170 and enable appropriate second access lines 130. Thus, in some examples, a memory cell 105 may be accessed by enabling a first access line 120 and a second access line 130 . In some examples, these access operations may be accompanied by a board assembly 145 biasing one or more of the third access lines 140 (eg, in the third access line 140 of the memory sector 110 ) One is biased, all third access lines 140 of the memory sector are biased, the memory sector 110 is biased or a common plate line of the memory device 100 is biased, the memory sector 110 is biased or a common node of the memory device 100 is biased), which may be referred to as a "moving" memory cell 105, a memory sector 110, or a "board" of the memory device 100.

In some examples, the memory controller 170 may control the operations of the memory cells 105 (eg, read operations, write operation, rewrite operation, refresh operation, discharge operation, voltage adjustment operation, dissipation operation, equalization operation). In some cases, one or more of column components 125 , row components 135 , board components 145 , and sense components 150 may be co-located or otherwise included within memory controller 170 . The memory controller 170 can generate column address signals and row address signals to enable a desired access line 120 and access line 130 . The memory controller 170 may also generate or control various voltages or currents used during the operation of the memory device 100 . Although only a single memory controller 170 is shown, other examples of a memory device 100 may have more than one memory controller 170 (eg, the sum of each of a set of memory sectors 110 of a memory device A memory controller 170 , a memory controller 170 of each of a number of subsets of memory sectors 110 of a memory device 100 , each of a chip set of a multi-chip memory device 100 a memory controller 170, a memory controller 170 for each of a bank of a multi-bank memory device 100, a memory controller 170 for each core of a multi-core memory device 100, or any combination thereof), wherein different memory controllers 170 may perform the same function or different functions.

Although memory device 100 is illustrated as including a single column assembly 125, a single row assembly 135, and a single board assembly 145, other examples of a memory device 100 may include different configurations to accommodate a set of memory sectors 110. For example, in various memory devices 100, a column of components 125 may be common among a set of memory sectors 110 (eg, having subcomponents common to all sets of memory sectors 110, having subcomponents that are specific to a set of memory a respective set of subcomponents in a sector 110 ), or a column of components 125 may be dedicated to one memory sector 110 in a set of memory sectors 110 . Likewise, in various memory devices 100, a row of components 135 may be shared among a set of memory sectors 110 (eg, having subcomponents common to all sets of memory sectors 110, having subcomponents that are dedicated to memory sectors 110 (sub-components of respective memory sectors in ), or a row of components 135 may be dedicated to one memory sector 110 in a group of memory sectors 110. Additionally, in various memory devices 100, a board component 145 may be shared among a set of memory sectors 110 (eg, having subcomponents common to all sets of memory sectors 110, having a subcomponent that is dedicated to memory sectors 110 (sub-components of respective memory sectors in the ), or a board component 145 may be dedicated to one memory sector 110 in a group of memory sectors 110.

In general, adjustments or changes can be made to the amplitude, shape, or duration of an applied voltage, current, or charge, and such amplitude, shape, or duration can be varied for the various operations discussed for operating the memory device 100 . different. Additionally, one, more, or all of the memory cells 105 within the memory device 100 may be accessed simultaneously. For example, each of memory cells 105 that share a common access line 120 or memory cells 105 that share a common access line 120 (eg, a common cell select line) can be accessed simultaneously Certain subsets (eg, according to a memory row access configuration, according to a "page" access configuration, according to a set of access lines 130 or rows that can be accessed or sensed simultaneously). In another example, multiple or all memory cells 105 of memory device 100 may be simultaneously accessed during a reset operation in which all or one of memory cells 105 Groups (eg, memory cells 105 of a memory sector 110) are set to a single logical state.

When accessing the memory cell 105 (eg, in cooperation with the memory controller 170 ), a memory cell 105 can be read (eg, sensed) by a sensing component 150 to determine whether to write to the memory cell 105 to or stored by memory cell 105 to a logic state. For example, the sensing element 150 may be configured to sense a current or charge transfer through or from the memory cell 105 or from the memory cell 105 and the sensing element 150 or other in response to a read operation An intermediate component (eg, a signal generating component between the memory cell 105 and the sensing component 150 ) is coupled to obtain a voltage. Sensing component 150 may provide an output signal indicative of the logic state read from memory cell 105 to one or more components (eg, to row component 135, input/output component 160, memory controller 170) . In various memory devices 100 , a sensing component 150 may be shared among a set of memory sectors 110 (eg, having subcomponents common to all sets of memory sectors 110 , having a subcomponent that is dedicated to a set of memory sectors 110 , subcomponents of respective memory sectors), or a sensing component 150 may be dedicated to one memory sector 110 in a group of memory sectors 110.

In some examples, during or after a memory cell 105 is accessed, a storage element of the memory cell 105 may discharge or otherwise allow charge or current to flow through its corresponding access line 120 , 130 or 140 . This charge or current may be formed by biasing or applying a voltage to memory cell 105 from one or more voltage sources or supplies (not shown) of memory device 100, which may be a series of components 125, a row of components 135, a board component 145, a sensing component 150, a memory controller 170, or part of some other component (eg, a biasing component). In some examples, the charge shared between a selected memory cell 105 and an access line 130 can cause the voltage of the access line 130 to change, and the sense element 150 can compare the voltage of the access line 130 to a The reference voltage is used to determine the logic state stored in the memory cell 105 .

A sensing element 150 may include various switching elements, selection elements, transistors, amplifiers, capacitors, resistors, or voltage sources to detect or amplify a difference in sense signals (eg, the difference between a read voltage and a reference voltage) A difference between a read current and a reference current, a difference between a read charge and a reference charge), in some instances, may be referred to as latching. In some examples, a sense component 150 may include a large number of components (eg, circuit elements) that are repeatedly used to connect to each of a set of access lines 130 of the sense component 150 . For example, a sense component 150 may include a separate sense circuit (eg, a separate or duplicated sense amplifier, a separate or Duplicated signal generation components) such that a logic state can be detected individually for a respective memory cell 105 coupled to a respective one of the set of access lines 130. In some instances, a reference signal source (eg, a reference component) or generated reference signal may be shared among components of memory device 100 (eg, shared among one or more sensing components 150, a Common among the individual sensing circuits of the sensing element 150, common among the access lines 120, 130 or 140 of a memory sector 110). In some examples, the detected logic state of a memory cell 105 may be output as an output through a row of elements 135 or an input/output element 160 .

Sensing component 150 may be included in a device including memory device 100 . For example, the sensing element 150 may be included with other read and write circuits, decoding circuits, or register circuits that may be coupled to the memory of the memory device 100 . In some examples, the detected logic state of a memory cell 105 may be output as an output through a row of elements 135 or an input/output element 160 . In some examples, a sensing element 150 may be part of a row of elements 135 or a column of elements 125 . In some examples, a sensing component 150 may be connected to or otherwise in electronic communication with a row of components 135 or a column of components 125 .

Although a single sensing element 150 is shown, a memory device 100 (eg, a memory sector 110 of a memory device 100 ) may include more than one sensing element 150 . For example, a first sense element 150 can be coupled with a first subset of access lines 130 and a second sense element 150 can be coupled with a second subset of access lines 130 (eg, different from the first subset of access lines 130 ) Take line 130) for coupling. In some examples, such a partitioning of sensing components 150 may support parallel (eg, simultaneous) operation of multiple sensing components 150 . In some examples, such a division of sensing components 150 may support matching of sensing components 150 with different configurations or characteristics to particular subsets of memory cells 105 of the memory device (eg, supporting different types of memory) Soma cell 105, supports different characteristics of subgroups of memory cells 105, supports different characteristics of subgroups of access lines 130). Additionally or alternatively, two or more sense components 150 may be coupled with the same set of access lines 130 (eg, component redundancy). In some instances, such a configuration may support maintaining functionality to overcome a failure or poor operation of one of the redundant sensing components 150 . In some instances, such a configuration may support the ability to select one of the redundant sensing components 150 for specific operating characteristics (eg, related to power consumption characteristics, related to access speed for a specific sensing operation) characteristics, related to operating the memory cell 105 in a volatile mode or a non-volatile mode).

In some memory architectures, accessing the memory cell 105 may degrade or destroy the stored logical state, and an overwrite or refresh operation may be performed to restore the stored logical state to the memory cell 105 . In DRAM or FeRAM, for example, a capacitor of a memory cell 105 may be partially or fully discharged during a sensing operation, thereby damaging the logic state stored in the memory cell 105 . Thus, in some instances, the logic state stored in a memory cell 105 may be overwritten during an access operation. Furthermore, activating a single access line 120, 130 or 140 can cause all memory cells 105 coupled to the activated access line 120, 130 or 140 to discharge. Thus, several or all memory cells 105 coupled to an access line 120, 130, or 140 associated with an access operation (eg, all cells of an access row) may be overwritten after an access operation , an access to all cells of a row).

In some examples, reading a memory cell 105 can be non-destructive. That is, the logic state of the memory cell 105 does not need to be rewritten after the memory cell 105 is read. However, in some instances, the logic state of memory cell 105 may or may not be required to be refreshed in the absence or presence of other access operations. For example, the logic state stored by a memory cell 105 may be refreshed at periodic intervals by applying an appropriate write pulse, rewrite pulse, refresh pulse, or equalization pulse or biasing voltage to maintain the stored logical state. Refreshing memory cells 105 can reduce or eliminate read disturb errors or logic state corruption due to a charge leakage or a change in a material configuration of a memory element over time.

A memory cell 105 may be set or written by activating the associated first access line 120, second access line 130, or third access line 140 (eg, via a memory controller 170) . In other words, a logic state can be stored in a memory cell 105 . For example, column element 125 , row element 135 , or board element 145 may receive data to be written to memory cell 105 via input/output element 160 . In some examples, a write operation can be performed at least in part by a sense component 150 , or a write operation can be configured to bypass a sense component 150 .

In the case of a capacitive memory element, it can be made possible by applying a voltage to or across a capacitor and then isolating the capacitor (eg, isolating the capacitor from a voltage source used to write to memory cell 105). capacitor float) to store a charge in the capacitor associated with a desired logic state for writing to a memory cell 105. In the case of ferroelectric memory, a ferroelectric memory element (eg, a ferroelectric capacitor) of a memory cell 105 can be written by applying a magnitude high enough to convert the ferroelectric The memory element is polarized to a voltage (eg, applying a saturation voltage) to a polarization associated with a desired logic state, and can isolate (eg, float) the ferroelectric memory element, or can span the ferroelectric memory The bulk element applies a zero net voltage or bias (eg, ground, virtual ground, or equalizing a voltage across the ferroelectric memory element). In the case of a material memory architecture, a memory cell can be configured by applying a current, voltage, or other heat or bias to a material memory element according to a corresponding logic state to configure the material 105 to write.

In some examples, memory device 100 may include a set of memory sectors 110 . Each of the memory sectors 110 may include a set of memory cells 105 and a set of second access lines 130 (eg, of the respective memory sectors 110) One and one of the set of third access lines 140 are coupled, or between one of the set of second access lines 130 and one of the set of third access lines 140 . Each of the memory cells 105 may include a cell selection element configured to selectively associate the memory cells 105 with (eg, of respective memory sectors 110 ) The associated second access line 130 or the associated third access line 140 is coupled. In some examples, each of the cell select elements may be coupled with a respective one of the first access lines 120 (eg, of memory sector 110) (eg, at a respective one of the first access lines 120). A control node or a control terminal of a cell selection element), which can be used to activate or deactivate a particular cell selection element.

Access operations may be performed on selected memory cells 105 of a memory sector 110, and such access operations may include read operations, write operations, rewrite operations, refresh operations, or various combinations thereof. In some examples, the access operation may be associated with biasing the second access line 130 or the third access line 140 associated with a selected memory cell 105 . During an access operation, the cell selection element for the selected memory cell 105 can be activated so that the selected memory cell 105 can be selectively coupled with the second access line 130 or the third access line 140 . Therefore, as the second access line 130 or the third access line 140 is biased for an access operation, signals associated with an access operation (eg, a voltage associated with an access operation, a voltage associated with an access operation, and a A charge associated with an access operation, a current associated with an access operation) can be transferred to, from or through the selected memory cell 105 .

In some instances, charge may leak from one portion of memory device 100 or memory sector 110 to another. Possible causes of leakage include manufacturing defects, device breakdown (eg, thin film transistor (TFT) breakdown or leakage), memory cell depletion mechanisms (eg, stress-induced leakage current (SILC), breakdown (BD) current), composition change or other reasons. For example, charge can traverse a cell select element of a memory cell 105, traverse a dielectric material of a capacitive storage element, from one access line of memory device 100 to another (eg, , leakage from one access line 130 to another access line 120, 130 or 130), across a transistor intended to be deactivated (eg, across a transistor switched to a non-conductive state), etc. In some instances, charge leakage can negatively impact the performance of memory device 100 (eg, causing a memory cell to be read from a logic state that is different from the one previously written to the memory cell) logical state). Thus, in accordance with the techniques disclosed herein, memory device 100 (eg, memory controller 170 ) may be configured to determine whether to convert a direct logic state based on a detection of charge leakage in memory device 100 A complementary logic state is also stored in a memory cell 105 or a group of memory cells 105 .

In some instances, deletions or other actions may cause an information state (eg, logical state) written to or stored by a memory cell 105 to be indeterminate (eg, a subsequent access in operation). For example, in some cases, the memory device 100 may not be able to distinguish whether a memory cell 105 stores one logic state or another logic state (eg, a memory cell stores a logic 1 is also a logic 0), or the memory device 100 may detect one logic state when reading a memory cell 105, but write a different logic state to the memory cell 105 (eg, when reading a memory cell 105 A logic 0 is detected during a read operation of the cell, but the memory cell is written with a logic 1).

In some examples, memory device 100 may be configured to identify various conditions that may be associated with an indeterminate or indeterminate information state. For example, memory device 100 may identify one or more memory cells 105, one or more access lines (eg, access line 130), or a One or more information locations of a codeword. A corresponding codeword (eg, generated during a read operation) may include certain information locations having a detected information state (eg, a logic 0 or logic 1) and having an indeterminate information state or undetermined information state Certain information locations are assigned information states (eg, a logical X, an empty logical state). Error handling operations may be performed on codewords in which information locations associated with an indeterminate or unassigned logic state are replaced or assigned a respective putative or speculative information state (e.g., a logic 0 replaces a logic X, Replacing a logical X) with a logical 1 improves one of the various errors and has other benefits.

2 illustrates an example circuit 200 that supports memory management and delete decoding for a memory device in accordance with examples disclosed herein. The circuit 200 includes a memory cell 105-a, which may be an example of the memory cell 105 described with reference to FIG. Circuit 200 also includes a sense amplifier 290, which may be part of one of the sense components 150 described with reference to FIG. Circuit 200 may also include a word line 205, a digit line 210, and a plate line 215, which in some examples may correspond, respectively, to those described with reference to FIG. 1 (eg, A first access line 120 , a second access line 130 and a third access line 140 of a memory sector 110 . In some examples, board line 215 may illustrate a common board line, a common board, or another common board line of memory cell 105-a and another memory cell 105 (not shown) of the same memory sector 110 node. Circuit 200 may also include a reference line 265 used by sense amplifier 290 to determine a logic state stored by memory cell 105-a.

As illustrated in FIG. 2, sense amplifier 290 may include a first node 291 and a second node 292, which in some examples may be different access lines to a circuit (eg, a signal line 260 and a reference line 265 of circuit 200, respectively), or in other examples may be coupled to a common access line of a different circuit (not shown). In some instances, the first node 291 may be referred to as a signal node, and the second node 292 may be referred to as a reference node. However, other configurations of access lines or reference lines may be used to support the techniques described herein.

The memory cell 105-a may include a logical storage element (eg, a memory element, a storage element, a memory storage element), such as having a first board, cell board 221 and a second board, cell A capacitor 220 at the bottom 222 of the cell. Cell plate 221 and cell bottom 222 may be capacitively coupled through a dielectric material therebetween (eg, in a DRAM application), or capacitively coupled through a ferroelectric material therebetween (eg, in a FeRAM application). Cell plate 221 may be associated with a voltage V _plate and cell bottom 222 may be associated with a voltage V _bottom , as illustrated in circuit 200 . The orientation of the cell plate 221 and the cell bottom 222 may be different (eg, flipped) without changing the operation of the memory cell 105-a. Cell board 221 is accessible via board line 215 , and cell bottom 222 is accessible via digit line 210 . As set forth herein, various logic states may be stored by charging, discharging, or polarizing capacitor 220 .

Capacitor 220 may be electrically connected to digit line 210 and the logic state stored by capacitor 220 may be read or sensed by operating various elements represented in circuit 200 . For example, memory cell 105-a may also include a cell select element 230, which in some instances may be referred to as being associated with an access line (eg, digit line 210) and Capacitor 220 is coupled or coupled to a switching element or a selector device between an access line and capacitor 220 . In some examples, a cell selection element 230 may be considered to be located outside the illustrative boundaries of memory cell 105-a, and cell selection element 230 may be referred to as being associated with an access line (eg, a bit Line 210) and memory cell 105-a are coupled or a switch element or selector device between an access line and memory cell 105-a.

Capacitor 220 may be selectively coupled to digit line 210 when cell selection element 230 is activated (eg, by an activation logic signal), and when cell selection element 230 is deactivated (eg, by a deactivation logic signal) signal), the capacitor 220 can be selectively isolated from the digit line 210. A logic signal or other select signal or voltage (eg, via word line 205, a selection line). In other words, cell selection component 230 can be configured to selectively couple or decouple capacitor 220 from digit line 210 based on a logic signal or a voltage applied to control node 235 via word line 205 .

Activating cell selection component 230 may be referred to as selecting or deactivating memory cell 105-a, and deactivating cell selection component 230 may be referred to as deselecting or deactivating memory cell 105-a. In some examples, cell selection component 230 is a transistor and its operation can be controlled by applying a startup voltage to the gate of the transistor (eg, a control or selection node or terminal). The voltage used to activate the transistor (eg, the voltage between the gate terminal of the transistor and the source of the transistor) may be a voltage greater than the threshold voltage magnitude of the transistor. Word line 205 may be used to activate cell select element 230 . For example, a select voltage (eg, a word line logic signal or a word line voltage) applied to word line 205 may be applied to the gate of a transistor of cell select element 230, which may select Capacitor 220 and digit line 210 are connected in a discrete manner (eg, to provide a conductive path between capacitor 220 and digit line 210). In some examples, enabling cell selection component 230 may be referred to as selectively coupling memory cell 105-a and digit line 210.

In other examples, the positions of cell selection element 230 and capacitor 220 in memory cell 105-a can be switched so that cell selection element 230 can be coupled to plate line 215 and cell plate 221 or to plate line 215 and the cell plate 221 , and the capacitor 220 may be coupled with the other terminal of the digit line 210 and the cell selection element 230 or between the other terminal of the digit line 210 and the cell selection element 230 . In this example, cell selection component 230 may be in electronic communication with digit line 210 through capacitor 220 . This configuration can be associated with alternate timing and biasing for access operations.

In the example employing a ferroelectric capacitor 220 , the capacitor 220 may or may not be fully discharged when connected to the digit line 210 . In various schemes, to sense the logic state stored by a ferroelectric capacitor 220, a voltage may be applied to the plate line 215 or the digit line 210, and the word line 205 may be biased (eg, by enabling the word line 205 ) to select memory cell 105-a. In some cases, plate line 215 or digit line 210 may be virtually grounded and then isolated from virtual ground prior to enabling word line 205, which may be referred to as a floating condition, an idle condition, or a standby condition.

Operating memory cell 105-a by varying the voltage of cell plate 221 (eg, via plate line 215) may be referred to as "moving the cell plate." Biasing the plate line 215 or the digit line 210 can result in a voltage difference across the capacitor 220 (eg, the voltage of the digit line 210 minus the voltage of the plate line 215). This voltage difference may be accompanied by a change in the charge stored on capacitor 220 (eg, due to the charge shared between capacitor 220 and digit line 210, due to the charge shared between capacitor 220 and plate line 215), wherein the stored charge The amount of change may depend on the initial state of capacitor 220 (eg, whether the initial charge or logic state stores a logic 1 or a logic 0). In some schemes, a change in the charge stored by capacitor 220 can cause a change in the voltage of one or both of digit line 210 or signal line 260, which can be used by sense amplifier 290 to determine memory cells Logic state stored in 105-a.

The digit line 210 can be coupled with additional memory cells 105 (not shown), and the digit line 210 can have properties that result in a non-negligible intrinsic capacitance 240 (eg, on the order of picofarads (pF)) that can The digit line 210 is coupled to a voltage source 250-a. Voltage source 250-a may represent a common ground or virtual ground voltage or the voltage of an adjacent access line of circuit 200 (not shown). Although illustrated as a separate element in FIG. 2 , intrinsic capacitance 240 may be associated with properties distributed throughout digit line 210 .

In some examples, the intrinsic capacitance 240 may depend on the physical characteristics of the digit line 210 , including the conductor dimensions (eg, length, width, thickness) of the digit line 210 . Intrinsic capacitance 240 may also depend on the characteristics of adjacent access lines or circuit elements, proximity to such adjacent access lines or circuit elements, or insulation characteristics between digit lines 210 and such access lines or circuit elements. Thus, a change in the voltage of digit line 210 after selection of memory cell 105-a may depend on (eg, be associated with) the net capacitance of digit line 210. In other words, as charges flow along the digit line 210 (eg, to and from the digit line 210 ), some finite charge may be stored along the digit line 210 (eg, stored in the inherent capacitance 240 , and the digit line 210 ). 210 is coupled to other capacitors or capacitances), and the resulting voltage of the digit line 210 may depend on the net capacitance of the digit line 210.

The sense amplifier 290 may compare the resulting voltage on the digit line 210 or the signal line 260 after selecting the memory cell 105-a to a reference (eg, a voltage on the reference line 265) to determine the voltage in the memory cell 105-a. The logical state of storage. In some examples, a reference component 285 may provide a voltage on reference line 265 . In other examples, reference component 285 may be omitted and a reference voltage may be provided, eg, generated by accessing memory cell 105-a (eg, in a self-referencing access operation). Other operations may be used to support selection or sensing of memory cell 105-a.

In some examples, circuit 200 can include a signal generation component 280, which can be coupled to memory cell 105-a and sense amplifier 290 or coupled to memory cell 105-a and sense amplifier 290 An example of a signal generating circuit between 290. The signal generation component 280 may amplify or otherwise convert the signal of the digit line 210 prior to a sensing operation. Signal generation component 280 may include, for example, a transistor, an amplifier, a tandem device, or any other charge or voltage converter or amplifier component. In some examples, the signal generation component 280 can include a charge transfer sense amplifier (CTSA) that can include one or more transistors in a tandem device configuration or a voltage control configuration. In some examples with a signal generation component 280, the line between the sense amplifier 290 and the signal generation component 280 may be referred to as a signal line (eg, signal line 260). In some instances (eg, instances with or without a signal generation component 280 ), the digit line 210 may be electrically connected directly to the sense amplifier 290 .

In some examples, circuit 200 may include a bypass line 270 that may permit selective bypassing of signal generation component 280 or some other signal generation circuit between memory cell 105-a and sense amplifier 290 . In some instances, bypass line 270 may be selectively enabled by a switching element 275 . In other words, when switching element 275 is activated, digit line 210 may be coupled with signal line 260 via bypass line 270 (eg, coupling memory cell 105-a with sense amplifier 290).

In some instances, when switching component 275 is activated, signal generating component 280 may be selectively isolated from one or both of digit lines 210 or signal lines 260 (eg, by another switching component or selection component, not exhibit). When switching component 275 is deactivated, digit line 210 can be selectively coupled to signal line 260 via signal generation component 280 . In other examples, a select element may be used to selectively couple memory cell 105-a (eg, digit line 210) with one of signal generation element 280 or bypass line 270. Additionally or alternatively, in some examples, a selection component may be used to selectively couple sense amplifier 290 with one of signal generating component 280 or bypass line 270 . In some examples, an optional bypass line 270 may support generating a sense signal for detecting a logic state of memory cell 105-a by using signal generation component 280, and generating a write signal to generate A logic state is written to memory cell 105 - a bypassing signal generation component 280 .

Certain examples of a memory device 100 supporting the techniques disclosed herein may include a common access line (not shown) shared between a memory cell 105 and a sense amplifier 290 to support from the same memory cell Element 105 generates a circuit 200 for a sense signal and a reference signal. In one example, a common access line between a signal generation component 280 and a sense amplifier 290 may replace the signal line 260 and reference line 265 illustrated in circuit 200 . In this example, the common access line may be connected to sense amplifier 290 at two different nodes (eg, a first node 291 and a second node 292, as set forth herein). In some examples, a common access line may permit a self-referencing read operation to be common in both a signal generation operation and a reference generation operation that may exist in sense amplifier 290 and a memory being accessed Components between cells 105. Such a configuration may reduce the use of sense amplifiers 290 for various components in a memory device 100 (eg, memory cells 105, access lines (eg, a word line 205, a digit line 210, a board line 215) , the sensitivity to changes in operation of the signal generating circuit (eg, the signal generating component 280), the transistor, the voltage source 250, etc.).

Although digit line 210 and signal line 260 are identified as separate lines, digit line 210, signal line 260, and any other line connecting a memory cell 105 and a sense amplifier 290 may be referred to as a single access Wire. In various example configurations, components of such an access line may be individually identified for purposes of illustrating intervening components and intervening signals.

The sense amplifier 290 may include various transistors or amplifiers to detect, convert or amplify a signal difference, which may be referred to as a latch. For example, sense amplifier 290 may include circuit elements that receive and compare a sense signal voltage (eg, V _sig ) at first node 291 with a reference signal voltage (eg, V _ref ) at second node 292 . One of the sense amplifier outputs can be driven to a higher voltage (eg, a positive voltage) or a lower voltage (eg, a negative voltage, a ground voltage) based on the comparison at the sense amplifier 290 .

For example, if the first node 291 has a lower voltage than the second node 292, the output of the sense amplifier 290 can be driven to a relatively lower voltage of a first sense amplifier voltage source 250-b (eg, A voltage _VL , which may be a ground voltage substantially equal to _V0 or may be a negative voltage). A sense element 150 including a sense amplifier 290 can latch the output of the sense amplifier 290 to determine the logic state stored in the memory cell 105-a (eg, when the first node 291 has a lower value than the second node 292) , a logic 0 is detected).

If the first node 291 has a higher voltage than the second node 292, the output of the sense amplifier 290 can be driven to a voltage of a second sense amplifier voltage source 250-c (eg, a voltage V _H ). A sense element 150 including a sense amplifier 290 can latch the output of the sense amplifier 290 to determine the logic state stored in the memory cell 105-a (eg, when the first node 291 has a higher value than the second node 292 When a voltage is detected, a logic 1) is detected. Then, via one or more input/output (I/O) lines (eg, I/O line 295 ), which may include one output through a row of components 135 , or one of the input/output components 160 described with reference to FIG. 1 The latched output of sense amplifier 290 corresponding to the detected logic state of memory cell 105-a is output.

To perform a write operation on memory cell 105-a, a voltage may be applied across capacitor 220. Various methods can be used. In one example, cell select element 230 may be activated through word line 205 (eg, by activating word line 205 ) to electrically connect capacitor 220 to digit line 210 . A voltage can be applied across capacitor 220 by controlling the voltage on cell plate 221 (eg, through plate line 215) and cell bottom 222 (eg, through digital line 210).

For example, to write a logic 0, cell plate 221 can be brought high (eg, applying a positive voltage to plate line 215), and cell bottom 222 can be brought low (e.g., applying a digital The line 210 is grounded, the digit line 210 is virtually grounded, and a negative voltage is applied to the digit line 210). The reverse procedure can be performed to write a logic 1, with cell plate 221 set low and cell bottom 222 set high. In some cases, the voltage applied across capacitor 220 during a write operation may have a magnitude equal to or greater than a saturation voltage of a ferroelectric material in capacitor 220 such that capacitor 220 is polarized, and thus A charge is maintained even when the magnitude of the applied voltage is reduced or with a zero net voltage applied across capacitor 220 . In some examples, sense amplifier 290 may be used to perform write operations, which may include coupling first sense amplifier voltage source 250-b or second sense element voltage source 250-c to a digit line . When sense amplifier 290 is used to perform a write operation, signal generation component 280 may or may not be bypassed (eg, by applying a write signal through bypass line 270).

Circuit 200 including sense amplifier 290, cell selection element 230, signal generation element 280, or reference element 285 may include various types of transistors. For example, circuit 200 may include an n-type transistor, wherein a relatively positive voltage is applied to the gate of the n-type transistor above a threshold voltage of the n-type transistor (eg, an applied voltage relative to a source The terminal terminals have a positive magnitude, greater than a threshold voltage, to achieve a conductive path between the other terminals of the n-type transistor (eg, a source terminal and a drain terminal).

In some instances, an n-type transistor can be used as a switching element where the applied voltage is a logic signal that is used by applying a relatively high logic signal voltage (eg, with a logic 1 state) Corresponding to a voltage, which may be associated with a positive logic signal voltage supply, enables conduction of the pass-through transistor, or by applying a relatively low logic signal voltage (eg, a voltage corresponding to a logic 0 state, which may Associated with a ground voltage or virtual ground voltage) disables the conduction of the pass-through transistor. In some instances where an n-type transistor is used as a switching element, the voltage applied to a logic signal at the gate terminal can be selected to be at a particular operating point (eg, in a saturation region or at an active region) to operate the transistor.

In some instances, the behavior of an n-type transistor can be more complex than a logic switching, and selective conductivity across the transistor can also be a function of varying source and drain voltages. For example, the voltage applied at the gate terminal may have a value for enabling the source and drain terminals when the source terminal voltage is below a certain level (eg, below the gate terminal voltage minus a threshold voltage) A specific voltage level (eg, a clamping voltage) for the conductivity between the cells. When the source terminal voltage or the drain terminal voltage rises above a certain level, the n-type transistor can be deactivated so that the conduction path between the source and drain terminals is broken.

Additionally or alternatively, circuit 200 may include a p-type transistor, wherein a relatively negative voltage (eg, an applied voltage relative to a threshold voltage of the p-type transistor) is applied to the gate of the p-type transistor Having a negative magnitude at a source terminal, greater than a threshold voltage, enables a conduction path between other terminals of the p-type transistor (eg, the source terminal and a drain terminal).

In some instances, a p-type transistor can be used as a switching element where the applied voltage is a logic signal that is used by applying a relatively low logic signal voltage (eg, with a logic "1" " state corresponds to a voltage, which can be associated with a negative logic signal voltage supply) to enable conduction, or by applying a relatively high logic signal voltage (eg, a voltage corresponding to a logic "0" state, can be a ground voltage or virtual ground voltage) disables conductivity. In some instances where a p-type transistor is used as a switching element, the voltage applied to a logic signal at the gate terminal can be selected to be at a particular operating point (eg, in a saturation region or at an active region) to operate the transistor.

In some instances, the behavior of a p-type transistor can be more complex than a logical switching by gate voltage, and selective conductivity across the transistor can also be a function of varying source and drain voltages. For example, the voltage applied at the gate terminal may have a value for enabling the source and drain terminals as long as the source terminal voltage is above a certain level (eg, above the gate terminal voltage plus a threshold voltage) A specific voltage level of conductivity between the sub-subs. When the voltage of the source terminal voltage drops below a certain level, the p-type transistor can be deactivated so that the conduction path between the source and drain terminals is broken.

A transistor of circuit 200 may be a field effect transistor (FET) that includes a metal-oxide-semiconductor FET, which may be referred to as a MOSFET. These and other types of transistors can be formed by doped regions of material on a substrate. In some examples, transistors may be formed on a substrate dedicated to a particular component of circuit 200 (eg, a substrate for sense amplifier 290, a substrate for signal generation component 280, a substrate for memory cell 105-a), or transistors may be formed on a substrate common to certain components of circuit 200 (eg, a common substrate for sense amplifier 290, signal generation component 280, and memory cell 105-a) ). Certain FETs may have a metal portion comprising aluminum or other metals, but certain FETs (including those that may be referred to as a MOSFET) may implement other non-metallic materials, such as polysilicon. Furthermore, although an oxide portion can be used as a dielectric portion of a FET, other non-oxide materials can be used in a dielectric material in a FET, including those FETs that can be referred to as a MOSFET.

Although circuit 200 illustrates a set of components with respect to a single memory cell 105, various components of circuit 200 may be repeated in a memory device 100 to support various operations. For example, to support column access or "page" access operations, a memory device 100 may be configured with one of sense amplifiers 290, signal lines 260, signal generation components 280, digital lines 210, or other components A plurality of or more, where the plurality can be configured according to a certain number of memory cells 105 that can be accessed in a row access or "page" access operation (eg, in a simultaneous operation). In various examples, a set of such multiples may correspond to or repeat for each memory sector 110 in a memory device 100, or This set of multiples may be shared among one or more memory sectors 110 in a memory device.

In one illustrative example, for a memory device 100 that supports a 256-cell column access (eg, common access to 256 rows) or a 256-bit page, the memory device 100 (eg, a sensing element 150) may include at least one set of 256 sense amplifiers 290, 256 signal lines 260, 256 signal generation components 280, and 256 digit lines 210, which in some instances may be accomplished by enabling a single common word line 205 to access a group of 256 memory cells 105 in a memory sector 110 . In some examples, such a repetition may correspond to a single memory sector 110 , or may correspond to more than one memory sector 110 . However, other configurations and combinations of various components may be used to support column access operations or page access operations of the techniques set forth herein, or other operations in which multiple memory cells 105 are accessed simultaneously.

In some instances, sense amplifier 290 may not be able to distinguish whether memory cell 105-a is written with one logic state or another logic state (eg, whether memory cell 105-a stores a logic 1 or a logic 1). logic 0), or sense amplifier 290 may detect one logic state when reading memory cell 105-a, but a different logic state is written to memory cell 105-a (eg, during a read A logic 0 was detected on a memory cell during operation, but the memory cell was written with a logic 1). Such a condition may be associated with an indeterminate information state of one of the memory cells 105-a, and may be associated with various conditions (eg, deletion, charge leakage, information state degradation (eg, one of the memory cells 105-a) logic state, charge state or material state degradation)) or other phenomena).

In some instances, an indeterminate information state of memory cell 105-a may be a result of charge leakage from one portion of circuit 200 to another. Possible causes of leakage include manufacturing defects, device breakdown (eg, thin film transistor (TFT) breakdown or leakage), memory cell depletion mechanisms (eg, stress-induced leakage current (SILC), breakdown (BD) current), circuit 200 Changes in material composition of one of the elements or other reasons. For example, the charge may traverse the cell select element 230 (eg, a leakage path "A"), across a dielectric material of the capacitor 220 (eg, a leakage path "B"), from a storage of the memory device 100 Leakage of the wire taken to another access line (eg, a leakage path "C" from the digit line 210 to another access line or backplane ground). Other examples not illustrated may include other leakage paths that permit charge transfer between components: between memory cell 105-a of memory device 100, one including circuit 200, and another component, between memory cells 105-a of memory device 100, including circuit 200, Between digit line 210 of a memory device 100 and another component (eg, between digit line 210 and another digit line 210 , not shown) or between signal line 260 of a memory device 100 including circuit 200 and between another component (eg, between a signal line 260 and another signal line 260, not shown) or various combinations thereof. In various examples, charge leakage can affect the information state of memory cell 105-a itself or the ability to generate or detect a signal (eg, a read signal) obtained from accessing memory cell 105-a, Either or both of the above two conditions may be associated with a read operation that cannot determine a logical state written to memory cell 105-a.

In certain examples of a memory device supporting the techniques described herein, circuit 200 may include one or more leakage detection components 201 to detect charge leakage (eg, between components intended to be electrically isolated). The presence or level of a charge transfer) such as one or both of a leak detection element 201-a connected to the digit line 210 or a leak detection element 201-b connected to the signal line 260. A leak detection component 201 can be configured to detect charge leakage in the circuit 200, eg, above a threshold value or satisfying a threshold value (eg, above a threshold value that would indicate normal operation of the circuit 200, Indicates abnormal operation of one or more elements of circuit 200 (either charge leakage), leakage or other charge transfer. Although leak detection component 201 is illustrated as a separate component, in some examples, a leak detection component 201 may be included in a signal generation component 280 or in a sense amplifier 290, and a leak detection Component 201 can be connected with multiple access lines or connected in series with an access line.

In some examples, a leak detection component 201 can be configured to change or compare a voltage to a reference voltage or threshold by identifying (eg, an access line, one of a memory cell 105) a voltage value (eg, using a sense amplifier, a multi-level cell (MLC) latch, a comparator, or other components of leak detection component 201) to detect a charge leak. For example, leak detection component 201 - a can be configured to monitor a voltage on digital line 210 , or leak detection component 201 - b can be configured to monitor a voltage on signal line 260 . In some examples, a leak detection component 201 can be configured to detect a charge flow (eg, where a charge flow or a charge flow above a threshold would indicate leakage other than normal an access operation associated with a charge transfer scenario or condition). For example, leak detection component 201-a may be configured to detect a flow of charge along digital line 210, or leak detection component 201-b may be configured to detect one along signal line 260 A charge flow, any of which may correspond to a charge flow across the signal generation component 280 . In some examples, detection of a charge flow can be supported by monitoring a voltage across a shunt resistor configured to deliver charge flow (eg, when a leak detection element 201 is connected to an access line or element when connected in series).

In some examples, a leak detection component 201 can be configured to detect charge leakage from a particular cell (eg, charge leakage along paths "A" or "B", which can be memory cell 105 - unique to a), this charge leakage is distinguishable from other charge leakages that may all exist in a set of memory cells 105 sharing a digit line 210 (eg, charge leakage along path "C"). In some examples, a leakage detection component 201 may not be configured to leak charge to a particular cell and other charge leakage more commonly associated with an access line (eg, charge leakage associated with digit line 210 ). , charge leakage associated with signal line 260, and charge leakage common to one or more of a set of memory cells 105).

In some examples, a leak detection component 201 can be configured to perform a leak detection during or based at least in part on an access operation (eg, of memory cell 105-a) A detection operation, which may include performing a leak detection operation while selecting memory cell 105-a (eg, while activating cell selection element 230, while activating word line 205). A leak detection component 201 can thus communicate with a memory controller 170, a sense component 150, sense amplifier 290, or word line 205, which can support leak detection component 201 during certain portions of an access operation Carry out the operation. In some examples, a leak detection component 201 can be configured to perform a leak detection operation during or based at least in part on a diagnostic mode of a memory device 100, This may or may not be included in or otherwise associated with an access operation.

In some examples, a leak detection component 201 can support providing information to support selectively performing a direct write operation or a complementary write operation, which can include providing an indication of whether a leak is detected to a One or more of memory controller 170, a sense component 150, sense amplifier 290, or other components. In various examples, the determination of whether to perform a direct write operation or a complementary write operation may be based on the charge leakage of a particular cell (eg, charge leakage along path "A" or path "B", and the memory cell 105-a associated charge leakage, charge leakage associated with capacitor 220), charge leakage associated with a particular access line (eg, charge leakage along path "C", and digit line 210 or signal line 260 the associated charge leakage) detection or other detected charge leakage or a combination thereof.

In some examples, a leak detection component 201 can provide information to support identification of the memory cell 105-a associated with an indeterminate logic state or an access line coupled to the memory cell 105-a ( For example, digit line 210, signal line 260) or indicate a condition that may not be a logical state. For example, a leak detection component may include providing an indication of whether a leak was detected (eg, for a particular memory cell 105, for a particular access line, for a particular memory address) to a memory One or more of a body controller 170, a sense component 150, a sense amplifier 290, or other components. This information can be used, for example, to identify information locations (eg, generated in a read operation) of a codeword with an indeterminate or unassigned information state, and one or more hypotheses or speculations can then be assigned to those information locations. Sexual information status to support various error handling operations in accordance with the techniques disclosed herein.

In some examples, a leak detection component 201 can include a storage element (eg, a temporary storage element, a latch that stores an indication of whether a leak is detected (eg, during an access operation) , a capacitor, a storage element). In some examples, a stored indication may be maintained or valid for a most recent access operation, and may be cleared or reset in response to another access being performed. A memory controller 170 can receive or request an indication of whether a leak is detected, and then a memory controller 170 or some other portion of a memory device 100 can use this indication to support the disclosures herein Various examples of the technology.

In some examples, a memory controller 170 or some other portion of a memory device 100 may store an indication of which type of write operation to perform, such as (eg, common to one or more memories of word lines 205 ) A one-bit flip indication of a cell 105, a row of memory cells 105, a page of memory cells 105, a group of memory cells 105). A bit flip indication can be used in a subsequent read operation to determine how to interpret a sensed logic state (eg, directly interpreting a sensed logic state or interpreting as the complement of the sensed logic state). For example, depending on the state of a bit toggle indication, an output on I/O line 295 may be provided directly (eg, indicating the logic state stored by memory cell 105-a) or I/O line 295 may be The previous output is inverted (eg, indicating the complement of the logic state stored by memory cell 105-a).

3A and 3B illustrate examples of nonlinear electrical properties of a ferroelectric memory cell using hysteresis curves 300-a and 300-b according to various examples disclosed herein. Hysteresis curves 300-a and 300-b may illustrate an example of a write process and a read process, respectively, using a memory cell 105 of a ferroelectric capacitor 220 described with reference to FIG. Hysteresis curves 300-a and 300-b depict charge Q stored on ferroelectric capacitor 220 as a function of a voltage difference V _cap between the terminals of ferroelectric capacitor 220 (eg, when charge is permitted to flow according to the voltage difference V _cap into or out of the ferroelectric capacitor 220). For example, the voltage difference V _cap may represent the voltage difference between a digit line side of capacitor 220 and a plate line side of capacitor 220 (eg, V _bottom −V _plate ).

A ferroelectric material is characterized in that the material can maintain an electrical polarization of a non-zero charge in the presence of an electric field. Examples of ferroelectric materials include barium titanate (BaTiO3 ₎ , lead titanate (PbTiO3 ₎ , lead titanate (PZT), and strontium bismuth tantalate (SBT). The ferroelectric capacitors 220 described herein may include these or other ferroelectric materials. The electrical polarization within a ferroelectric capacitor 220 creates a net charge at the surface of the ferroelectric material and attracts the opposite charge through the terminals of the ferroelectric capacitor 220 . Thus, charge can be stored at the interface of the ferroelectric material and the capacitor terminals. Because the electrical polarization can be maintained for relatively long periods of time, even indefinitely, in the absence of an externally applied electric field, compared to, for example, capacitors that do not have nonferroelectric properties (such as those used in some DRAM arrays), Charge leakage can be significantly reduced. The use of ferroelectric materials can reduce one of the need to perform refresh operations on certain DRAM architectures so that maintaining the logic state of a FeRAM architecture can be associated with lower power consumption than maintaining the logic state of a DRAM architecture.

Hysteresis curves 300 - a and 300 - b can be understood from the perspective of a single terminal of a ferroelectric capacitor 220 . For example, if the ferroelectric material has a negative polarization, a positive charge accumulates at the associated terminals of the ferroelectric capacitor 220 . Likewise, if the ferroelectric material has a positive polarization, a negative charge accumulates at the associated terminals of the ferroelectric capacitor 220 . Additionally, it should be understood that the voltages in the hysteresis curves 300-a and 300-b represent a voltage difference across the capacitor (eg, a potential between the terminals of the ferroelectric capacitor 220) and are directional. For example, by applying a positive voltage to the respective terminal (eg, a cell bottom 222 ) and maintaining the reference terminal (eg, a cell plate 221 ) at ground or virtual ground (or about zero volts (0V) )) to achieve a positive voltage. In some examples, a negative voltage can be applied by maintaining the respective terminal at ground and applying a positive voltage to the reference terminal (eg, cell plate 221). In other words, a positive voltage can be applied to achieve a negative voltage difference V _cap across the ferroelectric capacitor 220 and thereby negatively polarize the terminal in question. Similarly, two positive voltages, two negative voltages, or any combination of positive and negative voltages can be applied to the appropriate capacitor terminals to produce the voltage difference _Vcap shown in hysteresis curves 300-a and 300-b.

As depicted in hysteresis curve 300-a, a ferroelectric material used in a ferroelectric capacitor 220 can maintain a positive or negative polarization when there is no net voltage difference between the terminals of the ferroelectric capacitor 220. For example, hysteresis curve 300-a illustrates two possible polarization states: a charge state 305-a and a charge state 310-b, which may each represent a negative saturation polarization state and a positive saturation polarization state. Charge states 305-a and 310-a may be in a physical condition illustrating remanent polarization (Pr) values, which may refer to the polarization (or charge) that remains after removal of an external bias (eg, voltage) . According to the example of the hysteresis curve 300-a, the state of charge 305-a may represent a logic 1 when the voltage difference is not applied across the ferroelectric capacitor 220, and the state of charge 310-a may represent a logic 1 when the voltage difference is not applied across the ferroelectric capacitor 220 Represents a logical 0. In some examples, the logical values of the respective charge states or polarization states may be reversed or interpreted in an opposite manner to accommodate other schemes of operating a memory cell 105 .

A logic 0 or 1 can be written to the memory cell by applying a net voltage difference across the ferroelectric capacitor 220 by controlling the electrical polarization of the ferroelectric material and thus the charge on the capacitor terminals. For example, voltage 315 may be a voltage equal to or greater than a positive saturation voltage, and application of voltage 315 across ferroelectric capacitor 220 may cause charge to accumulate until charge state 305-b is reached (eg, a logic 1 is written). After the voltage 315 is removed from the ferroelectric capacitor 220 (eg, a zero net voltage is applied across the terminals of the ferroelectric capacitor 220), at zero voltage across the capacitor, the state of charge of the ferroelectric capacitor 220 can follow the path shown 320, between charge state 305-b and charge state 305-a. In other words, the charge state 305-a may represent a logic 1 state at an equal voltage across a ferroelectric capacitor 220 that is positively saturated.

Similarly, voltage 325 may be a voltage equal to or less than a negative saturation voltage, and applying voltage 325 across ferroelectric capacitor 220 may cause charge to accumulate until charge state 310-b is reached (eg, a logic 0 is written). After the voltage 325 is removed from the ferroelectric capacitor 220 (eg, a zero net voltage is applied across the terminals of the ferroelectric capacitor 220), at zero voltage across the capacitor, the state of charge of the ferroelectric capacitor 220 can follow the path shown 330, between charge state 310-b and charge state 310-a. In other words, the charge state 310-a may represent a logic 0 state at an equal voltage across a negatively saturated ferroelectric capacitor 220. In some examples, voltage 315 and voltage 325 representing the saturation voltage may have the same magnitude, but opposite polarities across ferroelectric capacitor 220 .

A voltage can also be applied across the ferroelectric capacitor 220 in order to read or sense the state stored by a ferroelectric capacitor 220 . In response to the applied voltage, the subsequent charge Q stored by the ferroelectric capacitor changes and the extent of the change may depend on the initial polarization state, the applied voltage, the inherent other capacitances or other capacitances on the access lines, and other factors. In other words, the charge state or access line voltage resulting from a read operation may depend on whether charge state 305-a, charge state 310-a, or some other charge state was originally stored and on other factors.

Hysteresis curve 300-b illustrates one example of an access operation to read stored charge states 305-a and 310-a. A read voltage 335 may be applied in the form of a voltage difference, eg, via a digit line 210 and a plate line 215 as described with reference to FIG. 2 . Hysteresis curve 300-b may illustrate a read operation where read voltage 335 is a positive voltage difference V _cap (eg, where V _bottom - V _plate is positive). A positive read voltage across ferroelectric capacitor 220 may be referred to as a "plate low" read operation, in which first a digit line 210 will be placed at a high voltage, and first a plate line 215 will be placed at a low voltage (eg , a ground voltage). Although read voltage 335 is shown as a positive voltage across ferroelectric capacitor 220, in alternative access operations, a read voltage may be a negative voltage across ferroelectric capacitor 220, which may be referred to as a "Board Height" read operation.

The read voltage 335 may be applied across the ferroelectric capacitor 220 when a memory cell 105 is selected (eg, by activating a cell select element 230 via a word line 205 as described with reference to FIG. 2). After the read voltage 335 is applied to the ferroelectric capacitor 220, charge may flow into or out of the ferroelectric capacitor 220 via the associated digit line 210 and plate line 215, and in some instances, may be based on the ferroelectric capacitor 220. Whether electrical capacitor 220 is in charge state 305-a (eg, a logic 1) or charge state 310-a (eg, a logic 0) or some other charge state results in different charge states or access line voltages.

When a read operation is performed on a ferroelectric capacitor 220 in charge state 305-a (eg, a logic 1), additional positive charge can accumulate across ferroelectric capacitor 220, and the charge state can follow path 340 until charge is reached The charge and voltage of state 305-c are terminated. The amount of charge flowing through capacitor 220 may be related to the intrinsic or other capacitance of digit line 210 (eg, intrinsic capacitance 240 described with reference to FIG. 2 ) or the intrinsic or other capacitance of other access lines (eg, signal line 260 ) . In a "board low" read configuration, a read operation associated with charge states 305-a and 305-c, or more generally a logic 1 state, may be associated with a relatively small read operation. The amount of charge transferred is associated (eg, compared to a read operation associated with charge states 310-a and 310-c, or more generally, a logic-zero state).

As shown by the transition between charge state 305-a and charge state 305-c, since the voltage change is relatively large for a given charge change at capacitor 220, the resulting voltage 350 across ferroelectric capacitor 220 may be is a relatively large positive value. Thus, after reading a logic 1 in a "plate low" read operation, the digital line voltage equal to the sum of _{VPL and Vcap (eg, Vbottom -Vplate ) at charge} state 310-c may be one relatively high voltage. Such a read operation may not change the remanent polarization of the ferroelectric capacitor 220 of the stored charge state 305-a, and thus when the read voltage 335 is removed (eg, by applying a At zero net voltage, by equalizing the voltage across ferroelectric capacitor 220 , ferroelectric capacitor 220 may return to state of charge 305 - a via path 340 . Thus, performing a read operation on a ferroelectric capacitor 220 having a state of charge 305-a with a positive read voltage can be considered a non-destructive read procedure.

When a read operation is performed on the ferroelectric capacitor 220 in the charge state 310-a (eg, a logic 0), the stored charge may reverse polarity as a net positive charge accumulates across the ferroelectric capacitor 220, and the charge The states may follow path 360 until the charge and voltage of charge state 310-c is reached. The amount of charge flowing through ferroelectric capacitor 220 may also be related to the intrinsic capacitance of digit line 210 (eg, intrinsic capacitance 240 described with reference to FIG. 2 ) or other capacitances. In a "board low" read configuration, a read operation associated with charge states 310-a and 310-c, or more generally a logic 0 state, may be associated with a relatively large The amount of charge transfer is associated (eg, as compared to a read operation associated with charge states 305-a and 305-c or, more generally, a logic 1 state).

As shown by the transition between charge state 310-a and charge state 310-c, in some cases the resulting voltage 355 can be A relatively small positive value. Thus, after reading a logic in a "plate low" read operation, the digit line voltage equal to the sum of V _PL and V _cap (eg, V _bottom - V _plate ) at charge state 310-c may be a relative low voltage.

The transition from charge state 310-a to charge state 310-d may illustrate a partial reduction or partial reversal of the polarization or charge of a ferroelectric capacitor 220 of a memory cell 105 (eg, from charge state 310 -a to charge state 310-d a decrease in the magnitude of the charge Q) associated with a sensing operation. In other words, depending on the nature of the ferroelectric material, after a read operation is performed, when the read voltage 335 is removed (eg, by applying a zero net voltage across the ferroelectric capacitor 220 , by equalizing the voltage across the ferroelectric capacitor 220 , ), the ferroelectric capacitor 220 cannot return to the state of charge 310-a. More specifically, when a net zero voltage is applied across ferroelectric capacitor 220 after one of the read operations of charge state 310-a with read voltage 335, the charge state may follow from charge state 310-c to charge state Path 365 of 310-d, which illustrates a net decrease in the magnitude of the polarization (eg, a positively polarized charge state less than initial charge state 310-a, by the difference between charge state 310-a and charge state 310-d). illustrated by the charge difference between the two). Thus, performing a read operation on a ferroelectric capacitor 220 having a state of charge 310-a with a positive read voltage can be described as a destructive read procedure. However, in some sensing schemes, a reduced remnant polarization can still be read as the same stored logic state, such as a saturated remnant polarization state (eg, supporting self-charge state 310-a and charge state 310-d Both detect a logic 0), thereby providing a degree of non-volatility for a memory cell 105 for read operations.

The location of charge state 305-c and charge state 310-c after initiating a read operation may depend on a number of factors, including the particular sensing scheme and circuitry. In some cases, the final charge may depend on the net capacitance of the digit line 210 coupled to the memory cell 105, which may include an inherent capacitance 240, integrator capacitors, and the like. For example, if a ferroelectric capacitor 220 is electrically coupled to a plate line 215 at 0V and a read voltage 335 is applied to a digit line 210, then when the memory cell 105 is selected, due to the charge from the digit line 210 The net capacitance flows to the ferroelectric capacitor 220 so the voltage of the digit line 210 can drop. Thus, in some examples, a voltage measured at a sensing element 150 may not be equal to the read voltage 335 or the resulting voltage 350 or 355, but may depend on the voltage of the digit line 210 after a period of charge sharing .

The position of charge state 305-c and charge state 310-c on hysteresis curve 300-b after initiating a read operation can depend on the net capacitance of a digit line 210 and can be determined through a load line analysis. In other words, the charge states 305-c and 310-c may be defined relative to the net capacitance of the digit line 210 or other access line (eg, a signal line 260). Thus, the voltage of ferroelectric capacitor 220 after initiating a read operation (eg, voltage 350 when reading ferroelectric capacitor 220 in stored charge state 305-a, ferroelectric capacitor 220 in reading stored charge state 310-a, The voltage 355 ) across the capacitor 220 may vary and may depend on the initial state of the ferroelectric capacitor 220 . In some examples, the amount of change in polarization of a ferroelectric capacitor 220 of a memory cell 105 due to a sensing operation can be selected according to a particular sensing scheme. In some examples, sensing operations that cause large changes in the polarization of a ferroelectric capacitor 220 of a memory cell 105 can be relatively robust to detecting a logic state of a memory cell 105 performance (eg, wider sensing margin).

can be obtained by comparing the voltage of a digit line 210 (or signal line 260, where applicable) resulting from the read operation to a reference voltage (eg, via a reference line 265 as described with reference to FIG. 2 or via a common storage device) line) to determine the initial state (eg, charge state, logic state) of the ferroelectric capacitor 220 . In some examples, the digit line voltage may be the plate line voltage and the final voltage across ferroelectric capacitor 220 (eg, voltage 350 when reading ferroelectric capacitor 220 having a stored charge state 305-a or when reading Take the sum of the voltages 355) when the ferroelectric capacitor 220 has a stored charge state 310-a. In some examples, the digit line voltage may be the difference between the read voltage 335 and the final voltage across capacitor 220 (eg, when reading ferroelectric capacitor 220 having a stored charge state 305-a (reading voltage 335 - voltage 350); when reading ferroelectric capacitor 220 with a stored state of charge 310-a (read voltage 335 - voltage 355)).

In some examples, a read operation of a memory cell 105 may be associated with a fixed voltage on a digit line 210, wherein after initiating a read operation, regardless of the initial charge state of the ferroelectric capacitor 220, A charge state of a ferroelectric capacitor 220 may be the same. For example, in a read operation with a digit line 210 held at a fixed read voltage 335, the ferroelectric capacitor may initially store a state of charge 305-a for the case where the ferroelectric 220 capacitor initially stores and the ferroelectric capacitor initially Both conditions of a charge state 310-a are stored and continue to a charge state 370. Thus, rather than using a voltage check on a digit line 210 to detect an initial charge state or logic state, in some examples, the ferroelectric capacitor 220 can be determined based at least in part on the difference in charge associated with a read operation The initial charge state or logic state. For example, as illustrated by hysteresis curve 300-b, a logic 1 may be detected based on the difference in charge Q between charge state 305-a and charge state 370 (eg, a relatively small amount of charge transfer), And a logic 0 can be detected based on a difference in charge Q between charge state 310-a and charge state 370 (eg, a relatively large amount of charge transfer).

In some examples, a charge transfer sense amplifier, a tandem device (eg, a transistor configuration in a tandem device configuration), or other signal generating circuit between a digit line 210 and a signal line 260 The system can support such a detection, where a voltage on the signal line 260 can be based, at least in part, on the amount of charge transferred from a capacitor 220 after initiating a read operation (eg, where the described charge transfer can correspond to sensing by charge transfer). a charge in a test amplifier, cascading device, or other signal-generating circuitry). In these examples, although the digit line 210 is held at a fixed voltage level, the voltage of the signal line 260 can be compared to a reference voltage (eg, at a sense amplifier 290) to determine that the ferroelectric capacitor was originally generated by the ferroelectric capacitor 220 stores the logical state.

In some instances where a digit line 210 is held at a fixed read voltage 335, whether capacitor 220 is initially in a state of charge 305-a (eg, a logic 1) or initially in a state of charge 310-a (eg, , a logic 0), a capacitor 220 can be positively saturated after a read operation. Therefore, after such a read operation, regardless of the initial logic state or the expected logic state, the capacitor 220 can be charged at least temporarily according to a logic 1 state. Therefore, when capacitor 220 is expected to store a logic 0 state, at least one rewrite operation may be required, wherein such a rewrite operation may include applying a write voltage 325 to store a logic 0 state, as shown with reference to hysteresis curve 300-a elaborate. This rewrite operation may be configured or described as a selective rewrite operation, since a rewrite voltage may not need to be applied when capacitor 220 is expected to store a logic 1 state. In some examples, such an access scheme may be referred to as a "2Pr" scheme, in which the charge difference used to distinguish a logic 0 from a logic 1 may be equal to the sum of the remanent polarizations of the two one-memory cells 105 twice (eg, a charge difference between charge state 305-a (a positive saturation charge state) and charge state 310-a (a negative saturation charge state)).

In some sensing schemes, a reference voltage can be generated such that the reference voltage is between possible voltages that can be obtained from reading different logic states (eg, a possible voltage for a digit line 210, a possible voltage for a signal line 260 voltage). For example, a reference voltage can be selected to be lower than the resulting voltage of a digit line 210 or signal line 260 when a logic 1 is read, and higher than the resulting voltage of a digit line 210 or signal line 260 when a logic 0 is read the resulting voltage. In other examples, a comparison can be made at a portion of a sense element 150 or sense amplifier 290 that is different from a portion coupled to a digit line 210 or a signal line 260, and thus a reference voltage can be selected to be used when reading Taking a logic 1 is lower than the resulting voltage at the comparison portion of sense element 150 or sense amplifier 290 and higher than the resulting voltage at the comparison portion of sense element 150 or sense amplifier 290 when a logic 0 is read. During comparison by sense element 150 or sense amplifier 290, the sense-based voltage can be determined to be higher or lower than the reference voltage, and thus the logic state (eg, a logic state) stored by memory cell 105 can be determined 0, a logic 1).

During a sensing operation, the signals obtained from reading the various memory cells 105 may vary due to manufacturing differences or operational differences between the various memory cells 105 . For example, the capacitors 220 of the various memory cells 105 can have different capacitance levels or saturation polarizations, so that a logic 1 can be associated with different charge levels for different memory cells, and a logic 0 can be Different charge levels are associated with different memory cells. In addition, intrinsic capacitance or other capacitances (eg, intrinsic capacitance 240 described with reference to FIG. 2 ) may vary from one digital line 210 to one in a memory device, and may vary from one signal line 260 to another, and in The intrinsic capacitance or other capacitances may also be different within a digit line 210 from the perspective of different memory cells 105 located on the same digit line 210 . Thus, for these and other reasons, reading a logic 1 may be associated with different voltage levels for a digit line 210 or a signal line 260 depending on the memory cell 105 (eg, the resulting voltage 350 may be read in varies from memory cell 105 to memory cell 105), and reading a logic 0 may be associated with different voltage levels depending on the memory cell 105 (eg, the resulting voltage 355 may be due to the memory being read somatic cell 105 varies).

In some examples, a reference voltage can be set between a statistical average of voltages associated with a logic 1 read and a statistical average of voltages associated with a logic read, but the The reference voltage may be relatively closer to the voltage obtained for any given memory cell 105 reading one of the logic states. The minimum difference between a voltage resulting from reading a particular logic state (eg, as a statistic for reading a plurality of memory cells 105 of a memory device) and an associated level of a reference voltage can be determined by referred to as a "minimum read voltage difference" or a "read margin," and having a low minimum read voltage difference or read margin can be used to reliably sense memory cells in a given memory device 100 The difficulty or sensitivity of the logic state of element 105 is associated.

In some memory devices 100 , charge leakage (eg, charge leakage above a threshold value) can negatively affect the ability of a memory device 100 to determine a logic state stored by a memory cell 105 . For example, for a read operation with a fixed read voltage 335 on a digit line 210 according to the hysteresis curve 300-b, when a memory cell 105 storing a logic 0 is read, charge leakage occurs may be superimposed on the charge difference between charge state 310-a and charge state 370, and charge leakage may be superimposed on charge state 305-a and charge state 370 when reading a memory cell 105 that stores a logic 1 the difference in charge between them. In some instances, when a memory cell 105 is read, the superimposed charge leakage can reduce the margin for turning on a logic 0 and a logic 1. For example, charge leakage from memory cell 105, digit line 210, or signal line 260 can increase a voltage on signal line 260 on the same side of a reference voltage when reading both a logic 1 and a logic 0 possibility above. In other words, this charge leakage can increase the likelihood that a memory cell 105 written with a logic 1 will be incorrectly read as storing a logic 0.

In some examples, a memory device 100 can identify a charge leakage associated with one or more memory cells 105 or access lines (eg, digit lines 210, signal lines 260), and can determine whether to A logic state stored by a memory cell 105 is intentionally inverted to make it more likely to properly read the logic state in the presence of charge leakage. For example, a memory device 100 may determine a logic state stored by a memory cell 105 during an access operation (eg, a read portion of an access operation, a write portion of an access operation) , and also detects whether the memory cell 105 or associated access line is associated with a charge leak (eg, during a leak detection portion of an access operation). In some cases, the memory device 100 may determine, based in part on the detection of charge leakage, a complement of the detected logic state (eg, a different logic state, an inverted logic state, an inverse logic state state) is written to a given memory cell 105 or to a group of memory cells 105 containing the given memory cell 105.

In some examples, determining the complement of the write logic state may be associated with a first amount of charge transfer based on the detected logic state (eg, for a logic 1, the difference between charge states 305-c and 305-a) A charge difference between or between charge states 370 and 305-a depends on the type of access operation or associated circuitry), and the complement of the logic state is a second greater than the first charge transfer amount The amount of charge transferred is associated (eg, for a logic 0, a charge difference between charge states 310-c and 310-a or a charge difference between charge states 370 and 310-a depends on the type of access operation or associated circuitry). For example, according to hysteresis curves 300-a and 300-b, based on identifying a memory cell 105 to store a logic 1 (eg, according to a write operation or a read operation) and detecting a A charge leakage associated with the cell 105 (eg, a charge leakage connected to a digit line 210 or a signal line 260 of the memory cell 105, a charge leakage detected during a write operation or a read operation ), the associated memory device may determine that memory cell 105 is written with a logical 0 (eg, one's complement of the identified logical 1).

Along with writing a complementary logic state (eg, a logic 0) to memory cell 105 , memory device 100 may also store the complement of the detected logic state written to at least memory cell 105 . An indication, such as a one-bit flip indication. In various examples, this one-bit flip indication may correspond to a set of one or more memory cells 105 including a memory cell 105 for which an associated charge leakage was detected (eg, a single-cell indication , corresponds to an indication of a plurality of memory cells 105 , corresponds to an indication of a column of memory cells 105 , corresponds to an indication of a page of memory cells 105 , corresponds to a group of memories that share a word line 205 One of the somatic cells 105 indicates). For example, a memory device 100 may store such an indication (eg, at a memory controller 170, at a storage component of a memory device 100 accessible to a memory controller 170) to track A memory cell 105 or group of memory cells 105 has been programmed to have a direct logic state or a complementary logic state (eg, a flipped state). Such an indication can be used in a subsequent read operation to properly interpret the changed logic state of the one or more memory cells 105 when reading information from memory device 100 (eg, based on a one-bit flip indication A determination is made whether to directly interpret the logic state stored by a memory cell 105 or to invert or otherwise alter the interpretation of the complementary logic state stored by the memory cell 105). Thus, detected charge leakage can be counteracted by changing a logic state stored by a memory cell 105 (eg, during a rewrite operation) and tracking this change in a subsequent read operation, This avoids an incorrect interpretation of one of the information stored by the memory cell 105 that could otherwise be caused by charge leakage.

4 illustrates one example of a circuit 400 that supports memory management and delete decoding, according to examples disclosed herein. Circuit 400 includes a sense amplifier 290-a for sensing a logic state of a memory cell 105-b. Charge or other signals may be communicated between sense amplifier 290-a and memory cell 105-b via a digit line 210-a and a signal line 260-a, which may The line collectively referred to as memory cell 105-b is a single access line. The signal of the access line may be illustrated by the voltage _VDL on the digit line 210-a and the _Vsig on the signal 260-a, as shown.

Example circuit 400 may include an amplifier 405 coupled between digit line 210-a and signal line 260-a, which may be enabled by voltage source 410-1. In various examples, amplifier 405 may be an instance of a signal generating component 280, or otherwise included as part of a signal generating component 280. Circuit 400 may also include: a word line 205-a for selecting or deselecting memory cell 105-b (eg, by logic signal WL); and a reference line 265-a for providing a A reference signal (eg, _Vref , as shown) is used for comparison with a signal on signal line 260-a when detecting a logic state of memory cell 105-b. Circuit 400 may also include a plate line 215-a for accessing a cell plate of a capacitor of memory cell 105-b. Thus, memory cell 105-b may be represented as coupled to a first access line (eg, digit line 210-a and signal line 260-a) and a second access line (eg, plate line 215-a) A memory cell 105 in between.

Circuit 400 may include various voltage sources 410 that may be coupled to various voltage supplies or common or virtual grounds of a memory device including one of example circuit 400 .

A voltage source 410-a may represent a common ground (eg, a chassis ground, a neutral), and may be associated with a common reference voltage having a voltage V ₀ from which other voltages are defined. The voltage source 410-a may be coupled to the digit line 210-a via the inherent capacitance 240-a of the digit line 210-a.

_A voltage source 410-b having a voltage V1 may represent a plate line voltage source, and may be coupled to memory cell 105-b via a plate line 215-a of memory cell 105-b. In some examples, voltage source 410- b to be controlled. In other words, in some examples, voltage source 410-b may be a variable voltage source, where _a voltage V1 may have multiple levels.

_A voltage source 410-c having a voltage V2 may represent a digitline voltage source, and may be coupled to digitline 210-a via a switching element 420-a, switching may be activated or deactivated by _a logic signal SW1 Assembly 420-a.

A voltage source 410-d having a voltage _V3 may represent a signal line precharge voltage source, and may be coupled to signal line 260-a via a switching element 420- _c , which may be activated or deactivated by a logic signal SW3 Switching component 420-c is activated.

A voltage source 410-e having a voltage _V4 can represent a reference signal voltage source and can be coupled to reference line 265-a via a switching element 420 _- f, switching can be activated or deactivated by a logic signal SW6 Assembly 420-f.

Voltage source 410 - 1 having a voltage V ₁₁ may represent an amplifier or tandem device voltage source, and may be coupled to amplifier 405 . In some examples, amplifier 405 may be a transistor, and voltage source 410-1 may be coupled to the gate of the transistor. Amplifier 405 may be coupled to signal line 260-a at a first terminal and to digit line 210-a at a second terminal. Amplifier 405 may provide conversion of one of charge, voltage, or other signal between digit line 210-a and signal line 260-a.

Amplifier 405 may allow a charge (eg, charge, current) to flow from signal line 260-a to digit line 210-a when the voltage on digit line 210a decreases (eg, when memory cell 105-b is selected), the amplifier 405 is enabled or enabled by voltage source 410-1. In some examples, the illustrated flow of charge across amplifier 405 may correspond to a charge transfer associated with the logic state of memory cell 105-b or one associated with accessing memory cell 105-b charge transfer. For example, when memory cell 105-b includes a ferroelectric capacitor as illustrated by hysteresis curves 300-a and 300-b, and amplifier 405 is configured to maintain the voltage of digit line 210-a at a When reading voltage 335, when memory cell 105-b stores a logic 1, a flow of charge across amplifier 405 (eg, during a read operation) may correspond to or be based at least in part on charge states 370 and 305 A charge difference Q between -a and when memory cell 105-b stores a logic 0, a flow of charge across amplifier 405 may correspond to or be based at least in part on the charge between charge states 370 and 310-a Poor Q.

The circuit 400 may also include a first integrator capacitor 430-a and a second integrator capacitor 430-b, which may each be associated with a respective A variable voltage source 450 is coupled. For example, the first integrator capacitor 430-a may be coupled to the signal line 260-a at a first terminal 431-a and to a variable voltage source 450-a at a second terminal 432-a . The second integrator capacitor 430-b may be coupled to the reference line 265-a at a first terminal 431-b and to a variable voltage source 450-b at a second terminal 432-b.

In some examples, a flow of charge across amplifier 405 may be accompanied by a voltage change on signal line 260-a. For example, when signal line 260-a is not coupled to a voltage source, a relatively small charge flow to digit line 210-a may be associated with a relatively small voltage change to signal line 260-a, while A relatively large charge flow of one of the digit lines 210-a may be associated with a relatively large voltage change of one of the signal lines 260-a. The voltage change of signal line 260-a associated with an access operation may be based on the net capacitance of signal line 260-a (eg, including integrator capacitor 430-a), wherein upon selection of memory cell 105-b, Signal line 260-a may experience a relatively small voltage change or a relatively large voltage change depending on the flow of charge across amplifier 405.

In various examples, amplifier 405 may be referred to as a "voltage regulator" or a "bias component" with respect to how amplifier 405 regulates a charge flow in response to the voltage or charge transfer of digit line 210-a. In some examples, amplifier 405 or the combination of amplifier 405 and integrator capacitor 430-a may be referred to as a charge transfer sense amplifier. Amplifier 405 can be isolated from digit line 210-a by a switch element 420 _- b, which can be activated or deactivated by a logic signal SW2. In some examples, switching element 420-b may be a row element 135, a multiplexer, or some other circuit configured to selectively couple digit line 210-a with amplifier 405 or signal line 260-a part of the system.

In the example of circuit 400, variable voltage sources 450-a may include a voltage source 410-f having a voltage _V5 and a voltage source 410 _- g having a voltage _V6 , which may be borrowed according to a logic signal SW4 The voltage source connected to the first integrator capacitor 430-a is selected by a switching element 420-d. In some examples, voltage source 410-f may be coupled to a common ground (not shown). In other examples, voltage source 410-f may be coupled with a voltage supply that provides a positive or negative voltage. Voltage source 410-g may be coupled to a voltage supply having a voltage higher than that of voltage source 410-f, which may provide a voltage boost function based on the voltage difference between voltage sources 410-g and 410-f , the voltage difference is equal to V ₆ -V ₅ or exactly equal to V ₆ when voltage source 410-f is grounded.

In the example of circuit 400, variable voltage sources 450-b may include a voltage source 410 _{- h} having a voltage V7 and a voltage source 410-i having a voltage V8, which may be borrowed according to a logic signal _SW5 The voltage source connected to the second integrator capacitor 430-b is selected by a switching element 420-e. In some examples, voltage source 410-h may be coupled to a common ground (not shown). In other examples voltage source 410-h may be coupled with a voltage supply that provides a positive or negative voltage. Voltage source 410-i may be coupled to a voltage supply having a voltage higher than that of voltage source 410-h, which may provide a voltage boost function based on the voltage difference between voltage sources 410-i and 410-h , the voltage difference is equal to V ₈ -V ₇ or exactly equal to V ₈ when voltage source 410-h is grounded.

In various examples, one or more components of circuit 400 may be included in or considered part of signal generation circuitry (eg, one of signal generation components 280 set forth with reference to FIG. 2 ). For example, voltage source 410-c, switching component 420-a, switching component 420-b, amplifier 405, voltage source 410-1, voltage source 410-d, switching component 420-c, variable voltage source 450-a Or any one or more of the integrator capacitors 430 - a may be included in a signal generating component 280 or considered to be within the illustrative boundaries of a signal generating component 280 .

Although circuit 400 is shown as including two variable voltage sources 450 , certain configurations in accordance with the present invention may include a single common variable voltage source 450 . For example, when a switching element 420 of a common variable voltage source 450 is deactivated, a first voltage source 410 of a common variable voltage source 450 may interact with the second terminal 432 of the first integrator capacitor 430-a- a and the second terminal 432-b of the second integrator capacitor 430-b are both coupled; and when the switching element 420 of the common variable voltage source 450 is activated, a second voltage source 410 of the common variable voltage source 450 can be Coupled to both the second terminal 432-a of the first integrator capacitor 430-a and the second terminal 432-b of the second integrator capacitor 430-b. In some examples using a common variable voltage source 450, due to differences in circuitry (eg, conductor length, width, resistance, capacitance) between the variable voltage source 450 and each of the integrator capacitors 430 , thus the source voltage provided to the second terminal 432-a of the first integrator capacitor 430-a may be different from the source voltage provided to the second terminal 432-b of the second integrator capacitor 430-b.

Furthermore, although variable voltage source 450 is illustrated as including two voltage sources 410 and a switching element 420, a variable voltage source 450 supporting operations herein may include other configurations, such as providing a variable voltage A voltage buffer to one or both of the second terminal 432-a of the first integrator capacitor 430-a and the second terminal 432-b of the second integrator capacitor 430-b. In other examples, a variable voltage source 450 may be replaced with a fixed voltage source or other type of voltage source. Additionally or alternatively, an access operation may omit the illustrated voltage boost operation.

To support the various operations described herein, sense amplifier 290-a may be isolated from portions of circuit 400. For example, sense amplifier 290-a may be coupled to signal line 260-a via a switching element 420-g (eg, an isolation element), which may be activated or deactivated by a logic signal ISO ₁ . Additionally or alternatively, sense amplifier 290-a may be coupled to reference line 265-a via a switching element 420-h (eg, an isolation element), which may be coupled by a logic signal ISO ₂ to activate or deactivate. Additionally, sense amplifier 290-a may be coupled with a voltage source 410-j having a voltage V9 and a voltage source 410-k having a voltage _V10 , which may be _respectively Examples of sense amplifier voltage sources 250-b and 250-c are described with reference to FIG.

Each of the logic signals illustrated in circuit 400 may be provided by a memory controller (not shown) (eg, memory controller 170 described with reference to FIG. 1). In some instances, certain logic signals may be provided by other components. For example, logic signal WL may be provided by a column decoder (not shown) that may be included in a column component 125 as described with reference to FIG. 1 .

In various examples, the voltage source 410 may be coupled with a voltage supply of a memory device including the example circuit 400 or with different configurations of common ground or virtual ground. For example, in some instances, voltage sources 410-a, 410-f, 410-h, or 410-j, or any combination thereof, may be coupled to the same ground or virtual ground, and may be access memory cells The various operations of element 105-b provide substantially the same reference voltage. In some examples, several voltage sources 410 may be coupled to the same voltage supply of a memory device. For example, in some instances, voltage sources 410-c, 410-d, 410-g, 410-i, or 410-k, or any combination thereof, may be combined with a voltage having a particular voltage, such as 1.5V, which may be referred to as "VARY") is coupled to a voltage supply. In these examples, signal line 260-a may be boosted to a voltage substantially equal to 2*VARY, or about 3.0V, prior to selecting the memory cell 105-b to be sensed via word line 205-a . In other examples, voltage sources 410-g and 410-i may be coupled to a voltage supply different from the other voltage supplies (eg, a voltage of 1.2V, which may be referred to as "PDS"), voltage source 410- g and 410-i can thus be associated with a voltage boost of 1.2V.

In some examples, voltage sources 410-j and 410-k may be selected according to certain input/output parameters. For example, according to certain input/output device specifications (eg, some DRAM specifications), voltage sources 410-j and 410-k may be substantially at 0V and 1V, respectively. Although the voltage sources 410 may be coupled to a common voltage supply or ground, due to the electrical circuit (eg, conductor length, width, resistance, capacitance) between the individual voltage sources 410 and the associated common voltage supply or common ground There are various differences, so the voltage of each of the voltage sources 410 coupled to a common voltage supply or common ground can be different.

Voltage source 410-e may provide a reference voltage for sensing the logic state of memory cell 105-b. For example, a voltage _V4 can be configured as an average value between the signal line voltages associated with sensing a logic 1 and a logic 0. In some examples, a voltage V ₄ may be set as a voltage lowered from a voltage supply of the memory device, which may be the same voltage supply to which other voltage sources 410 are coupled. For example, V4 may be provided by connecting voltage source 410-e to the same voltage supply as voltage source 410- _d , but with an intermediate electrical load between the voltage supply and voltage source 410-e (eg, , a resistive load or capacitance)).

Circuit 400 may also include a leak detection component 201-c, which may be configured to detect and memory cell 105-b, digital line 210-a, amplifier 405, or signal line 260- Charge leakage associated with one or more of a. For example, leak detection component 201-c can be configured to monitor a voltage (eg, _Vsig ) of signal line 260-a, and by identifying a voltage change of signal line 260-a or by comparing a voltage and a reference voltage or threshold (eg, using a sense amplifier, a multi-level cell (MLC) latch, a comparator) to detect a charge leakage. For example, leak detection component 201-c may be configured such that the voltage on signal line 260-a should be or is expected to be stable or above a threshold value (eg, on digital line 210-a or signal line A voltage drop on one of the signal lines 260-a is identified during a condition in which a signal on 260-a has been generated or should be stable. In some instances, identifying such a voltage drop may indicate that charge is flowing across amplifier 405 (eg, enabled by voltage source 410-1) or out of integrator capacitor 430-a, which may be responsive to digit line 210- The voltage of a drops due to charge leakage along path "A" or "B". Although illustrated as a separate component, in some examples, leak detection component 201-c may be included in sense amplifier 290-a.

In some instances, charge leakage can negatively impact the ability of sense amplifier 290 to detect a logic state stored by memory cell 105-a. Thus, in accordance with the techniques described, a memory device including circuit 400 can be configured to determine whether to store a charge leak in circuit 400 based on a detection (eg, by leak detection component 201-c) Whether a direct logic state is stored in memory cell 105-b or a complementary logic state is stored in memory cell 105-a. In some examples, circuit 400 can be configured to evaluate whether memory cell 105-b is associated with an indeterminate information state, where this evaluation can be used to improve various error repair techniques.

5 shows a timing diagram 500 illustrating the operation of an example access process to support memory management and delete decoding for a memory device according to the examples disclosed herein. The example access process is described with reference to the components of the example circuit 400 described with reference to FIG. 4 .

In the example of timing diagram 500, voltage sources 410-a, 410-f, 410-h, and 410-j are considered to be grounded, and therefore at a zero voltage (eg, V ₀ = 0 V, V ₅ = 0 V, V ₇ = 0 V and V ₉ = 0 V). However, in other examples, voltage sources 410-a, 410-f, and 410-h may be at non-zero voltages, and thus the voltages of timing diagram 500 may be adjusted accordingly. In some examples, prior to initiating operation of timing diagram 500, digit line 210-a and plate line 215-a may be controlled to the same voltage, which may minimize charge leakage across memory cell 105-b change. For example, according to the timing diagram 500, the digit line 210-a has an initial voltage of 0V, and the initial voltage of the digit line 210-a may be the same as the initial voltage of the plate line 215-a. The same in other examples, the digit line 210-a and the plate line 215-a may have some other initial voltage than the ground voltage.

At 501, the access process can include activating switch component 420- _c (eg, by activating logic signal SW3). The activation switching element 420-c may connect the voltage source 410-d and the signal line 260-a, and thus the voltage of the signal line 260-a may rise to the voltage level _V3 due to the flow of charge into the integrator capacitor 430-a. Thus, enabling switching component 420-c may initiate a precharge operation to one of integrator capacitors 430-a. For example, at 501, switching component 420-d may be deactivated such that voltage source 410-f (eg, at a ground voltage or virtual ground voltage of 0V) and second terminal 432 of integrator capacitor 430-a -a is coupled, and the voltage source 410-d is coupled to the first terminal 431-a of the integrator capacitor 430-a. Therefore, the integrator capacitor 430-a may be charged according to the voltage difference between the voltage source 410-d and the voltage source 410-f.

At 502, the access process can include enabling switch component 420 _- f (eg, by enabling logic signal SW6). Activation switching element 420-f may connect voltage source 410-e and reference line 265-a, and thus the voltage of reference line 265-a may rise to voltage level _V4 due to the flow of charge into integrator capacitor 430-b. Thus, enabling switching component 420-f may initiate a precharge operation to one of integrator capacitors 430-b. For example, at 502, switching component 420-e can be deactivated so that voltage source 410-h (eg, at a ground voltage or virtual ground voltage of 0 V) and the second terminal of integrator capacitor 430-b 432-b is coupled, and the voltage source 410-e is coupled to the first terminal 431-b of the integrator capacitor 430-b. Therefore, the integrator capacitor 430-b may be charged according to the voltage difference between the voltage source 410-e and the voltage source 410-h.

At 503, the access process can include activating switch component 420-b (eg, by activating logic signal SW2 ₎ . Activating switching component 420-b may initiate a precharge operation for one of log bit lines 210-a. For example, the activation switching element 420-b may connect the signal line 260-a and the digital line 210-a, and the digital line 210-a may be connected by the inherent capacitance 240-a and the voltage source 410-a (eg, a ground voltage or virtual ground voltage) coupling. When powered by voltage source 410-d, charge can flow through amplifier 405 and accumulate on digit line 210-a, causing the voltage on digit line 210-a to rise. The voltage of digit line 210-a may rise until the threshold voltage of amplifier 405 (eg, threshold voltage V _th,amp ) is no longer exceeded. Therefore, after the switching element 420-b is activated, the voltage of the digit line 210-a can rise to a voltage level V ₁₁ -V _{th, due to the flow of charges from the signal line (eg, powered by the voltage source 410-d), amp} , and the digit line 210-a including the intrinsic capacitance 240-a may be charged according to the voltage difference between the voltage levels V ₁₁ -V _th,amp and the voltage source 410-a (eg, 0 V). In some examples, voltage level V ₁₁ may be selected such that digit line 210-a is precharged to substantially the same level as signal line 260-a. For example, the voltage level V ₁₁ may be set at a level of V ₃ + V _th,amp , which may be provided by a voltage supply having a voltage level greater than that of the voltage source 410-d. Thus, in some examples, at 503, digit line 210-a may rise to a voltage level equal to voltage level _V3 in response to activating switching element 420-b. In some examples, after the operation of 503, the voltage between the digit line 210-a and the plate line 215-a may correspond to the read voltage 335 described with reference to FIG. 3B.

Additionally or alternatively, in some examples, digit line 210-a may be precharged by voltage source 410-c. For example, timing diagram 500 may include enabling switch element 420-a (eg, by enabling logic signal SW ₁ ) prior to enabling switch element 420-b. Activating switching component 420-a may initiate an alternate precharge operation for one of digit lines 210-a not shown in timing diagram 500. When powered by voltage source 410-c, charge may accumulate on digit line 210-a such that the voltage on digit line 210 _- a matches the voltage level V2. In some examples, voltage level V2 may be substantially equal to voltage level _V3 , such that digit line 210 _- a and signal line 260-a are precharged to the same voltage before switching element 420-b is activated. In some examples, precharging digit line 210-a with voltage source 410-c may reduce power consumption or shorten the precharging time associated with accessing memory cell 105-b. After the digit line 210-a is precharged by the voltage source 410-c, the access process may include activating the switch element 420-b (eg, by activating the logic signal SW2 ₎ to connect the signal line 260-a to the digit Line 210-a.

At 504, the access process can include deactivating switch component 420- _c (eg, by deactivating logic signal SW3). Deactivating switching element 420-c can isolate voltage source 410-d from signal line 260-a, and the voltage of signal line 260-a can be maintained at voltage level _V3 . After deactivating switching element 420-c, signal line 260-a, and thus first terminal 431-a of integrator capacitor 430-a, can float, and signal line 260-a can be based on the capacitance of signal line 260-a (including The capacitance of integrator capacitor 430-a) maintains a charge level.

At 505, the access process can include deactivating switch component 420 _- f (eg, by deactivating logic signal SW6). Deactivating switching element 420-f can isolate voltage source 410-i from reference line 265-a, and the voltage of reference line 265-a can be maintained at voltage level _V4 . After deactivating switching element 420-f, reference line 265-a, and thus first terminal 431-b of integrator capacitor 430-b, can float, and reference line 265-a can be based on the capacitance of signal line 260-a (including The capacitance of integrator capacitor 430-b) maintains a charge level.

At 506, the access process can include enabling switch component 420- _d (eg, by enabling logic signal SW4). Activating switching element 420-d may cause voltage source 410-f coupled with second terminal 432-a of integrator capacitor 430-a to voltage source 410-f coupled with second terminal 432-a of integrator capacitor 430-a A transformation of g. By connecting the second terminal 432-a of the integrator capacitor 430-a to a voltage source at a higher voltage, the charge stored by the integrator capacitor 430-a can be boosted to a higher voltage, and thus The voltage of the signal line 260-a coupled to the first terminal 431-a of the integrator capacitor 430-a can rise to the voltage level ( _V3 + _V6 ). Thus, activation of switching component 420-d may initiate boost operation of one of integrator capacitors 430-a.

At 507, the access process can include enabling switch component 420 _- e (eg, by enabling logic signal SW5). Activating switching element 420-e may cause voltage source 410-h coupled to second terminal 432-b of integrator capacitor 430-b to voltage source 410-h coupled to second terminal 432-b of integrator capacitor 430-b A transformation of i. By connecting the second terminal 432-b of the integrator capacitor 430-b to a voltage source at a higher voltage, the charge stored by the integrator capacitor 430-b can be boosted to a higher voltage, thus The voltage of the reference line 265-a, which is coupled to the first terminal 431-b of the integrator capacitor 430-b, may rise to the voltage level ( _V4 + _V8 ). Thus, activation of switching component 420-e may initiate a boost operation of one of integrator capacitors 430-b.

At 508, the access process may include selecting memory cell 105-b (eg, by enabling a word line via logic signal WL). Selecting memory cell 105-b may cause a capacitor of memory cell 105-b to be coupled to digit line 210-a. Thus, charge may be shared among memory cell 105-b, digit line 210-a, and signal line 260-a, which may depend on the logic state stored in memory cell 105-b (eg, the charge state , polarization state).

For example, when memory cell 105-b stores a logic 1, the capacitor of memory cell 105-b may store a positive charge (eg, a state of charge 305-a as described with reference to FIGS. 3A and 3B ) ). Thus, when memory cell 105-b is selected to store a logic 1, a relatively small amount of charge can flow from digit line 210-a to memory cell 105-b. As charge flows from digit line 210-a to memory cell 105-b, the voltage on digit line 210-a may drop, which may allow the threshold voltage of amplifier 405 to be exceeded. When the threshold voltage of amplifier 405 is exceeded, according to the characteristics of amplifier 405, charge may flow from signal line 260-a (eg, from integrator capacitor 430-a) across amplifier 405 to digit line 210-a with a relatively small The amount of charge flows from voltage source 410-1 across amplifier 405 to digit line 210-a. Therefore, charge can flow to digit line 210-a until the voltage of digit line 210-a returns to a voltage level equal to V ₁₁ -V _th,amp . When the memory cell 105-b storing a logic 1 is selected, the signal line 260-a may be after the memory cell 105-b is selected because a relatively small amount of charge flows into the memory cell 105-b. A relatively small voltage drop is experienced, as illustrated by the voltage V _sig,1 .

Alternatively, when memory cell 105-b stores a logic 0, the capacitor of memory cell 105-b may store a negative charge (eg, charge state 310- as described with reference to FIGS. 3A and 3B ). a). Therefore, when memory cell 105-b is selected to store a logic 0, a relatively large amount of charge can flow from digit line 210-a to memory cell 105-b. Thus, signal line 260-a may experience a relatively large voltage drop (as illustrated by voltage V _sig,0 ) as charge flows through amplifier 405 returning the digit line to voltage level V ₁₁ -V _th,amp , so that the threshold voltage V _th,amp of the amplifier 405 is no longer exceeded. In some instances, selecting memory cell 105-b to store a logic 0 may result in a partial loss of the polarization of a capacitor of memory cell 105-b. In the example employing a 2Pr sensing operation, selecting memory cell 105-b to store a logic 0 may cause the saturation polarization of the capacitor of memory cell 105-b to be reversed such that the Two times the associated amount of charge flows into memory cell 105-b. In either case, selecting a memory cell 105-b to store a logic 0 according to the present example may involve a subsequent refresh or rewrite operation.

At 509, the access process can include deactivating switch component 420- _d (eg, by deactivating logic signal SW4). Deactivating switching component 420-d may cause a voltage source from voltage source 410-g coupled to second terminal 432-a of integrator capacitor 430-a to a voltage source coupled to second terminal 432-a of integrator capacitor 430-a A transformation of 410-f. By connecting the second terminal 432-a of the integrator capacitor 430-a to a voltage source at a lower voltage, the charge stored by the integrator capacitor 430-b can be shifted to a lower voltage, and thus with The voltage of the signal line 260-a coupled to the first terminal 431-a of the integrator capacitor 430-a can drop to the voltage level (V6 _{- V5} , or in the event that the voltage source 410-f is coupled to a common ground which happens to be V ₆ ). Thus, deactivating switching element 420-d can initiate a shift operation of integrator capacitor 430-a, which can reduce the voltage on signal line 260-a to a level that can be read by sense amplifier 290-a . For example, after the shift operation at 509, _Vsig,1 sensed by sense amplifier 290-a may be about 1.5V, and _Vsig,0 sensed by sense amplifier 290-a may be about 1.2V .

At 510, the access process can include deactivating switch component 420 _- e (eg, by deactivating logic signal SW5). Deactivating switching element 420-e may cause voltage source 410-i coupled to second terminal 432-b of integrator capacitor 430-b to voltage source 410 coupled to second terminal 432-b of integrator capacitor 430-b A shift for -h. By connecting the second terminal 432-b of the integrator capacitor 430-b to a voltage source at a lower voltage, the charge stored by the integrator capacitor 430-b can be shifted to a lower voltage, and thus the integrator The voltage of the reference line 265-a coupled to the first terminal 431-b of the capacitor capacitor 430-b may drop to the voltage level (V8 _- V7, or in the event that the voltage source 410- _h is coupled to a common ground is exactly V ₈ ). Thus, deactivating switching element 420-e can initiate a shift operation of integrator capacitor 430-b, which can reduce the voltage on reference line 265-a to a level that can be read by sense amplifier 290-a . For example, after the shift operation at 510, sense amplifier 290-a senses that _Vref may be about 1.35V.

At 511, the access process may include isolating sense amplifier 290-a from signal line 260-a by deactivating switching component 420-g (eg, by deactivating logic signal _ISOi ). Isolating sense amplifier 290-a from signal line 260-a may allow sense amplifier 290-a to store and signal line voltages (eg, before the logic state stored in memory cell 105-b is determined) At the first terminal 131-b of 290-a, V _A = V _sig ) is associated with a voltage or charge.

At 512, the access process may include isolating sense amplifier 290-a from reference line 265-a by deactivating switching component 420-h (eg, by deactivating logic signal _ISO2 ). Isolating sense amplifier 290-a from reference line 265-a may allow sense amplifier 290-a to store and reference line voltages (eg, before the logic state stored in memory cell 105-b is determined) At the second terminal 132-b of 290-a, V _B = V _ref ) is associated with a voltage or charge.

At 513, the access process may include detecting a difference between the voltages stored at the first terminal 131-b and the second terminal 132-b of the sense amplifier 290-a, which may be referred to as "latching" The result of taking memory cell 105-b or detecting the logic state stored by memory cell 105-b. For example, if the signal stored at the first terminal 131-b is greater than the signal stored at the second terminal 132-b (eg, V _A > V _B ), the sense amplifier 290-a may output a high equal to the sensing element A voltage of the voltage source (eg, V ₁₀ , associated with voltage source 410-k, corresponding to a logic 1). If the signal stored at the first terminal 131-b is less than the signal stored at the second terminal 132-b (eg, V _A < V _B ), the sense amplifier 290-a may output one of the low voltage sources equal to the sensing element _A voltage (eg, V9, associated with voltage source 410-j, corresponding to a logic 0). The detected logic state may be output to an input/output component 160 of a memory device 100 including circuit 400, a memory controller 170, or other components for subsequent operations.

In some examples, charge may leak from one portion of circuit 400 to another during operation of timing diagram 500 . In one example, the charge leakage may follow a path "A" from digit line 210-a to plate line 215-a, which path "A" may be illustrated through memory cell 105-b (eg, across A charge leaks from a dielectric portion of a capacitor 220 of the memory cell 105-b or around a dielectric portion of the capacitor). In another example, leakage may follow a path "B" from digitline 210-a to voltage source 410-a, which path "B" may illustrate from digitline 210-a to a ground voltage source or reference Voltage or charge leakage of a component (eg, a backplane leakage). Other examples not illustrated may include other leakage paths that permit any other charge transfer between digit line 210 - a and another component of circuit 400 or between signal line 260 - a and another component of circuit 400 . In some examples, charge leakage in circuit 400 can be driven by a voltage difference between digit line 210 and plate line 215, and can be relatively high when cell select element 230-a is activated (eg, with specific cell charge leakage associated with memory cell 105-b). Therefore, after 508, when word line 205-a is enabled and the difference between _VDL and _VPL is relatively large (eg, when memory cell 105-b is at full bias), charge leakage can be caused by relatively high.

In some examples, this charge leakage may alter one or more of the signals illustrated in timing diagram 500 . For example, this charge leakage may be associated with additional charge transfer across amplifier 405 when digit line 210-a is maintained at a particular voltage level, which may be accompanied by a lower voltage than that shown in timing diagram 500 A voltage _Vsig of one of the signal lines 260-a. When memory cell 105-b stores a logic 1, for example, this leakage can thus be accompanied by a reduced difference between _Vsig,1 and _Vref , which can be reduced associated with reading a logic 1 One read margin, or this leakage, can cause _Vsig,1 to drop below _Vref , which can cause memory cells 105-b to be written with a logic 1 to be incorrectly read as a logic 0. Thus, to improve the likelihood of correctly reading memory cell 105-b, in some examples, an access operation may include determining to perform a direct write based at least in part on the charge leakage detected in circuit 400 The operation (eg, a direct overwrite operation) is also a complementary write operation (eg, a complementary overwrite operation).

At 514 , the access operation may include detecting a charge leakage in circuit 400 . For example, leak detection component 201-c may be configured to monitor the voltage of signal line 260-a, which may include detecting a drop in _Vsig (eg, a change in _Vsig , a time derivative of _Vsig ) or voltage) or compare _Vsig to a threshold (eg, a charge detection reference voltage, which may be a configurable voltage other than _Vref ). In one example, leak detection component 201-c can be configured to detect a change in _Vsig after isolating signal line 260-a from sense amplifier 290-a (eg, after 511, the difference between _Vsig a drop, as illustrated), this may include a comparison at 513 between Vsig of signal line 260- _a and _VA of sense amplifier 290-a. However, this is only one example of how charge leakage may be detected in circuit 400 . For example, according to a different set of operations, the signal line 260-a may be biased to certain voltages after isolating the sense amplifier 290-a (eg, after 511), where regardless of the memory cell 105- Whether b stores a logic 0 or a logic 1 voltage can be the same. In another example, signal line 260-a can be recoupled to sense amplifier 290-a (eg, by enabling switching element 420-g via logic signal ISO ₁ after detecting a logic state at 513), which Signal line 260-a may be concomitantly biased to a voltage that may or may not be the same depending on the logic state originally stored by memory cell 105-b. In various examples, the voltage of signal line 260-c may drop from this set voltage due to charge leakage and corresponding charge transfer across amplifier 405, which may be detected at 514 by leakage detection component 201-c . In some examples, such a leak detection may be performed at integrator capacitor 430-a, which may be associated with detecting a voltage or change in voltage across integrator capacitor 430-a or with detecting integration A charge state or charge state change of the capacitor capacitor 430-a is associated. In some examples, leak detection component 201-c or some other component may store at 514 an indication of whether a leak was detected (eg, a temporary indication associated with an access operation of timing diagram 500, a specific cell indication, a specific access line indication).

At 515 , the access operation can include determining whether to perform a direct rewrite operation or a complementary rewrite operation, which can be based, at least in part, on whether charge leakage is detected in circuit 400 . For example, if a charge leak is detected at 514, the access operation may determine to write one's complement of the logic state detected in memory cell 105-b (eg, at 513).

In some examples, determining whether to write a complementary logic state may be further based on a particular logic state detected in memory cell 105-b. For example, when charge leakage is detected at 514, it may be preferable for memory cell 105-b to store a logic state associated with a relatively large charge transfer. Taking hysteresis curves 300-a and 300-b as examples, a logic 0 may be associated with a relatively large charge transfer (eg, a charge difference between charge states 310-a and 370), and a logic 1 may be associated with A relatively small charge transfer (eg, a charge difference between charge states 305-a and 370) is associated. Thus, according to this example, if a charge leak is detected at 514 (eg, based on accessing memory cell 105-b), it may be preferable for memory cell 105-b to store a logic 0. Thus, at 515, when it is detected that memory cell 105-b has stored a logic 1 (eg, at 513), it may be determined to write a complement of the stored logic state (eg, with a logic 0) overwrites memory cell 105-b), and when detecting that memory cell 105-b has stored a logic 0 (eg, at 513), may decide to write directly to the stored logic state (eg, with A logic 0 overwrites memory cell 105-b). In some examples, such a determination may include identifying that self-memory cell 105-b may be positively saturated due to the operations of 508-515 (eg, charged at least temporarily according to a logic 1, such as the charge described with reference to FIG. 3B ) State 370) is followed by a selective overwrite operation. In some examples, a memory device 100 may store an indication of whether to determine at 514 to write a complementary logic state to memory cell 105-b. However, in some instances, the indication may not be determined, stored, or validated until after the corresponding write operation is performed or confirmed (eg, in a subsequent operation).

In some instances, the determination of whether to perform a direct overwrite operation or a complementary overwrite operation may be based on a group of memory cells 105, such as a column of memory cells sharing wordline 205-a with memory cell 105-b 105. A page of memory cells 105 or some other group of memory cells 105. For example, when determining whether to perform a direct overwrite operation or a complementary overwrite operation corresponding to a group of memory cells 105, circuits 400 (not shown) associated with respective memory cells 105 in the group may be addressed. Multiple components (eg, parallel sense amplifier 290, parallel signal line 260, parallel amplifier 405, parallel bit line 210) shown) repeat (eg, simultaneously during overlapping time intervals) the operations of 501-514. In these examples, determining whether to perform a direct rewrite operation on the set of memory cells 105 or a complementary rewrite operation on the set of memory cells 105 may be based, at least in part, on correlating storage with relatively low charge transfer The number of leaky memory cells 105 or corresponding access lines (eg, digit line 210, signal line 260) associated with one logic state is minimized.

For example, continuing with the example illustrated by hysteresis curves 300-a and 300-b, it may be preferable that those of the set associated with detected charge leakage above a threshold value will store a The number of logic 1 memory cells 105 is minimized. Thus, at 515, a memory device 100 (eg, a memory controller 170) may digitally combine the results of charge leakage detection for a group of memory cells 105 to assign a logic 0 to as many as possible The leaky memory cell 105 or corresponding access line has a data pattern for writing back to the set of memory cells 105. In these examples, memory cells 105 or corresponding access lines that are not associated with a detected charge leakage may be ignored when combining bits because storing one logic state or the other may not Negatively affects these memory cells 105 or corresponding access lines.

Since a determination of whether to perform a direct rewrite operation or a complementary rewrite operation can be based on a set of memory cells 105, the particular determination of a logic state of a rewrite operation of memory cell 105-b need not be based solely on whether Charge leakage is detected at 514 for memory cell 105-b. For example, when it is determined that other memory cells 105 in a group including memory cell 105-b benefit from performing a complementary rewrite operation, even if memory cell 105-b or associated memory is detected There is no charge leakage in fetching, and a memory device 100 can still determine to write a complement of a logic state detected for memory cell 105-b. In other words, according to determinations made for the group of memory cells 105, although no charge leakage was detected for that particular memory cell 105, writing to a logic state of a particular memory cell 105 in the group Still can be one's complement of the detected logic state of a particular memory cell 105 .

In some examples, the techniques described may be combined with other error correction techniques, such as an error correction code (ECC), a single cell ECC (eg, ECC1), or single error correction (SEC). In some examples, this combination can support up to 3-bit correction for a particular row or page access scheme. In other words, when using the described techniques for memory management based on detected charge leakage, the result can be that using a 1-bit ECC engine is equivalent to a 3-bit ECC.

In one example in which ECC is combined with the described techniques to invert data based on charge leakage detection, a page access operation may be associated with one of the page having a detected charge leakage above a threshold value Individual memory cells 105 or corresponding access lines (eg, digit lines 210, signal lines 260) are associated. In these examples, when memory cell 105 is initially associated with a logic state associated with a relatively small charge transfer, a memory device 100 may decide to invert the page of data (eg, transfer the memory cell A logical 1 of cell 105 inverts to a logical 0 of memory cell 105, and correspondingly inverts the other logical states of other memory cells 105 in the page). Alternatively, when the memory cell 105 is initially associated with a logic state associated with a relatively small charge transfer, a memory device 100 may decide not to invert the page of data, but instead read the memory The voxel 105 relies only on ECC to correct a possible error. When memory cell 105 is initially associated with a logic state associated with a relatively large charge transfer, memory device 100 may decide not to invert the page's data, since charge leakage may not affect read memory Cell 105 has a negative impact. Thus, in each of these situations, the memory device 100 can properly read the pages in the page despite charge leakage above the threshold of a single memory cell 105 or corresponding access line Memory cell 105.

In another example of combining ECC with the described techniques to invert data based on charge leakage detection, a page access operation can be combined with two of the pages that have a detected charge leakage above a threshold Each memory cell 105 or corresponding access line (eg, digit line 210, signal line 260) is associated. In these examples, when the two memory cells 105 are initially associated with a logic state associated with a relatively small charge transfer, a memory device 100 may determine to invert the page's data (eg, Inverting a logic 1 of memory cell 105 to a logic 0 of memory cell 105 and correspondingly inverting the other logic states of other memory cells 105 in the page). Therefore, none of the memory cells 105 associated with a charge leakage will store a logic state associated with a relatively small charge transfer. When the two memory cells 105 are initially associated with different logic states (eg, one is associated with a relatively large charge transfer and the other is associated with a relatively small charge transfer), a memory device 100 may determine that the opposite The data on the page may or may not be reversed because, whether reversed or not, one of the read memory cells 105 may not be negatively affected by charge leakage (eg, due to storage and relatively large charge transfer is associated with a logic state), and can be corrected by ECC to correct the read of the other of the memory cells 105 to handle a problem due to charge leakage when reading the memory cell 105 may be wrong. When two memory cells 105 are initially associated with a logic state associated with a relatively large charge transfer, the memory device 100 may decide not to invert the page's data, since charge leakage may not affect the read The two memory cells 105 are negatively impacted. Thus, in each of these situations, the memory device 100 can properly read the memory in the page despite the charge leakage being above the threshold of the two memory cells 105 or corresponding access lines Soma 105.

In another example of combining ECC with the described techniques to invert data based on charge leakage detection, a page access operation can be three times associated with a page that has a detected charge leakage above a threshold Memory cells 105 or corresponding access lines (eg, digit lines 210, signal lines 260) are associated. In these examples, when three memory cells 105 are initially associated with a logic state associated with a relatively small charge transfer, a memory device 100 may decide to invert the page of data (eg, store the memory A logic 1 of the memory cell 105 is inverted to a logic 0 of the memory cell 105, and correspondingly the other logic states of the other memory cells 105 in the page are inverted). Thus, none of the memory cells 105 associated with a charge leakage will store a logic state associated with a relatively small charge transfer.

When the three memory cells 105 are initially associated with different logic states (eg, one is associated with a relatively large charge transfer and the other two are associated with a relatively small charge transfer), a memory device 100 may determine Reverse the data on this page or not. For example, when both of the memory cells 105 store a logic state associated with a relatively large charge transfer, the memory device may decide not to invert the page of data, and when the memory cells Both of cells 105 store a logic state associated with a relatively small charge transfer that the memory device can determine to reverse the page of data. In either case, a subsequent read of the page can rely on ECC to handle a possible error due to charge leakage when reading one of the memory cells 105 (eg, subsequent storage in the memory cell 105 one of a logic state associated with a relatively small charge transfer). When the three memory cells 105 are initially associated with a logic state associated with a relatively large charge transfer, the memory device 100 may decide not to invert the page's data, since charge leakage may not affect the read Taking the three memory cells 105 has a negative impact. Thus, in each of these cases, the memory device 100 can properly read the pages in the page despite charge leakage above the threshold of three memory cells 105 or corresponding access lines Memory cell 105.

At 516, the access operation may include performing a write operation (eg, a write portion of the access operation, a rewrite portion of the access operation). For example, returning to the example of the hysteresis curve 300-a, at 514, when it is determined that the memory cell 105-b stores a logic 1, the access operation may include applying a voltage 315 (eg, a plate low write input voltage, where V _DL,w1 > V _PL,w1 ), or when it is determined that the memory cell 105-b stores a logic 0, the access operation may include applying a voltage 325 (eg, a board high write voltage, where V _PL,w0 > V _DL,w0 ). In some examples, applying a voltage 315 at 516 may be omitted because memory cell 105-b may have stored a positive saturated charge state (eg, a logic 1 due to one of the operations of 508-515 or more). In these examples, plate line 215-a can still be set to a high voltage (eg, a voltage associated with writing a logic 0), but digit line 210-a can also be set to a high voltage ( For example, where V _DL = V _PL ), such that the voltages of the memory cells 105 are equalized and thus maintain a positive saturated charge state (eg, logic 1).

In some examples, performing the write operation at 516 may be based, at least in part, on determining the one's complement of the identified logical state stored by the memory cell 105-b (eg, at 513). In these examples, the write operation at 516 may include an inversion of one of the aspects of the memory cell write as compared to when it was determined not to write the complement of the identified logic state. For example, when determining to write one's complement of the identified logic state, the write operation at 516 may include swapping the voltage or the connected voltage source (eg, swapping the relationship between plate line 215-a and digit line 210-a). a voltage or voltage source in between), grounding the digit line 210-a that is otherwise held at a relatively high voltage, or performing some other logical inversion of another component that manages the write or rewrite operation of 516.

Although illustrated as separate operations occurring at different times, certain operations may occur concurrently, or in a different order. In some instances, it may be advantageous to initiate various operations simultaneously to reduce the amount of time involved in sensing a logic state of memory cell 105-b. For example, the initial precharge at 501 and 502 may occur in a reverse order or simultaneously (eg, when logic signals _SW3 and _SW6 are driven as a common logic signal). Furthermore, connecting digit line 210-a to signal line 260-a at 503 may occur before 501 or 502, or all three operations may occur simultaneously. Boosting signal line 260-a at 506 and boosting reference line 265-a at 507 may also occur in a reverse order or simultaneously (eg, when using a common variable voltage source 450, or when driving When the logic signals _SW4 and _SW5 are used as a common logic signal). Similarly, shifting signal line 260-a at 509 and shifting reference line 265-a at 510 may also occur in a reverse order or simultaneously. In some examples, isolating sense amplifier 290-a and signal line 260-a at 511 and isolating sense amplifier 290-a and reference line 265-a at 512 may occur in a reverse order or concurrently (eg, , when the drive logic signals ISO ₁ and ISO ₂ are used as a common logic signal).

In some examples, the pressurization and displacement of reference line 265-a may be completely removed, and thus the operations at 507 and 510 may be omitted. Thus, in some examples of the described techniques, circuit 400 may omit second integrator capacitor 430-b and second variable voltage source 450-b and still be able to access memory cell 105-b when accessing memory cell 105-b. Self-boosting is supported for signal generation. Additionally or alternatively, in some examples, the boosting and shifting of signal line 260-a may be entirely removed, and thus the operations at 506 and 509 may be omitted. Thus, in some examples of the described techniques, circuit 400 may omit first integrator capacitor 430-a and first variable voltage source 450-a.

The order of operations shown in timing diagram 500 is for illustration purposes, and various other orders and combinations of steps may be implemented in support of the techniques described. Furthermore, the timing of operations of timing diagram 500 is also for illustrative purposes and is not intended to indicate a particular relative duration between one operation and another. Various operations may occur for one of relatively shorter or relatively longer durations than illustrated in various examples in accordance with the present invention.

Transitions of logic signals of timing diagram 500 illustrate transitions from one state to another, and typically reflect an enabled or enabled state (eg, state "0") and a disabled or deactivated state associated with a particular numbered operation A transition between states (eg, state "1"). In various examples, a state may be associated with a particular voltage of a logic signal (eg, a logic input voltage applied to a gate of a transistor used as a switch), and the voltage goes from one state to another The change is not instantaneous. Rather, in some examples, a voltage associated with a logic signal can follow a curve from one logic state to another logic state over time. Thus, the transition shown in timing diagram 500 does not necessarily indicate an instantaneous transition. Furthermore, the initial state of a logic signal associated with a transition at a numbered operation may have been reached at various time periods prior to the numbered operation, but still support the stated transition and associated operation.

Although the example of timing diagram 500 illustrates how the described techniques for leak detection and logic inversion may be applied in a read operation, the described techniques may also be combined with a write operation. For example, leak detection operations (eg, the leak detection operations described herein) may be performed before writing a logic state to a memory cell 105 or a group of memory cells 105 (eg, at During a leak detection portion of a write operation, during an operation used to determine which type of write operation to perform). In some instances, therefore, a write operation may be modified to perform based on a determination of whether to perform a direct write operation or a complementary write operation to memory cell 105 or a group of memory cells 105 (eg, Based on whether charge leakage is detected before writing a logic state to a memory cell, and whether the logic state is associated with a relatively large amount of charge transfer or a small amount of charge transfer).

In another example, leak detection operations (eg, the leak detection operations described herein) may be performed after writing a logic state to a memory cell 105 or a group of memory cells 105 (eg, , during a leak detection portion of a write operation, during a write validation or validation portion of a write operation), and thus, can be written to memory cell 105 or a group of memory cells 105 according to logic Whether the state is successfully modified to perform the write operation. For example, after performing a direct write operation to a page of memory cells 105, if charge leakage is detected in the page of memory cells 105 and the sum of the charge leakage and a relatively small amount of charge transferred An associated logic state is written to a leaky memory cell 105 or associated with a corresponding access line, then the write operation can be modified to include performing a complementary write operation on the page of memory cells 105 (eg, during a write into the rewrite section of one of the operations).

6 shows a flowchart illustrating a method 600 of memory management supporting charge leakage according to examples disclosed herein. The operations of method 600 may be implemented by a memory device 100 or components thereof as described herein. In some examples, memory device 100 may include a set of memory cells 105 (eg, a plurality of memory cells 105 , an array of memory cells 105 ), and each of memory cells 105 A respective storage element (eg, a respective capacitive storage element) may be included. The operations of method 600 may be carried out by various components or circuitry coupled to a set of memory cells (eg, coupled to a column of memory cells 105, a page of memory cells 105), including with reference to FIGS. 1-5 the example described. In some examples, the operations of method 600 may illustrate an access operation (eg, a read operation, a write operation, a rewrite operation, a renew operation) of a set of memory cells 105, or some thereof some parts.

At 605 , the method can include determining a respective logic state of one of each of the set of memory cells 105 . In some examples, determining the respective logic state may be based at least in part on being in the storage element of each of the set of memory cells 105 and a respective one of the set of access lines (eg, digit line 210, signal line 260), or some other operation involving determining the respective logic state that has been stored by memory cell 105 (eg, in a read operation, in a rewrite operation, in a repeat operation new operation). In some examples, this coupling can be based on activating a common select line (eg, a common word line 205). In some examples, determining the respective logical state may be based, at least in part, on some other determination of the logical state to be stored by memory cell 105 (eg, in a subsequent write to the memory cell, in a subsequent in a write operation, in an operation that does not involve accessing memory cell 105). For example, the logic state of each of memory cells 105 may be provided from a memory controller 170 as part of a write operation (eg, writing or overwriting information to memory cells 105 ) .

At 610, the method can include determining whether a threshold charge leakage is detected on one or more of a set of access lines (eg, digit line 210, signal line 260). In some examples, each of memory cells 105 may be coupled with a respective access line of a set of access lines. In some examples, the determination of whether a threshold amount of charge leakage is detected may be performed after coupling the memory cell 105 with a respective access line in a set of access lines. In some instances, charge leakage may have been detected in some other previous operation. In some examples, the detection of charge leakage can be triggered by initiating an access operation (eg, a read operation, a write operation, a rewrite operation, a new operation).

In some examples, determining the respective logic state of each of a set of memory cells at 605 may include latching a signal of a respective signal line 260 associated with the respective memory cell 105 ; and determining whether a threshold charge leakage amount is detected at 610 may be based on comparing a voltage of the respective signal line 260 to a threshold voltage after latching. In some examples, determining whether a threshold charge leakage amount is detected may be based on detecting (eg, directly or indirectly) across a signal generation component 280 that is electrically connected to a respective one of the set of access lines (eg, a transistor, an amplifier 405) a charge flow.

At 615 , the method can include selecting a direct write operation or a complementary write operation for the set of memory cells 105 . In some examples, selecting a direct write operation or a complementary write operation may be based on whether a threshold amount of charge leakage is detected on one or more of the set of access lines. In some examples, the method 600 can be associated with a first logic state corresponding to a first amount of charge transfer and a second logic state corresponding to a second amount of charge transfer, the second amount of charge transfer being low in the first charge transfer amount. In these examples, selection of a direct write operation or a complementary write operation may be based on the set of access lines associated with a detection of a threshold charge leakage and coupled with a memory cell storing the first logic state a number and a number of the set of access lines associated with a detection of threshold charge leakage and coupled to a memory cell storing the second logic state. In some examples, the selection at 615 may be based, at least in part, on whether the described techniques are combined with another error correction scheme (eg, ECC or ECC1). In some examples, method 600 may further include storing an indication of whether to select a direct overwrite operation or a complementary overwrite operation. The method may proceed to 625 when a direct write operation is selected to be performed, and the method may proceed to 630 when a complementary write operation is selected to be performed.

At 620, the method can include performing a direct write operation. For example, performing a direct write operation may include writing the respective logic state determined at 605 to each of the set of memory cells 105 . In some examples, method 600 may further include storing an indication to perform a direct write operation.

At 625, the method can include performing a complementary write operation. For example, performing a complementary write operation may include writing to each of the set of memory cells 105 one's complement in the respective logic state determined at 605 . In some examples, method 600 may further include storing an indication to perform a complementary write operation.

According to an example of method 600, a set of memory cells 105 can be written to using a direct write operation or a one's complement write operation, which can be made based at least in part on whether a threshold charge leakage is detected. A choice between direct write operations and complementary write operations. By performing operations, such as the operations of method 600 , a memory device 100 is more likely to properly read information from the set of memory cells 105 . For example, the operations of method 600 may be performed in a manner that minimizes the number of memory cells 105 or associated access lines storing a logic state corresponding to a relatively small charge transfer, such that a logic state may be More prone to being misread or being read with a read margin lower than one of the logic states associated with relatively higher charge transfer.

7 illustrates a graph 700 including the distribution of a read characteristic associated with different information states that can support erasure decoding of a memory device, according to examples disclosed herein. Graph 700 may illustrate various read characteristics (eg, read signals) when accessing a representative group of memory cells 105 of a memory device 100 with respect to a standard deviation σ or some other probabilistic measure. For example, the illustrated read characteristics may refer to memory cells 105 (eg, capacitive memory cells, ferroelectric memory cells, material memory cells) written to a respective information state based on accesses cell) generated read voltage, read current, detected resistance, threshold voltage, or other types of read signals. For illustration purposes, the sigma axis may be a non-linear axis such that a normal distribution of the read characteristics may be illustrated in the graph 700 as a linear distribution. In some instances, the distribution of the graph 700 may be referred to as a Gaussian distribution.

Distribution 710 may illustrate a first distribution of read characteristics when storing a first information state (eg, a first logic state, a first charge state, a first material state, a logic 0). In some examples, distribution 710 may illustrate a distribution of voltages at a signal line 260 when a memory cell 105 (eg, capacitor 220 ) written with a logic 0 is read. Distribution 710 may be associated with a lower boundary or edge (eg, edge 711), which may be referred to as "E1," and an upper boundary or edge (eg, edge 712), which may be referred to as "E2." Distribution 710 may illustrate various interpretations of a statistical distribution, such as a span of six standard deviations (eg, 6 σ), a span of twelve standard deviations (eg, twelve σ), or a representative set of memory Cell 105 is written with a span between a minimum level and a maximum level of a read characteristic at a logic 0.

Distribution 720 may illustrate a second distribution of read characteristics when storing a second information state (eg, a second logic state, a second charge state, a second material state, a logic 1). In some examples, distribution 720 may illustrate a distribution of voltages at a signal line 260 when a memory cell 105 (eg, capacitor 220) with a logic 1 is read and written. Distribution 720 may be associated with a lower boundary or edge (eg, edge 721), which may be referred to as "E3," and an upper boundary or edge (eg, edge 722), which may be referred to as "E4." Distribution 720 may illustrate various interpretations of a statistical distribution, such as a span of six standard deviations (eg, six σ), a span of twelve standard deviations (eg, twelve σ), or a representative set of memory The read characteristic of cell 105 when written with a logic 1 is a span between a minimum value and a maximum value.

In some examples, a memory device 100 may compare a read characteristic to a threshold to assess whether a memory cell 105 stores one information state or another information state. For example, when the illustrated read characteristic refers to a voltage on a signal line 260, a memory device 100 may include a reference element 285 between distribution 710 and distribution 720 (eg, A reference voltage (eg, a voltage demarcation) between edge 712 and edge 721) biases a reference line 265 to distinguish between a logic 0 and a logic 1. When a voltage (eg, a voltage of a first node 291 ) based on a signal line 260 accessing a memory cell 105 is lower than a reference voltage (eg, a voltage of a second node 292 ), the memory The device 100 can determine that the memory cell 105 stores a logic 0, and when a voltage based on a signal line 260 accessing a memory cell 105 is higher than a reference voltage, the memory device 100 can determine that the memory cell 105 A logical 1 is stored. The read margin in this scenario may include an E2 margin associated with a difference between the reference voltage and edge 712 and an E3 margin associated with a difference between the reference voltage and edge 721 .

In some cases, however, a read characteristic can be represented according to distributions 710 and 720 when a memory cell 105 is accessed. For example, in the presence of charge leakage, a voltage on the signal line 260 based on accessing a memory cell 105 may be lower than expected. In some cases, this leakage can cause a read voltage to be written to a memory cell 105 with a logic 1 to drop below a reference voltage, causing the memory cell 105 to be incorrectly determined to be written There is a logic 0 (eg, illustrating a reduction or elimination of one of the E3 margins). Thus, according to these and other examples, leakage conditions may be associated with an indeterminate or indeterminate logic state or other reduction or elimination of a read margin. In some examples, a leak detection component 201 (eg, the leak detection component described with reference to FIG. 2 ) may be used in a circuit to identify a logic state that may be correlated with a possibly indeterminate or indeterminate logic state (eg, a read The operation will detect a logic 0 (one increased probability) associated with the memory cell 105 or access line (eg, signal line 260, digital line 210).

In another example of techniques that can support identifying conditions associated with a deletion or indeterminate or indeterminate information state, a memory device 100 can include a plurality of read characteristics to be applied during an access operation Threshold value. For example, graph 700 illustrates an information state map 740 that includes two read thresholds that distinguish read characteristic conditions of three information states. A first read threshold 730-a (eg, _Tread,0 ) may be associated with a logic 0, and a second read threshold 730-b (eg, _Tread,1 ) may be associated with a Logic 1 is associated. In instances where the read characteristic refers to a read voltage, T _read,0 may be a reference voltage associated with a logic 0 (eg, a first information state, a determined information state), and T _{read ,1} may be a reference voltage associated with a logic 1 (eg, a first information state, a certain information state). In various examples, reference components 285 are included, reference lines 265 are included (eg, second nodes 292 at a sense amplifier 290 ), or different voltages are applied to a reference line 265 during different time intervals A memory device 100 can support multiple reference voltages. In other examples, T _read,0 and T _read,1 may refer to (eg, of a material memory device) respectively reference read current, respectively reference charge transfer, respectively reference resistance, respective threshold voltage or other read characteristic thresholds.

According to the information state map 740, when a read characteristic associated with accessing a memory cell 105 is below the first read threshold 730-a (or at or below the first read threshold 730- a), the read operation may identify or indicate a logic 0 of the memory cell 105 (eg, as a certain logic state). When a read characteristic associated with accessing a memory cell 105 is above the second read threshold 730-b (or equal to or above the second read threshold 730-b), the read The operation may identify or indicate a logic 1 of memory cell 105 (eg, as a certain logic state). However, when a read characteristic associated with accessing a memory cell 105 is between the first read threshold 730-a and the second read threshold 730-b (or equal to or between between the first read threshold 730-a and the second read threshold 730-b), the read operation may identify or indicate a logic X of the memory cell 105 (eg, as an indeterminate logic state, as an empty logical state, as a third information state). In other words, a region between the first read threshold value 730-a and the second read threshold value 730-b may illustrate a range of uncertainty that may support an identification or An indication, or may refer to a condition associated with an identification or an indication that an information state does not exist (eg, an empty information state, an unassigned information state).

In some examples, a memory device 100 may use the information state map 740 to improve the behavior of error handling at a memory device. For example, when a memory cell 105 is identified as being associated with an indeterminate range of a read characteristic (eg, a logical X or other empty or unassigned information state), the memory device may employ Error detection and error correction operations that assume one or more information states in an associated codeword. Such techniques may be preferred over other techniques, such as not identifying a location of memory cells 105 that may contain an error or have a high probability of error or an association that may contain an error or have a high probability of error Error handling techniques for the corresponding information locations of codewords.

Although certain instances of deleting or indeterminate logic states may be related to charge leakage, the described techniques may additionally or alternatively be applied in other contexts. For example, certain memory cells 105 may experience other types of degradation, such as material migration that degrades a stored logical state, degradation that impairs the ability to write to a target logical state, or impairs response to a read A fetch operation produces a degradation in the capability of a read signal. In various examples, two or more read thresholds 730 may be used to distinguish between a determined information state and an indeterminate information state, or to otherwise scale a detected information state A weight or confidence. Information locations of memory cells 105, access lines (eg, digit lines 210, signal lines 260), or a codeword that have an indeterminate, unassigned, or relatively low-confidence information state may be included in an attempt to identify a A valid codeword is assigned a hypothetical information state or an alternative error handling operation (eg, a codeword that properly represents information written to a set of memory cells 105).

8 illustrates an example of a method 800 of supporting delete decoding for a memory device according to examples disclosed herein. In some examples, method 800 may be performed by a memory device, such as the memory device 100 or associated circuitry described with reference to FIGS. 1-7 . In some examples, one of error detection, error correction, or other error handling techniques may be performed on information retrieved from a memory device 100 by a host device coupled to such a memory device 100 A host device) performs one or more of the operations of method 800.

At 810 , the method can include identifying a sensed codeword based on accessing a set of memory cells 105 . In some examples, the set of memory cells 105 may include a column or page of memory cells 105 or some portion thereof. A codeword may have a set of information locations, and one or more of the set of information locations may be associated with an indeterminate or unassigned information state (eg, an X logic state, an empty logic state, an indeterminate logic state) Associated. In some examples, an information location associated with an indeterminate or unassigned information state may correspond to a detected charge leakage or a charge leakage determined to be above or above a threshold (eg, using a reference Memory cells 105 or access lines (eg, digital lines 210, signal lines 260) of a leak detection device 201) illustrated in FIG. 2 or FIG. 4 . In some examples, an information location associated with an indeterminate information state may correspond to an associated read characteristic (eg, read signal) determined to be between a first adjacent state corresponding to a first information state The memory cell 105 between the limit value and a second threshold value corresponding to a second information state (eg, a read characteristic in an indeterminate region, a logic 0, a first read threshold A read characteristic between limit value 730-a and a second read threshold value 730-b of a logic 1, as explained with reference to FIG. 7).

In one example of method 800, the operations of 810 may include identifying a sensed codeword 815 having one of a value {1,X,0,1,1,X,1,0}, as shown. An example of sensed codeword 815 may illustrate a codeword having a set of eight information locations, where a second information location and a sixth information location are each associated with an indeterminate or unassigned information state (eg, an "X" logic state, an indeterminate logic state, an empty logic state). In other examples, according to the techniques described, a sensed codeword may have more or less than eight information locations, and a given sensed codeword may have any number of zeros or an indeterminate or undetermined Assign a more information location associated with the logical state.

In some examples, identifying a sensed codeword at 810 may be accompanied by identifying parity information corresponding to the sensed codeword, such as associated with accessing memory cell 105 that may support subsequent error handling operations (eg, error detection, error correction) one or more parity bits. In various examples, this parity information may be stored in the same row or memory sector 110 as the memory cells 105 corresponding to the sensed codewords, or this parity information may be retrieved from elsewhere in a memory system , such as another portion of a memory device 100 (eg, a portion of a memory device 100 allocated to co-located information), or from another memory device 100 (eg, when a host device stores information in a first memory in the memory device 100 and store the corresponding parity information in a second memory device 100).

At 820, method 800 can include assigning a respective hypothetical (eg, speculative) information state to each location having an indeterminate or unassigned information state. The assignment of 820 may be performed according to various techniques for assigning information states to one or more codewords (eg, speculative codewords, hypothetical codewords, hypothetical codewords) to perform subsequent error detection operations (eg, to Evaluate the assumed information state or the validity of one of the assumed codewords).

Continuing with the sensed codeword 815 having a value of {1,X,0,1,1,X,1,0} as an example, at 820, the method 800 can include placing the sensed codeword 815 having a logical X Each position of is assigned a logical 0, thereby generating a speculative codeword 825-a having a value of {1,0,0,1,1,0,1,0}. In various other examples, the assignment at 820 may include assigning each position with a logical X as a logical 1 or some other putative or speculative information state, or assigning a pattern of putative information states, such as Alternate locations with a logic X are assigned either a logic 0 or a logic 1.

In some examples, the operation of 820 may be performed based, at least in part, on a number of locations in the sensed codeword 815 having an indeterminate or unassigned information status satisfying a threshold. For example, operation 820 may be performed when a number of locations with an indeterminate or unassigned information status is less than a threshold value or less than or equal to a threshold value, where the threshold value may be equal to or A minimum distance or "hamming distance" is otherwise based at least in part on an error correction code or other error handling capability.

At 830, method 800 can include performing an error detection operation based on the codeword including the assumed information state (eg, the speculative codeword 825-a generated at 820). The error detection operation of 830 may be performed according to various techniques for identifying the presence or amount of one of the errors in the speculative codeword 825-a. For example, the speculative codeword 825-a may pass through an ECC engine, where an output may be referred to as a bus or string of syndromes. In some instances, the speculative codeword 825-a may be identified as valid (eg, matching the information written to all set of accessed memory cells 105, or consistent). In some examples, the error detection operations of 830 may include parity checking (eg, based at least in part on parity information associated with sensed codeword 815), and if based on processing all parities of speculative codeword 825-a The speculative codeword 825-a can be identified as valid if the bits are all 0 or match or match the parity information associated with the sensed codeword 815 (eg, of a set of accessed memory cells 105) .

At 840, method 800 can include determining whether a codeword including an assumed information state is valid (eg, based at least in part on the error detection operation of 830). For example, if one of the syndromes of the error detection operation 830 performed on a speculative codeword 825-a contains all 0s, or if the parity information based on processing the speculative codeword 825-a and the sensed code The parity information associated with word 815 matches, then method 800 may proceed to 845 and forward the codeword including the assumed information state (eg, assigned at 820). In a first instance referring to a speculative codeword 825-a having a value of {1,0,0,1,1,0,1,0}, if at 840 the speculative codeword 825-a is identified as valid, then the method may include forwarding at 845 the speculative codeword 825-a having the values {1,0,0,1,1,0,1,0}. If, at 840, the speculative codeword 825-a is determined to be invalid, method 800 may proceed to 850.

At 850, method 800 can include assigning a respective assumed information state to each location having an indeterminate or unassigned information state, the respective assumed information state may be different from the assumed information state at 820 assign. In some examples, the respective assumed information state assigned to each location at 850 may be the inverse or complement of one of the respective assumed information states assigned to the corresponding location at 820 .

Continuing with the example of the sensed codeword 815 having a value of {1,X,0,1,1,X,1,0}, at 850, the method 800 can include the sensed codeword 815 having a logical X Each position is assigned a logical 1, thereby generating a speculative codeword 825-b having a value of {1,1,0,1,1,1,1,0}. In various other examples, the assignment at 850 may include assigning each location with a logical X as a logical 1 or some other putative or speculative information state, or assigning a pattern of putative information states, such as Alternate positions with a logic X are assigned either a logic 1 or a logic 0.

At 860, method 800 can include performing an error detection operation based on the information state that the codeword contains the assumption (eg, the speculative codeword 825-b generated at 850). The error detection operation of 860 may be performed according to various techniques for identifying the presence or amount of one of the errors in the speculative codeword 825-b, which may be the same as, similar to, or different from the error detection of 830 operate.

At 870, method 800 can include determining whether a codeword including an assumed information state is valid (eg, based at least in part on the error detection operation of 860). For example, if a syndrome of an error detection operation of 860 performed on a speculative codeword 825-b contains all 0s, or if it is based on processing the parity information of the speculative codeword 825-b and the sensed code The parity information associated with word 815 matches, then method 800 may proceed to 875 and forward the codeword including the assumed information state (eg, assigned at 850). In a first instance referring to a speculative codeword 825-b having a value of {1,1,0,1,1,1,1,0}, as at 870 the speculative codeword 825-b is If identified as valid, the method may include, at 875, forwarding the speculative codeword 825-b having the values {1,1,0,1,1,1,1,0}. If, at 870, the speculative codeword 825-b is determined to be invalid, method 800 may proceed to 880.

At 880, method 800 can include identifying a codeword (eg, speculative codeword 825) having a minimum amount of error. For example, the first speculative codeword 825-a may be associated with a first number of errors, and the second speculative codeword 825-b may be associated with a second number of errors. When the first number of errors is different from the second number of errors, method 800 may include identifying a speculative codeword 825 associated with the smaller of the first number of errors and the second number of errors. When the first number of errors equals the second number of errors, method 800 may include identifying either or both of the speculative codewords. In some examples, method 800 may include identifying one of the first speculative codeword 825-a or the second speculative codeword 825-b preset (eg, when the respective numbers of errors are equal).

At 890, method 800 can include performing an error correction operation on a codeword comprising the assumed information state (eg, on a speculative codeword 825 identified at 880). In some examples, error correction at 890 may include processing a speculative codeword 825 and syndrome information (eg, generated at 830 or 860) to generate a corrected codeword. In some examples, error correction operations may identify erroneous locations of an incoming codeword and invert bits or otherwise alter the information state in their identified erroneous locations. At 890 , method 800 may also include generating a corrected codeword 891 for forwarding at 895 .

Continuing to mention that having a value of {1,1,0,1,1,1,1,0}, at 880 (eg, an instance of a speculative codeword 825-b invalid due to a single error) is A second instance of the identified and forwarded speculative codeword 825-b, at 890, the method 800 can include identifying that the speculative codeword 825-b has an error in the sixth position, and the method 800 can include generating a speculative codeword 825-b with a Corrected codeword 891 for one of the values {1,1,0,1,1,0,1,0}. Accordingly, method 800 may proceed to 895, where corrected codeword 891 may be forwarded.

845, 875 or 895 forwarding may include a forwarding to various components of a memory system. In some examples, forwarding may include forwarding the speculative codeword or corrected codeword from an ECC engine of a memory device 100 to an input/output component of the memory device 100 (eg, for output to and memory Device 100 is coupled to a host device). Additionally or alternatively, forwarding may include forwarding a speculative codeword or corrected codeword from an ECC engine of a memory device 100 to a write component of the memory device 100 (eg, for memory device 100 ), such as a rewrite or writeback component, a wear leveling component, an information real location component, or some other memory management component of a memory device 100 . In some examples, forwarding can include forwarding a speculative codeword or a corrected codeword from an ECC engine of a host device coupled with a memory device 100 to a processing component of the host device (eg, to process the self- information retrieved by the memory device 100). In some instances, a forwarding at 845, 875, or 895 may be accompanied by other operations, such as a diagnostic signaling that performs or requires a deletion correction or error correction, which may support a memory coupled to memory device 100 Additional diagnostic operations on device 100 or host device (eg, initiating leak detection operations, initiating remapping of memory addresses, signaling an error condition or potential error condition).

Although the operation of method 800 is described in the context of a serial method (eg, generating and processing a first speculative codeword 825-a and then generating a second speculative codeword 825-b, if necessary), In some instances, the operations of method 800 may be performed in a parallel method. For example, method 800 may be modified to generate two or more speculative codewords 825 simultaneously for parallel processing, such as performing operations 820 and 850 simultaneously, or performing operations 830 and 860 simultaneously (eg, simultaneously generating The first speculative codeword 825-a and the second speculative codeword 825-b) are processed. In some examples, parallelism supported by two or more ECC engines or portions thereof (eg, an ECC engine with two or more error detection components feeding a single error correction component) may be used Error detection processing implements such techniques. In some examples, two or more speculative codewords 825 may be generated prior to determining whether any of the speculative codewords 825 is valid, or determining to forward two or more speculative codewords 825 Which of these is used for error correction operations (eg, forwarding one of the speculative codewords with the lowest number of errors 825).

Although method 800 is illustrated with one example of two information locations being associated with an indeterminate information state (eg, deletion) and there are no other errors (eg, in addition to the information location identified as having an indeterminate information state (eg, deletion) information location), the techniques described for deletion decoding may support correction of various other combinations of errors and deletions. For example, the method can identify and correct an error unrelated to the indeterminate information state at 890 (eg, at the first information position, the third information position, the fourth information position, the fifth information position, the seventh information position position or the eighth information position). In addition, the techniques described for erasure decoding can be applied to various capabilities of an ECC engine, including support for detecting various error numbers, or support for correcting various error numbers.

For example, a minimum distance _dmin for an error correction code between a given codeword (eg, sensed codeword 815) and a valid codeword may be given by: _dmin > 2t+s+l (1) where t may be equal to a number of errors (eg, a location of an error is unknown), and s may be equal to a number of deletions (eg, a known information location where the information state may be uncertain). An example of error handling according to the illustrative relationship of Equation 1 is given in Table 1 below, indicating how error handling can be improved when the described techniques are applied to erasure decoding for a given error correction capability and error detection capability (e.g. , where ECC1 may refer to single-bit error correction capability and ECC2 may refer to double-bit error correction capability). code type dmin maximum correctable 2t + s + 1 ECC1, Single Cell Error Detection 3 1 error 3 2 delete 3 ECC1, two-bit error detection 4 1 error and 1 delete 4 3 delete 4 ECC2, two-bit error detection 5 2 error 5 1 error & 2 delete 5 4 delete 5 ECC2, three bit error detection 6 2 errors and 1 delete 6 1 error & 3 delete 6 5 delete 6 Table 1 - Error handling possibilities using delete decoding

Thus, according to these and other examples, the described techniques for erasure decoding may support an error correction capability greater than that which would otherwise be supported by an error handling code when the location of the information associated with the error is unknown. For example, leak detection or other techniques can be used to identify the type of deletion condition in which an information state can have an unknown value at a known location, and using this identification, a 1-bit error corrector and a A 2-bit error detector corrects for three of these deletions (eg, supported by 2-bit parity information for each sensed codeword).

The described techniques for erasure decoding may have additional advantages. For example, since data correction occurs during decoding (eg, as opposed to encoding), bit flipping can be advantageously employed for fatigue management in a memory array. Furthermore, since the repair of valid data occurs during decoding, up to 3 deletion failures (eg, using binary error detection and single-bit error correction) can be handled without prior knowledge of the valid data.

9 shows a block diagram 900 of a memory device 905 that supports memory management for charge leakage according to examples disclosed herein. Memory device 905 may be an example of one aspect of a memory device described with reference to FIGS. 1-8. Memory device 905 may include an access manager 910 , a sensing component 915 , a leak detection component 920 , a write operation manager 925 and a write operation indicator 930 . Each of these modules can communicate directly or indirectly with each other (eg, via one or more bus bars).

The access manager 910 can access a memory cell. In some examples, accessing the memory cell includes initiating a cell selection element for the memory cell. In some examples, access manager 910 can access a second memory cell. In various examples, an access memory cell may include a capacitive storage element.

The sensing component 915 can determine which memory cells are stored based on the access. A Logical State In some examples, the sensing component 915 can determine that the second memory cell stores a logical state based on accessing the second memory cell. In some examples, determining the logical state stored by the memory cell includes latching a signal on an access line associated with the memory cell. In some examples, the sensing component 915 can determine that a second logic state is stored by a second memory cell selected by an access line in common with the memory cell.

The leak detection component 920 can detect a charge leak based on accessing memory cells. In some examples, charge leakage detection is performed at least in part upon activation of the cell selection element. In some examples, detecting charge leakage includes determining that a voltage of an access line drops below a threshold voltage after latching. In some examples, leak detection component 920 can detect a flow of charge across a transistor electrically connected between the memory cell and a sensing component configured to determine the logical state of the memory cell's storage . In some examples, the leak detection component 920 can detect a second charge leak based on accessing the second memory cell.

The write operations manager 925 may determine whether to write the logic state or the one's complement of the logic state to the memory cell based in part on detecting the charge leakage. In some cases, the logic state is associated with a first charge transfer amount associated with the capacitive storage element and the complement of the logic state is associated with a second charge transfer amount greater than the first charge transfer amount The amount of charge transferred. In some examples, the write operation manager 925 can determine whether to write a logic state or the complement of the logic state based on the logic state being associated with a first amount of charge transfer and the complement of the logic state being associated with a second amount of charge transfer Associated, the second charge transfer amount is greater than the first charge transfer amount. In some examples, the write operation manager 925 may write the determined logic state to the memory cell. In some examples, the write operation manager 925 may write the second logical state or the complement of the second logical state to the second logical state based on determining whether to write the logical state or the complement of the logical state to the memory cell memory cells. In some examples, determining whether to write the logic state or the complement of the logic state to a memory cell is based on determining that another memory cell stores the logic state and detecting another charge leakage.

The write operation indicator 930 may store an indication of whether to write the logic state or the complement of the logic state to the memory cell. In some cases, the indication is associated with each memory cell in a set of memory cells that includes the memory cell. In some cases, each memory cell in the set of memory cells is selected by a common access line.

10 shows a block diagram 1000 of a memory device 1005 that supports memory management for charge leakage according to examples disclosed herein. Memory device 1005 may be an example of one aspect of a memory device described with reference to FIGS. 1-8. The memory device 1005 may include an array element 1010 , a sensing element 1015 , a leak detection element 1020 , a rewrite operation determiner 1025 , a rewrite operation controller 1030 and a rewrite operation indicator 1035 . Each of these modules may communicate directly or indirectly with each other (eg, via one or more bus bars). In some examples, memory device 1005 may include a plurality of memory cells each including a respective storage element, and the illustrated components may be included in a controller or circuitry coupled to the plurality of memory cells middle.

Column component 1010 can couple a storage element of each of a set of memory cells to a respective access line of a set of access lines. In some examples, column element 1010 can couple each memory cell with a respective access line in the set of access lines based on enabling a cell selection element associated with the respective memory cell. In some examples, column component 1010 can couple each memory cell in the set of memory cells with a respective access line in the set of access lines based on activating a common select line.

The sensing component 1015 can determine a respective logic state stored by each of the set of memory cells based on the coupling. In some examples, sense component 1015 can determine the respective logical state of each of the set of memory cells by latching a signal on a respective signal line associated with the respective memory cell .

The leakage detection component 1020 can determine whether a threshold charge leakage is detected on one or more of the set of access lines after determining the respective logic states. In some examples, leakage detection component 1020 can determine whether a threshold charge leakage amount is detected on one or more of the set of access lines, at least in part when a cell selection component is activated. In some examples, the leakage detection component 1020 may determine whether a threshold charge leakage amount is detected based on comparing a voltage of the respective signal line to a threshold voltage after latching. In some examples, leak detection component 1020 can determine whether there is a charge flow across a transistor electrically connected to a respective one of the set of access lines based on detecting a flow of charge in the set of access lines Threshold charge leakage is detected on one or more.

The rewrite operation determiner 1025 may select one of each of the memory cells for a direct rewrite operation or a memory cell based on whether a threshold charge leakage is detected on one or more of the set of access lines One of each of the elements is a complementary rewrite operation. In some examples, direct overwrite is selected for a first logic state associated with a first amount of charge transfer and a second logic state associated with a second amount of charge transfer less than the first amount of charge transfer The operation or complementary rewrite operation is based, at least in part, on: (1) the plurality of access lines associated with a detection of a threshold charge leakage and coupled to a memory cell storing the first logic state; A number, and (2) a number of the plurality of access lines associated with a detection of a threshold charge leakage and coupled to a memory cell storing the second logic state.

The rewrite operation controller 1030 may perform a selected direct rewrite operation or a complementary rewrite operation for each of the set of memory cells. In some cases, a direct overwrite operation includes writing a respective logical state stored by a respective memory cell and a complementary overwriting operation includes writing the respective logical state stored by a respective memory cell. One's complement.

The rewrite operation indicator 1035 may store an indication of whether to select a direct rewrite operation or a complementary rewrite operation.

11 shows a block diagram 1100 of a memory device 1105 supporting delete decoding for a memory device according to examples disclosed herein. Memory device 1105 may be an example of one aspect of a memory device described with reference to FIGS. 1-8. The memory device 1105 may include a memory cell access component 1110, an information state evaluation component 1115, a speculative codeword generation component 1120, an error detection component 1125, a codeword forwarding component 1130, an access signal Evaluation component 1135, a charge leakage evaluation component 1140, and an error correction component 1145. Each of these modules can communicate directly or indirectly with each other (eg, via one or more bus bars).

The memory cell access component 1110 can access a set of memory cells of the memory device.

The information state assessment component 1115 can determine, based on accessing the set of memory cells, that one or more memory cells in the set of memory cells are associated with an indeterminate or indeterminate information state.

The speculative codeword generation component 1120 can generate a first codeword (eg, a speculative codeword) comprising a set of information locations, each information location in the set of information locations corresponding to a value in the set of memory cells A respective memory cell, wherein the generating includes assigning a respective putative or speculative information state to each information location corresponding to one of the one or more memory cells.

In some examples, the speculative codeword generation component 1120 can be based on assigning a respective second hypothetical information state to one of the information locations corresponding to one of the one or more memory cells One or more generates a third codeword.

In some examples, the speculative codeword generation component 1120 can be based on assigning a respective third hypothetical information state to one of the information locations corresponding to one of the one or more memory cells or more to generate a fourth codeword.

Error detection component 1125 can perform an error detection operation based on the first codeword (eg, a speculative codeword). In various examples, an error detection operation performed by error detection component 1125 can indicate whether the first codeword is valid or invalid.

In some examples, error detection component 1125 can perform a second error detection operation based on a third codeword (eg, a speculative codeword). In various examples, an error detection operation performed by error detection component 1125 can indicate whether the third codeword is valid or invalid.

In some examples, error detection component 1125 can perform a third error detection operation based on the fourth codeword (eg, a speculative codeword). In various examples, an error detection operation performed by error detection component 1125 can indicate whether the fourth codeword is valid or invalid.

The codeword forwarding component 1130 can forward a second codeword based on performing error detection operations. In some examples, forwarding the second codeword includes forwarding the second codeword having the same information as the first codeword at each information location of the second codeword (eg, an identical codeword as a speculative numbers). In some examples, codeword forwarding component 1130 can forward a second codeword (eg, a corrected codeword) based on performing a second error detection operation.

In some examples, forwarding the second codeword includes forwarding the second codeword having the same information as the third codeword at each information location of the second codeword (eg, an identical codeword as a speculative code Character). In some examples, codeword forwarding component 1130 can forward the second codeword (eg, a corrected codeword) based on performing a third error detection operation.

In some examples, to determine that the one or more memory cells are associated with an indeterminate information state, the access signal evaluation component 1135 can determine for each of the one or more memory cells A signal based on accessing the respective memory cell is between a first threshold value associated with a first logic state and a second threshold value associated with a second logic state.

In some examples, to determine that the one or more memory cells are associated with an indeterminate information state, the access signal evaluation component 1135 can determine that an access line coupled to the respective memory cell has a value based on A voltage between a first threshold voltage and a second threshold voltage obtained by accessing the respective memory cells.

In some instances, to determine that the one or more memory cells are associated with an indeterminate information state, the access signal evaluation component 1135 can determine that a current based on accessing the respective memory cell is between a between the first threshold current and a second threshold current.

In some examples, to determine that the one or more memory cells are associated with an indeterminate information state, the charge leakage assessment component 1140 can determine, for each of the one or more memory cells, each A charge leakage of one of the memory cells meets a threshold.

In some examples, to determine that the one or more memory cells are associated with an indeterminate information state, the charge leakage assessment component 1140 can determine for each of the one or more memory cells A charge leakage associated with an access line coupled to the respective memory cell satisfies a threshold.

In some examples, error correction component 1145 can generate a second codeword (eg, a corrected codeword) based on assigning an information state different from the first codeword to one or more information locations of the second codeword.

In some examples, error correction component 1145 can generate a second codeword (eg, a corrected codeword) based on assigning an information state different from the third codeword to one or more information locations of the second codeword.

12 shows a flowchart illustrating one or more methods 1200 of supporting memory management for charge leakage in accordance with examples disclosed herein. The operations of method 1200 may be implemented by a memory device or components thereof, as described herein. For example, the operations of method 1200 may be performed by a memory device, as described with reference to FIG. 9 . In some examples, a memory device can execute a set of instructions to control functional elements of the memory device to perform the functions described. Additionally or alternatively, a memory device may use special purpose hardware or circuitry to implement aspects of the functions described.

At 1205, the memory device can access a memory cell having a capacitive storage element. The operations of 1205 may be performed according to the methods set forth herein. In some examples, aspects of the operation of 1205 may be performed by an access manager 910 described with reference to FIG. 9 .

At 1210, the memory device may store a logical state by the memory cell based on the access determination. The operations of 1210 may be performed according to the methods set forth herein. In some examples, aspects of the operation of 1210 may be performed by one of the sensing components 915 described with reference to FIG. 9 .

At 1215, the memory device may detect a charge leak based on accessing the memory cell. The operations of 1215 may be performed according to the methods set forth herein. In some examples, aspects of the operation of 1215 may be performed by a leak detection component 920 described with reference to FIG. 9 .

At 1220, the memory device may determine whether to write the logic state or the one's complement of the logic state to the memory cell based in part on detecting the charge leakage. The operations of 1220 may be performed according to the methods set forth herein. In some examples, aspects of the operations of 1220 may be performed by one of the write operations manager 925 described with reference to FIG. 9 .

At 1225, the memory device may write the predicated logic state to the memory cell. The operations of 1225 may be performed according to the methods set forth herein. In some examples, aspects of the operations of 1225 may be performed by one of the write operations manager 925 described with reference to FIG. 9 .

In some instances, an apparatus set forth herein may perform one or more methods, such as method 1200 . An apparatus may include circuitry, features, components or instructions (eg, a non-transitory computer-readable medium storing instructions executable by a processor) for accessing a memory cell having a capacitive storage element , a logic state stored by the memory cell is determined based on the access, a charge leak is detected based on the access memory cell, the logic state or the complement of the logic state is determined in part based on the detection of the charge leak to the memory cell, and write the predicated logic state to the memory cell.

Certain examples of the method 1200 and apparatus described herein may further include operations, circuitry, features, components, or instructions for associating with a first charge transfer amount based on a logic state and the complement of the logic state being greater than the One of the first charge transfer amounts and the second charge transfer amount is associated to determine whether to write the logic state or the complement of the logic state.

Certain examples of the method 1200 and apparatus described herein may further include operations, circuitry, features, components, or instructions for: determining a second logic state stored by a second memory cell, the second memory The voxel is selected by an access line common to the memory cell; and the second logical state or the second logical state is determined based on whether the logical state or the complement of the logical state is written to the memory cell The complement of the state is written to the second memory cell.

Certain examples of the method 1200 and apparatus described herein may further include operations, circuitry, features, components, or instructions for accessing a second memory cell having a second capacitive storage element based on memory The second memory cell is taken to determine the logical state stored in the second memory cell, and a second charge leakage is detected based on accessing the second memory cell. In some examples, determining whether to write the logic state or the complement of the logic state to a memory cell may be based on determining that a second memory cell stores the logic state and detecting a second charge leakage.

Certain examples of the method 1200 and apparatus described herein may further include operations, circuitry, features, components, or instructions for storing whether to write a logic state or the complement of a logic state to one of the memory cells instruct. In certain instances of the method 1200 and apparatus described herein, the indication may be associated with each memory cell in a set of memory cells that includes the memory cell. In some examples of the method 1200 and apparatus described herein, each memory cell in the set of memory cells may be selected by a common access line.

In certain examples of the method 1200 and apparatus described herein, accessing a memory cell may include operations, circuitry, features, components, or instructions for activating a cell selection component of the memory cell, and Detecting charge leakage may be performed at least in part upon activation of the cell selection element.

In certain examples of the method 1200 and apparatus described herein, determining the logic state stored by the memory cell may include operations for latching a signal of an access line associated with the memory cell, The circuitry, features, components, or instructions, and detecting charge leakage may include operations, circuitry, features, components, or instructions for determining that a voltage of an access line falls below a threshold voltage after latching.

In certain examples of the method 1200 and apparatus described herein, detecting charge leakage may include operations, circuitry, features, components, or instructions for detecting across electrical connections to memory cells and being configured to A charge flow of a transistor between a sensing element of a memory cell storage logic state is determined.

In certain examples of the method 1200 and apparatus described herein, the logic state is associated with a first amount of charge transfer associated with the capacitive storage element, and the complement of the logic state may be greater than the first amount of charge transfer is associated with a second charge transfer amount.

13 shows a flow diagram illustrating one or more methods 1300 of supporting delete decoding for a memory device according to aspects of the present invention. The operations of method 1300 may be implemented by one of the memory devices set forth herein or components thereof. For example, the operations of method 1300 may be performed by a memory device as described with reference to FIG. 11 . In some examples, a memory device can execute a set of instructions to control functional elements of the memory device to perform the functions described. Additionally or alternatively, a memory device may use special purpose circuitry or hardware to implement aspects of the functions described.

At 1305, the memory device can access a set of memory cells of the memory device. The operations of 1305 may be performed according to the methods set forth herein. In some examples, aspects of the operation of 1305 may be performed by one of the memory cell access components described with reference to FIG. 11 .

At 1310, the memory device may determine that one or more memory cells in the set of memory cells are associated with an indeterminate information state based on accessing the set of memory cells. The operations of 1310 may be performed according to the methods set forth herein. In some examples, aspects of the operation of 1310 may be performed by an information state evaluation component described with reference to FIG. 11 .

At 1315, the memory device may generate a first codeword comprising a set of information locations, each information location in the set of information locations corresponding to a respective memory cell in the set of memory cells. In some examples, generating the first codeword may include assigning a respective assumed information state to each information location corresponding to a memory cell of the one or more memory cells. The operations of 1315 may be performed according to the methods set forth herein. In some examples, aspects of the operations of 1315 may be performed by one of the speculative codeword generation components described with reference to FIG. 11 .

At 1320, the memory device may perform an error detection operation based on the first codeword. The operations of 1320 may be performed according to the methods set forth herein. In some examples, aspects of the operation of 1320 may be performed by one of the error detection components described with reference to FIG. 11 .

At 1325, the memory device may forward a second codeword based on performing an error detection operation. The operations of 1325 may be performed according to the methods set forth herein. In some examples, aspects of the operation of 1325 may be performed by a codeword forwarding component as described with reference to FIG. 11 .

In some instances, one of the apparatuses set forth herein may perform one or more methods, such as method 1300 . Apparatus may include features, circuitry, components, or instructions (eg, a non-transitory computer-readable medium storing instructions executable by a processor) for: accessing one of memory devices at a memory device a set of memory cells; based on accessing the set of memory cells, determine that one or more of the memory cells in the set of memory cells are associated with an indeterminate information state; generate a memory cell that includes a set of information locations a first codeword, each information location in the set of information locations corresponding to a respective memory cell in the set of memory cells, wherein the generating includes assigning a respective assumed information state to the one performing an error detection operation based on the first codeword; and forwarding a second codeword based on performing the error detection operation.

In certain instances of the method 1300 and apparatus described herein, determining that the one or more memory cells can be associated with an indeterminate information state can include operations, features, circuitry, components, or instructions to for determining, for each of the one or more memory cells, that a signal based on accessing the respective memory cell is between a first threshold value associated with a first logic state and a A second logic state is associated between a second threshold value.

In certain examples of the method 1300 and apparatus described herein, determining that a signal based on accessing the respective memory cell is between a first threshold value and a second threshold value may include operations, features, circuits System, means or instructions for determining that an access line coupled to a respective memory cell has between a first threshold voltage and a second threshold voltage based on accessing the respective memory cell a voltage between.

In certain examples of the method 1300 and apparatus described herein, determining that a signal based on accessing the respective memory cell is between a first threshold value and a second threshold value may include operations, features, circuits A system, component or instruction for determining that a current obtained based on accessing respective memory cells is between a first threshold current and a second threshold current.

In certain instances of the method 1300 and apparatus described herein, determining that the one or more memory cells are associated with an indeterminate information state may include operations, features, circuitry, components, or instructions for , for each of the one or more memory cells, it is determined that a charge leakage of the respective memory cell satisfies a threshold value.

In certain instances of the method 1300 and apparatus described herein, determining that the one or more memory cells are associated with an indeterminate information state may include operations, features, circuitry, components, or instructions for A charge leakage associated with an access line coupled to the respective memory cell is determined to satisfy a threshold for each of the one or more memory cells.

In certain examples of the method 1300 and apparatus described herein, performing an error detection operation may indicate that the first codeword is valid, and forwarding the second codeword may include operations, features, circuitry, components, or instructions to for forwarding the second codeword having the same information as the first codeword at each information location of the second codeword.

In certain instances of the method 1300 and apparatus described herein, performing an error detection operation may indicate that the first codeword is invalid and within an error correction capability of the memory device, and the method 1300 described herein Or the apparatus may further include operations, features, circuitry, components, or instructions for generating the second codeword based on assigning an information state that may be different from the first codeword to one or more information locations of the second codeword.

In certain instances of the method 1300 and apparatus described herein, performing an error detection operation may indicate that the first codeword is invalid and exceeds an error correction capability of the memory device, and the method 1300 and apparatus described herein may further include operations, features, circuitry, components or instructions for assigning a respective second assumed information state to an information location corresponding to a memory cell of the one or more memory cells One or more of generating a third codeword, performing a second error detection operation based on the third codeword, and forwarding the second codeword based on performing the second error detection operation.

In certain examples of the method 1300 and apparatus described herein, performing the second error detection operation may indicate that the third codeword is valid, and forwarding the second codeword may include operations, features, circuitry, components, or Instructions for forwarding the second codeword having the same information as the third codeword at each information location of the second codeword.

In certain instances of the method 1300 and apparatus described herein, performing the second error detection operation may indicate that the first codeword is invalid and within an error correction capability of the memory device, and the The method 1300 or apparatus may further include operations, features, circuitry, components, or instructions to generate the second codeword based on assigning an information state different from the third codeword to one or more information locations of the second codeword.

In certain instances of the method 1300 and apparatus described herein, performing the second error detection operation may indicate that the first codeword is invalid and exceeds an error correction capability of the memory device, and the methods described herein 1300 or apparatus may further include operations, features, circuitry, components or instructions for assigning a respective third hypothetical information state to a memory cell corresponding to one of the one or more memory cells based on One or more of the information locations generates a fourth codeword, performs a third error detection operation based on the fourth codeword, and forwards the second codeword based on performing the third error detection operation.

It should be noted that the methods set forth above illustrate possible implementations, and that operations and steps may be reconfigured or modified, and other implementations may be taken. Furthermore, portions from two or more of the methods may be combined.

Describe a device. The apparatus may include: a memory cell; a sensing device configuration for detecting a logic state stored by the memory cell during an access operation; circuitry configured to Detecting a charge leakage after the logic state is detected during the access operation; and a controller configured to satisfy a threshold based on the detected charge leakage during the access operation One's complement of the logical state is written to the memory cell.

In some examples, the controller may be configured to associate a first charge transfer amount with a first charge transfer amount based on the logic state and the complement of the logic state and a second charge transfer amount greater than the first charge transfer amount The complement of the logical state is associated with the write.

In some examples, the sensing component can be configured to detect logic states during a read portion of the access operation, and the circuitry can be configured to precede a rewrite portion of an access operation Detect charge leakage.

In some examples, the circuitry includes a second sensing component.

In some instances, the sensing component includes circuitry.

In some examples, the sensing element can be configured to latch a signal on an access line associated with the memory cell, and the circuitry can be configured to determine access after latching The voltage of one of the lines drops below a threshold voltage.

In some examples, the circuitry can be configured to detect a flow of charge across a cascade of devices electrically connected between the memory cell and the sensing element.

Describe another device. The apparatus can include: a set of memory cells, each including a respective storage element; and a controller coupled to the set of memory cells and configured to each of the set of memory cells A storage element of one is coupled to a respective one of a set of access lines, a respective logic state stored by each of the set of memory cells is determined based on the coupling, upon determining the respective The logic state then determines whether a threshold charge leakage is detected on one or more of the set of access lines, based on whether a threshold charge leakage is detected on one or more of the set of access lines Quantity selects a direct overwrite operation for each of the memory cells or a complementary overwrite operation for each of the memory cells, and performs the selection for each of the set of memory cells Direct rewrite operation or complementary rewrite operation.

In some examples, direct overwrite operations include writing to respective logical states stored by a respective memory cell, and complementary overwrite operations include writing respective logical states stored by a respective memory cell one's complement.

In some examples, a number of the set of access lines are associated with a detection of threshold charge leakage and coupled with a memory cell storing the first logic state, and a number of the set of access lines The line is associated with a detection of a threshold charge leakage and a memory cell coupling that stores a second logic state.

Some examples may further include storing an indication of whether to select a direct overwrite operation or a complementary overwrite operation.

In some examples, coupling a storage element of each of the set of memory cells to a respective access line of the set of access lines may include operations, circuitry, features, components, or instructions for Each memory cell of the set of memory cells is coupled to a respective access line of the set of access lines based on activating a common select line.

Certain examples may further include: coupling each memory cell with a respective access line in the set of access lines based on activating a cell selection element associated with the respective memory cell; and at least in part It is determined whether a threshold charge leakage amount is detected on one or more of the set of access lines when the cell selection element is activated.

Some examples may further include by latching a signal of a respective signal line associated with the respective memory cell and determining whether to detect or not after the latching based on comparing a voltage of the respective signal line to a threshold voltage. The threshold charge leakage is measured to determine the respective logic state of each of the set of memory cells.

Certain examples may further include determining whether a threshold charge leakage amount is detected on one or more of the set of access lines may be based on detecting electrical connections across a respective one of the set of access lines. A charge flow of a transistor.

Describe another device. The apparatus can include: a memory array including a set of memory cells; an access component coupled to the memory array and configured to generate a first code based on accessing the set of memory cells word; a leak detection component coupled to the memory array and configured to determine that a charge leak associated with one or more of the set of memory cells satisfies a threshold value; a an error detection component coupled with an access component and a leak detection component and configured to be based on assigning a respectively assumed information state to the one or more memory cells corresponding to the first codeword Each information location performs one or more error detection operations; and an input/output component configured to forward a second codeword based on performing the one or more error detection operations.

In some examples, the error detection component can be configured to evaluate each information location corresponding to the one or more memory cells based on assigning a respective first assumed information state to the first codeword performing a first error detection operation on a third codeword of the A fourth codeword in position performs a second error detection operation.

In some examples, the error detection component can be configured to perform the first error detection operation and the second error detection operation simultaneously.

In some examples, the error detection component can be configured to select the third based on a number of errors detected by the first error detection operation and a number of errors detected by the second error detection operation one of the codeword or the fourth codeword, and forwards the selected codeword.

In some examples, the error detection component can be configured to select the first error detection operation when the number of errors detected by the first error detection operation is less than the number of errors detected by the second error detection operation Three code words, and a fourth code word is selected when the number of errors detected by the second error detection operation is less than the number of errors detected by the first error detection operation.

In some examples, the error detection component can be configured to forward the selected codeword to an error correction component when an error number corresponding to the selected codeword is within an error correction capability of the error correction component.

In some examples, the error detection component can be configured to forward the selected codeword to the input/output component when the number of errors corresponding to the selected codeword is zero.

Describe a device. The apparatus can include: a memory array including a set of memory cells; and a controller coupled to the memory array. The controller can be configured to access the set of memory cells; determining one or more memory cells in the set of memory cells and an indeterminate information state based on accessing the set of memory cells associating; generating a first codeword comprising a set of information locations, each information location in the set of information locations corresponding to a respective memory cell in the set of memory cells, wherein the generating comprises converting a assigning a respective assumed information state to each information location corresponding to a memory cell of the one or more memory cells; performing an error detection operation based on the first codeword; and performing error detection based on The operation forwards a second codeword.

In some examples, to determine that the one or more memory cells are associated with an indeterminate information state, the controller can be configured to target each of the one or more memory cells It is determined that a charge leakage of the respective memory cell satisfies a threshold value.

In some examples, to determine that the one or more memory cells are associated with an indeterminate information state, the controller can be configured to target each of the one or more memory cells It is determined that a charge leakage associated with an access line coupled to the respective memory cell satisfies a threshold.

In some examples, to determine that the one or more memory cells are associated with an indeterminate information state, the controller can be configured to target each of the one or more memory cells The determination is based on a signal accessing the respective memory cell between a first threshold value associated with a first logic state and a second threshold value associated with a second logic state.

In some examples, to determine that the signal is between a first threshold value and a second threshold value based on accessing the respective memory cell, the controller may be configured to determine that the signal is between the respective memory cell and the respective memory cell. An access line coupled has a voltage between a first threshold voltage and a second threshold voltage based on accessing the respective memory cell.

In some examples, to determine that the signal based on accessing the respective memory cell is between the first threshold value and the second threshold value, the controller may be configured to determine that the signal based on accessing the respective memory cell is between the first threshold value and the second threshold value. A current of the voxel is between a first threshold current and a second threshold current.

The information and signals set forth herein may be represented using any of a variety of different technologies and techniques. For example, data, instructions, commands, information, signals, bits, symbols and chips that may be referred to throughout the above description may be represented by voltages, currents, electromagnetic waves, magnetic fields or particles, light fields or particles, or any combination thereof . Certain figures may illustrate the signal as a single signal; however, those skilled in the art will understand that the signal may represent a bus of signals, where the bus may have various bit widths.

As used herein, the term "virtual ground" refers to a node of a circuit that is maintained at a voltage of approximately zero volts (0V) but is not directly coupled to ground. Therefore, the voltage of a virtual ground can temporarily float and return to about 0V in a steady state. A virtual ground can be implemented using various electronic circuit elements, such as a voltage divider consisting of operational amplifiers and resistors. Other embodiments are also possible. "Virtual ground" or "via virtual ground" means connected to approximately 0 V.

The terms "electronic communication," "conductive contact," "connection," and "coupling" may refer to a relationship between components that supports the flow of signals between those components. Components are considered to be in electronic communication (or conductive contact or connection or coupling) with each other if there is any conductive path between them that can support the flow of signals between those components at any time. At any given time, the conductive paths between components that are in electronic communication (conductive contact or connection or coupling) with each other can be either an open circuit or a closed circuit based on the operation of the device that includes the connected components. The conductive path between connected components may be a direct conductive path between components, or the conductive path between connected components may be an indirect conductive path that may include intermediate components such as switches, transistors, or other components . In some cases, signal flow between connected components may be interrupted for a period of time, eg, using one or more intermediate components (eg, switches or transistors).

The term "coupled" refers to the condition of moving from an open relationship between components to a closed relationship between components, in which signals cannot currently communicate between components via a conductive path, in which signals Communication between components may be via conductive paths. When a component (eg, a controller) couples other components together, the component initiates a change that allows signals to flow between the other components via a conductive path that previously disallowed signal flow.

The term "isolation" refers to a relationship between components where signals cannot currently flow between those components. If there is an open circuit between the components, the components are isolated from each other. For example, when the switch is open, two components separated by a switch located between the components are isolated from each other. When a controller isolates two components from each other, the controller affects a change in preventing signal flow between components using a conductive path that previously permitted signal flow.

As used herein, the term "substantially" means that the modified property (eg, a verb or adjective that the term "substantially" modifies) is not necessarily exact but close enough to achieve the benefit of the property.

As used herein, the term "electrode" can refer to an electrical conductor and, in some cases, can be used as an electrical contact to a memory cell or other component of a memory array. An electrode may include traces, wires, conductive lines, conductive layers, etc. that provide a conductive path between elements or components of a memory array.

As used herein, the term "short circuit" refers to a relationship between components that establishes a conductive path between the components by activating a single intermediate component between the components in question. For example, a first element shorted to a second element can exchange signals with the second element when a switch between the first element and the second element is closed. Thus, a short circuit can be a dynamic operation that enables charge to flow between components (or wires) of electronic communication.

The devices discussed herein, including a memory array, can be formed on a semiconductor substrate such as silicon, germanium, silicon germanium, gallium arsenide, gallium nitride, and the like. In some cases, the substrate is a semiconductor wafer. In other cases, the substrate may be a silicon-on-insulator (SOI) substrate, such as silicon-on-glass (SOG) or silicon-on-sapphire (SOP), or an epitaxial layer of semiconductor material on another substrate. The conductivity of the substrate or sub-regions of the substrate can be controlled by doping with various chemical species including but not limited to phosphorous, boron or arsenic. Doping can be performed by ion implantation or by any other doping means during initial formation or growth of the substrate.

A switching element or a transistor discussed herein may represent a field effect transistor (FET) and includes a three-terminal device including a source, drain, and gate. The terminals can be connected to other electronic components through conductive material (eg, metal). The source and drain can be conductive and can include a heavily doped (eg, degenerated) semiconductor region. The source and drain can be separated by a lightly doped semiconductor region or channel. If the channel is n-type (ie, the majority carriers are electrons), the FET can be referred to as an n-type FET. If the channel is p-type (ie, the majority carrier is holes), the FET can be referred to as a p-type FET. The channel can be capped with an insulating gate oxide. Channel conductivity can be controlled by applying a voltage to the gate. For example, applying a positive or negative voltage to an n-type FET or a p-type FET, respectively, can make the channel conductive. A transistor can be "turned on" or "activated" when a voltage greater than or equal to the threshold voltage of a transistor is applied to the gate of the transistor. When a voltage less than the threshold voltage of the transistor is applied to the gate of the transistor, the transistor can be "turned off" or "deactivated."

The descriptions set forth herein in connection with the appended drawings illustrate example configurations and do not represent all examples that may be implemented or that are within the scope of the claims. As used herein, the term "exemplary" means "serving as an example," ideal, or illustration, not "preferable" or "preferable to other examples." The detailed description contains specific details to provide an understanding of one of the techniques described. However, these techniques may be practiced without these specific details. In other instances, well-known structures and devices are shown in block diagram form in order to avoid obscuring the concepts of the illustrated examples.

In the drawings, similar components or features may have the same reference labels. In addition, various components of the same type can be distinguished by following the reference label with a dash and a second label that distinguishes among similar components. If only the first reference label is used in the description, the description may apply to any of the similar components having the same first reference label, regardless of the second reference label.

The information and signals set forth herein may be represented using any of a variety of different technologies and techniques. For example, data, instructions, commands, information, signals, bits, symbols, and chips that may be referred to throughout the above description may be generated by voltages, currents, electromagnetic waves, magnetic fields or particles, light fields or particles, or any combination thereof. express.

A general purpose processor, a digital signal processor (DSP), an application specific integrated circuit (ASIC), a field programmable gate array (FPGA) or other programmable logic device, discrete gate or transistor logic , discrete hardware components, or any combination thereof designed to perform the functions set forth herein to implement or perform the various illustrative blocks and modules set forth in connection with the disclosure herein. A general purpose processor may be a microprocessor, but in the alternative, the processor may be any processor, controller, microcontroller, or state machine. A processor may also be implemented as a combination of computing devices, such as a combination of a DSP and a microprocessor, a combination of multiple microprocessors, a combination of one or more microprocessors and a DSP core, or any other such configuration.

The functions described herein can be implemented in hardware, software executed by a processor, firmware, or any combination thereof. If implemented in software, the functions may be stored on or transmitted over as one or more instructions or code on a computer-readable medium. Other examples and implementations are within the scope of this disclosure and the accompanying claims. For example, due to the nature of software, the functions described may be implemented using software executed by a processor, hardware, firmware, hardwiring, or a combination of any of these. Features implementing a function may also be physically located at various locations, including interspersed such that portions of the function are implemented at different physical locations. Furthermore, as used herein (included in the scope of this application), "or" used in a list of items (for example, preceded by such as "at least one of" or "one or more of" A phrase such as "a list of items" indicates an inclusive list such that, for example, a list of at least one of A, B, or C means A or B or C, or AB or AC or BC, or ABC (ie, A and B and C). Furthermore, as used herein, the phrase "based on" should not be construed as referring to a closed set of conditions. For example, an exemplary step described as "based on condition A" may be based on a condition A and a condition B without departing from the scope of the present invention. In other words, as used herein, the phrase "based on" should be construed as synonymous with the phrase "based at least in part on."

The descriptions herein are provided to enable any person skilled in the art to make or use the present invention. Various modifications to this invention will be readily apparent to those skilled in the art, and the generic principles defined herein may be applied to other variations without departing from the scope of this invention. Thus, the present disclosure is not intended to be limited to the examples and designs described herein but is to be accorded the widest scope consistent with the principles and novel features disclosed herein.

100: memory device 105: memory cell 105-a: memory cell 105-b: memory cell 110: memory sector 120: first access line/access line/common access line 130 : second access line/access line 131-b: first terminal 132-b: second terminal 135: row component 140: third access line/access line 145: board component 150: sensing component/th A sensing element/second sensing element 160: I/O element 170: Memory controller 200: Circuit 201-a: Leak detection element 201-b: Leak detection element 201-c: Leak detection element 205 : word line/common word line 205-a: word line 210: digit line 210-a: digit line 215: plate line 215-a: plate line 220: capacitor/ferroelectric capacitor 221: cell plate 222: cell bottom 230: cell selection component 230-a: cell selection component 235: control node 240: intrinsic capacitance 240-a: intrinsic capacitance 250-a: voltage source 250-b: first sense amplifier voltage source/sense amplifier voltage source 250-c: second sense amplifier voltage source/sense amplifier voltage source 260: signal line 260-a: signal line 265: reference line 265-a: reference line 270: bypass line 275: switching component 280: signal generation component 285: reference component 290: sense amplifier 290-a: sense amplifier 291: first node 292: second node 295: input/output line 300-a: hysteresis curve 300-b: hysteresis curve 305-a :charge state 305-b:charge state 305-c:charge state 310-a 335: Read Voltage/Fixed Read Voltage 340: Path 350: Resulting Voltage/Voltage 355: Resulting Voltage/Voltage 360: Path 365: Path 370: State of Charge 400: Circuit 405: Amplifier 410-a: Voltage Source 410-b : voltage source 410-c: voltage source 410-d: voltage source 410-e: voltage source 410-f: voltage source 410-g: voltage source 410-h: voltage source 410-i: voltage source 410-j: voltage source 410-k: voltage source 410-l: voltage source 420-a: switching component 420-b: switching component 420-c: switching component 420-d: switching component 420-e: switching component 420-f: switching component 420 -g: switching assembly 420-h: switching assembly 430-a: first integrator capacitor 430-b: second integrator capacitor 431-a: first terminal 431-b: first terminal 432-a: second terminal 432-b: second terminal 450-a: variable voltage source/first variable voltage source 450-b: variable voltage source/second variable voltage source 500: timing diagram 50 1:Operation 502:Operation 503:Operation 504:Operation 505:Operation 506:Operation 507:Operation 508:Operation 509:Operation 510:Operation 511:Operation 512:Operation 513:Operation 514:Operation 515:Operation 516:Operation 600: method 605: operation 610: operation 615: operation 620: operation 625: operation 700: graph 710: distribution 711: edge 712: edge 720: distribution 721: edge 722: edge 730-a: first read threshold 730 -b: second read threshold 740: info state map 800: method 810: operation 815: sensed codeword 820: operation 825-a: speculative codeword/first speculative codeword 825-b: speculative Speculative Codeword/Second Speculative Codeword 830: Operation 840: Operation 845: Operation 850: Operation 860: Operation 870: Operation 875: Operation 880: Operation 890: Operation 891: Corrected Codeword 895: Operation 900: Block Diagram 905: Memory Device 910: Access Manager 915: Sensing Component 920: Leak Detection Component 925: Write Operation Manager 930: Write Operation Indicator 1000: Block Diagram 1005: Memory Device 1010: Column Component 1015 : sensing component 1020 : leak detection component 1025 : rewrite operation determiner 1030 : rewrite operation controller 1035 : rewrite operation indicator 1100 : block diagram 1105 : memory device 1110 : memory cell access component 1115 : information state evaluation component 1120 : speculative codeword generation component 1125 : error detection component 1130 : codeword forwarding component 1135 : access signal evaluation component 1140 : charge leakage evaluation component 1145 : error correction component 1200 : method 1205 : operation 1210 :Operation 1215:Operation 1220:Operation 1225:Operation 1300:Method 1305:Operation 1310:Operation 1315:Operation 1320:Operation 1325:Operation A:leak path B:leak path C:leak path DL:digital line DL ₁ :digital line DL ₂ : digit line DL ₃ : digit line DL _N : digit line ISO ₁ : logic signal ISO ₂ : logic signal PL: board line PL ₁ : board line PL ₂ : board line PL ₃ : board line PL _N : board line SW ₁ : logic signal SW ₂ : logic signal SW ₃ : logic signal SW ₄ : logic signal SW ₅ : logic signal SW ₆ : logic signal T _{read, 0} : first read threshold value/read voltage T _{read, 1} : Second read threshold value V ₀ : voltage V ₁ : voltage V ₂ : voltage/voltage level V ₃ : voltage/voltage level V ₄ : voltage/voltage level V ₅ : voltage V ₆ : voltage V ₇ : Voltage V ₈ : Voltage/Voltage Level V ₉ : Voltage V ₁₀ : voltage V ₁₁ : voltage/voltage level VA _: signal _VB : signal V _bottom : voltage V _cap : voltage difference/negative voltage difference/positive voltage difference V _DL : voltage V _DL,w0 : voltage V _{DL, w1} : voltage V _H : voltage _VL : voltage V _plate : voltage V _PL : voltage V _{PL, w0} : plate high write voltage V _{PL, w1} : plate low write voltage V _sig : sensing signal voltage/voltage V _{sig ,0} : voltage V _{sig, 1} : voltage V _ref : reference signal voltage/reference signal V _th,amp : threshold voltage WL: word line/logic signal WL ₁ : word line WL ₂ : word line WL ₃ : word line WL _M : word line

1 illustrates one example of a memory device that supports memory management and delete decoding in accordance with the examples disclosed herein.

2 illustrates an example circuit that supports memory management and delete decoding for a memory device according to examples disclosed herein.

3A and 3B illustrate examples of nonlinear electrical properties of a ferroelectric memory cell using hysteresis curves according to various examples disclosed herein.

4 illustrates one example of a circuit that supports memory management and delete decoding for a memory device in accordance with the examples disclosed herein.

5 shows a timing diagram illustrating the operation of an example access process that supports memory management and delete decoding for a memory device, according to examples disclosed herein.

6 shows a flow diagram illustrating one method of supporting memory management for charge leakage in accordance with examples disclosed herein.

7 illustrates a graph including a distribution of a read characteristic associated with different information states that can support erasure decoding for a memory device, according to examples disclosed herein.

8 illustrates one example of a method of supporting delete decoding for a memory device in accordance with examples disclosed herein.

9 shows a block diagram of a memory device that supports memory management for charge leakage according to examples disclosed herein.

10 shows a block diagram of a memory device that supports memory management for charge leakage according to examples disclosed herein.

11 shows a block diagram of a memory device supporting delete decoding for a memory device according to an aspect of the present invention.

12 shows a flowchart illustrating one or more methods of supporting memory management for charge leakage in accordance with aspects of the present invention.

13 shows a flowchart illustrating one or more methods of supporting delete decoding for a memory device according to examples disclosed herein.

105-a: memory cell

200: Circuit

201-a: Leak Detection Components

201-b: Leak Detection Components

205: word line/common word line

210: Digital Line

215: Board Line

220: Capacitors/Ferroelectric Capacitors

221: Cell Plate

222: cell bottom

230: Cell Selection Components

235: Control Node

240: Inherent capacitance

250-a: Voltage Source

250-b: First sense amplifier voltage source/sense amplifier voltage source

250-c: 2nd sense amp voltage source/sense amp voltage source

260: signal line

265: Reference Line

280: Signal Generation Components

285: Reference Components

290: Sense Amplifier

291: First Node

292: Second Node

295: input/output line

A: Leak path

B: Leak path

C: leak path

DL: digital line

PL: Board Line

V ₀ : Voltage

V _bottom : Voltage

V _H : Voltage

V _L : Voltage

V _plate : Voltage

V _ref : reference signal voltage/reference signal

V _sig : sense signal voltage/voltage

WL: word line/logic signal

Claims (25)

A method for operating a memory device, comprising: accessing a plurality of memory cells of the memory device at the memory device; determining the plurality of memory cells based at least in part on accessing the plurality of memory cells One or more of the memory cells are associated with an indeterminate information state; generating a first codeword including a plurality of information locations, each information location of the plurality of information locations corresponding to at a respective one of the plurality of memory cells, wherein the generating includes assigning a respective assumed information state to a respective one of the one or more memory cells performing an error detection operation based at least in part on the first codeword; and forwarding a second codeword based at least in part on performing the error detection operation. The method of claim 1, wherein determining that the one or more memory cells are associated with the indeterminate information state comprises: determining, for each of the one or more memory cells, based at least in part on memory cells Taking a signal of the respective memory cell of the plurality of memory cells between a first threshold value associated with a first logic state and a second threshold value associated with a second logic state between the thresholds. The method of claim 2, wherein determining is based at least in part on the signal accessing the respective memory cell of the plurality of memory cells being between the first threshold value and the second threshold value including: determining an access wire coupled to the respective memory cell of the plurality of memory cells There is a voltage between a first threshold voltage and a second threshold voltage based at least in part on accessing the respective memory cell of the plurality of memory cells. The method of claim 2, wherein determining is based at least in part on the signal accessing the respective memory cell of the plurality of memory cells being between the first threshold value and the second threshold value The interval includes determining that a current of the respective memory cell accessing the plurality of memory cells is between a first threshold current and a second threshold current based at least in part on the current. The method of claim 1, wherein determining that the one or more memory cells are associated with the indeterminate information state comprises: determining the plurality of memories for each of the one or more memory cells A charge leakage of the respective memory cell of the cell satisfies a threshold. 9. The method of claim 1, wherein determining that the one or more memory cells are associated with the indeterminate information state comprises: determining and coupling to the complex number for each of the one or more memory cells A charge leakage associated with an access line of the respective memory cell of each memory cell satisfies a threshold. A method as claimed in claim 1, wherein: performing the error detection operation indicates that the first codeword is valid; and forwarding the second codeword includes forwarding with the first codeword at each information location of the second codeword The codeword has the same information as the second codeword. The method of claim 1, wherein performing the error detection operation indicates that the first codeword is invalid and within an error correction capability of the memory device, the method further comprising: based at least in part on comparing the first codeword with the first codeword A different information state of the codeword is assigned to one or more information locations of the second codeword to generate the second codeword. The method of claim 1, wherein performing the error detection operation indicates that the first codeword is invalid and exceeds an error correction capability of the memory device, the method further comprising: based at least in part on applying a respective second codeword The assumed information state is assigned to one or more of the information locations corresponding to one of the one or more memory cells to generate a third codeword; based at least in part on the third code performing a second error detection operation on the word; and forwarding the second codeword based at least in part on performing the second error detection operation. 9. The method of claim 9, wherein: performing the second error detection operation indicates that the third codeword is valid; and forwarding the second codeword includes forwarding at each information location of the second codeword with the The third codeword has the same information as the second codeword. The method of claim 9, wherein performing the second error detection operation indicates that the third codeword is invalid and within an error correction capability of the memory device, the method further comprising: based at least in part on comparing the third codeword with the first A different information state of the three code words is assigned to the second code one or more information locations of the word to generate the second codeword. The method of claim 9, wherein performing the error detection operation indicates that the third codeword is invalid and exceeds the error correction capability of the memory device, the method further comprising: based at least in part on assigning a respective third codeword to A putative information state is assigned to one or more of the information locations corresponding to one of the one or more memory cells to generate a fourth codeword; based at least in part on the fourth code performing a third error detection operation on the word; and forwarding the second codeword based at least in part on performing the third error detection operation. An electronic memory device comprising: a memory array including a plurality of memory cells; an access component coupled with the memory array and configured to be based at least in part on accessing the plurality of memories a cell generating a first codeword; a leak detection component coupled to the memory array and configured to determine the memory cell associated with one or more of the plurality of memory cells a charge leakage meeting a threshold; an error detection element coupled with the access element and the leak detection element and configured to be based at least in part on assigning a respective assumed information state to the first performing one or more error detection operations for each information location of the codeword corresponding to a respective one of the one or more memory cells; an input/output element configured to at least A second codeword is forwarded based in part on performing the one or more error detection operations. The electronic memory device of claim 13, wherein the error detection component is configured to: perform a first error detection operation on a third codeword based at least in part on applying a respective assigning a first assumed information state to each information location of the first codeword corresponding to the one or more memory cells; and performing a second error detection operation on a fourth codeword, the fourth The codeword is based at least in part on assigning a respective second assumed information state to each information location of the first codeword corresponding to the one or more memory cells. The electronic memory device of claim 14, wherein the error detection component is configured to perform the first error detection operation and the second error detection operation simultaneously. The electronic memory device of claim 14, wherein the error detection component is configured to: based at least in part on a number of errors detected by the first error detection operation and a number of errors detected by the second error detection operation selecting one of the third codeword or the fourth codeword by a number of detected errors; and forwarding the selected codeword. The electronic memory device of claim 16, wherein the error detection component is configured to: when the number of errors detected by the first error detection operation is less than that detected by the second error detection operation the third codeword is selected when the number of errors detected by the second error detection operation is less than the number of errors detected by the first error detection operation , select the fourth codeword. The electronic memory device of claim 16, wherein the error detection component is configured to forward the selected codeword to an error correction capability of an error correction component when an error number corresponding to the selected codeword is within an error correction capability of the error correction component the error correction component. The electronic memory device of claim 16, wherein the error detection component is configured to forward the selected codeword to the input/output component when an error number corresponding to the selected codeword is zero. An electronic memory device comprising: a memory array including a plurality of memory cells; and a controller coupled to the memory array and configured to: access the plurality of memory cells ; determining that one or more of the plurality of memory cells is associated with an indeterminate information state based at least in part on accessing the plurality of memory cells; generating a data including a plurality of information locations a first codeword, each information location of the plurality of information locations corresponding to a respective one of the plurality of memory cells, wherein the generating includes assigning a respective assumed information state to each information location corresponding to a respective one of the one or more memory cells; performing an error detection operation based at least in part on the first codeword; and performing the error at least in part The detection operation forwards a second codeword. The electronic memory device of claim 20, wherein for determining the one or more memory cells Associated with the indeterminate information state, the controller is configured to: determine for each of the one or more memory cells based at least in part on accessing each of the plurality of memory cells A signal of a specific memory cell is between a first threshold value associated with a first logic state and a second threshold value associated with a second logic state. The electronic memory device of claim 21, wherein determining that the signal of the respective memory cell accessing the plurality of memory cells is between the first threshold and the second based at least in part Between thresholds, the controller is configured to: determine that an access line coupled to the respective memory cell of the plurality of memory cells has an access line based at least in part on accessing the plurality of memory cells A voltage between a first threshold voltage and a second threshold voltage of the respective memory cell of the cell. The electronic memory device of claim 21, wherein determining that the signal of the respective memory cell accessing the plurality of memory cells is between the first threshold and the second based at least in part Between thresholds, the controller is configured to: determine that a current of the respective memory cell accessing the plurality of memory cells is between a first threshold current and a current based, at least in part, on accessing the plurality of memory cells between the second threshold current. The electronic memory device of claim 20, wherein to determine that the one or more memory cells are associated with the indeterminate information state, the controller is configured to: for the one or more memory cells Each of them determines that a charge leakage of the respective memory cell of the plurality of memory cells satisfies a threshold value. The electronic memory device of claim 20, wherein to determine that the one or more memory cells are associated with the indeterminate information state, the controller is configured to: Each of them determines that a charge leakage associated with an access line coupled to the respective memory cell of the plurality of memory cells satisfies a threshold.

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