CN114144834A

CN114144834A - Memory management and erasure decoding for memory devices

Info

Publication number: CN114144834A
Application number: CN202080052191.XA
Authority: CN
Inventors: R·E·法肯索尔; A·维斯孔蒂
Original assignee: Micron Technology Inc
Current assignee: Micron Technology Inc
Priority date: 2019-06-14
Filing date: 2020-05-08
Publication date: 2022-03-04
Also published as: EP3984035A4; TWI762932B; EP3984035A1; TW202105402A; WO2020251708A1; TW202230388A

Abstract

Memory management and erasure decoding for memory devices is described. A memory device may identify charge leakage associated with one or more memory cells and may determine whether to invert the logic states stored by one or more memory cells to increase the likelihood of properly reading the memory cells. In some examples, the memory device may store an indication of the complement of the logical state detected that was written, which may correspond to one memory cell or a group of memory cells. In some examples, a memory device may be configured to identify conditions associated with deleted or otherwise indeterminate logical states, which may be used to enhance aspects of error handling operations, including error handling operations that may be performed at the memory device or a host device (e.g., error handling operations performed at a memory controller located external to the memory device).

Description

Memory management and erasure decoding for memory devices

Cross referencing

The present patent application claims priority from us patent application No. 16/441,722 entitled "MEMORY MANAGEMENT FOR charge leakage in MEMORY DEVICEs (MEMORY MANAGEMENT FOR CHARGE LEAKAGE IN A MEMORY DEVICE)" filed on 14.6.2019 and us patent application No. 16/840,286 entitled "ERASURE DECODING FOR MEMORY DEVICEs (erase DECODING FOR a MEMORY DEVICE)" filed on 3.2020.4.16.16.farkenchul et al, each of which is assigned to the assignee of the present invention and each of which is expressly incorporated herein by reference in its entirety.

Background

Memory devices are widely used to store information in various electronic devices, such as computers, wireless communication devices, cameras, digital displays, and the like. Information is stored by programming different states of the memory device. For example, binary devices most commonly store one of two states, typically designated as a logic 1 or a logic 0. In other devices, more than two states may be stored. To access the stored information, components of the device may read or sense at least one state stored in the memory device. To store information, components of the device may write or program a state in the memory device.

There are various types of memory devices, including magnetic hard disks, Random Access Memory (RAM), Read Only Memory (ROM), dynamic RAM (dram), synchronous dynamic RAM (sdram), ferroelectric RAM (feram), magnetic RAM (mram), resistive RAM (rram), flash memory, Phase Change Memory (PCM), and others. The memory device may be volatile or non-volatile. Non-volatile memory (e.g., FeRAM) can maintain its stored logic state for long periods of time even in the absence of an external power source. Volatile memory devices (e.g., DRAMs) may lose their stored state when disconnected from an external power source. Ferams may be capable of achieving densities similar to volatile memories due to the use of ferroelectric capacitors as storage devices but may have non-volatile properties.

Drawings

FIG. 1 illustrates an example of a memory device supporting memory management and erasure decoding in accordance with examples disclosed herein.

FIG. 2 illustrates an example circuit supporting memory management and erasure decoding of a memory device in accordance with examples disclosed herein.

Fig. 3A and 3B illustrate examples of nonlinear electrical properties of ferroelectric memory cells utilizing hysteresis curves in accordance with various examples disclosed herein.

FIG. 4 illustrates an example of a circuit supporting memory management and erasure decoding for a memory device in accordance with examples disclosed herein.

FIG. 5 shows a timing diagram illustrating the operation of an example access procedure supporting memory management and erasure decoding of memory devices in accordance with an example disclosed herein.

FIG. 6 shows a flow diagram illustrating a method of supporting memory management for charge leakage in accordance with an example disclosed herein.

FIG. 7 illustrates a graph including distributions of read characteristics associated with different information states that can support erasure decoding for a memory device, according to an example disclosed herein.

Fig. 8 illustrates an example of a method of supporting erasure decoding of a memory device in accordance with examples disclosed herein.

FIG. 9 shows a block diagram of a memory device supporting memory management for charge leakage, according to an example disclosed herein.

FIG. 10 shows a block diagram of a memory device supporting memory management for charge leakage, according to an example disclosed herein.

FIG. 11 shows a block diagram of a memory device that supports erasure decoding of the memory device, according to aspects of the present disclosure.

FIG. 12 shows a flow diagram illustrating one or more methods of supporting memory management for charge leakage, according to aspects of the present disclosure.

Fig. 13 shows a flow diagram illustrating one or more methods of supporting erasure decoding of a memory device in accordance with an example disclosed herein.

Detailed Description

In some memory devices, charge leakage or other phenomena can negatively impact the memory device's ability to determine the logic state stored by a memory cell. For example, charge leakage in a memory device may result in detection or otherwise identification of a charge transfer that is greater than that otherwise associated with a particular logic state previously stored to a memory cell, such as detection of a voltage on a signal line that is lower than a corresponding voltage when there is no charge leakage. In some examples, charge leakage may reduce read margin of the memory device, or may be associated with reading an incorrect logic state from a memory cell (e.g., a logic state different from a logic state already stored at the memory cell). These effects may be related, for example, to capacitive memory technologies or other charge storage memory technologies in which memory cells may store different amounts of charge or different polarization polarities to store different logic states.

In one example, a memory cell of a memory device can be configured to store (e.g., in a capacitive memory element, in a ferroelectric memory element) a first logic state associated with a first amount of charge transfer or a second logic state associated with a second amount of charge transfer, greater than the first amount of charge transfer, or both. The first amount of charge transfer may refer to or otherwise correspond to a transfer of charge to or from a memory cell storing a first logic state, a first amount of charge stored at the memory cell, or a first polarity of charge stored at the memory cell during a read operation, or the first amount of charge transfer may generally correspond to a relatively low current logic state.

The second amount of charge transfer may refer to or otherwise correspond to an amount of charge transfer to or from the memory cell storing the second logic state, a second amount of charge stored at the memory cell, or a second polarity of charge stored at the memory cell during a read operation, or the second amount of charge transfer may generally correspond to a relatively high current logic state. During a read operation on a memory cell storing a first logic state, the sensing component can detect or otherwise identify a first amount of charge transfer to determine that the memory cell stores the first logic state. During a read operation on a memory cell storing a second logic state, the sensing component can detect or otherwise identify a second amount of charge transfer to determine that the memory cell stores the second logic state.

When there is charge leakage, for example, a memory device (e.g., a sensing component within the memory device) may detect a higher charge transfer than normally associated with a particular logic state, which may be partially representative of a charge transfer from a memory cell storing the logic state and partially representative of charge leakage. In other words, charge leakage may be superimposed on charge transfers normally associated with a particular logic state (e.g., associated with a read operation for that logic state). In some cases, the superimposed charge leakage may reduce read margin for reading memory cells storing a first logic state (e.g., normally associated with a relatively low charge transfer), or may cause the memory device to incorrectly detect a second logic state (e.g., associated with a higher charge transfer during a read operation) from memory cells written with the first logic state.

In some cases, a memory device may identify charge leakage associated with one or more memory cells or access lines, and may determine whether to intentionally invert the logic state stored by one or more memory cells when charge leakage is present to increase the likelihood of properly detecting the logic state. For example, a memory device may determine a logic state stored by a memory cell during an access operation (e.g., during a read portion of the access operation, during a write portion of the access operation), and also detect whether the memory cell or an associated access line is associated with charge leakage (e.g., during a leakage detection portion of the access operation).

In some cases, the memory device may determine to write the complement of the determined logic state (e.g., a logic state different from a logic state associated with a read or write portion of an access operation, a complementary logic state, an inverted logic state, an opposite logic state) to the memory cell based in part on detecting charge leakage or some other phenomenon. In some examples, determining to write the complement of the logic state may be based on the detected logic state being associated with a first amount of charge transfer and the complement of the logic state being associated with a second amount of charge transfer, the second amount of charge transfer being greater than the first amount of charge transfer. In some cases, the memory device may then write the complement of the logic state to the memory cell (e.g., during the rewrite portion of the access operation).

Along with writing complementary logic states to the memory cells, the memory device may also store an indication, such as a bit flip indication, that the complement of the detected logic state is written, where such an indication may correspond to a set of one or more memory cells, including the memory cell for which the associated charge leakage is detected. For example, a memory device may store such an indication to track whether a memory cell or a group of memory cells (e.g., a row or page) is programmed with a direct logic state or a complementary logic state (e.g., a flipped state). This indication may be used in subsequent read operations to properly interpret the changed logic state of one or more memory cells when information of the memory device is read (e.g., to directly interpret or to invert or otherwise change the interpretation of the logic state stored by the memory cell).

Thus, detected charge leakage or other phenomena in the memory device may be accounted for by changing the logic state stored by the memory cell (e.g., during a rewrite operation), which may avoid incorrectly interpreting the information stored by the memory cell, or may avoid or reduce the effect of read margin narrowing. In some examples, this technique may support improved performance of the memory device, such as extended-to-fail (ctf) performance, relaxed Bit Error Rate (BER) requirements, and other benefits.

In some memory devices, a delete or other action may cause a condition in which the state of information (e.g., logic state) written to or stored by a memory cell may be indeterminate (e.g., during a subsequent access operation). For example, in some cases, a memory device may not be able to distinguish whether a memory cell stores one logic state or another (e.g., whether a memory cell stores a logic 1 or a logic 0), or a memory device may read one logic state when reading a memory cell, but a different logic state is written to the memory cell (e.g., a logic 0 is detected during a read operation on a memory cell, but the memory cell is written to a logic 1). In some examples, memory cells with indeterminate logic states may cause errors in the corresponding codeword that need to be corrected (e.g., by an Error Correction Code (ECC) or ECC engine), or may cause the number of errors in the corresponding codeword to exceed the error correction capability (e.g., the error correction capability of the memory device, the error correction capability of a host device coupled with the memory device). Conditions such as these may degrade the performance of the memory device or a host device using the memory device for information storage, or may cause the operation of the memory device or the host device to fail.

In some examples, a memory device may be configured to identify an information location of a memory cell or corresponding codeword generated during an access operation associated with a deletion, a condition indicating a potential deletion, or a condition otherwise associated with an indeterminate information state. In some examples, a memory device may be configured to identify a condition indicative of charge leakage (e.g., charge leakage via a memory cell, charge leakage via an access line associated with an access operation) that may be associated with a higher likelihood of sensing that the memory cell stores a particular logic state (e.g., degrade or eliminate a read margin associated with reading a logic state). In some examples, a memory device may be configured to identify that a signal associated with reading a memory cell is within a range between a first threshold corresponding to a first information state (e.g., a signal threshold indicating a logic 0) and a second threshold corresponding to a second information state (e.g., a signal threshold indicating a logic 1), and that the signal within such range may indicate an uncertainty as to whether the memory cell stores the first information state or the second information state.

Identifying conditions associated with indeterminate information states may enhance aspects of error detection or error correction operations, including error detection or error correction operations that may be performed at a memory device or a host device (e.g., error correction operations performed at a memory controller located external to the memory device). For example, a memory device may identify that one or more information locations of one or more memory cells, one or more access lines, or a codeword are associated with an indeterminate information state. A corresponding codeword (e.g., generated during a read operation) may include some information locations having a detected or determined information state (e.g., a logical 0 or a logical 1) and some information locations having an indeterminate information state or otherwise unassigned information state (e.g., a logical X, a null logic state). An error detection operation or an error correction operation may be performed on one or more codewords (e.g., speculative codewords) in which information locations associated with indeterminate or unassigned logic states are replaced or assigned with respective assumed information states (e.g., logic X is replaced with logic 0, logic X is replaced with logic 1). By identifying information locations to be assigned this assumed information state, the ability to perform error detection or error correction to handle indeterminate states or combinations of indeterminate states and other error conditions (e.g., errors in the information state sensed at unknown memory cell or codeword locations) can be improved.

The features of the present disclosure are initially described in the context of memory devices, circuitry, and memory cell characteristics with reference to fig. 1-3. Features of the present disclosure are further described in the context of the example circuits and corresponding access operations with reference to fig. 4-5 and the generalized memory management approach for charge leakage in a memory device with reference to fig. 6. Features of the present disclosure are further described in the context of examples of read characteristics and erasure decoding methods with reference to fig. 7-8. These and other features of the present disclosure are further illustrated and described by and with reference to apparatus diagrams and flow diagrams related to memory management and erasure decoding of memory devices described with reference to fig. 9-13.

FIG. 1 illustrates an example of a memory device 100 supporting memory management and erasure decoding in accordance with examples disclosed herein. Memory device 100 may also be referred to as an electronic memory device. Memory device 100 may include memory cells 105 that are programmable to store different logic states. In some cases, memory cell 105 may be programmed to store two logic states, labeled logic 0 and logic 1. In some cases, memory cell 105 may be programmable to store more than two logic states. In various examples, memory cells 105 may include capacitive storage elements, ferroelectric storage elements, material memory elements, resistive memory elements, thresholded memory elements, phase change memory elements, or other types of storage elements (e.g., memory elements, charge storage elements, polarization storage elements).

A set of memory cells 105 may be part of a memory section 110 of the memory device 100 (e.g., including an array of memory cells 105), where in some examples, a memory section 110 may refer to a contiguous tile of memory cells 105 (e.g., a contiguous set of elements of a semiconductor chip). In some examples, memory segment 110 may refer to a minimum set of memory cells 105 that may be biased in an access operation or a minimum set of memory cells 105 that share a common electrical node (e.g., a common plate line, a set of plate lines biased to a common voltage). Although only a single memory segment 110 of the memory device 100 is shown, various examples of memory devices supporting the described techniques may have a set of one or more memory segments 110. In one illustrative example, the memory device 100 may include 32 "banks" and each bank may include 32 segments. Thus, memory device 100 according to an illustrative example may include 1,024 memory segments 110.

In some examples, memory cell 105 can store a charge representative of a programmable logic state (e.g., store a charge in a capacitor, a capacitive memory element, a capacitive storage element). In one example, charged and uncharged capacitors may represent two logic states, respectively. In another example, a positively charged (e.g., first polarity, positive polarity) and a negatively charged (e.g., second polarity, negative polarity) capacitor may represent two logic states, respectively. DRAM or FeRAM architectures may use this design, and the employed capacitors may include dielectric materials with linear or paraelectric polarization properties as insulators. In some examples, different charge levels of the capacitors may represent different logic states, which may support more than two logic states in respective memory cells 105 in some examples. In some examples, such as a FeRAM architecture, memory cell 105 may include a ferroelectric capacitor having a ferroelectric material as an insulating (e.g., non-conductive) layer between terminals of the capacitor. Different polarization levels or different polarization polarities of the ferroelectric capacitors may represent different logic states (e.g., two or more logic states are supported in the respective memory cells 105). The ferroelectric material has non-linear polarization properties, including those discussed in more detail with reference to fig. 3A and 3B.

In some examples, memory cells 105 may include or otherwise be associated with configurable materials, which may be referred to as material memory elements, material storage elements, material portions, and others. A configurable material may have one or more variable and configurable characteristics or properties (e.g., material states) that represent (e.g., correspond to) different logic states. For example, the configurable material may take on different forms, different atomic configurations, different degrees of crystallinity, different atomic distributions, or otherwise maintain different characteristics that may be used to represent one logic state or another. In some examples, such characteristics may be associated with different resistances, different threshold voltages, or other properties that may be detected or distinguished during a read operation to identify a logic state written to or stored by the configurable material.

In some cases, the configurable material of memory cell 105 may be associated with a threshold voltage. For example, when a voltage greater than a threshold voltage is applied across memory cell 105, current may flow through the configurable material, and when a voltage less than the threshold voltage is applied across memory cell 105, current may not flow through the configurable material or may flow through the configurable material at a rate below a certain level (e.g., in terms of a leakage rate). Thus, a voltage applied to memory cell 105 may result in a different current or a different sensed resistance or change in resistance (e.g., a thresholding event or a switching event), depending on whether the configurable material portion of memory cell 105 is written with one logic state or another. Thus, the magnitude of the current or other characteristic associated with the current resulting from applying the read voltage to memory cell 105 (e.g., thresholding behavior, resistive breakdown behavior, snap-back behavior) may be used to determine the logical state written to or stored by memory cell 105.

The memory device 100 may include a three-dimensional (3D) memory array, with multiple two-dimensional (2D) memory arrays (e.g., levels) formed on top of each other. In various examples, such arrays may be divided into a set of memory sections 110, where each memory section 110 may be arranged within a level or hierarchy, distributed across multiple levels or hierarchies, or distributed in any combination thereof. Such an arrangement may increase the number of memory cells 105 that can be placed or formed on a single die or substrate, which in turn may reduce production costs or increase performance of the memory device 100, or both, as compared to a 2D array. The layers or levels may be separated by electrically insulating material. Each level or level may be aligned or positioned such that memory cells 105 may be substantially aligned with each other across each level, therebyForming a stack of memory cells 105. In the example of the memory device 100, each row of memory cells 105 of the memory segment 110 can be associated with one of a set of first access lines 120 (e.g., a Word Line (WL), such as WL₁To WL_MSelect line) and each column of memory cells 105 may be coupled with one of a set of second access lines 130 (e.g., Digit Line (DL), such as DL) ₁To DL_NOne of the) is coupled. In some examples, a row of memory cells 105 of different memory sections 110 (not shown) may be associated with one of different pluralities of first access lines 120 (e.g., with a WL)₁To WL_MDifferent word lines) and a column of memory cells 105 of different memory segments 110 may be coupled with one of a different plurality of second access lines 130 (e.g., with DL)₁To DL_NDifferent digit lines). In some cases, first access line 120 and second access line 130 may be substantially perpendicular to each other in memory device 100 (e.g., when viewing a plane of a deck of memory device 100, as shown in fig. 1). The word lines and bit lines mentioned are interchangeable and do not compromise understanding or operation.

Typically, one memory cell 105 can be located at an intersection of an access line 120 and an access line 130 (e.g., coupled with the access line 120 and the access line 130, coupled between the access line 120 and the access line 130). This intersection may be referred to as the address of memory cell 105. The target or selected memory cell 105 may be a memory cell 105 located at the intersection of the activated or otherwise selected access line 120 and the activated or otherwise selected access line 130. In other words,

access lines

120 and 130 may be activated or otherwise selected to access (e.g., read, write, rewrite, refresh) memory cells 105 located at their intersection. Other memory cells 105 in electronic communication with (e.g., connected to) the

same access line

120 or 130 may be referred to as non-targeted or non-selected memory cells 105.

In some architectures, the logical storage component (e.g., capacitive storage element, ferroelectric storage element, material storage element) of memory cell 105 may be electrically isolated (e.g., selectively isolated) from second access line 130 by a cell selection component, which in some examples may be referred to as a switching component or selector device of memory cell 105 or otherwise associated with memory cell 105. The first access line 120 may be coupled with a cell select component (e.g., via a control node or terminal of the cell select component) and may control the cell select component of the memory cell 105. For example, the cell selection component may be a transistor and the first access line 120 may be coupled with a gate of the transistor (e.g., where a gate node of the transistor may be a control node of the transistor). Activating a first access line 120 of a memory cell 105 may form an electrical connection or close a circuit between the logic storage component of the memory cell 105 and its corresponding second access line 130. Second access line 130 may then be accessed to read or write to memory cell 105.

In some examples, memory cells 105 of memory section 110 may also be in communication with one of a plurality of third access lines 140 (e.g., Plate Lines (PLs), such as PLs) ₁To PL_NOne of the) is coupled. Although illustrated as separate lines, in some examples, the plurality of third access lines 140 may represent or otherwise be functionally equivalent to a common plate line, a common plate, or other common node of the memory section 110 (e.g., a node common to each of the memory cells 105 in the memory section 110), or other common node of the memory device 100. In some examples, the plurality of third access lines 140 may couple memory cells 105 with one or more voltage sources for various sense operations or write operations, including those described herein. For example, when memory cell 105 employs a capacitor to store a logic state, second access line 130 may provide access to a first terminal or plate of the capacitor, and third access line 140 may provide access to a second terminal or plate of the capacitor (e.g., a terminal associated with an opposing plate of the capacitor opposite the first terminal of the capacitor, a terminal on the otherwise opposite side of the capacitance from the first terminal of the capacitor). In some examples, storage of different memory sections 110 (not shown) The cell 105 may be associated with one of a different plurality of third access lines 140 (e.g., with PL)₁To PL_NDifferent sets of plate lines, different common plates, different common nodes).

The plurality of third access lines 140 may be coupled with a plate assembly 145, which may control various operations, such as activating one or more of the plurality of third access lines 140 or selectively coupling one or more of the plurality of third access lines 140 with a voltage source or other circuit elements. Although the plurality of third access lines 140 of memory device 100 are shown substantially parallel to the plurality of second access lines 130, in other examples, plurality of third access lines 140 may be substantially parallel to the plurality of first access lines 120, or in any other configuration (e.g., common planar conductor, common plate layer).

Although the access lines described with reference to FIG. 1 are shown as pass-through lines between the memory cells 105 and the coupled components, the access lines may include other circuit elements, such as capacitors, resistors, transistors, amplifiers, voltage sources, switching components, selection components, and others, which may be used to support access operations, including those described herein. In some examples, the electrodes may be coupled with memory cells 105 and access lines 120 (e.g., between memory cells 105 and access lines 120) or coupled with memory cells 105 and access lines 130 (e.g., between memory cells 105 and access lines 130). The term electrode may refer to an electrical conductor or other electrical interface between components, and may be used as an electrical contact to memory cell 105 in some cases. The electrodes may include traces, wires, conductive lines, conductive layers, conductive pads, etc., that provide conductive paths between elements or components of the memory device 100.

Access operations (e.g., read, write, rewrite, and refresh) may be performed on memory cells 105 by activating or selecting first access line 120, second access line 130, or third access line 140 coupled with memory cells 105, which may include applying voltages, charges, or currents to the respective access lines.

Access lines

120, 130, and 140 can be made of conductive materials, such as metals (e.g., copper (Cu), silver (Ag), aluminum (Al), gold (Au), tungsten (W), titanium (Ti))), metal alloys, carbon, or other conductive or semiconductive materials, alloys, or compounds. The generated signal may be used to determine the logic state stored by memory cell 105 when selecting memory cell 105. For example, a memory cell 105 having a capacitive memory element storing a logic state may be selected, and a resulting flow of charge through an access line or a resulting voltage of the access line may be detected to determine a programmed logic state stored by the memory cell 105.

Access to the memory cells 105 may be controlled by row components 125 (e.g., a row decoder), column components 135 (e.g., a column decoder), or plate components 145 (e.g., a plate driver), or a combination thereof. For example, row component 125 may receive a row address from memory controller 170 and activate the appropriate first access line 120 based on the received row address. Similarly, the column component 135 may receive a column address from the memory controller 170 and activate the appropriate second access line 130. Thus, in some examples, memory cells 105 may be accessed by activating first access line 120 and second access line 130. In some examples, such access operations may be accompanied by the board assembly 145 biasing one or more of the third access lines 140 (e.g., biasing one of the third access lines 140 of the memory segment 110, biasing all of the third access lines 140 of the memory segment, biasing a common board line of the memory segment 110 or the memory device 100, biasing a common node of the memory segment 110 or the memory device 100), which may be referred to as "moving" the memory cell 105, the memory segment 110, or the "board" of the memory device 100.

In some examples, memory controller 170 may control the operation (e.g., read operation, write operation, rewrite operation, refresh operation, discharge operation, voltage adjustment operation, dissipation operation, equilibrate operation) of memory cells 105 through various components (e.g., row components 125, column components 135, plate components 145, sense components 150). In some cases, one or more of the row components 125, column components 135, plate components 145, and sensing components 150 may be co-located or otherwise included with the memory controller 170. Memory controller 170 may generate row address signals and column address signals to activate desired access lines 120 and access lines 130. Memory controller 170 may also generate or control various voltages or currents used during operation of memory device 100. Although only a single memory controller 170 is shown, other examples of the memory device 100 may have more than one memory controller 170 (e.g., a memory controller 170 for each of a set of memory sections 110 of the memory device, a memory controller 170 for each of a number of subsets of memory sections 110 of the memory device 100, a memory controller 170 for each of a set of chips of the multi-chip memory device 100, a memory controller 170 for each of a set of banks of the multi-bank memory device 100, a memory controller 170 for each core of the multi-core memory device 100, or any combination thereof), where different memory controllers 170 may perform the same function or different functions.

Although the memory device 100 is illustrated as including a single row component 125, a single column component 135, and a single plate component 145, other examples of the memory device 100 may include different configurations to accommodate a set of memory segments 110. For example, in various memory devices 100, a row component 125 may be shared among a set of memory segments 110 (e.g., having a subcomponent common to all memory segments in a set of memory segments 110, having a subcomponent dedicated to a respective memory segment in a set of memory segments 110), or a row component 125 may be dedicated to one memory segment 110 in a set of memory segments 110. Likewise, in various memory devices 100, a bank component 135 may be shared among a set of memory segments 110 (e.g., having a subcomponent common to all memory segments in a set of memory segments 110, having a subcomponent dedicated to a respective memory segment in a set of memory segments 110), or a bank component 135 may be dedicated to one memory segment 110 in a set of memory segments 110. Additionally, in various memory devices 100, the board assembly 145 may be shared among a set of memory segments 110 (e.g., having a subcomponent common to all memory segments in a set of memory segments 110, having a subcomponent dedicated to a respective memory segment in a set of memory segments 110), or the board assembly 145 may be dedicated to one memory segment 110 in a set of memory segments 110.

In general, adjustments or variations can be made to the amplitude, shape, or duration of the applied voltage, current, or charge, and the amplitude, shape, or duration can be different for the various operations discussed for operating the memory device 100. Further, one, more, or all of the memory cells 105 within the memory device 100 may be accessed simultaneously. For example, each of the memory cells 105 sharing a common access line 120 or some subset of the memory cells 105 sharing a common access line 120 (e.g., a common cell select line) may be accessed simultaneously (e.g., according to a memory row access arrangement, according to a "page" access arrangement, according to a set of access lines 130, or columns that may be accessed or sensed simultaneously). In another example, multiple or all memory cells 105 of the memory device 100 may be accessed simultaneously during a reset operation in which all memory cells 105 or groups of memory cells 105 (e.g., memory cells 105 of a memory segment 110) are set to a single logic state.

When accessing memory cell 105 (e.g., in cooperation with memory controller 170), memory cell 105 may be read (e.g., sensed) by sensing component 150 to determine a logical state written to or stored by memory cell 105. For example, the sensing component 150 may be configured to sense a current or charge transfer through or from the memory cell 105 or a voltage resulting from coupling the memory cell 105 with the sensing component 150 or other intervening components (e.g., a signal generating component between the memory cell 105 and the sensing component 150) in response to a read operation. The sensing component 150 can provide an output signal indicative of the logic state read from the memory cell 105 to one or more components (e.g., to the column component 135, the input/output component 160, the memory controller 170). In various memory devices 100, the sensing component 150 may be shared among a set of memory segments 110 (e.g., having a subcomponent common to all memory segments in a set of memory segments 110, having a subcomponent dedicated to a respective memory segment in a set of memory segments 110), or the sensing component 150 may be dedicated to one memory segment 110 in a set of memory segments 110.

In some examples, during or after access to memory cell 105, the storage element of memory cell 105 may discharge or otherwise permit charge or current to flow through its

corresponding access line

120, 130, or 140. Such charge or current may result from biasing or applying a voltage to memory cells 105 from one or more voltage sources or supplies (not shown) of memory device 100, where such voltage sources or supplies may be part of row components 125, column components 135, plate components 145, sense components 150, memory controller 170, or some other component (e.g., a biasing component). In some examples, the charge shared between the selected memory cell 105 and the access line 130 may cause the voltage of the access line 130 to change, and the sensing component 150 may compare the voltage of the access line 130 to a reference voltage to determine the logical state stored by the memory cell 105.

The sensing component 150 can include various switching components, selection components, transistors, amplifiers, capacitors, resistors, or voltage sources to detect or amplify differences in the sense signal (e.g., differences between read voltage and reference voltage, differences between read current and reference current, differences between read charge and reference charge), which can be referred to as latching in some examples. In some examples, the sensing component 150 can include a set of components (e.g., circuit elements) that is repeated for each of a set of access lines 130 connected to the sensing component 150. For example, the sensing component 150 can include separate sensing circuitry (e.g., separate or duplicate sense amplifiers, separate or duplicate signal generation components) for each of a set of access lines 130 coupled with the sensing component 150 such that a logic state can be separately detected for respective memory cells 105 coupled with respective access lines of the set of access lines 130. In some examples, the reference signal source (e.g., reference component) or generated reference signal may be shared among components of the memory device 100 (e.g., shared among one or more sense components 150, shared among separate sense circuits of the sense components 150, shared among

access lines

120, 130, or 140 of the memory segment 110). In some examples, the detected logic state of the memory cell 105 may be output as an output by the column component 135 or the input/output component 160.

The sensing component 150 can be included in a device that includes the memory device 100. For example, the sensing component 150 may be included with other read and write circuits, decode circuits, or register circuits that may be coupled to a memory of the memory device 100. In some examples, the detected logic state of the memory cell 105 may be output as an output by the column component 135 or the input/output component 160. In some instances, the sensing component 150 may be part of the column component 135 or the row component 125. In some examples, the sensing component 150 can be connected to or otherwise in electronic communication with the column component 135 or the row component 125.

Although a single sense component 150 is shown, the memory device 100 (e.g., the memory section 110 of the memory device 100) may include more than one sense component 150. For example, a first sensing component 150 can be coupled with a first subset of access lines 130 and a second sensing component 150 can be coupled with a second subset of access lines 130 (e.g., different from the first subset of access lines 130). In some examples, this division of sensing components 150 may support parallel (e.g., simultaneous) operation of multiple sensing components 150. In some examples, this division of sensing components 150 may support sensing components 150 having different configurations or characteristics to match particular subsets of memory cells 105 of a memory device (e.g., support different types of memory cells 105, support different characteristics of subsets of access lines 130). Additionally or alternatively, two or more sense components 150 can be coupled with the same set of access lines 130 (e.g., for component redundancy). In some examples, such a configuration may support maintenance functionality to overcome operational failure or otherwise poor operation of one of the redundant sensing components 150. In some examples, such a configuration may support the ability to select one of the redundant sense components 150 for particular operating characteristics (e.g., as a function of power consumption characteristics, as a function of access speed characteristics for a particular sense operation, as a function of operating the memory cell 105 in a volatile mode or a non-volatile mode).

In some memory architectures, accessing the memory cell 105 may degrade or destroy the stored logic state, and a rewrite or refresh operation may be performed to restore the memory cell 105 to the stored logic state. In a DRAM or FeRAM, for example, the capacitor of memory cell 105 may be partially or fully discharged during a sensing operation, thus corrupting the logic state stored in memory cell 105. Thus, in some examples, the logic state stored in memory cell 105 may be rewritten during an access operation. Moreover, activating a

single access line

120, 130, or 140 can cause all memory cells 105 coupled with the activated

access line

120, 130, or 140 to discharge. Thus, several or all of the memory cells 105 coupled with the

access line

120, 130, or 140 associated with the access operation (e.g., all cells of an accessed row, all cells of an accessed column) may be rewritten after the access operation.

In some examples, reading memory cell 105 may be non-destructive. That is, the logic state of memory cell 105 may not need to be rewritten after memory cell 105 is read. However, in some examples, the logic state of memory cell 105 may or may not need to be refreshed when there are no or other access operations. For example, the logic state stored by memory cell 105 may be refreshed at periodic intervals by applying appropriate write pulses, rewrite pulses, refresh pulses, or equalization pulses or biases to maintain the stored logic state. Refreshing memory cells 105 may reduce or eliminate read disturb errors or logic state damage due to charge leakage or changes in the material configuration of the memory element over time.

Memory cells 105 may be set or written to by activating the relevant first access line 120, second access line 130, or third access line 140 (e.g., via memory controller 170). In other words, a logic state may be stored in memory cell 105. For example, row component 125, column component 135, or board component 145 can accept data to be written to memory cells 105 via input/output component 160. In some examples, the write operation may be performed at least partially by the sensing component 150, or the write operation may be configured to bypass the sensing component 150.

In the case of a capacitive memory element, memory cell 105 may be written by applying a voltage to or across the capacitor and then isolating the capacitor (e.g., isolating the capacitor from the voltage source used to write to memory cell 105, floating the capacitor) to store a charge associated with the desired logic state in the capacitor. In the case of ferroelectric memory, the ferroelectric memory element (e.g., ferroelectric capacitor) of memory cell 105 may be written to by: a voltage is applied that is sufficiently high in magnitude to polarize the ferroelectric memory element into a polarization associated with the desired logic state (e.g., a saturation voltage is applied), and the ferroelectric memory element may be isolated (e.g., floated), or a zero net voltage or bias may be applied across the ferroelectric memory element (e.g., ground, virtual ground, or equalize the voltage across the ferroelectric memory element). In the case of a material memory architecture, memory cells 105 may be written by applying a current, voltage, or other heating or biasing to the material memory element to configure the material according to the corresponding logic state.

In some examples, memory device 100 may include a set of memory segments 110. Each of the memory segments 110 may include a set of memory cells 105, the set of memory cells 105 being coupled with one of a set of second access lines 130 and one of a set of third access lines 140 (e.g., of the respective memory segment 110), or between one of a set of second access lines 130 and one of a set of third access lines 140. Each of the memory cells 105 may include a cell select component configured to selectively couple the memory cells 105 with either the associated second access line 130 or the associated third access line 140 (e.g., of the respective memory segment 110). In some examples, each of the cell selection components may be coupled with a respective first access line in first access line 120 (e.g., of memory segment 110) (e.g., at a control node or control terminal of the respective cell selection component), which may be used to activate or deactivate the particular cell selection component.

An access operation may be performed on selected memory cells 105 of the memory segment 110, which may include a read operation, a write operation, a rewrite operation, a refresh operation, or various combinations thereof. In some examples, an access operation may be associated with biasing the second access line 130 or the third access line 140 associated with the selected memory cell 105. During an access operation, the cell select component for a selected memory cell 105 may be activated such that the selected memory cell 105 may be selectively coupled with the second access line 130 or the third access line 140. Thus, as a result of biasing second access line 130 or third access line 140 for an access operation, signals associated with the access operation (e.g., voltages associated with the access operation, charges associated with the access operation, currents associated with the access operation) may pass to, from, or through selected memory cells 105.

In some examples, charge may leak from one portion of memory device 100 or memory section 110 to another. Possible leakage causes include manufacturing defects, component breakdown (e.g., Thin Film Transistor (TFT) breakdown or leakage), memory cell wear mechanisms (e.g., Stress Induced Leakage Current (SILC), Breakdown (BD) current), compositional changes, or other causes. For example, charge may leak across cell select components of memory cell 105, across dielectric material of capacitive storage elements, from one access line to another access line of memory device 100 (e.g., from access line 130 to another

access line

120, 130, or 130), across transistor leakage intended to deactivate (e.g., across transistor leakage to switch to a non-conductive state), and other leakage is present. In some examples, charge leakage can negatively impact the performance of the memory device 100 (e.g., cause a different logic state to be detected when a memory cell is read than was previously written to the memory cell). Thus, in accordance with the techniques disclosed herein, a memory device 100 (e.g., memory controller 170) may be configured to determine whether to store a direct logic state or a complementary logic state to a memory cell 105 or a group of memory cells 105 based on a detection of charge leakage in the memory device 100.

In some examples, a delete or other action may result in a condition in which the state of information (e.g., logic state) written to or stored by memory cell 105 may be indeterminate (e.g., in a subsequent access operation). For example, in some cases, memory device 100 may not be able to distinguish whether memory cell 105 stores one logic state or another (e.g., whether the memory cell stores a logic 1 or a logic 0), or memory device 100 may detect one logic state when reading memory cell 105 but write to memory cell 105 a different logic state (e.g., a logic 0 is detected during a read operation on the memory cell but the memory cell is written to a logic 1).

In some examples, memory device 100 may be configured to identify various conditions that may be associated with an indeterminate or indeterminate state of information. For example, memory device 100 may identify one or more memory cells 105, one or more access lines (e.g., access line 130), or one or more information locations of a codeword associated with an indeterminate or indeterminate information state. A corresponding codeword (e.g., generated during a read operation) may include some information locations having a detected information state (e.g., a logical 0 or a logical 1) and some information locations having an indeterminate information state or otherwise unassigned information state (e.g., a logical X, a null logic state). Error handling operations may be performed on codewords in which information locations associated with indeterminate or unassigned logical states are replaced or assigned with respective assumed or speculative information states (e.g., logic X is replaced with logic 0, logic X is replaced with logic 1), which may improve the ability to handle various errors and have other benefits.

FIG. 2 illustrates an example circuit 200 that supports memory management and erasure decoding of memory devices in accordance with examples disclosed herein. The circuit 200 includes a memory cell 105-a, which memory cell 105-a may be an example of the memory cell 105 described with reference to FIG. 1. The circuit 200 also includes a sense amplifier 290, which sense amplifier 290 may be part of the sensing component 150 described with reference to FIG. 1. The circuit 200 may also include word lines 205, digit lines 210, and plate lines 215, in some examples, the word lines 205, digit lines 210, and plate lines 215 may correspond to the first access lines 120, second access lines 130, and third access lines 140 (of the memory segment 110, for example) described with reference to fig. 1, respectively. In some examples, plate line 215 may illustrate a common plate line, a common plate, or another common node of memory cell 105-a and another memory cell 105 (not shown) of the same memory segment 110. Circuit 200 may also include a reference line 265 used by sense amplifier 290 to determine the logic state stored by memory cell 105-a.

As illustrated in fig. 2, the sense amplifier 290 may include a first node 291 and a second node 292, which may be coupled with different access lines of circuitry (e.g., with the signal line 260 and the reference line 265, respectively, of the circuit 200) in some examples, or with a common access line of different circuitry (not shown) in other examples. In some examples, the first node 291 may be referred to as a signal node and the second node 292 may be referred to as a reference node. However, other configurations of access lines or reference lines may be used to support the techniques described herein.

Memory cell 105-a may include a logic storage component (e.g., memory element, storage element, memory storage element), such as a capacitor 220 having a first plate, a cell plate 221, and a second plate, a cell bottom 222. Cell plate 221 and cell bottom 222 may be capacitively coupled by a dielectric material located therebetween (e.g., in DRAM applications) or by a ferroelectric material located therebetween (e.g., in FeRAM applications). The cell plate 221 may be connected to a voltage V_plateAssociated with, and cell bottom 222 can be at a voltage V_bottomAssociated as illustrated in circuit 200. The orientation of the cell plate 221 and the cell bottom 222 can be different (e.g., flipped) without changing the operation of the memory cell 105-a. Can be passed throughCell plate 221 is accessed by plate line 215 and cell bottom 222 can be accessed via digit line 210. As described herein, various logic states may be stored by charging, discharging, or polarizing capacitor 220.

The capacitor 220 may be electrically connected to the digit line 210 and the logic state stored by the capacitor 220 may be read or sensed by operating the various elements represented in the circuit 200. For example, memory cell 105-a may also include a cell select component 230, which in some examples, the cell select component 230 may be referred to as a switching component or selector device coupled with or between an access line (e.g., digit line 210) and a capacitor 220. In some examples, cell selection component 230 may be considered to be located outside of the illustrative boundaries of memory cell 105-a, and cell selection component 230 may be referred to as a switching component or selector device coupled with or between an access line (e.g., digit line 210) and memory cell 105-a.

The capacitor 220 may be selectively coupled with the digit line 210 when the cell selection component 230 is activated (e.g., by activating a logic signal), and the capacitor 220 may be selectively isolated from the digit line 210 when the cell selection component 230 is deactivated (e.g., by deactivating the logic signal). A logic signal or other select signal or voltage (e.g., via word line 205, select line) may be applied to a control node 235 (e.g., control node, control terminal, select node, select terminal) of the cell select component 230. In other words, the cell select component 230 may be configured to selectively couple or decouple the capacitor 220 and the digit line 210 based on a logic signal or voltage applied to the control node 235 via the word line 205.

The active unit selection component 230 may be referred to as selecting or activating the memory unit 105-a, and de-selecting or de-activating the active unit selection component 230 may be referred to as de-selecting or de-activating the memory unit 105-a. In some examples, cell select component 230 is a transistor and its operation may be controlled by applying an activation voltage to a transistor gate (e.g., a control or select node or terminal). The voltage used to activate the transistor (e.g., the voltage between the transistor gate terminal and the transistor source terminal) may be a voltage greater than the threshold voltage magnitude of the transistor. The word line 205 may be used to activate the cell select component 230. For example, a selection voltage (e.g., a word line logic signal or a word line voltage) applied to the word line 205 may be applied to the gate of a transistor of the cell select component 230, which cell select component 230 may selectively connect the capacitor 220 with the digit line 210 (e.g., provide a conductive path between the capacitor 220 and the digit line 210). In some examples, activating cell selection component 230 can be referred to as selectively coupling memory cell 105-a with digit line 210.

In other examples, the location of cell select component 230 and capacitor 220 in memory cell 105-a may be switched such that cell select component 230 may be coupled with or between plate line 215 and cell plate 221, and capacitor 220 may be coupled with or between digit line 210 and another terminal of cell select component 230. In this example, cell select component 230 may be in electronic communication with digit line 210 through capacitor 220. Such a configuration may be associated with alternative timing and biasing for access operations.

In examples employing ferroelectric capacitors 220, the capacitors 220 may or may not fully discharge when connected to the digit lines 210. In various schemes, to sense the logic state stored by the ferroelectric capacitor 220, a voltage can be applied to the plate line 215 or the digit line 210, and the word line 205 can be biased (e.g., by activating the word line 205) to select the memory cell 105-a. In some cases, prior to activating the word line 205, the plate line 215 or the digit line 210 may be virtually grounded and then isolated from the virtual ground, which may be referred to as a floating condition, an idle condition, or a standby condition.

Operating memory cell 105-a by varying the voltage to cell plate 221 (e.g., via plate line 215) may be referred to as "moving the cell plate". Biasing plate line 215 or digit line 210 may result in a voltage difference (e.g., the voltage of digit line 210 minus the voltage of plate line 215) across capacitor 220. The voltage difference may be accompanied by a change in the stored charge on the capacitor 220 (e.g., due to charge sharing between the capacitor 220 and the digit line 210, due to charge sharing between the capacitor 220 and the plate line 215), where the amount of change in the stored charge may depend on the initial state of the capacitor 220 (e.g., whether the initial charge or logic state stores a logic 1 or a logic 0). In some schemes, a change in the charge stored by capacitor 220 may result in a change in the voltage of one or both of digit line 210 or signal line 260, which may be used by sense amplifier 290 to determine the logic state stored by memory cell 105-a.

Digit line 210 may be coupled with additional memory cells 105 (not shown), and digit line 210 may have properties that result in a non-negligible intrinsic capacitance 240, e.g., on the order of a few picofarads (pF), that intrinsic capacitance 240 may couple digit line 210 with voltage source 250-a. The voltage source 250-a may represent a common ground or virtual ground voltage or a voltage of an adjacent access line of the circuit 200 (not shown). Although illustrated as a separate element in fig. 2, the inherent capacitance 240 may be associated with properties distributed throughout the digit line 210.

In some examples, intrinsic capacitance 240 may depend on physical characteristics of digit line 210, including conductor dimensions (e.g., length, width, thickness) of digit line 210. The inherent capacitance 240 may also depend on the characteristics of, proximity to, or insulating characteristics between the digit line 210 and neighboring access line or circuit components. Thus, the change in voltage of digit line 210 after selecting memory cell 105-a can depend on (e.g., be associated with) the net capacitance of digit line 210. In other words, as charge flows along digit line 210 (e.g., to digit line 210, from digit line 210), some finite charge may be stored along digit line 210 (e.g., stored in inherent capacitance 240, other capacitors coupled with digit line 210, or capacitance), and the resulting voltage of digit line 210 may depend on the net capacitance of digit line 210.

Sense amplifier 290 may compare the resulting voltage of digit line 210 or signal line 260 to a reference (e.g., the voltage of reference line 265) after selecting memory cell 105-a to determine the logic state stored in memory cell 105-a. In some examples, reference component 285 may provide a voltage of reference line 265. In other examples, the reference component 285 may be omitted and the reference voltage may be provided, for example, by accessing the memory cell 105-a to generate the reference voltage (e.g., in a self-reference access operation). Other operations may be used to support selection or sensing of memory cell 105-a.

In some examples, circuit 200 may include signal generation component 280, signal generation component 280 may be an example of a signal generation circuit coupled with memory cell 105-a and sense amplifier 290 or coupled between memory cell 105-a and sense amplifier 290. Prior to the sensing operation, signal generation component 280 may amplify or otherwise convert the signal of digit line 210. The signal generating component 280 may include, for example, a transistor, an amplifier, a cascode, or any other charge or voltage converter or amplifier component. In some examples, signal generation component 280 may include a Charge Transfer Sense Amplifier (CTSA) that may include one or more transistors in a gate-cathode configuration or a voltage controlled configuration. In some examples with signal generating component 280, the line between sense amplifier 290 and signal generating component 280 may be referred to as a signal line (e.g., signal line 260). In some instances (e.g., instances with or without signal generating component 280), digit lines 210 may be directly electrically connected with sense amplifiers 290.

In some examples, the circuit 200 may include a bypass line 270, which bypass line 270 may permit selective bypass of the signal generating component 280 or some other signal generating circuit between the memory cell 105-a and the sense amplifier 290. In some examples, the bypass line 270 may be selectively enabled by the switching component 275. In other words, when the switching component 275 is activated, the digit line 210 can be coupled with the signal line 260 via the bypass line 270 (e.g., coupling the memory cell 105-a with the sense amplifier 290).

In some examples, when the switching component 275 is activated, the signal generation component 280 may be selectively isolated from one or both of the digit line 210 or the signal line 260 (e.g., by another switching component or selection component, not shown). When the switching component 275 is deactivated, the digit line 210 may be selectively coupled with the signal line 260 via the signal generation component 280. In other examples, the selection component can be used to selectively couple the memory cell 105-a (e.g., digit line 210) with one of the signal generation component 280 or the bypass line 270. Additionally or alternatively, in some examples, a selection component may be used to selectively couple the sense amplifier 290 with one of the signal generation component 280 or the bypass line 270. In some examples, the selectable bypass line 270 may support generating a sense signal for detecting the logic state of the memory cell 105-a using the signal generation component 280 and generating a write signal to write the logic state to the memory cell 105-a bypassing the signal generation component 280.

Some examples of memory devices 100 supporting the techniques disclosed herein may include circuitry 200 that shares a common access line (not shown) between memory cells 105 and sense amplifiers 290 to support the generation of sense and reference signals from the same memory cells 105. In one example, a common access line between the signal generating component 280 and the sense amplifier 290 can replace the signal line 260 and the reference line 265 illustrated in the circuit 200. In such examples, a common access line may be connected to the sense amplifier 290 at two different nodes (e.g., a first node 291 and a second node 292, as described herein). In some examples, a common access line may permit a self-reference read operation to share components that may exist between the sense amplifier 290 and the memory cell 105 being accessed in both signal generation and reference generation operations. This configuration may reduce the sensitivity of the sense amplifier 290 to operational variations of various components in the memory device 100, such as the memory cells 105, access lines (e.g., word lines 205, digit lines 210, plate lines 215), signal generation circuitry (e.g., signal generation component 280), transistors, voltage source 250, and others.

Although digit line 210 and signal line 260 are identified as separate lines, digit line 210, signal line 260, and any other lines connecting memory cell 105 and sense amplifier 290 may all be referred to as a single access line. In various example configurations, the constituent parts of such an access line may be separately identified for purposes of illustrating intervening components and intervening signals.

The sense amplifier 290 may include various transistors or amplifiers to detect, convert, or amplify the signal difference, which may be referred to as latching. For example, the sense amplifier 290 may include a voltage (e.g., V) of a sense signal received and compared at the first node 291_sig) And a reference signal voltage (e.g., V) at a second node 292_ref) The circuit element of (1). The output of the sense amplifier may be driven to a higher voltage (e.g., positive voltage) or a lower voltage (e.g., negative voltage, ground voltage) based on the comparison at the sense amplifier 290.

For example, if the first node 291 has a lower voltage than the second node 292, the output of the sense amplifier 290 may be driven to a relatively lower voltage (e.g., voltage V) of the first sense amplifier voltage source 250-b_LIt may be substantially equal to V₀May be a negative voltage). The sensing component 150 including the sense amplifier 290 may latch the output of the sense amplifier 290 to determine the logic state stored in the memory cell 105-a (e.g., a logic 0 is detected when the first node 291 has a lower voltage than the second node 292).

If the first node 291 has a higher voltage than the second node 292, then the output of the sense amplifier 290 may be driven to the voltage of the second sense amplifier voltage source 250-c (e.g., voltage V_H). The sensing component 150 including the sense amplifier 290 may latch the output of the sense amplifier 290 to determine the logic state stored in the memory cell 105-a (e.g., a logic 1 is detected when the first node 291 has a higher voltage than the second node 292). The latched output of the sense amplifier 290 corresponding to the detected logic state of memory cell 105-a may then be output via one or more input/output (I/O) lines (e.g., I/O line 295) that may include an output through the column component 135 or the input/output component 160 described with reference to fig. 1.

To perform a write operation on memory cell 105-a, a voltage may be applied across capacitor 220. Various methods may be used. In one example, the cell select component 230 can be activated by the wordline 205 (e.g., by activating the wordline 205) to electrically connect the capacitor 220 to the digit line 210. A voltage may be applied across the capacitor 220 by controlling the voltage of the cell plate 221 (e.g., through plate line 215) and the cell bottom 222 (e.g., through digit line 210).

For example, to write a logic 0, cell plate 221 may be placed high (e.g., a positive voltage is applied to plate line 215), and cell bottom 222 may be placed low (e.g., digit line 210 is grounded, digit line 210 is virtually grounded, a negative voltage is applied to digit line 210). The reverse process may be performed to write a logic 1, with cell plate 221 placed low and cell bottom 222 placed high. In some cases, the voltage applied across the capacitor 220 during a write operation may have a magnitude equal to or greater than the saturation voltage of the ferroelectric material in the capacitor 220, such that the capacitor 220 is polarized and thus charge is maintained even when the magnitude of the applied voltage is reduced or with zero net voltage applied across the capacitor 220. In some examples, the sense amplifier 290 may be used to perform a write operation, which may include coupling the first sense amplifier voltage source 250-b or the second sense component voltage source 250-c with a digit line. When the sense amplifier 290 is used to perform a write operation, the signal generation component 280 may or may not be bypassed (e.g., by applying a write signal via the bypass line 270).

The circuit 200 including the sense amplifier 290, the cell selection component 230, the signal generation component 280, or the reference component 285 may include various types of transistors. For example, the circuit 200 may include an n-type transistor, wherein application of a relatively positive voltage to the gate of the n-type transistor (e.g., the applied voltage has a positive magnitude relative to the source terminal that is greater than the threshold voltage) that is higher than the threshold voltage of the n-type transistor enables a conductive path between other terminals (e.g., the source terminal and the drain terminal) of the n-type transistor.

In some examples, an n-type transistor may be used as a switching component, where the applied voltage is a logic signal whose usage is: the conductivity of the pass-through transistor is enabled by applying a relatively high logic signal voltage (e.g., a voltage corresponding to a logic 1 state, which may be associated with a positive logic signal voltage supply), or disabled by applying a relatively low logic signal voltage (e.g., a voltage corresponding to a logic 0 state, which may be associated with a ground voltage or a virtual ground voltage). In some examples where an n-type transistor is used as the switching component, the voltage of the logic signal applied to the gate terminal may be selected to cause the transistor to operate at a particular operating point (e.g., in the saturation region or in the active region).

In some examples, the behavior of an n-type transistor may be more complex than logic switching, and the selective conductivity across the transistor may also be a function of varying source and drain voltages. For example, the voltage applied at the gate terminal may have a particular voltage level (e.g., a clamping voltage) for enabling conductivity between the source terminal and the drain terminal when the source terminal voltage is below a particular level (e.g., below the gate terminal voltage minus a threshold voltage). When the voltage of the source terminal voltage or the drain terminal voltage rises above a certain level, the n-type transistor may be deactivated such that the conductive path between the source terminal and the drain terminal is broken.

Additionally or alternatively, the circuit 200 may include a p-type transistor, wherein application of a relatively negative voltage to a gate of the p-type transistor (e.g., the applied voltage has a negative magnitude relative to a source terminal that is greater than a threshold voltage) that is higher than a threshold voltage of the p-type transistor enables a conductive path between other terminals (e.g., a source terminal and a drain terminal) of the p-type transistor.

In some examples, a p-type transistor may be used as a switching component, where the applied voltage is a logic signal whose usage is: conductivity is enabled by applying a relatively low logic signal voltage (e.g., a voltage corresponding to a logic "1" state, which may be associated with a negative logic signal voltage supply) or disabled by applying a relatively high logic signal voltage (e.g., a voltage corresponding to a logic "0" state, which may be associated with a ground voltage or a virtual ground voltage). In some examples where a p-type transistor is used as the switching component, the voltage of the logic signal applied to the gate terminal may be selected to cause the transistor to operate at a particular operating point (e.g., in the saturation region or in the active region).

In some examples, the behavior of a p-type transistor may be more complex than logical switching by gate voltage, and the selective conductivity across the transistor may also vary with varying source and drain voltages. For example, the voltage applied at the gate terminal may have a particular voltage level for enabling conductivity between the source and drain terminals as long as the source terminal voltage is above a particular level (e.g., above the gate terminal voltage plus a threshold voltage). When the voltage of the source terminal voltage drops below a certain level, the p-type transistor may be deactivated such that the conductive path between the source terminal and the drain terminal is broken.

The transistors of the circuit 200 may be Field Effect Transistors (FETs), including metal oxide semiconductor FETs, which may be referred to as MOSFETs. These and other types of transistors may be formed by doped regions of material on a substrate. In some examples, the transistor may be formed on a substrate dedicated to particular components of the circuit 200 (e.g., a substrate for the sense amplifier 290, a substrate for the signal generation component 280, a substrate for the memory cell 105-a), or the transistor may be formed on a substrate common to particular components of the circuit 200 (e.g., a substrate common to the sense amplifier 290, the signal generation component 280, and the memory cell 105-a). Some FETs may have metal portions that include aluminum or other metals, but some FETs (including those that may be referred to as MOSFETs) may implement other non-metallic materials, such as polysilicon. Further, while oxide portions may be used as dielectric portions of FETs, other non-oxide materials may be used in the dielectric materials in FETs, including those FETs that may be referred to as MOSFETs.

Although the circuit 200 illustrates a set of components relative to a single memory cell 105, various components of the circuit 200 may be duplicated in the memory device 100 to support various operations. For example, to support a row access or "page" access operation, the memory device 100 may be configured with multiple ones of one or more of the sense amplifiers 290, the signal lines 260, the signal generation components 280, the digit lines 210, or other components, where the multiple ones may be configured according to the number of memory cells 105 that may be accessed in a row access or "page" access operation (e.g., in a concurrent operation). In various examples, a set of such pluralities may correspond to or otherwise be repeated for each memory segment 110 in the memory device 100, or such a set of pluralities may be shared among one or more memory segments 110 in the memory device.

In one illustrative example, for a memory device 100 that supports 256 cell row accesses (e.g., 256 columns accessed in common) or 256 bit pages, the memory device 100 (e.g., the sense component 150) can include at least a set of 256 sense amplifiers 290, 256 signal lines 260, 256 signal generation components 280, and 256 word lines 210, wherein in some examples a set of 256 memory cells 105 in a memory section 110 can be accessed by activating a single common word line 205. In some examples, such repetition may correspond to a single memory segment 110, or may correspond to more than one memory segment 110. However, various other configurations and combinations of components may be used for row access operations or page access operations in support of the techniques described herein, or other operations in which multiple memory cells 105 are accessed simultaneously.

In some examples, sense amplifier 290 may not be able to distinguish whether memory cell 105-a is written with one logic state or another (e.g., whether memory cell 105-a stores a logic 1 or a logic 0), or sense amplifier 290 may detect one logic state when reading memory cell 105-a, but a different logic state is written to memory cell 105-a (e.g., a logic 0 is detected on the memory cell during a read operation, but the memory cell is written with a logic 1). Such a condition may be associated with an indeterminate information state of memory cell 105-a, and may relate to various conditions, such as deletion, charge leakage, degradation of the information state (e.g., degradation of the logic state, charge state, or material state of memory cell 105-a), or other phenomena.

In some examples, the indeterminate information state of memory cell 105-a may be the result of charge leakage from one portion of circuit 200 to another. Possible causes of leakage include manufacturing defects, component breakdown (e.g., Thin Film Transistor (TFT) breakdown or leakage), memory cell wear mechanisms (e.g., Stress Induced Leakage Current (SILC), Breakdown (BD) current), changes in the material composition of elements of the circuit 200, or other causes. For example, charge may leak across the cell select component 230 (e.g., leakage path "a"), across the dielectric material of the capacitor 220 (e.g., leakage path "B"), from one access line to another access line of the memory device 100 (e.g., leakage path "C" from the digit line 210 to another access line or to bottom plate ground). Other examples not illustrated may include other leakage paths that permit charge transfer between: between a memory cell 105-a of the memory device 100 including the circuit 200 and another component, between a digit line 210 and another component of the memory device 100 including the circuit 200 (e.g., between a digit line 210 and another digit line 210 (not shown)), or between a signal line 260 and another component of the memory device 100 including the circuit 200 (e.g., between a signal line 260 and another signal line 260 (not shown)), or various combinations thereof. In various examples, charge leakage may affect the informational state of memory cell 105-a itself or the ability to generate or detect a signal (e.g., a read signal) resulting from accessing memory cell 105-a, either or both of which may be associated with a read operation that fails to determine the logical state written to memory cell 105-a.

In some examples of memory devices supporting the techniques described herein, the circuit 200 may include one or more leakage detection components 201 to detect the presence or level of charge leakage (e.g., charge transfer between components intended to be electrically isolated), such as one or both of the leakage detection component 201-a connected with the digit line 210 or the leakage detection component 201-b connected with the signal line 260. The leakage detection component 201 may be configured to detect charge leakage in the circuit 200, such as leakage or other charge transfer above a threshold or otherwise meeting a threshold (e.g., above a threshold that would indicate normal operation of the circuit 200, an amount of charge leakage indicating abnormal operation of one or more elements of the circuit 200). Although the leak detection component 201 is illustrated as a separate component, in some examples, the leak detection component 201 may be included in the signal generation component 280 or in the sense amplifier 290, and the leak detection component 201 may be connected with multiple access lines or in series with access lines.

In some examples, the leakage detection component 201 may be configured to detect charge leakage by identifying a voltage change (e.g., of an access line, memory cell 105) or comparing a voltage to a reference voltage or threshold (e.g., using a sense amplifier, a multi-level cell (MLC) latch, a comparator, or other component of the leakage detection component 201). For example, the leakage detection component 201-a may be configured to monitor the voltage of the digit line 210, or the leakage detection component 201-b may be configured to monitor the voltage of the signal line 260. In some examples, the leakage detection component 201 may be configured to detect charge flow (e.g., in situations or conditions where such charge flow or charge flow above a threshold would indicate leakage rather than charge transfer normally associated with an access operation). For example, the leakage detection component 201-a may be configured to detect a flow of charge along the digit line 210, or the leakage detection component 201-b may be configured to detect a flow of charge along the signal line 260, any of which may correspond to a flow of charge across the signal generation component 280. In some examples, detecting charge flow may be supported by monitoring a voltage across a shunt resistor configured to convey charge flow (e.g., when the leakage detection component 201 is connected in series with an access line or component).

In some examples, leakage detection component 201 may be configured to detect cell-specific charge leakage (e.g., charge leakage along path "a" or "B," which may be specific to memory cell 105-a) that may be distinguished from other charge leakage that may be common to a set of memory cells 105 sharing a digit line 210 (e.g., charge leakage along path "C"). In some examples, the leakage detection component 201 may not be configured to distinguish cell-specific charge leakage from other charge leakage more commonly associated with access lines (e.g., charge leakage associated with the digit line 210, charge leakage associated with the signal line 260, charge leakage common to one or more of the set of memory cells 105).

In some examples, leak detection component 201 may be configured to perform a leak detection operation during or otherwise based at least in part on an access operation (e.g., of memory cell 105-a), which may include performing a leak detection operation while memory cell 105-a is selected (e.g., while cell selection component 230 is activated, while word line 205 is activated). The leakage detection component 201 may thus communicate with the memory controller 170, the sensing component 150, the sense amplifier 290, or the wordline 205, which may enable the leakage detection component 201 to perform operations during particular portions of an access operation. In some examples, the leak detection component 201 may be configured to perform a leak detection operation during a diagnostic mode of the memory device 100 or otherwise based at least in part on the diagnostic mode of the memory device 100, which may or may not be included in or otherwise associated with an access operation.

In some examples, the leak detection component 201 may support providing information to support selectively performing direct write operations or complementary write operations, which may include providing an indication of whether a leak is detected to one or more of the memory controller 170, the sensing component 150, the sense amplifier 290, or other components. In various examples, the determination of whether to perform a direct write operation or a complementary write operation may be based on detection of cell-specific charge leakage (e.g., charge leakage along path "a" or path "B", charge leakage associated with memory cell 105-a, charge leakage associated with capacitor 220), charge leakage associated with a particular access line (e.g., charge leakage along path "C", charge leakage associated with digit line 210 or signal line 260), or other detected charge leakage, or a combination thereof.

In some examples, leak detection component 201 may provide information to support identifying memory cell 105-a associated with an indeterminate logic state or an access line (e.g., digit line 210, signal line 260) coupled with memory cell 105-a or otherwise indicating a condition that may indeterminate logic state. For example, the leak detection component may include providing an indication of whether a leak is detected (e.g., for a particular memory cell 105, for a particular access line, for a particular memory address) to one or more of the memory controller 170, the sensing component 150, the sense amplifier 290, or other components. Such information may be used, for example, to identify an information location (e.g., generated in a read operation) of a codeword having an indeterminate or unassigned information state, which may then be assigned one or more assumed or speculative information states to support various error handling operations in accordance with the techniques disclosed herein.

In some examples, the leakage detection component 201 may include a storage element (e.g., a temporary storage element, a latch, a capacitor, a storage element) that stores an indication of whether a leakage is detected (e.g., during an access operation). In some examples, the stored indication may be maintained or otherwise valid for the most recent access operation, and may be cleared or reset in response to performing another access. Memory controller 170 may receive or request an indication of whether a leak is detected, and subsequently, memory controller 170 or some other portion of memory device 100 may use this indication to support various examples of the techniques disclosed herein.

In some examples, memory controller 170 or some other portion of memory device 100 may store an indication of which type of write operation is performed, such as a bit flip indication (e.g., one or more memory cells 105, a row of memory cells 105, a page of memory cells 105, a group of memory cells 105 for a shared word line 205). The bit flip indication may be used in subsequent read operations to determine how to interpret the sensed logic state (e.g., directly to interpret the sensed logic state or as the complement of the sensed logic state). For example, depending on the state indicated by the bit flip, the output on I/O line 295 may be provided directly (e.g., indicating the logic state stored by memory cell 105-a) or the output on I/O line 295 may be inverted (e.g., indicating the complement of the logic state stored by memory cell 105-a).

FIGS. 3A and 3B are in accordance with the disclosure hereinVarious examples utilize hysteresis curves 300-a and 300-b to illustrate examples of nonlinear electrical properties of ferroelectric memory cells. Hysteresis curves 300-a and 300-b may illustrate examples of write and read processes, respectively, of a memory cell 105 employing the ferroelectric capacitor 220 described with reference to fig. 2. Hysteresis curves 300-a and 300-b depict the charge Q stored on ferroelectric capacitor 220 as a function of the voltage difference V between the terminals of ferroelectric capacitor 220_capChange (e.g. when dependent on the voltage difference V_capPermitting charge to flow into or out of the ferroelectric capacitor 220). For example, the voltage difference V_capMay represent a voltage difference (e.g., V) between a digit line side of the capacitor 220 and a plate line side of the capacitor 220_bottom–V_plate)。

Ferroelectric materials are characterized by an electric polarization in which the material can maintain a non-zero charge in the absence of an electric field. An example of a ferroelectric material includes barium titanate (BaTiO)₃) Lead titanate (PbTiO)₃) Lead zirconium titanate (PZT), and Strontium Bismuth Tantalate (SBT). The ferroelectric capacitor 220 described herein may include these or other ferroelectric materials. The electric polarization within the ferroelectric capacitor 220 creates a net charge at the surface of the ferroelectric material and attracts the opposite charge through the terminals of the ferroelectric capacitor 220. Thus, charge can be stored at the interface of the ferroelectric material and the capacitor terminals. Since the electrical polarization can be maintained for a relatively long time, even indefinitely, in the absence of an externally applied electric field, charge leakage can be significantly reduced compared to, for example, capacitors that do not have ferroelectric properties (such as those used in some DRAM arrays). Employing ferroelectric materials may reduce the need to perform refresh operations on some DRAM architectures, such that maintaining the logic state of a FeRAM architecture may be associated with lower power consumption than maintaining the logic state of a DRAM architecture.

The hysteresis curves 300-a and 300-b may be understood from the perspective of a single terminal of the ferroelectric capacitor 220. For example, if the ferroelectric material has a negative polarization, positive charge accumulates at the associated terminal of the ferroelectric capacitor 220. Likewise, if the ferroelectric material has a positive polarization, negative charge accumulates at the associated terminal of the ferroelectric capacitor 220. In addition, it should be understood that the hysteresis curves 300-a andthe voltage in 300-b represents the voltage difference across the capacitor (e.g., the potential between the terminals of ferroelectric capacitor 220) and is directional. For example, a positive voltage may be achieved by applying a positive voltage to the respective terminal (e.g., cell bottom 222) and maintaining the reference terminal (e.g., cell plate 221) at ground or virtual ground (or approximately zero volts (0V)). In some examples, a negative voltage may be applied by maintaining the respective terminals at ground and applying a positive voltage to the reference terminal (e.g., cell plate 221). In other words, a positive voltage may be applied to achieve a negative voltage difference V across the ferroelectric capacitor 220_capAnd thereby negatively polarize the terminal in question. Similarly, two positive voltages, two negative voltages, or any combination of positive and negative voltages may be applied to the appropriate capacitor terminals to generate the voltage difference V shown in the hysteresis curves 300-a and 300-b _cap。

As depicted in hysteresis curve 300-a, the ferroelectric material used in ferroelectric capacitor 220 may maintain either positive or negative polarization when there is no net voltage difference between the terminals of ferroelectric capacitor 220. For example, the hysteresis curve 300-a illustrates two possible polarization states: charge state 305-a and charge state 310-b, which charge state 305-a and charge state 310-b may represent a negative saturation polarization state and a positive saturation polarization state, respectively. The charge states 305-a and 310-a may be in a physical condition that illustrates a remanent polarization (Pr) value, which may refer to a polarization (or charge) that remains after an external bias (e.g., voltage) is removed. According to an example of hysteresis curve 300-a, charge state 305-a may represent a logic 1 when no voltage difference is applied across ferroelectric capacitor 220 and charge state 310-a may represent a logic 0 when no voltage difference is applied across ferroelectric capacitor 220. In some examples, the logic values of the respective charge states or polarization states may be inverted or interpreted in the opposite manner to accommodate other schemes of operating memory cell 105.

A

logic

0 or 1 can be written to the memory cell by controlling the electrical polarization of the ferroelectric material and thus controlling the charge on the capacitor terminals, by applying a net voltage difference across the ferroelectric capacitor 220. For example, voltage 315 may be a voltage equal to or greater than a positive saturation voltage, and applying voltage 315 across ferroelectric capacitor 220 may cause charge to accumulate until charge state 305-b is reached (e.g., a logic 1 is written). After voltage 315 is removed from ferroelectric capacitor 220 (e.g., a zero net voltage is applied across terminals of ferroelectric capacitor 220), at zero voltage across the capacitor, the charge state of ferroelectric capacitor 220 may follow shown path 320, between charge state 305-b and charge state 305-a. In other words, charge state 305-a may represent a logic 1 state at an equilibrium voltage across ferroelectric capacitor 220 that is already being saturated.

Similarly, voltage 325 may be a voltage equal to or less than a negative saturation voltage, and applying voltage 325 across ferroelectric capacitor 220 may cause charge to accumulate until charge state 310-b is reached (e.g., a logic 0 is written). After voltage 325 is removed from ferroelectric capacitor 220 (e.g., a zero net voltage is applied across terminals of ferroelectric capacitor 220), at zero voltage across the capacitor, the charge state of ferroelectric capacitor 220 may follow shown path 330, between charge state 310-b and charge state 310-a. In other words, charge state 310-a may represent a logic 0 state at an equilibrium voltage across ferroelectric capacitor 220 that has been negatively saturated. In some examples, voltage 315 and voltage 325, which represent saturation voltages, may have the same magnitude, but opposite polarities across ferroelectric capacitor 220.

To read or sense the state stored by ferroelectric capacitor 220, a voltage may also be applied across ferroelectric capacitor 220. The subsequent charge Q stored by the ferroelectric capacitor changes in response to the applied voltage and the degree of change may depend on the initial polarization state, the applied voltage, the inherent or other capacitance on the access line, and other factors. In other words, the charge state or access line voltage resulting from a read operation may depend on whether charge state 305-a or charge state 310-a was originally stored or some other charge state and other factors.

The hysteresis curve 300-b illustrates an example of an access operation that reads the stored charge states 305-a and 310-a. The read voltage 335 may be applied as a voltage difference, for example, via the digit line 210 and the plate line 215 described with reference to FIG. 2. Hysteresis curve 300-b may illustrate where reading is performedVoltage 335 is a positive voltage difference V_cap(e.g., wherein V_bottom–V_platePositive). The positive read voltage across ferroelectric capacitor 220 may be referred to as a "plate-low" read operation, where digit line 210 is initially placed at a high voltage and plate line 215 is initially at a low voltage (e.g., ground). Although the read voltage 335 is shown as a positive voltage across the ferroelectric capacitor 220, in an alternative access operation, the read voltage may be a negative voltage across the ferroelectric capacitor 220, which may be referred to as a "plate-high" read operation.

A read voltage 335 may be applied across the ferroelectric capacitor 220 while the memory cell 105 is selected (e.g., by activating the cell select component 230 via the word line 205 described with reference to fig. 2). After applying a read voltage 335 to ferroelectric capacitor 220, charge may flow into or out of ferroelectric capacitor 220 via associated digit line 210 and plate line 215, and in some examples, a different charge state or access line voltage may be formed depending on whether ferroelectric capacitor 220 is in charge state 305-a (e.g., a logic 1), charge state 310-a (e.g., a logic 0), or in some other charge state.

When a read operation is performed on ferroelectric capacitor 220 in charge state 305-a (e.g., a logic 1), additional positive charge may accumulate across ferroelectric capacitor 220 and the charge state may follow path 340 until the charge and voltage of charge state 305-c is reached. The amount of charge flowing through capacitor 220 may be related to the inherent capacitance or other capacitance of digit line 210 (e.g., inherent capacitance 240 described with reference to fig. 2) or the inherent capacitance or other capacitance of other access lines (e.g., signal line 260). In a "plate low" read configuration, read operations associated with charge states 305-a and 305-c, or more generally logic 1 states, may be associated with relatively small amounts of charge transfer (e.g., as compared to read operations associated with charge states 310-a and 310-c, or more generally logic 0 states).

As shown by the transition between charge state 305-a and charge state 305-c, the voltage changes due to a given charge change at capacitor 220Is relatively large and therefore the resulting voltage 350 across the ferroelectric capacitor 220 may be relatively large positive. Thus, after reading a logic 1 in a "plate low" read operation, equal to V at charge state 310-c _PLAnd V_cap(e.g., V)_bottom–V_plate) The digit line voltage of the sum of (1) may be a relatively high voltage. This read operation may not change the remnant polarization of ferroelectric capacitor 220 storing charge state 305-a, and thus ferroelectric capacitor 220 may return to charge state 305-a via path 340 when read voltage 335 is removed (e.g., by applying a zero net voltage across ferroelectric capacitor 220, by equalizing the voltage across ferroelectric capacitor 220) after the read operation is performed. Thus, performing a read operation on ferroelectric capacitor 220 having charge state 305-a with a positive read voltage may be considered a non-destructive read process.

When a read operation is performed on ferroelectric capacitor 220 in charge state 310-a (e.g., a logic 0), the stored charge may reverse polarity as a net positive charge accumulates across ferroelectric capacitor 220, and the charge state may follow path 360 until the charge and voltage of charge state 310-c is reached. The amount of charge flowing through ferroelectric capacitor 220 may again be related to the inherent capacitance or other capacitance of digit line 210 (e.g., inherent capacitance 240 described with reference to fig. 2). In a "plate-low" read configuration, read operations associated with charge states 310-a and 310-c, or more generally logic 0 states, may be associated with relatively large amounts of charge transfer (e.g., as compared to read operations associated with charge states 305-a and 305-c, or more generally logic 1 states).

As shown by the transitions between charge states 310-a and 310-c, in some cases the resulting voltage 355 may be a relatively small positive value because the voltage change is relatively small with a given charge change at the capacitor 220. Thus, after reading the logic in a "plate low" read operation, equal to V at charge state 310-c_PLAnd V_cap(e.g., V)_bottom–V_plate) The digit line voltage of the sum of (1) may be a relatively low voltage.

The transition from charge state 310-a to charge state 310-d may illustrate a sensing operation associated with a partial reduction or partial reversal of the polarization or charge of ferroelectric capacitor 220 of memory cell 105 (e.g., a reduction in the magnitude of charge Q from charge state 310-a to charge state 310-d). In other words, depending on the properties of the ferroelectric material, ferroelectric capacitor 220 may not return to charge state 310-a when read voltage 335 is removed (e.g., by applying a zero net voltage across ferroelectric capacitor 220, by equalizing the voltage across ferroelectric capacitor 220) after performing the read operation. More specifically, when a zero net voltage is applied across ferroelectric capacitor 220 after a read operation of charge state 310-a with read voltage 335, the charge state may follow path 365 from charge state 310-c to charge state 310-d, which illustrates a net decrease in polarization magnitude (e.g., a positively polarized charge state that is less than the initial charge state 310-a, illustrated by the charge difference between charge state 310-a and charge state 310-d). Thus, performing a read operation on ferroelectric capacitor 220 having charge state 310-a with a positive read voltage may be described as a destructive read process. However, in some sensing schemes, the reduced remnant polarization may still be read to the same stored logic state as the saturated remnant polarization state (e.g., supporting the detection of a logic 0 from both charge states 310-a and 310-d), thereby providing a degree of non-volatility to memory cell 105 with respect to read operations.

The location of the charge states 305-c and 310-c after the initial read operation may depend on a number of factors, including the particular sensing scheme and circuitry. In some cases, the final charge may depend on the net capacitance of digit line 210 coupled with memory cell 105, which may include inherent capacitance 240, integrator capacitor, and others. For example, if ferroelectric capacitor 220 is electrically coupled with plate line 215 at 0V and a read voltage 335 is applied to digit line 210, the voltage of digit line 210 may drop when memory cell 105 is selected because charge flows from the net capacitance of digit line 210 to ferroelectric capacitor 220. Thus, in some examples, the voltage measured at the sensing component 150 may not be equal to the read voltage 335 or the generated voltage 350 or 355, but may depend on the voltage of the digit line 210 after a charge sharing cycle.

The location of charge states 305-c and 310-c on hysteresis curve 300-b after the initial read operation may depend on the net capacitance of digitline 210 and may be determined by load line analysis. In other words, charge states 305-c and 310-c may be defined relative to the net capacitance of digit line 210 or other access lines (e.g., signal line 260). Thus, the voltage of ferroelectric capacitor 220 after the initial read operation (e.g., voltage 350 when reading ferroelectric capacitor 220 storing charge state 305-a, voltage 355 when reading ferroelectric capacitor 220 storing charge state 310-a) may be different and may depend on the initial state of ferroelectric capacitor 220. In some examples, the amount of change in the polarization of ferroelectric capacitor 220 of memory cell 105 due to the sensing operation may be selected according to a particular sensing scheme. In some examples, a sensing operation that causes a large change in the polarization of the ferroelectric capacitor 220 of the memory cell 105 may be associated with relatively greater robustness (e.g., a wider sensing margin) in detecting the logic state of the memory cell 105.

The initial state (e.g., charge state, logic state) of ferroelectric capacitor 220 may be determined by comparing the voltage of digit line 210 (or signal line 260, where applicable) resulting from a read operation to a reference voltage (e.g., via reference line 265 or via a common access line as described with reference to fig. 2). In some examples, the digit line voltage may be the sum of the plate line voltage and the final voltage across ferroelectric capacitor 220 (e.g., voltage 350 when reading ferroelectric capacitor 220 having stored charge state 305-a or voltage 355 when reading ferroelectric capacitor 220 having stored charge state 310-a). In some examples, the digit line voltage may be the difference between the read voltage 335 and the final voltage across the capacitor 220 (e.g., when reading the ferroelectric capacitor 220 with the stored charge state 305-a (read voltage 335-voltage 350); when reading the ferroelectric capacitor 220 with the stored charge state 310-a (read voltage 335-voltage 355)).

In some examples, a read operation of memory cell 105 may be associated with a fixed voltage of digit line 210, where the charge state of ferroelectric capacitor 220 may be the same after the initial read operation, regardless of the initial charge state of ferroelectric capacitor 220. For example, in a read operation where digit line 210 is held at a fixed read voltage 335, ferroelectric capacitor 220 can continue to charge state 370 for both the case where the ferroelectric capacitor initially stores charge state 305-a and the case where the ferroelectric capacitor initially stores charge state 310-a. Thus, rather than using the voltage difference of digit lines 210 to detect an initial charge state or logic state, in some examples, the initial charge state or logic state of ferroelectric capacitor 220 may be determined based at least in part on the charge difference associated with the read operation. For example, as illustrated by hysteresis curve 300-b, a logic 1 may be detected based on a difference in charge Q between charge state 305-a and charge state 370 (e.g., a relatively small amount of charge transfer), and a logic 0 may be detected based on a difference in charge Q between charge state 310-a and charge state 370 (e.g., a relatively large amount of charge transfer).

In some examples, a charge transfer sense amplifier, a cascode amplifier (e.g., transistors configured in a cascode arrangement), or other signal generation circuitry between digit line 210 and signal line 260 may support such detection, wherein the voltage of signal line 260 may be based at least in part on an amount of charge transfer of capacitor 220 after initiating a read operation (e.g., wherein the described charge transfer may correspond to an amount of charge passing through the charge transfer sense amplifier, cascode amplifier, or other signal generation circuitry). In such examples, although digit line 210 remains at a fixed voltage level, the voltage of signal line 260 may be compared to a reference voltage (e.g., at sense amplifier 290) to determine the logic state initially stored by ferroelectric capacitor 220.

In some examples where the digit line 210 is held at a fixed read voltage 335, the capacitor 220 may be positively saturated after a read operation, whether the capacitor 220 is initially in a charge state 305-a (e.g., a logic 1) or a charge state 310-a (e.g., a logic 0). Thus, after such a read operation, the capacitor 220 may be at least temporarily charged according to a logic 1 state, regardless of the initial or expected logic state of the capacitor 220. Accordingly, a rewrite operation may be required, at least when the capacitor 220 is expected to store a logic 0 state, where such a rewrite operation may include applying the write voltage 325 to store a logic 0 state, as described with reference to the hysteresis curve 300-a. Such rewrite operations may be configured or otherwise described as selective rewrite operations, as the rewrite voltage may not need to be applied when the capacitor 220 is expected to store a logic 1 state. In some examples, this access scheme may be referred to as a "2 Pr" scheme, where the charge difference used to distinguish a logic 0 from a logic 1 may be equal to twice the residual polarization of the memory cell 105 (e.g., the charge difference between charge state 305-a (positive saturated charge state) and charge state 310-a (negative saturated charge state)).

In some sensing schemes, a reference voltage may be generated such that it is between the possible voltages that may result from reading different logic states (e.g., possible voltages for digit line 210, possible voltages for signal line 260). For example, the reference voltage may be selected to be lower than the generated voltage of the dummy line 210 or the signal line 260 when reading a logic 1 and higher than the generated voltage of the dummy line 210 or the signal line 260 when reading a logic 0. In other examples, the comparison may be made at a portion of the sensing component 150 or the sense amplifier 290 that is different from the portion coupling the digit line 210 or the signal line 260, and thus the reference voltage may be selected to be lower than a generated voltage at the comparing portion of the sensing component 150 or the sense amplifier 290 when reading a logic 1, and higher than a generated voltage at the comparing portion of the sensing component 150 or the sense amplifier 290 when reading a logic 0. During the comparison by the sensing component 150 or the sense amplifier 290, the voltage based sensing may be determined to be above or below the reference voltage, and thus the logic state (e.g., logic 0, logic 1) stored by the memory cell 105 may be determined.

During a sensing operation, the signals generated from reading the various memory cells 105 may vary with manufacturing or operating differences between the various memory cells 105. For example, the capacitors 220 of the various memory cells 105 may have different capacitance levels or saturation polarization levels, such that a logic 1 may be associated with different charge levels between one memory cell and the next, and a logic 0 may be associated with different charge levels between one memory cell and the next. Furthermore, the inherent capacitance or other capacitance (e.g., inherent capacitance 240 described with reference to fig. 2) may differ from one digit line 210 to another digit line 210 in a memory device, may differ from one signal line 260 to another signal line 260, and may also differ within a digit line 210 from the perspective of one memory cell 105 and the next memory cell 105 located on the same digit line 210. Thus, for these and other reasons, read logic 1 may be associated with different voltage levels of digit line 210 or signal line 260 between one memory cell 105 and another memory cell 105 (e.g., generated voltage 350 may differ between reading one memory cell 105 and reading the next memory cell 105), and read logic 0 may be associated with different voltage levels between one memory cell 105 and another memory cell 105 (e.g., generated voltage 355 may differ between reading one memory cell 105 and reading the next memory cell 105).

In some examples, a reference voltage may be provided that is between the statistical average of the voltages associated with reading a logic 1 and the statistical average of the voltages associated with reading a logic 0, but that may be relatively closer to the voltage generated by reading one of the logic states for any given memory cell 105. The minimum difference between the voltage resulting from reading a particular logic state (e.g., as a statistic of reading the plurality of memory cells 105 of the memory device) and the associated level of the reference voltage may be referred to as a "minimum read voltage difference" or "read margin," and having a low minimum read voltage difference or read margin may be associated with difficulty or sensitivity in reliably sensing the logic state of the memory cells 105 in a given memory device 100.

In some memory devices 100, charge leakage (e.g., charge leakage above a threshold) may negatively impact the memory device 100's ability to determine the logic state stored by the memory cell 105. For example, with a read operation utilizing a fixed read voltage 335 on digit line 210 in accordance with hysteresis curve 300-b, charge leakage may be superimposed on the charge difference between charge state 310-a and charge state 370 when reading a memory cell 105 storing a logic 0, and charge leakage may be superimposed on the charge difference between charge state 305-a and charge state 370 when reading a memory cell 105 storing a logic 1. In some examples, the superimposed charge leakage may reduce the margin of distinguishing logic 0 from logic 1 when reading memory cell 105. For example, charge leakage of memory cell 105, digit line 210, or signal line 260 may increase the likelihood that the voltage of signal line 260 is on the same side of the reference voltage when reading both logic 1 and logic 0. In other words, this charge leakage may increase the likelihood that a memory cell 105 written with a logic 1 is incorrectly read as storing a logic 0.

In some examples, memory device 100 may identify charge leakage associated with one or more memory cells 105 or access lines (e.g., digit lines 210, signal lines 260), and may determine whether to intentionally invert the logic state stored by memory cells 105 so that it is more likely that the logic state will be properly read when charge leakage is present. For example, the memory device 100 may determine a logic state stored by the memory cell 105 during an access operation (e.g., a read portion of the access operation, a write portion of the access operation), and also detect whether the memory cell 105 or an associated access line is associated with charge leakage (e.g., during a leakage detection portion of the access operation). In some cases, memory device 100 may determine to write the complement of the detected logic state (e.g., a different logic state, an inverted logic state, an opposite logic state) to a given memory cell 105 or a group of memory cells 105 that includes the given memory cell 105 based in part on detecting charge leakage.

In some examples, determining the complement of the write logic state may be based on the detected logic state being associated with a first amount of charge transfer (e.g., for a logic 1, the difference in charge between charge states 305-c and 305-a or the difference in charge between charge states 370 and 305-a, depending on the type of access operation or associated circuitry) and the complement of the logic state being associated with a second amount of charge transfer greater than the first amount of charge transfer (e.g., for a logic 0, the difference in charge between charge states 310-c and 310-a or the difference in charge between charge states 370 and 310-a, depending on the type of access operation or associated circuitry). For example, according to the hysteresis curves 300-a and 300-b, based on identifying that the memory cell 105 stores a logic 1 (e.g., according to a write operation or a read operation) and detecting charge leakage associated with the memory cell 105 (e.g., charge leakage of the digit line 210 or the signal line 260 connected to the memory cell 105, charge leakage detected during a write operation or a read operation), the associated memory device may determine to write the memory cell 105 instead with a logic 0 (e.g., the complement of the identified logic 1).

Along with writing complementary logic states (e.g., logic 0) to memory cell 105, memory device 100 may also store an indication, such as a bit flip indication, that the complement of the detected logic state was written to at least memory cell 105. In various examples, such a bit-flip indication can correspond to a set of one or more memory cells 105 including the memory cell 105 for which the associated charge leakage is detected (e.g., an indication of a single cell, an indication corresponding to a plurality of memory cells 105, an indication corresponding to a row of memory cells 105, an indication corresponding to a page of memory cells 105, an indication corresponding to a set of memory cells 105 sharing a word line 205). For example, the memory device 100 may store such an indication (e.g., at the memory controller 170, at a storage component of the memory device 100 accessible to the memory controller 170) to track whether a memory cell 105 or a group of memory cells 105 has been programmed with a direct logic state or a complementary logic state (e.g., a flipped state). This indication may be used in subsequent read operations to properly interpret the changed logic state of the set of one or more memory cells 105 when reading information of the memory device 100 (e.g., determining whether to directly interpret the logic state stored by the memory cell 105 or to invert or otherwise change the interpretation of the complementary logic state stored by the memory cell 105 based on the bit flip indication). Thus, detected charge leakage may be accounted for by changing the logic state stored by memory cell 105 (e.g., during a rewrite operation) and tracking this change in a subsequent read operation, which may avoid incorrect interpretation of the information stored by memory cell 105 that may otherwise result from charge leakage.

Fig. 4 illustrates an example of a circuit 400 that supports memory management and erasure decoding in accordance with examples disclosed herein. Circuit 400 includes a sense amplifier 290-a for sensing the logic state of memory cell 105-b. Charge or other signals may be communicated between sense amplifier 290-a and memory cell 105-b via digit line 210-a and signal line 260-a, which digit line 210-a and signal line 260-a may be referred to in combination as a single access line for memory cell 105-b. Signals for the access line may pass through voltage V on digit line 210-a_DLAnd the voltage V on the signal line 260-a_sigIllustrated as shown.

The example circuit 400 may include an amplifier 405 coupled between the digit line 210-a and the signal line 260-a, the amplifier 405 being enabled by a voltage source 410-l. In various instances, amplifier 405 may be an instance of signal generation component 280, or otherwise included as part of signal generation component 280. The circuit 400 may also include: word line 205-a, which is used to select or deselect memory cell 105-b (e.g., by logic signal WL); and a reference line 265-a for providing a reference signal (e.g., V)_refAs shown) for comparison with the signal of signal line 260-a in detecting the logic state of memory cell 105-b. The circuit 400 may also include a plate line 215-a for accessing a cell plate of a capacitor of the memory cell 105-b. Thus, memory cell 105-b may represent memory cell 105 coupled between a first access line (e.g., digit line 210-a and signal line 260-a) and a second access line (e.g., plate line 215-a).

The circuit 400 may include various voltage sources 410, which various voltage sources 410 may be coupled with various voltage supplies or common ground or virtual ground points of the memory device including the example circuit 400.

Voltage source 410-a may represent a common ground point (e.g., a bottom plate ground, a neutral point), which may have a voltage V₀Are associated, with other voltages being defined in terms of the common ground. Voltage source 410-a may be coupled to digit line 210-a via the inherent capacitance 240-a of digit line 210-a.

Having a voltage V₁Voltage source 410-b of (a) may represent a plate line voltage source and may be coupled with memory cell 105-b via plate line 215-a of memory cell 105-b. In some examples, the voltage source 410-B may be controlled for access operations (e.g., read or write operations, including those described with reference to the hysteresis curves 300-a and 300-B of fig. 3A and 3B). In other words, in some examples, voltage source 410-b may be a variable voltage source, where voltage V is₁There may be multiple levels.

Having a voltage V₂May represent a digit line voltage source and may be coupled to digit line 210-a via switching element 420-a, which may be passed through logic signal SW by switching element 420-a ₁Activate or deactivate activation.

Having a voltage V₃Can represent a signal line precharge voltage source and can be coupled to the signal line 260-a via a switching element 420-c, the switching element 420-c being accessible by a logic signal SW₃Activate or deactivate activation.

Having a voltage V₄Can represent a reference signal voltage source and can be coupled to reference line 265-a via switching element 420-f, which can be enabled by logic signal SW₆Activate or deactivate activation.

Having a voltage V₁₁May represent an amplifier or a cascode voltage source and may be coupled with amplifier 405. In some examples, amplifier 405 may be a transistor and voltage source 410-l may be coupled with a gate of the transistor. Amplifier 405 may be coupled with signal line 260-a at a first terminal and coupled with digit line 210-a at a second terminal. The amplifier 405 may provide conversion of charge, voltage, or other signals between the digit line 210-a and the signal line 260-a.

Amplifier 405 may permit charge (e.g., charge, current) to flow from signal line 260-a to digit line 210-a when fed or enabled by voltage source 410-l when the voltage of digit line 210-a is reduced (e.g., when memory cell 105-b is selected). In some examples, the described flow of charge across amplifier 405 may correspond to a charge transfer associated with a logic state of memory cell 105-b or a charge transfer otherwise associated with accessing memory cell 105-b. For example, when memory cell 105-b includes a ferroelectric capacitor (as illustrated by hysteresis curves 300-a and 300-b) and amplifier 405 is configured to maintain the voltage of digit line 210-a at read voltage 335, the flow of charge across amplifier 405 (e.g., during a read operation) may correspond to or otherwise be based at least in part on the charge difference Q between charge states 370 and 305-a when memory cell 105-b stores a logic 1, and the flow of charge across amplifier 405 may correspond to or otherwise be based at least in part on the charge difference Q between charge states 370 and 310-a when memory cell 105-b stores a logic 0.

The circuit 400 may also include a first integrator capacitor 430-a and a second integrator capacitor 430-b, which may each be coupled with a respective variable voltage source 450. For example, a first integrator capacitor 430-a may be coupled with the signal line 260-a at a first terminal 431-a and coupled with the variable voltage source 450-a at a second terminal 432-a. Second integrator capacitor 430-b may be coupled with reference line 265-a at a first terminal 431-b and coupled with variable voltage source 450-b at a second terminal 432-b.

In some examples, the flow of charge across amplifier 405 may be accompanied by a change in voltage of signal line 260-a. For example, when signal line 260-a is not otherwise coupled with a voltage source, a relatively small flow of charge to digit line 210-a may be associated with a relatively small voltage change of signal line 260-a, while a relatively large flow of charge to digit line 210-a may be associated with a relatively large voltage change of signal line 260-a. The voltage change of signal line 260-a associated with the access operation may be based on the net capacitance of signal line 260-a (e.g., including integrator capacitor 430-a), where after selecting memory cell 105-b, signal line 260-a may undergo a relatively small voltage change or a relatively large voltage change depending on the flow of charge across amplifier 405.

In various examples, amplifier 405 may be referred to as a "voltage regulator" or "bias component" with respect to how amplifier 405 regulates charge flow in response to voltage or charge transfer of digit line 210-a. In some examples, the amplifier 405 or the combination of the amplifier 405 and the integrator capacitor 430-a may be referred to as a charge transfer sense amplifier. Amplifier 405 may be isolated from digit line 210-a by switching element 420-b, which switching element 420-b may be enabled by logic signal SW₂Activate or deactivate activation. In some examples, switching component 420-b may be part of column component 135, a multiplexer, or some other circuitry configured to selectively couple digit line 210-a with amplifier 405 or signal line 260-a.

In the example of circuit 400, variable voltage source 450-a may include a voltage having a voltage V₅410-f and having a voltage V₆Can be passed by the switching element 420-d via the logic signal SW 410-g₄Selected to be connected to the first integrator capacitor 430-a. In some examples, voltage sources 410-f may be coupled with a common ground (not shown). In other examples, voltage source 410-f may be coupled with a voltage supply that provides a positive voltage or a negative voltage. Voltage source 410-g may be coupled with a voltage supply having a voltage higher than the voltage of voltage source 410-f, which may provide a voltage boosting function according to a voltage difference between voltage sources 410-g and 410-f, which is equal to V ₆–V₅Or simply V when voltage source 410-f is grounded₆。

In the example of circuit 400, variable voltage source 450-b may include a voltage having a voltage V₇Voltage source 410-h and having a voltage V₈By the switching element 420-e via the logic signal SW 410-i₅Selected to be connected to the second integrator capacitor 430-b. In some examples, voltage sources 410-h may be coupled with a common ground (not shown). In other examples, the voltage sources 410-h may be coupled with voltage supplies that provide positive or negative voltages. Electric powerVoltage source 410-i may be coupled with a voltage supply having a voltage higher than the voltage of voltage source 410-h, which may provide a voltage boosting function according to a voltage difference between voltage sources 410-i and 410-h, which is equal to V₈–V₇Or simply V when the voltage source 410-h is grounded₈。

In various examples, one or more components of circuit 400 may be included in or otherwise considered part of signal generation circuitry (e.g., signal generation component 280 described with reference to fig. 2). For example, any one or more of voltage source 410-c, switching component 420-a, switching component 420-b, amplifier 405, voltage source 410-l, voltage source 410-d, switching component 420-c, variable voltage source 450-a, or integrator capacitor 430-a may be included in signal generation component 280 or otherwise considered to be within the illustrative boundaries of such signal generation component 280.

Although circuit 400 is shown to include two variable voltage sources 450, some configurations according to the present disclosure may include a single common variable voltage source 450. For example, when the switching component 420 of the common variable voltage source 450 is deactivated, the first voltage source 410 of the common variable voltage source 450 may be coupled with both the second terminal 432-a of the first integrator capacitor 430-a and the second terminal 432-b of the second integrator capacitor 430-b; and the second voltage source 410 of the common variable voltage source 450 may be coupled with both the second terminal 432-a of the first integrator capacitor 430-a and the second terminal 432-b of the second integrator capacitor 430-b when the switching component 420 of the common variable voltage source 450 is activated. In some examples using a common variable voltage source 450, the source voltage provided to the second terminal 432-a of the first integrator capacitor 430-a may be different than the source voltage provided to the second terminal 432-b of the second integrator capacitor 430-b due to differences in circuitry (e.g., conductor length, width, resistance, capacitance) between the variable voltage source 450 and each of the integrator capacitors 430.

Further, although variable voltage source 450 is illustrated as including two voltage sources 410 and switching components 420, variable voltage source 450 supporting operations herein may include other configurations, such as a voltage buffer that provides a variable voltage to one or both of the second terminal 432-a of the first integrator capacitor 430-a and the second terminal 432-b of the second integrator capacitor 430-b. In other examples, variable voltage source 450 may be replaced with a fixed voltage source or other type of voltage source. Additionally or alternatively, the access operation may omit the voltage boosting operation described.

To support the various operations described herein, the sense amplifier 290-a may be isolated from portions of the circuit 400. For example, sense amplifier 290-a may be coupled with signal line 260-a via switching component 420-g (e.g., an isolation component), which switching component 420-g may pass a logic signal ISO₁Activate or deactivate activation. Additionally or alternatively, sense amplifier 290-a may be coupled with reference line 265-a via switching component 420-h (e.g., an isolation component), which switching component 420-h may pass a logic signal ISO₂Activate or deactivate activation. In addition, the sense amplifier 290-a may have a voltage V₉Voltage source 410-j and having a voltage V₁₀Voltage source 410-k, voltage source 410-j and voltage source 410-k may be examples of sense amplifier voltage sources 250-b and 250-c, respectively, as described with reference to fig. 2.

Each of the logic signals illustrated in the circuit 400 may be provided by a memory controller (not shown), such as the memory controller 170 described with reference to fig. 1. In some examples, the particular logic signal may be provided by other components. For example, the logic signal WL may be provided by a row decoder (not shown) that may be included in the row component 125 described with reference to fig. 1.

In various examples, voltage source 410 may be coupled with different configurations of voltage supplies or a common ground or virtual ground for a memory device including example circuit 400. For example, in some examples, voltage sources 410-a, 410-f, 410-h, or 410-j, or any combination thereof, may be coupled with the same ground or virtual ground, and may provide substantially the same reference voltage for various operations accessing memory cell 105-b. In some examples, several voltage sources 410 may be coupled with the same voltage supply of the memory device. For example, in some examples, voltage source 410-c, 410-d, 410-g, 410-i, or 410-k, or any combination thereof, may be coupled with a voltage supply having a particular voltage (e.g., a voltage of 1.5V, which may be referred to as "VARY"). In such examples, signal line 260-a may be boosted to a voltage substantially equal to 2 VARY or approximately 3.0V before selecting memory cell 105-b to be sensed via word line 205-a. In other examples, voltage sources 410-g and 410-i may be coupled with a different voltage supply (e.g., a voltage of 1.2V, which may be referred to as a "PDS") than the other voltage supplies, which may thus be associated with a voltage boost of 1.2V.

In some examples, voltage sources 410-j and 410-k may be selected according to particular input/output parameters. For example, according to a particular input/output component convention (e.g., some DRAM conventions), the voltage sources 410-j and 410-k may be substantially at 0V and 1V, respectively. Although the voltage sources 410 may be coupled to a common voltage supply or a ground point, the voltage of each of the voltage sources 410 coupled to a common voltage supply or a common ground point may be different due to various differences in circuitry (e.g., conductor length, width, resistance, capacitance) between the respective voltage source 410 and the associated common voltage supply or common ground point.

Voltage source 410-e may provide a reference voltage for sensing the logic state of memory cell 105-b. For example, voltage V₄May be configured as an average between the signal line voltages associated with sensing logic 1 and logic 0. In some examples, the voltage V₄May be provided as a voltage stepped down from a voltage supply of the memory device, which may be the same voltage supply coupled with the other voltage source 410. For example, V may be provided by connecting voltage sources 410-e and 410-d to the same voltage supply ₄But with an intermediate electrical load (e.g., a resistive load or a capacitance) between the voltage supply and the voltage source 410-e.

Circuit 400 may also include a leakage detection component 201-c, which leakage detection component 201-c may be configured to detect charge leakage associated with one or more of memory cell 105-b, digit line 210-a, amplifier 405, or signal line 260-a. For example, the leak detection component 201-c may be configured to monitor the voltage (e.g., V) of the signal line 260-a_sig) And charge leakage is detected by identifying a change in voltage of signal line 260-a or by comparing the voltage to a reference voltage or threshold (e.g., using sense amplifiers, multi-level cell (MLC) latches, comparators). For example, the leakage detection component 201-c may be configured to identify a voltage drop of the signal line 260-a during a condition in which the voltage of the signal line 260-a should be or otherwise expected to be stable or above a threshold (e.g., a signal on the digit line 210-a or the signal line 260-a has been generated or otherwise should be stable). In some examples, identifying this voltage drop may indicate that charge is flowing across amplifier 405 (e.g., enabled by voltage source 410-l) or flowing out of integrator capacitor 430-a, which may be in response to the voltage of digit line 210-a dropping due to charge leakage along path "a" or "B". Although illustrated as separate components, in some examples, the leakage detection component 201-c may be included in the sense amplifier 290-a.

In some examples, charge leakage can negatively impact the ability of the sense amplifier 290 to detect the logic state stored by the memory cell 105-a. Thus, in accordance with the described techniques, a memory device including circuit 400 can be configured to determine whether to store a direct logic state to memory cell 105-b or a complementary logic state to memory cell 105-a based on detection of charge leakage in circuit 400 (e.g., by leakage detecting component 201-c). In some examples, circuit 400 may be configured to evaluate whether memory cell 105-b is associated with an indeterminate information state, where such evaluation may be used to improve various error repair techniques.

FIG. 5 shows a timing diagram 500 illustrating the operation of an example access procedure supporting memory management and erasure decoding of a memory device in accordance with an example disclosed herein. An exemplary access procedure is described with reference to components of exemplary circuit 400, exemplary circuit 400 is described with reference to fig. 4.

In the example of timing diagram 500, voltage sources 410-a, 410-f, 410-h, and 410-j are considered to be ground, and thusAt zero voltage (e.g. V)₀＝0V，V₅＝0V，V₇0V and V₉0V). However, in other examples, the voltage sources 410-a, 410-f, and 410-h may be at non-zero voltages, and thus adjustments may be made to the voltages of the timing diagram 500 accordingly. In some examples, prior to initiating operation of timing diagram 500, digit line 210-a and plate line 215-a may be controlled to the same voltage, which may minimize charge leakage across memory cell 105-b. For example, according to timing diagram 500, digit line 210-a has an initial voltage of 0V, which may be the same as the initial voltage of plate line 215-a. In other examples, the digit line 210-a and the plate line 215-a may have some other initial voltage different from the ground voltage.

At 501, an access procedure may include activating a switching component 420-c (e.g., by activating a logic signal SW)₃). Activating switching component 420-c may connect voltage source 410-d with signal line 260-a, and thus the voltage of signal line 260-a may rise to voltage level V due to the flow of charge into integrator capacitor 430-a₃. Thus, activating switching component 420-c may initiate a precharge operation on integrator capacitor 430-a. For example, at 501, the switching component 420-d may be deactivated such that the voltage source 410-f (e.g., ground voltage at 0V or virtual ground voltage) is coupled with the second terminal 432-a of the integrator capacitor 430-a and the voltage source 410-d is coupled with the first terminal 431-a of the integrator capacitor 430-a. Thus, integrator capacitor 430-a may be charged according to the voltage difference between voltage source 410-d and voltage source 410-f.

At 502, the access procedure may include activating the switching component 420-f (e.g., by activating the logic signal SW)₆). Activating switching component 420-f may connect voltage source 410-e with reference line 265-a, and thus the voltage of reference line 265-a may rise to voltage level V due to the flow of charge into integrator capacitor 430-b₄. Thus, activating switching component 420-f may initiate a precharge operation on integrator capacitor 430-b. For example, at 502, the switching component 420-e may be deactivated such that the voltage source 410-h (e.g., at ground voltage of 0V or virtual ground voltage) and the second terminal 4 of the integrator capacitor 430-b 32-b and the voltage source 410-e is coupled with a first terminal 431-b of the integrator capacitor 430-b. Thus, integrator capacitor 430-b may be charged according to the voltage difference between voltage sources 410-e and 410-h.

At 503, the access procedure may include activating the switching component 420-b (e.g., by activating the logic signal SW)₂). Activating the switching component 420-b may initiate a precharge operation on the digit line 210-a. For example, the activation switching component 420-b may connect the signal line 260-a with the digit line 210-a, which digit line 210-a may be coupled with a voltage source 410-a (e.g., a ground voltage or a virtual ground voltage) through the inherent capacitance 240-a. When fed by voltage source 410-d, charge may flow through amplifier 405 and accumulate on digit line 210-a, causing the voltage on digit line 210-a to rise. The voltage of digit line 210-a may rise until the threshold voltage of amplifier 405 (e.g., threshold voltage V) is no longer exceeded_th,amp) Until now. Thus, after activation of switching component 420-b, the voltage of digit line 210-a may rise to voltage level V due to charge flowing from the signal line (e.g., fed by voltage source 410-d)₁₁-V_th,ampAnd the digit line 210-a including the inherent capacitance 240-a may be dependent upon the voltage level V ₁₁-V_th,ampThe voltage difference with the voltage source 410-a (e.g., 0V) is charged. In some examples, voltage level V₁₁May be selected such that digit line 210-a is precharged to substantially the same level as signal line 260-a. For example, the voltage level V may be adjusted₁₁Is arranged at V₃+V_th,ampMay be provided by a voltage supply having a voltage level greater than that of voltage source 410-d. Thus, in some examples, at 503, digit line 210-a may rise to equal voltage level V in response to activating switching component 420-b₃The voltage level of (c). In some examples, after operation at 503, the voltage between the digit line 210-a and the plate line 215-a may correspond to the read voltage 335 described with reference to FIG. 3B.

Additionally or alternatively, in some examples, digit line 210-a may be precharged by voltage source 410-c. For example, prior to activating switching component 420-b, timing diagram 500 may include activating switching component 420-a (e.g., by activating logic signal SW)₁). Activating the switching component 420-a may initiate an alternative precharge operation for the digit line 210-a that is not shown in the timing diagram 500. When fed by voltage source 410-c, charge may accumulate on digit line 210-a, thereby causing a voltage on digit line 210-a to vary from voltage level V ₂And (6) matching. In some examples, voltage level V₂May be substantially equal to voltage level V₃Such that digit line 210-a and signal line 260-a are precharged to the same voltage prior to activation of switching component 420-b. In some examples, precharging digit line 210-a with voltage source 410-c may reduce power consumption or reduce the precharge time associated with accessing memory cell 105-b. After precharging the digit line 210-a by the voltage source 410-c, the access procedure may include activating the switching component 420-b (e.g., by activating the logic signal SW)₂) To connect signal line 260-a to digit line 210-a.

At 504, the accessor may include deactivating the toggle component 420-c (e.g., by deactivating the logic signal SW)₃). Deactivating the switching component 420-c may isolate the voltage source 410-d from the signal line 260-a and the voltage of the signal line 260-a may remain at the voltage level V₃. After deactivating the switching component 420-c, the signal line 260-a, and thus the first terminal 431-a of the integrator capacitor 430-a, may float and the signal line 260-a may maintain a charge level according to the capacitance of the signal line 260-a, including the capacitance of the integrator capacitor 430-a.

At 505, the access procedure may include deactivating the switching component 420-f (e.g., by deactivating the logic signal SW) ₆). Deactivating switching component 420-f may isolate voltage source 410-i from reference line 265-a, and the voltage of reference line 265-a may remain at voltage level V₄. After deactivating the switching component 420-f, the reference line 265-a, and thus the first terminal 431-b of the integrator capacitor 430-b, may float, and the reference line 265-a may maintain a charge level according to the capacitance of the signal line 260-a, including the capacitance of the integrator capacitor 430-b.

At 506, the access procedure may include activating the switching component 420-d (e.g., by activating the logic signal SW)₄). Activating cutterThe switching component 420-d may cause a transition from the coupling of the voltage source 410-f with the second terminal 432-a of the integrator capacitor 430-a to the coupling of the voltage source 410-g with the second terminal 432-a of the integrator capacitor 430-a. By connecting the second terminal 432-a of the integrator capacitor 430-a to a voltage source at a higher voltage, the charge stored by the integrator capacitor 430-a may be boosted to the higher voltage, and thus the voltage of the signal line 260-a coupled with the first terminal 431-a of the integrator capacitor 430-a may rise to a voltage level (V)₃+V₆). Thus, activating switching component 420-d may initiate a boost operation of integrator capacitor 430-a.

At 507, the access procedure may include activating the switching component 420-e (e.g., by activating the logic signal SW) ₅). Activating the switching component 420-e may cause a transition from the coupling of the voltage source 410-h with the second terminal 432-b of the integrator capacitor 430-b to the coupling of the voltage source 410-i with the second terminal 432-b of the integrator capacitor 430-b. By connecting the second terminal 432-b of the integrator capacitor 430-b to a voltage source at a higher voltage, the charge stored by the integrator capacitor 430-b may be boosted to the higher voltage, and thus the voltage of the reference line 265-a coupled with the first terminal 431-b of the integrator capacitor 430-b may rise to a voltage level (V)₄+V₈). Thus, activating switching component 420-e may initiate a boost operation of integrator capacitor 430-b.

At 508, the access procedure may include selecting memory cell 105-b (e.g., by activating a word line via logic signal WL). Selecting memory cell 105-b may cause the capacitor of memory cell 105-b to couple with digit line 210-a. Accordingly, charge may be shared between memory cell 105-b, digit line 210-a, and signal line 260-a, which may depend on the logic state (e.g., charge state, polarization state) stored in memory cell 105-b.

For example, when memory cell 105-B stores a logic 1, the capacitor of memory cell 105-B may store a positive charge (e.g., charge state 305-a described with reference to FIGS. 3A and 3B). Thus, when memory cell 105-b storing a logic 1 is selected, a relatively small amount of charge may flow from digit line 210-a to memory cell 105-b. With charge Flowing from digit line 210-a to memory cell 105-b, the voltage of digit line 210-a may drop, which may allow the threshold voltage of amplifier 405 to be exceeded. When the threshold voltage of amplifier 405 is exceeded, charge may flow across amplifier 405 from signal line 260-a (e.g., from integrator capacitor 430-a) to digit line 210-a, and a relatively small amount of charge flows across amplifier 405 from voltage source 410-l to digit line 210-a, depending on the characteristics of amplifier 405. Thus, charge may flow to the digit line 210-a until the voltage of the digit line 210-a returns to a voltage level equal to V₁₁-V_th,ampUntil now. When memory cell 105-b storing a logic 1 is selected, signal line 260-a may experience a relatively small voltage drop, such as voltage V, after selecting memory cell 105-b because a relatively small amount of charge flows into memory cell 105-b_sig,1Illustrated is shown.

Alternatively, when memory cell 105-B stores a logic 0, the capacitor of memory cell 105-B may store a negative charge (e.g., charge state 310-a as described with reference to FIGS. 3A and 3B). Thus, when memory cell 105-b storing a logic 0 is selected, a relatively large amount of charge may flow from digit line 210-a to memory cell 105-b. Thus, the digit line returns to voltage level V as charge flows through amplifier 405 ₁₁-V_th,ampThe signal line 260-a may experience a relatively large voltage drop (e.g., voltage V)_sig,0Illustrated) so that the threshold voltage V of amplifier 405 is no longer exceeded_th,amp. In some examples, selecting memory cell 105-b to store a logic 0 may result in a partial loss of polarization of the capacitor of memory cell 105-b. In an example employing a 2Pr sense operation, selecting memory cell 105-b to store a logic 0 may cause the saturation polarization of the capacitor of memory cell 105-b to be reversed, such that an amount of charge associated with twice the saturation polarization flows into memory cell 105-b. In either case, selecting memory cell 105-b to store a logic 0 according to the present example may involve a subsequent refresh or rewrite operation.

At 509, the access procedure may include deactivating the switching component 420-d (e.g., by deactivating the logic signal SW)₄). Deactivating switching component 420-d may be actuatedTransitioning from the coupling of voltage source 410-g with the second terminal 432-a of integrator capacitor 430-a to the coupling of voltage source 410-f with the second terminal 432-a of integrator capacitor 430-a. By connecting the second terminal 432-a of the integrator capacitor 430-a to a voltage source at a lower voltage, the charge stored by the integrator capacitor 430-b may be shifted to the lower voltage, and thus the voltage of the signal line 260-a coupled with the first terminal 431-a of the integrator capacitor 430-a may drop by a voltage level (V) ₆-V₅Or exactly V in the case where voltage sources 410-f are coupled to a common ground₆). Thus, deactivating the switching component 420-d may initiate an offset operation of the integrator capacitor 430-a, which may reduce the voltage of the signal line 260-a to a level that may be read by the sense amplifier 290-a. For example, after the offset operation of 509, the sense amplifier 290-a senses V_sig,1May be about 1.5V and sense amplifier 290-a senses V_sig,0May be about 1.2V.

At 510, the access procedure may include deactivating the switching component 420-e (e.g., by deactivating the logic signal SW)₅). Deactivating the switching component 420-e may cause a transition from the voltage source 410-i being coupled with the second terminal 432-b of the integrator capacitor 430-b to the voltage source 410-h being coupled with the second terminal 432-b of the integrator capacitor 430-b. By connecting the second terminal 432-b of the integrator capacitor 430-b to a voltage source at a lower voltage, the charge stored by the integrator capacitor 430-b may be shifted to the lower voltage, and thus the voltage of the reference line 265-a coupled with the first terminal 431-b of the integrator capacitor 430-b may be lowered by a voltage level (V)₈-V₇Or exactly V in the case of voltage sources 410-h coupled to a common ground point ₈). Thus, deactivating switching component 420-e may initiate an offset operation of integrator capacitor 430-b, which may reduce the voltage of reference line 265-a to a level that may be read by sense amplifier 290-a. For example, after the offset operation of 510, the sense amplifier 290-a senses V_refMay be about 1.35V.

At 511, the access procedure may include deactivating switching component 420-g (e.g., by deactivating logic signal ISO)₁) The sense amplifier 290-a is isolated from the signal line 260-a. Isolating sense amplifier 290-a from signal line 260-a may allow sense amplifier 290-a to store a voltage or charge associated with the signal line voltage (e.g., V at first terminal 131-b of sense amplifier 290-a) prior to determining the logic state stored in memory cell 105-b_A＝V_sig)。

At 512, the access procedure may include deactivating the switching component 420-h (e.g., by deactivating the logic signal ISO)₂) The sense amplifier 290-a is isolated from the reference line 265-a. Isolating sense amplifier 290-a from reference line 265-a may allow sense amplifier 290-a to store a voltage or charge associated with a reference line voltage (e.g., V at second terminal 132-b of sense amplifier 290-a) prior to determining a logic state stored in memory cell 105-b _B＝V_ref)。

At 513, the access procedure may include detecting a difference in the voltages stored at the first and second terminals 131-b and 132-b of the sense amplifier 290-a, which may be referred to as "latching" the result of accessing the memory cell 105-b or detecting the logic state stored by the memory cell 105-b. For example, if the signal stored at the first terminal 131-b is greater than the signal stored at the second terminal 132-b (e.g., V)_A>V_B) Then the sense amplifier 290-a may output a voltage (e.g., V) equal to the high voltage source of the sense component₁₀Associated with voltage source 410-k, corresponding to a logic 1). If the signal stored at the first terminal 131-b is less than the signal (e.g., V) stored at the second terminal 132-b_A<V_B) Then the sense amplifier 290-a may output a voltage (e.g., V) equal to the low voltage source of the sense component₉Associated with voltage source 410-j, corresponding to a logic 0). The detected logic state may be output to the input/output components 160, memory controller 170, or other components of the memory device 100 including the circuit 400 for subsequent operation.

In some examples, charge may leak from one portion of circuit 400 to another during operation of timing diagram 500. In one example, charge leakage may follow A path "a" from digit line 210-a to plate line 215-a, which may illustrate charge leakage through memory cell 105-b (e.g., across or otherwise around a dielectric portion of capacitor 220 of memory cell 105-b). In another example, leakage may follow a path "B" from digit line 210-a to voltage source 410-a, which may illustrate charge leakage (e.g., bottom plate leakage) from digit line 210-a to a grounded voltage source or reference voltage or component. Other examples not illustrated may include other leakage paths permitting any other charge transfer between digit line 210-a and another component of circuit 400 or between signal line 260-a and another component of circuit 400. In some examples, charge leakage in circuit 400 may be driven by a voltage difference between digit line 210 and plate line 215, and may be relatively high when cell select component 230-a is activated (e.g., cell-specific charge leakage associated with memory cell 105-b). Thus, after 508, when wordline 205-a is activated and V_DLAnd V_PLWhen the difference between is relatively large (e.g., when memory cell 105-b is under full bias), charge leakage may be relatively high.

In some examples, such charge leakage may alter one or more of the signals illustrated in timing diagram 500. For example, such charge leakage may be associated with additional charge transfer across the amplifier 405 while the digit line 210-a is maintained at a particular voltage level, which may be accompanied by a voltage V of the signal line 260-a that is lower than the voltage shown in the timing diagram 500_sig. When memory cell 105-b stores a logic 1, for example, such leakage may thus be accompanied by V_sig,1And V_refA reduced difference therebetween, which may reduce the read margin associated with reading a logic 1, or such leakage may cause V to_sig,1Down to below V_refThis may result in memory cell 105-b written with a logic 1 being incorrectly read as a logic 0. Thus, to increase the likelihood of correctly reading memory cell 105-b, in some examples, an access operation may include determining, based at least in part on charge leakage detected in circuit 400, whether to perform a direct write operation (e.g., direct re-write)A write operation) or a complementary write operation (e.g., a complementary overwrite operation).

At 514, the access operation may include detecting charge leakage in the circuit 400. For example, the leak detection component 201-c may be configured to monitor the voltage of the signal line 260-a, which may include detecting V _sigIs decreased (e.g., V)_sigChange of (V)_sigTime derivative or voltage) or comparison V_sigAnd a threshold (e.g., a charge detection reference voltage, which may be different from V)_refConfigurable voltage). In one example, the leakage detection component 201-c may be configured to detect V after isolating the signal line 260-a from the sense amplifier 290-a_sigChange (e.g., V after 511)_sigAs illustrated), which may include V of signal line 260-a at 513_sigV to sense Amplifier 290-a_AA comparison between them. However, this is only one example of how charge leakage may be detected in circuit 400. For example, according to a different set of operations, signal line 260-a may be biased to a voltage after signal line 260-a is isolated from sense amplifier 290-a (e.g., after 511), where the voltage may be the same whether memory cell 105-b stores a logic 0 or a logic 1. In another example, signal line 260-a may be re-coupled with sense amplifier 290-a (e.g., after detecting a logic state at 513, by passing through logic signal ISO₁Activating switching component 420-g), which may be accompanied by biasing signal line 260-a to a voltage that may be the same or different depending on the logic state initially stored by memory cell 105-b. In various examples, the voltage of signal line 260-c may drop from this set voltage due to charge leakage, which may be detected by leakage detection component 201-c at 514, and corresponding charge transfer across amplifier 405. In some examples, such leakage detection may be performed at the integrator capacitor 430-a, which may be associated with detecting a voltage or voltage change across the integrator capacitor 430-a or with detecting a charge state or charge state change of the integrator capacitor 430-a. In some examples, leak detection component 201-c or some other component may store an indication of whether a leak was detected at 514 (e.g., such as Temporary indications, cell-specific indications, access line-specific indications associated with access operations of timing diagram 500).

At 515, the access operation may include determining whether to perform a direct overwrite operation or a complementary overwrite operation, which may be based at least in part on whether charge leakage is detected in the circuit 400. For example, if charge leakage is detected at 514, the access operation may determine to write the complement of the logic state detected in memory cell 105-b (e.g., at 513).

In some examples, determining whether to write a complementary logic state may be further based on the particular logic state detected in memory cell 105-b. For example, when charge leakage is detected at 514, it may be preferable for memory cell 105-b to store a logic state associated with a relatively large charge transfer. Taking hysteresis curves 300-a and 300-b as examples, a logic 0 may be associated with a relatively large charge transfer (e.g., a charge difference between charge states 310-a and 370) and a logic 1 may be associated with a relatively small charge transfer (e.g., a charge difference between charge states 305-a and 370). Thus, according to this example, if charge leakage is detected at 514 (e.g., based on accessing the memory cell 105-b), it may be preferable for the memory cell 105-b to store a logic 0. Thus, at 515, when it is detected that memory cell 105-b has stored a logic 1 (e.g., at 513), the complement of the stored logic state may be determined to be written (e.g., memory cell 105-b is rewritten with a logic 0), and when it is detected that memory cell 105-b has stored a logic 0 (e.g., at 513), the stored logic state may be determined to be written directly (e.g., memory cell 105-b is rewritten with a logic 0). In some examples, such a determination may include identifying that a selective rewrite operation needs to be performed because memory cell 105-B may be saturating (e.g., at least temporarily charged according to a logic 1, such as charge state 370 described with reference to fig. 3B) as a result of the operations of 508 through 515. In some examples, memory device 100 may store an indication of whether it is determined at 514 to write a complementary logic state to memory cell 105-b. However, in some examples, such an indication may not be determined, stored, or validated until after the corresponding write operation is performed or acknowledged (e.g., in a subsequent operation).

In some examples, determining whether to perform a direct rewrite operation or a complementary rewrite operation may be based on a group of memory cells 105, such as a row of memory cells 105, a page of memory cells 105, or some other group of memory cells 105 that share a word line 205-a with memory cell 105-b. For example, when determining whether to perform a direct rewrite operation or a complementary rewrite operation corresponds to a set of memory cells 105, the operations of 501-514 may be repeated (e.g., simultaneously, during overlapping time intervals) for repeating components (e.g., parallel sense amplifier 290, parallel signal line 260, parallel amplifier 405, parallel digit line 210) of circuit 400 (not shown) associated with respective memory cells 105 in the set. In such examples, determining whether to perform a direct rewrite operation on the set of memory cells 105 or a complementary rewrite operation on the set of memory cells 105 may be based at least in part on minimizing the number of leaky memory cells 105 or corresponding access lines (e.g., digit lines 210, signal lines 260) that will store logic states associated with relatively low charge transfers.

For example, continuing with the example illustrated by hysteresis curves 300-a and 300-b, it may be preferable to minimize the number of memory cells 105 in the set that are associated with detected charge leakage above a threshold that will store a logic 1. Thus, at 515, the memory device 100 (e.g., memory controller 170) may digitally combine the results of the charge leakage detection for a set of memory cells 105 with a data pattern to be used for write back to the set of memory cells 105 in order to assign a logic 0 to as many leaking memory cells 105 or corresponding access lines as possible. In such examples, memory cells 105 or corresponding access lines not associated with detected charge leakage may be ignored in digital combination, as they may not be negatively affected by whether one logic state or another is stored.

Because the determination of whether to perform a direct overwrite operation or a complementary overwrite operation may be based on a group of memory cells 105, the particular determination of the logic state of the overwrite operation of memory cell 105-b may not necessarily be based solely on whether charge leakage is detected for memory cell 105-b at 514. For example, when it is determined that other memory cells 105 in a set including memory cell 105-b benefit from performing a complementary rewrite operation, memory device 100 may determine to write the complement of the logical state detected for memory cell 105-b even if it is detected that there is no charge leakage from memory cell 105-b or an associated access line. In other words, depending on the determination made for the set of memory cells 105, although no charge leakage is detected for a particular memory cell 105 in the set, the logic state written to the particular memory cell 105 may still be the complement of the detected logic state of the particular memory cell 105.

In some examples, the described techniques may be combined with other error correction techniques, such as Error Correction Codes (ECC), single unit ECC (e.g., ECC1), or Single Error Correction (SEC). In some examples, this combination may support up to 3 bits of correction for a particular row or page access scheme. In other words, when the described techniques are used for memory management based on detected charge leakage, the result may be that using a 1-bit ECC engine is equivalent to 3-bit ECC.

In one example of combining ECC with the described techniques of flipping data based on charge leakage detection, a page access operation may be associated with a single memory cell 105 or corresponding access line (e.g., digit line 210, signal line 260) in the page that has a charge leakage detected above a threshold. In such examples, when memory cell 105 is initially associated with a logic state associated with a relatively small charge transfer, memory device 100 may determine to flip the data of the page (e.g., invert logic 1 of memory cell 105 to logic 0 of memory cell 105, and correspondingly invert other logic states of other memory cells 105 in the page). Alternatively, when memory cell 105 is initially associated with a logical state associated with a relatively small charge transfer, memory device 100 may determine not to flip the page of data, but rather rely on ECC to correct possible errors when reading memory cell 105. When memory cell 105 is initially associated with a logic state associated with a relatively large charge transfer, memory device 100 may determine not to flip the page of data because charge leakage may not negatively impact reading memory cell 105. Thus, in each of these cases, the memory device 100 can properly read the memory cells 105 in the page despite the charge leakage of a single memory cell 105 or corresponding access line being above the threshold.

In another example combining ECC with the described techniques of flipping data based on charge leakage detection, a page access operation may be associated with two memory cells 105 or corresponding access lines (e.g., digit lines 210, signal lines 260) in the page that have charge leakage detected above a threshold. In such examples, when two memory cells 105 are initially associated with a logic state associated with a relatively small charge transfer, the memory device 100 may determine to flip the data of the page (e.g., invert the logic 1 of the memory cell 105 to the logic 0 of the memory cell 105 and correspondingly invert the other logic states of the other memory cells 105 in the page). Thus, any of the memory cells 105 associated with charge leakage will not store a logic state associated with a relatively small charge transfer. When the two memory cells 105 are initially associated with different logic states (e.g., one associated with a relatively large charge transfer and the other associated with a relatively small charge transfer), the memory device 100 can determine to flip the page of data or not flip the page of data because, whether flipped or not, one of the read memory cells 105 may not be negatively affected by charge leakage (e.g., due to storing the logic state associated with the relatively large charge transfer) and the read of the other of the memory cells 105 can be corrected by ECC to handle possible errors due to charge leakage when the memory cells 105 are read. When two memory cells 105 are initially associated with a logic state associated with a relatively large charge transfer, the memory device 100 may determine not to flip the page of data because charge leakage may not negatively impact reading the two memory cells 105. Thus, in each of these cases, the memory device 100 can properly read the memory cells 105 in a page despite the charge leakage of two memory cells 105 or corresponding access lines being above a threshold.

In another example combining ECC with the described techniques of flipping data based on charge leakage detection, a page access operation may be associated with three memory cells 105 or corresponding access lines (e.g., digit lines 210, signal lines 260) in the page that have charge leakage detected above a threshold. In such examples, when the three memory cells 105 are initially associated with a logic state associated with a relatively small charge transfer, the memory device 100 may determine to flip the data of the page (e.g., invert the logic 1 of the memory cell 105 to the logic 0 of the memory cell 105 and correspondingly invert the other logic states of the other memory cells 105 in the page). Thus, none of the memory cells 105 associated with charge leakage will store a logic state associated with a relatively small charge transfer.

When the three memory cells 105 are initially associated with different logic states (e.g., one associated with a relatively large charge transfer and the other two associated with a relatively small charge transfer), the memory device 100 can determine whether to flip the page of data or not to flip the page of data. For example, when two of the memory cells 105 store a logical state associated with a relatively large charge transfer, the memory device may determine not to flip the page of data, and when two of the memory cells 105 store a logical state associated with a relatively small charge transfer, the memory device may determine to flip the page of data. In either case, a subsequent read of the page may rely on ECC to handle possible errors due to charge leakage when reading one of the memory cells 105 (e.g., one of the memory cells 105 that subsequently stores a logic state associated with a relatively small charge transfer). When the three memory cells 105 are initially associated with a logic state associated with a relatively large charge transfer, the memory device 100 may determine not to flip the page of data because charge leakage may not negatively impact reading the three memory cells 105. Thus, in each of these cases, the memory device 100 can properly read the memory cells 105 in the page despite the charge leakage of three memory cells 105 or corresponding access lines being above the threshold.

At 516, the access operation may include performing a write operation (e.g., a write portion of the access operation, an overwrite portion of the access operation). For example, returning to the example of the hysteresis curve 300-a, at 514, when it is determined that the memory cell 105-b stores a logic 1, the access operation may include applying the voltage 315 (e.g., a plate low write voltage, where V is_DL,w1>V_PL,w1) Or, when it is determined that memory cell 105-b stores a logic 0, the access operation may include applying voltage 325 (e.g., a plate high write voltage, where V is_PL,w0>V_DL,w0). In some examples, applying voltage 315 at 516 may be omitted because memory cell 105-b may already store a positive saturation charge state (e.g., a logic 1, due to one or more of the operations of 508-515). In such examples, plate line 215-a may still be placed at a high voltage (e.g., a voltage associated with writing a logic 0), but digit line 210-a may also be placed at a high voltage (e.g., where V is_DL＝V_PL) So that the voltage of the memory cell 105 is equalized and thus maintains a positive saturation charge state (e.g., logic 1).

In some examples, performing the write operation at 516 may be based at least in part on determining the complement of the identified logical state stored by the write memory cell 105-b (e.g., at 513). In such examples, the write operation at 516 may include an inversion of an aspect of the memory cell write as compared to when it is determined not to write the complement of the identified logic state. For example, when determining to write the complement of the identified logic state, the write operation at 516 may include swapping a voltage or connected voltage source (e.g., swapping a voltage or voltage source between plate line 215-a and digit line 210-a), grounding digit line 210-a that otherwise remains at a relatively high voltage, or performing some other logical inversion of another component that manages the write operation or the rewrite operation of 516.

Although illustrated as separate operations occurring at different times, some of the operationsMay occur simultaneously or in a different order. In some examples, it may be advantageous to initiate various operations simultaneously to shorten the amount of time involved in sensing the logic state of memory cell 105-b. For example, initiating precharging at 501 and 502 may occur in reverse order or simultaneously (e.g., when logic signal SW is asserted)₃And SW₆When driven as a common logic signal). Further, connecting digit line 210-a with signal line 260-a at 503 may occur before 501 or 502, or all three operations may occur simultaneously. Boosting the signal line 260-a at 506 and the reference line 265-a at 507 may also occur in reverse order or simultaneously (e.g., when using a common variable voltage source 450 or when boosting the logic signal SW₄And SW₅When driven as a common logic signal). Similarly, offsetting signal line 260-a at 509 and offsetting reference line 265-a at 510 may also occur in reverse order or simultaneously. In some examples, isolating sense amplifier 290-a from signal line 260-a at 511 and isolating sense amplifier 290-a from reference line 265-a at 512 may occur in reverse order or simultaneously (e.g., when logic signal ISO is to be asserted) ₁And ISO₂When driven as a common logic signal).

In some examples, the boosting and offset of reference line 265-a may be eliminated altogether, and thus the operations at 507 and 510 may be omitted. Thus, in some examples of the described techniques, the circuit 400 may omit the second integrator capacitor 430-b and the second variable voltage source 450-b and may still support self boosting for signal generation when accessing the memory cell 105-b. Additionally or alternatively, in some examples, boosting and shifting of signal line 260-a may be eliminated altogether, and thus operations at 506 and 509 may be omitted. Thus, in some examples of the described techniques, the circuit 400 may omit the first integrator capacitor 430-a and the first variable voltage source 450-a.

The order of operations shown in the timing diagram 500 is for illustration purposes, and various other orders and combinations of steps may be performed to support the described techniques. Further, the operational timing of the timing diagram 500 is also for purposes of illustration and is not intended to indicate a particular relative duration between one operation and another. Various operations may occur in relatively shorter or relatively longer durations than illustrated in various examples in accordance with the disclosure.

The transitions of the logic signals of the timing diagram 500 illustrate transitions from one state to another, and generally reflect transitions between an enabled or activated state (e.g., state "0") and a disabled or deactivated state (e.g., state "1") associated with a particular numbered operation. In various examples, a state may be associated with a particular voltage of a logic signal (e.g., a logic input voltage applied to a gate of a transistor used as a switch), and a change in voltage from one state to another may not be instantaneous. More specifically, in some examples, a voltage associated with a logic signal may follow a curve from one logic state to another logic state over time. Thus, the transitions shown in timing diagram 500 are not necessarily indicative of instantaneous transitions. Furthermore, the initial state of the logic signals associated with the transitions at the numbering operation may have been reached during various times prior to the numbering operation, yet still support the described transitions and associated operations.

Although the example of timing diagram 500 illustrates the described techniques of how leak detection and logical inversion may be applied in a read operation, the described techniques may also be combined with a write operation. For example, a leak detection operation (e.g., the leak detection operation described herein) may be performed prior to writing a logic state to a memory cell 105 or group of memory cells 105 (e.g., during a leak detection portion of a write operation, during an operation for determining which type of write operation to perform). In some examples, a write operation may be modified or performed accordingly depending on a determination of whether a direct write operation or a complementary write operation is performed on a memory cell 105 or a group of memory cells 105 (e.g., based on whether charge leakage is detected prior to writing a logic state to a memory cell, and whether the logic state is associated with a relatively large or small amount of charge transfer).

In another example, a leak detection operation (e.g., the leak detection operation described herein) may be performed after writing a logic state to a memory cell 105 or group of memory cells 105 (e.g., during a leak detection portion of a write operation, during a write verify or confirm portion of a write operation), and the write operation may be modified or performed accordingly depending on whether writing the logic state to the memory cell 105 or group of memory cells 105 was successful. For example, after performing a direct write operation on a page of memory cells 105, if charge leakage is detected in the page of memory cells 105 and the charge leakage is associated with writing a logic state associated with a relatively small amount of charge transfer to the leaky memory cells 105 or a corresponding access line, the write operation may be modified to include performing a complementary write operation on the page of memory cells 105 (e.g., in a rewrite portion of the write operation).

Fig. 6 shows a flow diagram illustrating a method 600 of supporting memory management for charge leakage, in accordance with an example disclosed herein. The operations of the method 600 may be implemented by the memory device 100 described herein or components thereof. In some examples, memory device 100 can include a set of memory cells 105 (e.g., a plurality of memory cells 105, an array of memory cells 105), and each of memory cells 105 can include a respective storage element (e.g., a respective capacitive storage element). The operations of method 600 may be performed by various components or circuitry coupled with a set of memory cells (e.g., coupled with a row of memory cells 105, a page of memory cells 105), including the examples described with reference to fig. 1-5. In some examples, the operations of method 600 may illustrate an access operation (e.g., a read operation, a write operation, an overwrite operation, a refresh operation) of a group of memory cells 105, or some portion thereof.

At 605, the method can include determining a respective logic state of each of the set of memory cells 105. In some examples, determining the respective logic state may be based at least in part on coupling the storage element of each of the set of memory cells 105 with a respective access line of a set of access lines (e.g., digit line 210, signal line 260), or some other operation that includes determining the respective logic state that has been stored by the memory cell 105 (e.g., in a read operation, in a rewrite operation, in a refresh operation). In some examples, this coupling may be based on activating a common select line (e.g., common word line 205). In some examples, determining the respective logic state may be based at least in part on some other determination of the logic state to be stored by memory cell 105 (e.g., in a subsequent write to the memory cell, in a subsequent write operation, in an operation that does not include accessing memory cell 105). For example, the logic state of each of the memory cells 105 may be provided from the memory controller 170 as part of a write operation (e.g., writing or overwriting information to the memory cells 105).

At 610, the method may include determining whether a threshold amount of charge leakage is detected on one or more of a set of access lines (e.g., digit line 210, signal line 260). In some examples, each of memory cells 105 may be coupled with a respective access line of a set of access lines. In some examples, the determination of whether the threshold amount of charge leakage is detected may be performed after coupling memory cell 105 with a respective access line of a set of access lines. In some examples, charge leakage may have been detected in some other prior operation. In some examples, detection of charge leakage may be otherwise triggered by initiating an access operation (e.g., a read operation, a write operation, a rewrite operation, a refresh operation).

In some examples, determining the respective logic state of each of a set of memory cells at 605 may include latching a signal of the respective signal line 260 associated with the respective memory cell 105; and determining whether a threshold charge leakage amount is detected at 610 may be based on comparing the voltage of the respective signal line 260 to the threshold voltage after latching. In some examples, determining whether a threshold amount of charge leakage is detected may be based on detecting (e.g., directly or indirectly) charge flow across signal generating components 280 (e.g., transistors, amplifiers 405) electrically connected with respective access lines of the set of access lines.

At 615, the method can include selecting a direct write operation or a complementary write operation for the set of memory cells 105. In some examples, selecting whether a direct write operation or a complementary write operation may be based on whether a threshold amount of charge leakage is detected on one or more of the set of access lines. In some examples, the method 600 may be associated with a first logic state corresponding to a first amount of charge transfer and a second logic state corresponding to a second amount of charge transfer, the second amount of charge transfer being lower than the first amount of charge transfer. In such examples, selecting whether a direct write operation or a complementary write operation may be based on the number of the set of access lines associated with detecting the threshold amount of charge leakage and coupled with the memory cells storing the first logic state and the number of the set of access lines associated with detecting the threshold amount of charge leakage and coupled with the memory cells storing the second logic state. In some examples, the selection at 615 may be based at least in part on whether the described techniques are combined with another error correction scheme (e.g., ECC or ECC 1). In some examples, method 600 may further include storing an indication of whether the selection of the direct overwrite operation or the complementary overwrite operation. The method may proceed to 625 when a direct write operation is selected for execution and may proceed to 630 when a complementary write operation is selected for execution.

At 620, the method may include performing a direct write operation. For example, performing a direct write operation may include writing the respective logic state determined at 605 to each of the set of memory cells 105. In some examples, method 600 may further include storing an indication that the direct write operation was performed.

At 625, the method may include performing a complementary write operation. For example, performing complementary write operations may include writing to each of the set of memory cells 105 the complement of the respective logic state determined at 605. In some examples, method 600 may further include storing an indication that the complementary write operation was performed.

According to an example of method 600, a set of memory cells 105 may be written with a direct write operation or a complementary write operation, where a selection between the direct write operation and the complementary write operation may be made based at least in part on whether a threshold amount of charge leakage is detected. By performing operations, such as the operations of method 600, memory device 100 is more likely to properly read information from the set of memory cells 105. For example, the operations of method 600 may be performed in a manner that minimizes the number of memory cells 105 or associated access lines storing a logic state corresponding to a relatively small charge transfer, as such a logic state may be more susceptible to being misread or read with a lower read margin than a logic state associated with a relatively higher charge transfer.

FIG. 7 illustrates a graph 700 that includes distributions of read characteristics associated with different information states that can support erasure decoding for a memory device, in accordance with an example disclosed herein. Graph 700 may illustrate various read characteristics (e.g., read signals) when accessing a group of representative memory cells 105 of memory device 100 with respect to a standard deviation σ or some other probabilistic metric. For example, the illustrated read characteristics may refer to a read voltage, a read current, a detected resistance, a threshold voltage, or other types of read signals generated based on accessing a memory cell 105 (e.g., a capacitive memory cell, a ferroelectric memory cell, a material memory cell) written with a respective information state. For purposes of illustration, the σ -axis may be a non-linear axis such that the normal distribution of the read characteristic may be illustrated in the graph 700 as a linear distribution. In some examples, the distribution of the graph 700 may be referred to as a gaussian distribution.

Distribution 710 may illustrate a first distribution of read characteristics when storing a first information state (e.g., a first logic state, a first charge state, a first material state, a logic 0). In some examples, distribution 710 may illustrate the distribution of voltage at signal line 260 when reading a memory cell 105 (e.g., capacitor 220) written with a logic 0. Distribution 710 may be associated with a lower boundary or edge (e.g., edge 711), which may be referred to as "E1," and an upper boundary or edge (e.g., edge 712), which may be referred to as "E2. Distribution 710 may illustrate various interpretations of a statistical distribution, such as a span of six standard deviations (e.g., 6 σ), a span of twelve standard deviations (e.g., twelve σ), or a span between a minimum level and a maximum level of a read characteristic of a group of representative memory cells 105 when written with a logic 0.

Distribution 720 may illustrate a second distribution of read characteristics when a second information state (e.g., a second logic state, a second charge state, a second material state, a logic 1) is stored. In some examples, distribution 720 may illustrate the distribution of the voltage at signal line 260 when reading a memory cell 105 (e.g., capacitor 220) written with a logic 1. Distribution 720 may be associated with a lower boundary or edge (e.g., edge 721), which may be referred to as "E3," and an upper boundary or edge (e.g., edge 722), which may be referred to as "E4. Distribution 720 may illustrate various interpretations of a statistical distribution, such as a span of six standard deviations (e.g., six σ), a span of twelve standard deviations (e.g., twelve σ), or a span between the minimum and maximum of the read characteristics of a group of representative memory cells 105 when written with a logical 1.

In some examples, memory device 100 may compare the read characteristics to a threshold to evaluate whether memory cell 105 stores one information state or another information state. For example, when the illustrated read characteristic is a voltage of the signal line 260, the memory device 100 may include a reference component 285, the reference component 285 biasing the reference line 265 to distinguish between a logic 0 and a logic 1 with a reference voltage (e.g., a voltage boundary) between the distribution 710 and the distribution 720 (e.g., between the edge 712 and the edge 721). When the voltage based on accessing the signal line 260 of the memory cell 105 (e.g., the voltage of the first node 291) is lower than the reference voltage (e.g., the voltage of the second node 292), the memory device 100 may determine that the memory cell 105 stores a logic 0, and when the voltage based on accessing the signal line 260 of the memory cell 105 is higher than the reference voltage, the memory device 100 may determine that the memory cell 105 stores a logic 1. The read margin in this scenario may include an E2 margin associated with the difference between the reference voltage and the margin 712 and an E3 margin associated with the difference between the reference voltage and the margin 721.

However, in some cases, the read characteristics may not appear to be according to distributions 710 and 720 when accessing memory cell 105. For example, when there is charge leakage, the voltage of the signal line 260 based on accessing the memory cell 105 may be lower than expected. In some cases, this leakage may cause the read voltage of memory cell 105 written with a logic 1 to drop below the reference voltage, such that memory cell 105 is incorrectly determined to be written with a logic 0 (e.g., illustrating a reduction or elimination of the margin of E3). Thus, according to these and other examples, a leakage condition may be associated with an indeterminate or non-determinate logic state or other reduction or elimination of read margin. In some examples, a leakage detection component 201 (e.g., the leakage detection component described with reference to fig. 2) may be used in a circuit to identify memory cells 105 or access lines (e.g., signal lines 260, digit lines 210) that may be associated with a logic state (e.g., an increased likelihood that a read operation will detect a logic 0) that may be indeterminate or non-determinate.

In another example of a technique that may support identifying a condition associated with a deleted or otherwise indeterminate or non-determinate information state, the memory device 100 may include multiple thresholds of read characteristics to be applied during an access operation. For example, the graph 700 illustrates an information state map 740, the information state map 740 including two read thresholds that distinguish read characteristic conditions of three information states. First read threshold 730-a (e.g., T) _read,0) May be associated with a logic 0 and a second read threshold 730-b (e.g., T)_read,1) May be associated with a logical 1. In the example where the read characteristic refers to a read voltage, T_read,0May be a reference voltage associated with a logic 0 (e.g., first information state, determined information state), and T_read,1May be a reference voltage associated with a logic 1 (e.g., first information state, determined information state). In various examples, a memory device 100 including multiple reference components 285 may support multiple reference voltages, including multiple reference lines 265 (e.g., multiple second nodes 292 at the sense amplifier 290) or applying different voltages to the reference lines 265 during different time intervals. In other embodiments, the first and second light sources may be,T_read,0and T_read,1May refer to a respective reference read current, a respective reference charge transfer, a respective reference resistance, a respective threshold voltage, or other read characteristic threshold (e.g., of a material memory element).

According to information state map 740, a read operation may identify or indicate a logic 0 of memory cell 105 (e.g., as a determined logic state) when a read characteristic associated with accessing memory cell 105 is below first read threshold 730-a (or equal to or below first read threshold 730-a). When the read characteristic associated with accessing the memory cell 105 is above the second read threshold 730-b (or equal to or above the second read threshold 730-b), the read operation may identify or indicate a logic 1 of the memory cell 105 (e.g., as a determined logic state). However, when the read characteristic associated with accessing memory cell 105 is between first read threshold 730-a and second read threshold 730-b (or equal to or between first read threshold 730-a and second read threshold 730-b), the read operation may identify or indicate logic X of memory cell 105 (e.g., as an indeterminate logic state, as a null logic state, as a third information state). In other words, the region between the first read threshold 730-a and the second read threshold 730-b may illustrate a non-affirmative range, which may support an identification or indication that is different from a determined logical state, or may refer to a condition associated with an identification or indication that no information state is present (e.g., a null information state, an unassigned information state).

In some examples, memory device 100 may use information state map 740 to improve aspects of error handling at the memory device. For example, when memory cell 105 is identified as being associated with a non-affirmative range of read characteristics (e.g., a logical X or other null information state or unassigned information state), the memory device may employ techniques that assume one or more information states in an associated codeword when performing error detection and error correction operations. Such techniques may be advantageous over other techniques, such as error handling techniques that do not identify locations of memory cells 105 that may include errors or have a high likelihood of errors or corresponding information locations of associated codewords that may include errors or have a high likelihood of errors.

Although some examples of logic states that are deleted or otherwise indeterminate may be related to charge leakage, the described techniques may be applied additionally or alternatively in other contexts. For example, some memory cells 105 may experience other types of degradation, such as material migration that degrades a stored logic state, degradation that compromises the ability to write to a target logic state, or degradation that compromises the ability to generate a read signal in response to a read operation. In various examples, two or more read thresholds 730 may be used to distinguish between determined and indeterminate information states, or to otherwise scale the weight or confidence of a detected information state. Memory cells 105, access lines (e.g., digit lines 210, signal lines 260), or information locations of codewords having indeterminate, unassigned, or relatively low confidence information states can be included in error handling operations that assign assumed information states, or alternatives thereof, when attempting to identify valid codewords (e.g., codewords that properly represent information written to a set of memory cells 105).

Fig. 8 illustrates an example of a method 800 of supporting erasure decoding of a memory device in accordance with examples disclosed herein. In some examples, method 800 may be performed by a memory device (such as memory device 100 described with reference to fig. 1-7 or associated circuitry). In some examples, one or more of the operations of method 800 may be performed by a host device coupled with such memory device 100 (e.g., a host device that performs error detection, error correction, or other error handling techniques on information retrieved from memory device 100).

At 810, the method can include identifying a sensed codeword based on accessing a set of memory cells 105. In some examples, the set of memory cells 105 may include a row or page of memory cells 105 or some portion thereof. A codeword may have a set of information positions, and one or more of the set of information positions may be associated with an indeterminate or unassigned information state (e.g., an X logic state, a null logic state, a non-asserted logic state). In some examples, information locations associated with indeterminate or unassigned information states may correspond to memory cells 105 or access lines (e.g., digit lines 210, signal lines 260) for which charge leakage is detected or determined to be above or otherwise meet a threshold (e.g., using leakage detection component 201 described with reference to fig. 2 or 4). In some examples, an information location associated with an indeterminate information state may correspond to a memory cell 105 for which an associated read characteristic (e.g., read signal) is determined to be between a first threshold corresponding to a first information state and a second threshold corresponding to a second information state (e.g., read characteristic in the non-affirmative region, read characteristic between a first read threshold 730-a of logic 0 and a second read threshold 730-b of logic 1, as described with reference to FIG. 7).

In the example of method 800, the operation of 810 may include identifying a sensed codeword 815 with a value {1, X,0,1,1, X,1,0}, as shown. An example of sensed codeword 815 may illustrate a codeword having a set of eight information positions, where the second information position and the sixth information position are each associated with an indeterminate or unassigned information state (e.g., "X" logic state, a no-positive logic state, a null logic state). In other examples, sensed codewords can have more or less than eight information positions, and a given sensed codeword can have any number of 0 or more information positions associated with indeterminate or unassigned logic states, in accordance with the described techniques.

In some examples, identifying the sensed codeword at 810 may be accompanied by identifying parity information corresponding to the sensed codeword, such as one or more parity bits associated with the accessed memory cell 105 that may support subsequent error handling operations (e.g., error detection, error correction). In various examples, this parity information may be stored in the same row or memory segment 110 as the memory cells 105 corresponding to the sensed codeword, or this parity information may be retrieved from other locations in the memory system, such as another portion of the memory device 100 (e.g., the portion of the memory device 100 allocated to the parity information), or from another memory device 100 (e.g., when a host device stores information in a first memory device 100 and corresponding parity information in a second memory device 100).

At 820, method 800 may include assigning a respective assumed (e.g., speculative) information state to each location having an uncertain or unassigned information state. The assignment of 820 may be performed according to various techniques for assigning an information state to one or more codewords (e.g., speculative, hypothetical codewords) to perform subsequent error detection operations (e.g., to evaluate the validity of a hypothetical information state or hypothetical codeword).

Continuing with the example of sensed codeword 815 having a value of {1, X,0,1,1, X,1,0}, method 800 may include, at 820, assigning each location of sensed codeword 815 having a logical X with a logical 0, thereby generating speculative codeword 825-a having a value of {1,0,0,1,1,0,1,0 }. In various other examples, the assignment at 820 may include assigning each location having a logic X with a logic 1 or some other assumed or speculative information state, or assigning a pattern of assumed information states, such as assigning alternate locations having a logic X with a logic 0 or a logic 1.

In some examples, the operations of 820 may be performed based at least in part on a number of locations in sensed codeword 815 having an uncertain or unassigned information state satisfying a threshold. For example, when the number of locations with uncertain or unassigned information states is less than a threshold or less than or equal to a threshold, operations of 820 may be performed, where such a threshold may be equal to or otherwise based at least in part on a minimum distance or "hamming" distance of an error correction code or other error handling capability.

At 830, method 800 may include performing an error detection operation based on a codeword that includes the assumed information state (e.g., speculative codeword 825-a generated at 820). The error detection operation of 830 may be performed according to various techniques for identifying the presence or number of errors in speculative codeword 825-a. For example, speculative codeword 825-a may pass through an ECC engine, with the output being a bus or string that may be referred to as a syndrome. In some examples, when the syndrome contains all logical 0 s, speculative codeword 825-a may be identified as valid (e.g., matching or otherwise consistent with information written to a set of accessed memory cells 105). In some examples, the error detection operation of 830 may include parity (e.g., based at least in part on parity information associated with the sensed codeword 815), and the speculative codeword 825-a may be identified as valid if all parity bits based on processing the speculative codeword 825-a are 0 or otherwise match or agree with parity information associated with the sensed codeword 815 (e.g., of a set of accessed memory cells 105).

At 840, method 800 may include determining whether a codeword including the assumed information state is valid (e.g., based at least in part on an error detection operation of 830). For example, if the syndrome of the error detection operation of 830 performed on speculative codeword 825-a contains all 0 s, or if the parity information based on processing speculative codeword 825-a otherwise matches the parity information associated with sensed codeword 815, method 800 may proceed to 845 and forward the codeword including the assumed information state (e.g., assigned at 820). In a first example referring to speculative codeword 825-a with a value of {1,0,0,1,1,0,1,0}, if speculative codeword 825-a is identified as valid at 840, the method may include forwarding speculative codeword 825-a with a value of {1,0,0,1,1,0, 0}, at 845. If at 840, speculative codeword 825-a is determined to be invalid, method 800 may proceed to 850.

At 850, method 800 may include assigning a respective hypothesized information state to each location having an uncertain or unassigned information state, which may be different from the hypothesized information state assigned at 820. In some examples, the respective assumed information state assigned to each location at 850 may be the inverse or complement of the respective assumed information state assigned to the corresponding location at 820.

Continuing with the example of sensed codeword 815 having a value of {1, X,0,1,1, X,1,0}, at 850 method 800 may include assigning each location of sensed codeword 815 having a logical X with a logical 1, thereby generating speculative codeword 825-b having a value of {1,1,0,1,1,1,1,0 }. In various other examples, the assignment at 850 may include assigning each location having a logic X with a logic 1 or some other assumed or speculative information state, or assigning a pattern of assumed information states, such as assigning alternate locations having a logic X with a logic 1 or a logic 0.

At 860, method 800 may include performing an error detection operation based on the codeword that includes the assumed information state (e.g., speculative codeword 825-b generated at 850). The error detection operation of 860, which may be the same as, similar to, or different from the error detection operation of 830, may be performed according to various techniques for identifying the presence or number of errors in speculative codeword 825-b.

At 870, method 800 may include determining whether a codeword including the assumed information state is valid (e.g., an error detection operation based at least in part on 860). For example, if the syndrome of the error detection operation of 860 performed on speculative codeword 825-b contains all 0 s, or if the parity information based on processing speculative codeword 825-b otherwise matches the parity information associated with sensed codeword 815, method 800 may proceed to 875 and forward the codeword that includes the assumed information state (e.g., assigned at 850). In a first example of referring to speculative codeword 825-b with a value of {1,1,0,1,1,1, 0}, if speculative codeword 825-b is identified as valid at 870, the method may include forwarding speculative codeword 825-b with a value of {1,1,0,1,1,1,1,0}, at 875. If at 870 the speculative codeword 825-b is determined to be invalid, method 800 may proceed to 880.

At 880, method 800 may include identifying a codeword (e.g., speculative codeword 825) with a minimum number of errors. For example, a first speculative codeword 825-a may be associated with a first number of errors and a second speculative codeword 825-b may be associated with a second number of errors. When the first number of errors is different than the second number of errors, method 800 may include identifying a speculative codeword 825 associated with the smaller of the first number of errors and the second number of errors. When the first number of errors is equal to the second number of errors, method 800 may include identifying either or both of the speculative codewords. In some examples, method 800 may include a default value for identifying first speculative codeword 825-a or second speculative codeword 825-b (e.g., when the respective numbers of errors are equal).

At 890, method 800 may include performing an error correction operation on a codeword that includes the assumed information state (e.g., on speculative codeword 825 identified at 880). In some examples, error correction of 890 may include processing speculative codeword 825 with syndrome information (e.g., generated at 830 or 860) to generate a corrected codeword. In some examples, an error correction operation may identify erroneous locations of an incoming codeword and flip bits or otherwise alter the information state in those identified erroneous locations. At 890, method 800 may also include generating a corrected codeword 891 for forwarding at 895.

With continuing reference to the second instance of speculative codeword 825-b having a value {1,1,0,1,1,1,1,0}, identified and forwarded at 880 (e.g., the instance of speculative codeword 825-b invalid due to a single error), at 890 method 800 may include identifying speculative codeword 825-b as having an error in the sixth location, and method 800 may include generating corrected codeword 891 having a value {1,1,0,1,1,0,1,0 }. Accordingly, method 800 may proceed to 895, at 895 corrected codeword 891 may be forwarded.

845. The forwarding of 875 or 895 may include forwarding to various components of the memory system. In some examples, forwarding may include forwarding the speculative or corrected codewords from an ECC engine of the memory device 100 to an input/output component of the memory device 100 (e.g., to output to a host device coupled with the memory device 100). Additionally or alternatively, forwarding may include forwarding the speculative or corrected codeword from an ECC engine of the memory device 100 to a write component of the memory device 100 (e.g., for use within the memory device 100), such as a rewrite or write-back component, a wear leveling component, an information redistribution component, or some other memory management component of the memory device 100. In some examples, forwarding may include forwarding the speculative or corrected codewords from an ECC engine of a host device coupled with the memory device 100 to a processing component of the host device (e.g., to process information retrieved from the memory device 100). In some examples, forwarding at 845, 875, or 895 may be accompanied by other operations, such as diagnostic signaling that performs or requires deletion of corrections or error corrections, which may support additional diagnostic operations (e.g., initiating a leak detection operation, initiating remapping of memory addresses, signaling an error condition, or a potential error condition) of the memory device 100 or a host device coupled with the memory device 100.

Although the operations of method 800 are described in the context of a serial approach (e.g., first generating and processing a first speculative codeword 825-a and then generating a second speculative codeword 825-b, if necessary), in some instances, the operations of method 800 may be performed in a parallel approach. For example, method 800 may be modified to concurrently generate two or more speculative codewords 825 for parallel processing, such as concurrently performing operations 820 and 850, or concurrently performing operations 830 and 860 (e.g., concurrently generating and processing a first speculative codeword 825-a and a second speculative codeword 825-b). In some examples, such techniques may be performed using parallel error detection processing supported by two or more ECC engines or portions thereof (e.g., an ECC engine having two or more error detection components feeding a single error correction component). In some examples, two or more speculative codewords 825 may be generated first, followed by a determination of whether any of the speculative codewords 825 are valid, or a determination of which of the two or more speculative codewords 825 to forward for error correction operations (e.g., forwarding the speculative codeword 825 with the lowest number of errors).

Although method 800 is described with an example in which two information locations are associated with an ambiguous information state (e.g., an erasure) and there are no other errors (e.g., at information locations other than the information location identified as having the ambiguous information state), the described techniques for erasure decoding may support correction of various other combinations of errors and erasures. For example, the method may identify and correct an error that is not related to an uncertain information state (e.g., at the first information location, the third information location, the fourth information location, the fifth information location, the seventh information location, or the eighth information location) at 890. Furthermore, the described techniques for erasure decoding may be applied to various capabilities of the ECC engine, including supporting that various numbers of errors may be detected, or that various numbers of errors may be corrected.

For example, the minimum distance d of the error correction code between a given codeword (e.g., sensed codeword 815) and a valid codeword_minThis can be given by:

d_min>2t+s+l (1)

where t may equal the number of errors (e.g., locations are unknown) and s may equal the number of erasures (e.g., known information locations where the information state may be uncertain). An example of error handling according to the illustrative relationship of equation 1 is given in table 1 below, indicating how error handling may be improved when the described techniques are applied to erasure decoding given error correction capability and error detection capability (e.g., where ECC1 may refer to single bit error correction capability and ECC2 may refer to double bit error correction capability).

TABLE 1 error handling probability Using erasure decoding

Thus, according to these and other examples, the described techniques for erasure decoding may support greater error correction capabilities than could otherwise be supported by error handling codes when the information location associated with the error is unknown. For example, leak detection or other techniques may be used to identify the type of erasure condition where the information state may have an unknown value at a known location, and using this identification, three of these erasures may be corrected (e.g., supported by the two-bit parity information for each sensed codeword) using a 1-bit error corrector and a 2-bit error detector.

The described techniques for erasure decoding may have additional advantages. For example, since data correction occurs during decoding (e.g., as compared to encoding), bit flipping may be advantageously employed for fatigue management in a memory array. Furthermore, since the repair of valid data occurs during decoding, up to 3 deletion failures can be handled without prior knowledge of valid data (e.g., using two-bit error detection and single-bit error correction).

FIG. 9 shows a block diagram 900 of a memory device 905 supporting memory management for charge leakage according to an example disclosed herein. The memory device 905 may be an example of aspects of the memory devices described with reference to fig. 1-8. The memory device 905 may include an access manager 910, a sensing component 915, a leak detection component 920, a write operation manager 925, and a write operation indicator 930. Each of these modules may communicate with each other directly or indirectly (e.g., via one or more buses).

The access manager 910 may access the memory units. In some examples, accessing the memory cell includes activating a cell selection component for the memory cell. In some examples, access manager 910 may access the second memory unit. In various examples, an accessed memory cell may include a capacitive storage element.

The sensing component 915 can determine the stored logic state of the memory cell based on the access. In some examples, the sensing component 915 can determine that the second memory cell stores the logical state based on accessing the second memory cell. In some examples, determining the logic state stored by the memory cell includes latching a signal of an access line associated with the memory cell. In some examples, the sensing component 915 can determine a second logic state stored by a second memory cell, the second memory cell being selected by an access line common to the memory cells.

The leakage detection component 920 can detect charge leakage based on accessing the memory cell. In some examples, charge leakage detection is performed at least partially while the cell selection component is activated. In some examples, detecting charge leakage includes determining that a voltage of the access line drops below a threshold voltage after latching. In some examples, the leakage detection component 920 may detect a flow of charge across a transistor electrically connected between the memory cell and a sense component configured to determine that the memory cell stores a logic state. In some examples, leakage detecting component 920 may detect the second charge leakage based on accessing the second memory cell.

The write operation manager 925 may determine whether to write a logical state or a complement of a logical state to a memory cell based in part on detecting charge leakage. In some cases, the logic state is associated with a first amount of charge transfer associated with the capacitive storage element and the complement of the logic state is associated with a second amount of charge transfer, the second amount of charge transfer being greater than the first amount of charge transfer. In some examples, the write operation manager 925 may determine whether to write a logical state or a complement of a logical state based on the logical state being associated with a first amount of charge transfer and the complement of the logical state being associated with a second amount of charge transfer, the second amount of charge transfer being greater than the first amount of charge transfer. In some examples, the write operation manager 925 may write the determined logical state to the memory cell. In some examples, the write operation manager 925 may write the second logic state or the complement of the second logic state to the second memory cell based on determining whether to write the logic state or the complement of the logic state to the memory cell. In some examples, determining whether to write the logic state or the complement of the logic state to the memory cell is based on determining a logic state stored by another memory cell and detecting another charge leakage.

The write operation indicator 930 may store an indication of whether to write the logical state or the complement of the logical state to the memory cell. In some cases, the indication is associated with each memory cell in a set of memory cells that includes the memory cell. In some cases, each memory cell in the set of memory cells is selected by a common access line.

FIG. 10 shows a block diagram 1000 of a memory device 1005 supporting memory management for charge leakage, according to an example disclosed herein. The memory device 1005 may be an example of aspects of the memory devices described with reference to fig. 1-8. The memory device 1005 may include a row component 1010, a sensing component 1015, a leak detection component 1020, a rewrite operation determiner 1025, a rewrite operation controller 1030, and a rewrite operation indicator 1035. Each of these modules may communicate with each other directly or indirectly (e.g., via one or more buses). In some examples, memory device 1005 may include a plurality of memory cells that each include a respective storage element, and the described components may be included in a controller or circuitry coupled with the plurality of memory cells.

The row component 1010 can couple storage elements of each of a set of memory cells with a respective access line of a set of access lines. In some examples, row component 1010 may couple each memory cell with a respective access line of the set of access lines based on activating a cell selection component associated with the respective memory cell. In some examples, row component 1010 can couple each memory cell in the set of memory cells with a respective access line in the set of access lines based on activating a common select line.

The sense component 1015 can determine a respective logic state stored by each of the set of memory cells based on the coupling. In some examples, the sense component 1015 can determine the respective logic state of each of the set of memory cells by latching signals of respective signal lines associated with the respective memory cells.

Leakage detection component 1020 may determine whether a threshold amount of charge leakage is detected on one or more of the set of access lines after determining the respective logic state. In some examples, leakage detection component 1020 may determine whether a threshold amount of charge leakage is detected on one or more of the set of access lines at least partially while the cell selection component is activated. In some examples, leakage detection component 1020 may determine whether a threshold amount of charge leakage is detected based on comparing the voltage of the respective signal line to a threshold voltage after latching. In some examples, leakage detection component 1020 may determine whether a threshold amount of charge leakage is detected on one or more of the set of access lines based on detecting charge flow across transistors electrically connected with respective access lines of the set of access lines.

The rewrite operation determiner 1025 may select a direct rewrite operation for each of the memory cells or a complementary rewrite operation for each of the memory cells based on whether a threshold amount of charge leakage is detected on one or more of the set of access lines. In some examples, selecting whether to directly rewrite the operation or the complementary rewrite operation for a first logic state associated with a first amount of charge transfer and a second logic state associated with a second amount of charge transfer lower than the first amount of charge transfer is based, at least in part, on: (1) a number of the plurality of access lines associated with detecting the threshold amount of charge leakage and coupled with the memory cells storing the first logic state, and (2) a number of the plurality of access lines associated with detecting the threshold amount of charge leakage and coupled with the memory cells storing the second logic state.

The rewrite operation controller 1030 may perform a selected direct rewrite operation or a complementary rewrite operation on each of the set of memory cells. In some cases, the direct overwrite operation includes writing the respective logic state stored by the respective memory cell and the complementary overwrite operation includes writing a complement of the respective logic state stored by the respective memory cell.

The overwrite operation indicator 1035 may store an indication of whether a direct overwrite operation or a complementary overwrite operation is selected.

FIG. 11 shows a block diagram 1100 of a memory device 1105 supporting erasure decoding of the memory device, according to an example disclosed herein. Memory device 1105 may be an example of aspects of the memory devices described with reference to fig. 1-8. Memory device 1105 can include memory cell access component 1110, information state evaluation component 1115, speculative codeword generation component 1120, error detection component 1125, codeword forwarding component 1130, access signal evaluation component 1135, charge leakage evaluation component 1140, and error correction component 1145. Each of these modules may communicate with each other directly or indirectly (e.g., via one or more buses).

The memory cell access component 1110 can access a set of memory cells of a memory device.

The information state evaluation component 1115 can determine, based on accessing the set of memory cells, that one or more memory cells in the set of memory cells are associated with an indeterminate or non-determinate information state.

Speculative codeword generation component 1120 may generate a first codeword (e.g., a speculative codeword) that includes a set of information locations, each information location of the set of information locations corresponding to a respective memory unit of the set of memory units, wherein the generating includes assigning a respective assumed or speculative information state to each information location corresponding to a memory unit of the one or more memory units.

In some examples, speculative codeword generation component 1120 may generate a third codeword based on assigning a respective second assumed information state to one or more of the information positions corresponding to memory cells of the one or more memory cells.

In some examples, speculative codeword generation component 1120 may generate a fourth codeword based on assigning a respective third assumed information state to one or more of the information positions corresponding to the memory cells of the one or more memory cells.

Error detection component 1125 may perform an error detection operation based on a first codeword (e.g., a speculative codeword). In various examples, the error detection operation performed by the error detection component 1125 can indicate whether the first codeword is valid or invalid.

In some examples, the error detection component 1125 may perform a second error detection operation based on a third codeword (e.g., a speculative codeword). In various examples, the error detection operation performed by the error detection component 1125 may indicate whether the third codeword is valid or invalid.

In some examples, the error detection component 1125 may perform a third error detection operation based on a fourth codeword (e.g., a speculative codeword). In various examples, the error detection operation performed by the error detection component 1125 may indicate whether the fourth codeword is valid or invalid.

Codeword forwarding component 1130 may forward the second codeword based on performing an error detection operation. In some examples, forwarding the second codeword includes forwarding the second codeword (e.g., the same codeword as the speculative codeword) having the same information as the first codeword at each information location of the second codeword. In some examples, codeword forwarding component 1130 may forward a second codeword (e.g., a corrected codeword) based on performing a second error detection operation.

In some examples, forwarding the second codeword includes forwarding the second codeword (e.g., the same codeword as the speculative codeword) having the same information as the third codeword at each information location of the second codeword. In some examples, codeword forwarding component 1130 may forward the second codeword (e.g., the corrected codeword) based on performing the third error detection operation.

In some examples, to determine that the one or more memory cells are associated with an indeterminate information state, access signal evaluation component 1135 may determine, for each of the one or more memory cells, that a signal based on accessing the respective memory cell is between a first threshold associated with a first logic state and a second threshold associated with a second logic state.

In some examples, to determine that the one or more memory cells are associated with an indeterminate information state, access signal evaluation component 1135 may determine that an access line coupled with the respective memory cell has a voltage between a first threshold voltage and a second threshold voltage based on accessing the respective memory cell.

In some examples, to determine that the one or more memory cells are associated with an indeterminate information state, access signal evaluation component 1135 may determine that the current based on accessing the respective memory cell is between a first threshold current and a second threshold current.

In some examples, to determine that the one or more memory cells are associated with an indeterminate information state, charge leakage evaluation component 1140 may determine, for each of the one or more memory cells, that the charge leakage of the respective memory cell satisfies a threshold.

In some examples, to determine that the one or more memory cells are associated with an indeterminate information state, charge leakage evaluation component 1140 may determine, for each of the one or more memory cells, that a charge leakage associated with an access line coupled to the respective memory cell satisfies a threshold.

In some examples, error correction component 1145 may generate a second codeword (e.g., a corrected codeword) based on assigning a different information state than the first codeword to one or more information positions of the second codeword.

In some examples, error correction component 1145 may generate a second codeword (e.g., a corrected codeword) based on assigning a different information state to one or more information positions of the second codeword than the third codeword.

Fig. 12 shows a flow diagram illustrating one or more methods 1200 of supporting memory management for charge leakage in accordance with examples disclosed herein. The operations of method 1200 may be implemented by a memory device described herein or components thereof. For example, the operations of method 1200 may be performed by the memory device described with reference to fig. 9. In some examples, a memory device may execute a set of instructions to control the functional elements of the memory device to perform the described functions. Additionally or alternatively, the memory device may perform aspects of the described functions using dedicated hardware or circuitry.

At 1205, the memory device can access a memory cell having a capacitive storage element. The operations of 1205 may be performed according to methods described herein. In some examples, aspects of the operations of 1205 may be performed by the access manager 910 described with reference to fig. 9.

At 1210, the memory device may determine a logic state stored by the memory cell based on the access. The operations of 1210 may be performed according to methods described herein. In some examples, aspects of the operations of 1210 may be performed by the sensing component 915 described with reference to fig. 9.

At 1215, the memory device can detect charge leakage based on accessing the memory cell. The operations of 1215 may be performed in accordance with the methods described herein. In some examples, aspects of the operations of 1215 may be performed by the leak detection component 920 described with reference to fig. 9.

At 1220, the memory device can determine whether to write a logic state or a complement of a logic state to the memory cell based in part on detecting charge leakage. The operations of 1220 may be performed according to methods described herein. In some examples, aspects of the operations of 1220 may be performed by the write operation manager 925 described with reference to fig. 9.

At 1225, the memory device can write the determined logic state to the memory cell. The operations of 1225 may be performed according to methods described herein. In some examples, aspects of the operations of 1225 may be performed by the write operation manager 925 described with reference to fig. 9.

In some examples, an apparatus described herein may perform one or more methods, such as method 1200. The apparatus may include circuitry, features, means, or instructions (e.g., a non-transitory computer-readable medium storing instructions executable by a processor) for: the method includes accessing a memory cell having a capacitive storage element, determining a logic state stored by the memory cell based on the accessing, detecting charge leakage based on accessing the memory cell, determining whether to write the logic state or a complement of the logic state to the memory cell based in part on detecting the charge leakage, and writing the determined logic state to the memory cell.

Some examples of the method 1200 and apparatus described herein may further include operations, circuitry, features, means, or instructions for: determining whether to write a logic state or a complement of a logic state based on the logic state being associated with a first amount of charge transfer and a complement of the logic state being associated with a second amount of charge transfer greater than the first amount of charge transfer.

Some examples of the method 1200 and apparatus described herein may further include operations, circuitry, features, means, or instructions for: determining a second logic state stored by a second memory cell, the second memory cell being selected by a common access line of the memory cells; and writing a second logic state or a complement of the second logic state to the second memory cell based on the determination of whether to write the logic state or the complement of the logic state to the memory cell.

Some examples of the method 1200 and apparatus described herein may further include operations, circuitry, features, means, or instructions for: the method further includes accessing a second memory cell having a second capacitive storage element, determining that the second memory cell stores the logical state based on accessing the second memory cell, and detecting a second charge leakage based on accessing the second memory cell. In some examples, determining whether to write the logic state or the complement of the logic state to the memory cell may be based on determining that the second memory cell stores the logic state and detecting the second charge leakage.

Some examples of the method 1200 and apparatus described herein may further include operations, circuitry, features, means, or instructions for: an indication of whether to write the logic state or the complement of the logic state to the memory cell is stored. In some examples of the method 1200 and apparatus described herein, the indication may be associated with each memory cell in a set of memory cells that includes the memory cell. In some examples of the method 1200 and apparatus described herein, each memory cell in the set of memory cells may be selected by a common access line.

In some examples of the method 1200 and apparatus described herein, accessing a memory cell may include operations, circuitry, features, means, or instructions for activating a cell select component of the memory cell, and detecting charge leakage may be performed at least partially while the cell select component is activated.

In some examples of the method 1200 and apparatus described herein, determining the logical state stored by the memory cell may include operations, circuitry, features, means, or instructions for latching a signal of an access line associated with the memory cell, and detecting charge leakage may include operations, circuitry, features, means, or instructions for determining that a voltage of the access line falls below a threshold voltage after latching.

In some examples of the method 1200 and apparatus described herein, detecting charge leakage may include operations, circuitry, features, means, or instructions for: charge flow is detected across a transistor electrically connected between a memory cell and a sense component configured to determine that the memory cell stores a logic state.

In some examples of the method 1200 and apparatus described herein, the logic state is associated with a first amount of charge transfer associated with the capacitive storage element and the complement of the logic state is associated with a second amount of charge transfer that may be greater than the first amount of charge transfer.

Fig. 13 shows a flow diagram illustrating one or more methods 1300 of supporting erasure decoding for a memory device, according to aspects of the present disclosure. The operations of method 1300 may be implemented by a memory device described herein or components thereof. For example, the operations of method 1300 may be performed by the memory device described with reference to FIG. 11. In some examples, a memory device may execute a set of instructions to control the functional elements of the memory device to perform the described functions. Additionally or alternatively, the memory device may perform aspects of the described functions using dedicated circuitry or hardware.

At 1305, a memory device may access a set of memory cells of the memory device. The operations of 1305 may be performed in accordance with methods described herein. In some examples, aspects of the operations of 1305 may be performed by the memory cell access component described with reference to fig. 11.

At 1310, the memory device may determine that one or more memory cells in the set of memory cells are associated with an indeterminate information state based on accessing the set of memory cells. The operations of 1310 may be performed in accordance with the methods described herein. In some examples, aspects of the operations of 1310 may be performed by the information state evaluation component described with reference to fig. 11.

At 1315, the memory device may generate a first codeword that includes a set of information locations, each information location of the set of information locations corresponding to a respective memory cell of the set of memory cells. In some examples, generating the first codeword may include assigning a respective assumed information state to each information location corresponding to a memory cell of the one or more memory cells. The operations of 1315 may be performed in accordance with the methods described herein. In some examples, aspects of the operations of 1315 may be performed by the speculative codeword generation component described with reference to fig. 11.

At 1320, the memory device may perform an error detection operation based on the first codeword. The operations of 1320 may be performed in accordance with the methods described herein. In some examples, aspects of the operations of 1320 may be performed by the error detection component described with reference to fig. 11.

At 1325, the memory device may forward the second codeword based on performing the error detection operation. The operations of 1325 may be performed according to the methods described herein. In some examples, aspects of the operations of 1325 may be performed by the codeword forwarding component described with reference to fig. 11.

In some examples, an apparatus described herein may perform one or more methods, such as method 1300. The apparatus may include features, circuitry, means, or instructions (e.g., a non-transitory computer-readable medium storing instructions executable by a processor) for: accessing, at a memory device, a set of memory cells of the memory device; determining, based on accessing the set of memory cells, that one or more memory cells of the set of memory cells are associated with an indeterminate information state; generating a first codeword including a set of information locations, each information location of the set of information locations corresponding to a respective memory cell of the set of memory cells, wherein the generating includes assigning a respective assumed information state to each information location corresponding to a memory cell of the one or more memory cells; performing an error detection operation based on the first codeword; and forwarding a second codeword based on performing the error detection operation.

In some examples of method 1300 and apparatus described herein, determining that the one or more memory cells may be associated with an indeterminate information state may include operations, features, circuitry, means, or instructions for: determining, for each of the one or more memory cells, that a signal based on accessing the respective memory cell is between a first threshold associated with a first logic state and a second threshold associated with a second logic state.

In some examples of the method 1300 and apparatus described herein, determining that the signal based on accessing the respective memory cell is between the first threshold and the second threshold may include operations, features, circuitry, means, or instructions for: determining that an access line coupled with a respective memory cell has a voltage between a first threshold voltage and a second threshold voltage based on accessing the respective memory cell.

In some examples of the method 1300 and apparatus described herein, determining that the signal based on accessing the respective memory cell is between the first threshold and the second threshold may include operations, features, circuitry, means, or instructions for: a determination is made that the current based on accessing the respective memory cell is between the first threshold current and the second threshold current.

In some examples of the method 1300 and apparatus described herein, determining that the one or more memory cells are associated with an indeterminate information state may include operations, features, circuitry, means, or instructions for: determining, for each of the one or more memory cells, that a charge leakage of the respective memory cell satisfies a threshold.

In some examples of the method 1300 and apparatus described herein, determining that the one or more memory cells are associated with an indeterminate information state may include operations, features, circuitry, means, or instructions for: determining, for each of the one or more memory cells, that a charge leakage associated with an access line coupled to the respective memory cell satisfies a threshold.

In some examples of the method 1300 and apparatus described herein, performing the error detection operation may indicate that the first codeword is valid, and forwarding the second codeword may include operations, features, circuitry, means, or instructions for: forwarding a second codeword having the same information as the first codeword at each information location of the second codeword.

In some examples of the method 1300 and apparatus described herein, performing the error detection operation may indicate that the first codeword is invalid and within the error correction capability of the memory device, and the method 1300 or apparatus described herein may further include operations, features, circuitry, means, or instructions for: a second codeword is generated based on assigning an information state, which may be different from the first codeword, to one or more information positions of the second codeword.

In some examples of the method 1300 and apparatus described herein, performing the error detection operation may indicate that the first codeword is invalid and exceeds the error correction capability of the memory device, and the method 1300 and apparatus described herein may further include operations, features, circuitry, means, or instructions for: the method further includes generating a third codeword based on assigning respective second assumed information states to one or more of the information locations corresponding to memory cells of the one or more memory cells, performing a second error detection operation based on the third codeword, and forwarding the second codeword based on performing the second error detection operation.

In some examples of the method 1300 and apparatus described herein, performing the second error detection operation may indicate that the third codeword is valid, and forwarding the second codeword may include operations, features, circuitry, means, or instructions for: the second codeword is forwarded with the same information as the third codeword at each information position of the second codeword.

In some examples of the method 1300 and apparatus described herein, performing the second error detection operation may indicate that the first codeword is invalid and within the error correction capability of the memory device, and the method 1300 or apparatus described herein may further include operations, features, circuitry, means, or instructions for: a second codeword is generated based on assigning a different information state to one or more information positions of the second codeword than the third codeword.

In some examples of the method 1300 and apparatus described herein, performing the second error detection operation may indicate that the first codeword is invalid and exceeds the error correction capability of the memory device, and the method 1300 or apparatus described herein may further include operations, features, circuitry, means, or instructions for: the method further includes generating a fourth codeword based on assigning respective third hypothesized information states to one or more of the information locations corresponding to memory cells of the one or more memory cells, performing a third error detection operation based on the fourth codeword, and forwarding a second codeword based on performing the third error detection operation.

It should be noted that the methods described above describe possible implementations, and that the operations and steps may be rearranged or otherwise modified, and other implementations may be resorted to. Further, portions from two or more of the methods may be combined.

An apparatus is described. The apparatus may include: a memory cell; a sense component configured to detect a logic state stored by the memory cell during an access operation; circuitry configured to detect charge leakage after detecting the logic state during the access operation; and a controller configured to write a complement of the logic state to a memory cell during the access operation based on the detected charge leakage satisfying a threshold.

In some examples, the controller may be configured to write the complement of the logic state based on the logic state being associated with a first amount of charge transfer and the complement of the logic state being associated with a second amount of charge transfer that is greater than the first amount of charge transfer.

In some examples, the sensing component may be configured to detect a logic state during a read portion of the access operation, and the circuitry may be configured to detect charge leakage prior to a rewrite portion of the access operation.

In some examples, the circuitry includes a second sensing component.

In some examples, the sensing component includes circuitry.

In some examples, the sensing component can be configured to latch a signal of an access line associated with the memory cell, and the circuitry can be configured to determine that a voltage of the access line falls below a threshold voltage after latching.

In some examples, the circuitry can be configured to detect a flow of charge across a cascode electrically connected between the memory cell and the sense component.

Another apparatus is described. The apparatus may include: a set of memory cells each including a respective storage element; and a controller coupled with the set of memory cells and configured to couple storage elements of each of the set of memory cells with respective access lines of a set of access lines, determine a respective logic state stored by each of the set of memory cells based on the coupling, determine whether a threshold amount of charge leakage is detected on one or more of the set of access lines after determining the respective logic state, select a direct overwrite operation for each of the memory cells or a complementary overwrite operation for each of the memory cells based on whether a threshold amount of charge leakage is detected on one or more of the set of access lines, and perform the selected direct overwrite operation or the complementary overwrite operation on each of the set of memory cells.

In some examples, the direct overwrite operation includes writing a respective logic state stored by the respective memory cell, and the complementary overwrite operation includes writing a complement of the respective logic state stored by the respective memory cell.

In some examples, a number of the set of access lines is associated with detecting a threshold amount of charge leakage and is coupled with memory cells storing the first logic state, and a number of the set of access lines is associated with detecting a threshold amount of charge leakage and is coupled with memory cells storing a second logic state.

Some examples may further include storing an indication of whether the selection of the direct overwrite operation or the complementary overwrite operation.

In some examples, coupling the storage element of each of the set of memory cells with a respective access line of the set of access lines may include operations, circuitry, features, means, or instructions for: each memory cell in the set of memory cells is coupled with a respective access line in the set of access lines based on activating a common select line.

Some examples may further include: coupling each memory cell with a respective access line of the set of access lines based on activating a cell select component associated with the respective memory cell; and determining whether a threshold amount of charge leakage is detected on one or more of the set of access lines at least partially while the cell select component is activated.

Some examples may further include determining the respective logic state of each of the set of memory cells by latching a signal of a respective signal line associated with the respective memory cell and determining whether an amount of threshold charge leakage is detected based on comparing a voltage of the respective signal line to a threshold voltage after latching.

Some examples may further include: determining whether an amount of threshold charge leakage is detected on one or more of the set of access lines may be based on detecting charge flow across transistors electrically connected with respective access lines of the set of access lines.

Another apparatus is described. The apparatus may include: a memory array comprising a set of memory cells; an access component coupled with the memory array and configured to generate a first codeword based on accessing the set of memory cells; a leakage detection component coupled with the memory array and configured to determine that charge leakage associated with one or more memory cells in the set of memory cells satisfies a threshold; an error detection component coupled with the access component and the leakage detection component and configured to perform one or more error detection operations based on assigning a respective assumed information state to each information location of the first codeword corresponding to the one or more memory cells; and an input/output component configured to forward a second codeword based on performing the one or more error detection operations.

In some examples, the error detection component may be configured to perform a first error detection operation on a third codeword based on assigning respective first assumed information states to each information location of a first codeword corresponding to the one or more memory cells; and performing a second error detection operation on a fourth codeword based on each information location assigned a respective second assumed information state to the first codeword corresponding to the one or more memory cells.

In some examples, the error detection component may be configured to perform the first error detection operation and the second error detection operation concurrently.

In some examples, the error detection component may be configured to select one of the third codeword or the fourth codeword based on a number of errors detected by the first error detection operation and a number of errors detected by the second error detection operation, and forward the selected codeword.

In some examples, the error detection component may be configured to select a third codeword when the number of errors detected by a first error detection operation is less than the number of errors detected by a second error detection operation, and select a fourth codeword when the number of errors detected by a second error detection operation is less than the number of errors detected by a first error detection operation.

In some examples, the error detection component can be configured to forward the selected codeword to the error correction component when a number of errors corresponding to the selected codeword is within the error correction capabilities of the error correction component.

In some examples, the error detection component may be configured to forward the selected codeword to the input/output component when the number of errors corresponding to the selected codeword is zero.

An apparatus is described. The apparatus may include: a memory array comprising a set of memory cells; and a controller coupled with the memory array. The controller may be configured to access the set of memory cells; determining, based on accessing the set of memory cells, that one or more memory cells of the set of memory cells are associated with an indeterminate information state; generating a first codeword including a set of information locations, each information location of the set of information locations corresponding to a respective memory cell of the set of memory cells, wherein the generating includes assigning a respective assumed information state to each information location corresponding to a memory cell of the one or more memory cells; performing an error detection operation based on the first codeword; and forwarding the second codeword based on performing the error detection operation.

In some examples, to determine that the one or more memory cells are associated with an indeterminate information state, the controller may be configured to determine, for each of the one or more memory cells, that a charge leakage of the respective memory cell satisfies a threshold.

In some examples, to determine that the one or more memory cells are associated with an indeterminate information state, the controller may be configured to determine, for each of the one or more memory cells, that a charge leakage associated with an access line coupled to the respective memory cell satisfies a threshold.

In some examples, to determine that the one or more memory cells are associated with an indeterminate information state, the controller may be configured to determine, for each of the one or more memory cells, that a signal based on accessing the respective memory cell is between a first threshold associated with a first logic state and a second threshold associated with a second logic state.

In some examples, to determine that the signal based on accessing the respective memory cell is between the first threshold and the second threshold, the controller may be configured to determine that the access line coupled with the respective memory cell has a voltage based on accessing the respective memory cell that is between the first threshold voltage and the second threshold voltage.

In some examples, to determine that the signal based on accessing the respective memory cell is between the first threshold and the second threshold, the controller may be configured to determine that the current based on accessing the respective memory cell is between the first threshold current and the second threshold current.

Information and signals described herein may be represented using any of a variety of different technologies and techniques. For example, data, instructions, commands, information, signals, bits, symbols, and chips that may be referenced throughout the above description may be represented by voltages, currents, electromagnetic waves, magnetic fields or particles, optical fields or particles, or any combination thereof. Some figures may illustrate signals as a single signal; however, those skilled in the art will appreciate that the signals may represent a signal bus, where the bus may have various bit widths.

As used herein, the term "virtual ground" refers to a circuit node that is held at a voltage of approximately zero volts (0V) but is not directly coupled to ground. Therefore, the voltage of the virtual ground may temporarily float and return to about 0V in a steady state. The virtual ground may be implemented using various electronic circuit elements, such as a voltage divider composed of an operational amplifier and a resistor. Other embodiments are also possible. "virtual ground" or "virtually grounded" means connected to about 0V.

The terms "electronic communication," "conductive contact," "connection," and "coupling" may refer to a relationship between components that enables a signal to flow between the components. Components are considered to be in electronic communication with each other (or in conductive contact or connection or coupling) if there are any conductive paths between them that can support signals flowing between them at any time. At any given time, the conductive path between components that are in electronic communication with each other (or in conductive contact or connection or coupling) may be open or closed based on the operation of the device that includes the connected components. The conductive path between connected components may be a direct conductive path between components, or the conductive path between connected components may be an indirect conductive path that may include intermediate components (e.g., switches, transistors, or other components). In some cases, signal flow between connected components may be interrupted for a certain time, for example, using one or more intermediate components (e.g., switches or transistors).

The term "coupled" refers to a condition that moves from an open circuit relationship between components, in which signals cannot currently pass between components via conductive paths, to a closed circuit relationship between components, in which signals can pass between components via conductive paths. When a component (e.g., a controller) couples other components together, the component initiates a change that allows a signal to flow between the other components via a conductive path that previously disallowed the signal flow.

The term "isolation" refers to the relationship between components between which signals cannot currently flow. The components are isolated from each other if there is an open circuit between the components. For example, when a switch positioned between components is open, the two components separated by the switch are isolated from each other. When the controller isolates two components from each other, the controller affects changes that prevent signals from flowing between the components using the conductive paths that previously permitted the flow of signals.

As used herein, the term "substantially" means that a modified property (e.g., a verb or adjective modified by the term "substantially") is not necessarily completely, but sufficiently close to achieve the benefit of the property.

As used herein, the term "electrode" may refer to an electrical conductor and, in some cases, may serve as an electrical contact to a memory cell or other component of a memory array. The electrodes may include traces, wires, conductive lines, conductive layers, etc., that provide a conductive path between elements or components of the memory array.

As used herein, the term "short circuit" refers to a relationship between components that establishes a conductive path between the components via activation of a single intermediate component between the two components in question. For example, a first component shorted to a second component may exchange signals with the second component when a switch between the first component and the second component is closed. Thus, a short circuit may be a dynamic operation that enables charge to flow between components (or lines) in electronic communication.

The devices discussed herein, including memory arrays, may be formed on a semiconductor substrate, such as silicon, germanium, silicon-germanium alloys, gallium arsenide, gallium nitride, and the like. In some cases, the substrate is a semiconductor wafer. In other cases, the substrate may be a silicon-on-insulator (SOI) substrate, such as silicon-on-glass (SOG) or silicon-on-Sapphire (SOP), or an epitaxial layer of semiconductor material on another substrate. The conductivity of the substrate or sub-regions of the substrate may be controlled by doping using various chemistries including, but not limited to, phosphorous, boron, or arsenic. The doping may be performed during the initial formation or growth of the substrate by ion implantation or by any other doping means.

The switching elements or transistors discussed herein may represent Field Effect Transistors (FETs) and include three-terminal devices including sources, drains, and gates. The terminals may be connected to other electronic components through conductive materials (e.g., metals). The source and drain may be conductive and may include heavily doped (e.g., degenerated) semiconductor regions. The source and drain may be separated by a lightly doped semiconductor region or channel. If the channel is n-type (i.e., the majority carriers are electrons), the FET may be referred to as an n-type FET. If the channel is p-type (i.e., the majority carriers are holes), the FET may be referred to as a p-type FET. The channel may be capped by an insulated gate oxide. Channel conductivity can be controlled by applying a voltage to the gate. For example, applying a positive or negative voltage to an n-type FET or a p-type FET, respectively, may cause the channel to become conductive. A transistor may be "on" or "activated" when a voltage greater than or equal to the threshold voltage of the transistor is applied to the transistor gate. A transistor may be "off" or "deactivated" when a voltage less than the transistor threshold voltage is applied to the transistor gate.

The illustrations set forth herein in connection with the figures describe example configurations and are not intended to represent all examples that may be implemented or within the scope of the claims. The term "exemplary" as used herein means "serving as an example, instance, or illustration," and is not "preferred" or "advantageous over other examples. The detailed description includes specific details to provide an understanding of the described technology. However, the techniques may be practiced without these specific details. In other instances, well-known structures and devices are shown in block diagram form in order to avoid obscuring the concepts of the described examples.

In the drawings, similar components or features may have the same reference label. Further, various components of the same type may be distinguished by following the reference label by a dash and a second label that distinguishes among the similar components. If only the first reference label is used in the specification, the description may apply to any one of the similar components having the same first reference label, regardless of the second reference label.

Information and signals described herein may be represented using any of a variety of different technologies and techniques. For example, data, instructions, commands, information, signals, bits, symbols, and chips that may be referenced throughout the above description may be represented by voltages, currents, electromagnetic waves, magnetic fields or particles, optical fields or particles, or any combination thereof.

The various illustrative blocks and modules described in connection with the disclosure herein may be implemented or performed with a general purpose processor, a Digital Signal Processor (DSP), an Application Specific Integrated Circuit (ASIC), a Field Programmable Gate Array (FPGA) or other programmable logic device, discrete gate or transistor logic, discrete hardware components, or any combination thereof designed to perform the functions described herein. A general purpose processor may be a microprocessor, but in the alternative, the processor may be any processor, controller, microcontroller, or state machine. A processor may also be implemented as a combination of computing devices (e.g., a combination of a DSP and a microprocessor, a plurality of microprocessors, one or more microprocessors in conjunction with a DSP core, or any other such configuration).

The functions described herein may be implemented in hardware, software executed by a processor, firmware, or any combination thereof. If implemented in software executed by a processor, the functions may be stored on or transmitted over as one or more instructions or code on a computer-readable medium. Other examples and implementations are within the scope of the disclosure and the following claims. For example, due to the nature of software, the functions described may be implemented using software executed by a processor, hardware, firmware, hard-wired, or a combination of any of these. Features implementing functions may also be physically located at various locations, including being interspersed so that portions of functions are implemented at different physical locations. Further, as used herein (including in the claims), a "or" (e.g., a list of items preceded by a phrase such as "at least one of …" or one or more of …) "as used in a list of items indicates an inclusive list such that, for example, a list of at least one of A, B or C means a or B or C or AB or AC or BC or ABC (i.e., a and B and C). Further, as used herein, the phrase "based on" should not be construed to refer to a set of closure conditions. For example, an exemplary step described as "based on condition a" may be based on both condition a and condition B without departing from the scope of the present disclosure. In other words, as used herein, the phrase "based on" should be interpreted in the same manner as the phrase "based at least in part on".

The description herein is provided to enable any person skilled in the art to make or use the present disclosure. Various modifications to the disclosure will be readily apparent to those skilled in the art, and the generic principles defined herein may be applied to other variations without departing from the scope of the disclosure. Thus, the disclosure is not intended to be limited to the examples and designs described herein but is to be accorded the widest scope consistent with the principles and novel features disclosed herein.

Claims

1. A method, comprising:

accessing, at a memory device, a plurality of memory cells of the memory device;

based at least in part on accessing the plurality of memory cells, determining that one or more memory cells of the plurality of memory cells are associated with an indeterminate information state;

generating a first codeword comprising a plurality of information locations, each information location of the plurality of information locations corresponding to a respective memory cell of the plurality of memory cells, wherein the generating comprises assigning a respective assumed information state to each information location corresponding to a memory cell of the one or more memory cells;

performing an error detection operation based at least in part on the first codeword; and

Forwarding a second codeword based at least in part on performing the error detection operation.

2. The method of claim 1, wherein determining that the one or more memory cells are associated with an indeterminate information state comprises:

determining, for each of the one or more memory cells, that a signal based, at least in part, on accessing the respective memory cell is between a first threshold associated with a first logic state and a second threshold associated with a second logic state.

3. The method of claim 2, wherein determining that the signal based at least in part on accessing the respective memory cell is between the first threshold and the second threshold comprises:

determining that an access line coupled with the respective memory cell has a voltage between a first threshold voltage and a second threshold voltage based at least in part on accessing the respective memory cell.

4. The method of claim 2, wherein determining that the signal based at least in part on accessing the respective memory cell is between the first threshold and the second threshold comprises:

determining is based at least in part on whether the current accessing the respective memory cell is between a first threshold current and a second threshold current.

5. The method of claim 1, wherein determining that the one or more memory cells are associated with an indeterminate information state comprises:

determining, for each of the one or more memory cells, that a charge leakage of the respective memory cell satisfies a threshold.

6. The method of claim 1, wherein determining that the one or more memory cells are associated with an indeterminate information state comprises:

determining, for each of the one or more memory cells, that a charge leakage associated with an access line coupled to the respective memory cell satisfies a threshold.

7. The method of claim 1, wherein:

performing the error detection operation indicates that the first codeword is valid; and is

Forwarding the second codeword comprises forwarding the second codeword with the same information as the first codeword at each information location of the second codeword.

8. The method of claim 1, wherein performing the error detection operation indicates that the first codeword is invalid and within an error correction capability of the memory device, the method further comprising:

generating the second codeword based at least in part on assigning a different information state to one or more information positions of the second codeword than the first codeword.

9. The method of claim 1, wherein performing the error detection operation indicates that the first codeword is invalid and exceeds an error correction capability of the memory device, the method further comprising:

generating a third codeword based at least in part on assigning respective second assumed information states to one or more of the information locations corresponding to memory cells of the one or more memory cells;

performing a second error detection operation based at least in part on the third codeword; and

forwarding the second codeword based at least in part on performing the second error detection operation.

10. The method of claim 9, wherein:

performing the second error detection operation indicates that the third codeword is valid; and is

Forwarding the second codeword comprises forwarding the second codeword with the same information as the third codeword at each information location of the second codeword.

11. The method of claim 9, wherein performing the second error detection operation indicates that the third codeword is invalid and within the error correction capability of the memory device, the method further comprising:

Generating the second codeword based at least in part on assigning a different information state to one or more information positions of the second codeword than the third codeword.

12. The method of claim 9, wherein performing the error detection operation indicates that the third codeword is invalid and exceeds the error correction capability of the memory device, the method further comprising:

generating a fourth codeword based at least in part on assigning respective third assumed information states to one or more of the information locations corresponding to memory cells of the one or more memory cells;

performing a third error detection operation based at least in part on the fourth codeword; and

forwarding the second codeword based at least in part on performing the third error detection operation.

13. An apparatus, comprising:

a memory array comprising a plurality of memory cells;

an access component coupled with the memory array and configured to generate a first codeword based at least in part on accessing the plurality of memory cells;

a leakage detection component coupled with the memory array and configured to determine that a charge leakage associated with one or more memory cells of the plurality of memory cells satisfies a threshold;

An error detection component coupled with the access component and the leakage detection component and configured to perform one or more error detection operations based at least in part on assigning respective assumed information states to each information location of the first codeword corresponding to the one or more memory cells;

an input/output component configured to forward a second codeword based at least in part on performing the one or more error detection operations.

14. The apparatus of claim 13, wherein the error detection component is configured to:

performing a first error detection operation on a third codeword that is based at least in part on assigning a respective first assumed information state to each information position of the first codeword corresponding to the one or more memory cells; and

performing a second error detection operation on a fourth codeword that is based at least in part on assigning a respective second assumed information state to each information position of the first codeword corresponding to the one or more memory cells.

15. The apparatus of claim 14, wherein the error detection component is configured to perform the first error detection operation and the second error detection operation concurrently.

16. The apparatus of claim 14, wherein the error detection component is configured to:

selecting one of the third codeword or the fourth codeword based at least in part on a number of errors detected by the first error detection operation and a number of errors detected by the second error detection operation; and

forwarding the selected codeword.

17. The apparatus of claim 16, wherein the error detection component is configured to:

selecting the third codeword when the number of errors detected by the first error detection operation is less than the number of errors detected by the second error detection operation; and

selecting the fourth codeword when the number of errors detected by the second error detection operation is less than the number of errors detected by the first error detection operation.

18. The apparatus of claim 16, wherein the error detection component is configured to forward the selected codeword to an error correction component when a number of errors corresponding to the selected codeword is within an error correction capability of the error correction component.

19. The apparatus of claim 16, wherein the error detection component is configured to forward the selected codeword to the input/output component when a number of errors corresponding to the selected codeword is zero.

20. An apparatus, comprising:

a memory array comprising a plurality of memory cells; and

a controller coupled with the memory array and configured to:

accessing the plurality of memory cells;

21. The apparatus of claim 20, wherein to determine that the one or more memory cells are associated with an indeterminate information state, the controller is configured to:

22. The apparatus of claim 21, wherein to determine that the signal based at least in part on accessing the respective memory cell is between the first threshold and the second threshold, the controller is configured to:

23. The apparatus of claim 21, wherein to determine that the signal based at least in part on accessing the respective memory cell is between the first threshold and the second threshold, the controller is configured to:

24. The apparatus of claim 20, wherein to determine that the one or more memory cells are associated with an indeterminate information state, the controller is configured to:

25. The apparatus of claim 20, wherein to determine that the one or more memory cells are associated with an indeterminate information state, the controller is configured to: