TWI762057B - Gate driving circuit - Google Patents

Abstract

A gate driving circuit is provided. The gate driving circuit includes a plurality of shift register circuits coupled in series, where a Nth stage shift register circuit includes a direction selecting circuit, a voltage adjustment circuit, a pull-down circuit, and an output stage circuit. The direction selecting circuit generates a first driving signal on a first driving end. The voltage adjustment circuit pulls up a second driving signal according to a first scanning direction signal or a second scanning direction signal. The pull-down circuit is based on a previous gate drive signal and a next gate drive signal, and pulls down the second driving signal according to the first scanning direction signal or the second scanning direction signal. The output stage circuit generates a Nth stage gate driving signal according to the first driving signal and the second driving signal.

Description

gate drive circuit

The present invention relates to a gate drive circuit, and more particularly, to a gate drive circuit of a display device.

With the advancement of electronic technology, automotive panels have become more and more widely used in recent years, and the issues of safety evaluation and reliability of display panels have also attracted more and more attention from consumers.

In the technology of the display panel, the pull-down circuit in the conventional shift register circuit often has a race condition, which causes a large current to exist in the leakage path of the pull-down circuit. In this case, the drive terminal in the shift register circuit that is to be charged will be affected by the competition phenomenon, resulting in an unexpected situation, which will seriously affect the reliability of the entire circuit.

The present invention provides a gate driving circuit, which can effectively improve the reliability of the circuit.

The gate driving circuit of the present invention includes a shift temporary storage circuit coupled in series, The shift temporary storage circuit of the Nth stage includes a direction selection circuit, a voltage adjustment circuit, a pull-down circuit and an output stage circuit. The direction selection circuit is coupled to the first driving terminal, and selects the first scanning direction signal or the second scanning direction signal according to the front-stage gate driving signal and the rear-stage gate driving signal to generate the first driving signal on the first driving terminal . The voltage adjustment circuit is coupled to the second driving terminal, and pulls up the second driving signal on the second driving terminal according to the first scanning direction signal or the second scanning direction signal. The pull-down circuit is coupled to the first driving terminal and the second driving terminal, and the pull-down circuit is based on the front-stage gate driving signal and the rear-stage gate driving signal, and according to the first scanning direction signal or the second scanning direction signal to pull down the second the second drive signal on the drive end. The output stage circuit is coupled to the first driving terminal and the second driving terminal, and generates an N-th gate driving signal according to the first driving signal and the second driving signal.

Based on the above, the shift register circuit of the gate driving circuit according to the embodiments of the present invention can effectively pull down the second driving signal on the second driving terminal through the pull-down circuit with bidirectional driving function, so that the circuit does not Competition will occur. In this way, when the first driving terminal is about to perform a charging operation, the first driving terminal will not be affected by the second driving signal on the second driving terminal and will be smoothly charged to a high voltage level, thereby improving the reliability of the circuit. .

100, 200, 300: The shift temporary storage circuit of the Nth stage

110, 210, 310: Direction selection circuit

120, 220, 320: Voltage adjustment circuit

130, 230, 330: pull-down circuit

140, 240, 340: output stage circuit

231, 331: Signal selector

232, 332: signal transmitter

350: Pull Down Drive

360: Resistor leakage element

CK1~CK6: Clock signal

D2U: Second scan direction signal

DE1: The first drive end

DS1: The first drive signal

DE2: The second drive end

DS2: The second drive signal

GOFF: gate off signal

M11, M12, M21~M24, M31~M34, M42~M53, M61, M62: Transistor

MD1: pull-down transistor

OUT1: output terminal

OUT2: Auxiliary output terminal

PD: Signal output terminal

RST: reset signal

SR[N]: Nth gate drive signal

SR_T[N]: Nth stage auxiliary gate drive signal

SR_T[N-1]: Front stage gate drive signal

SR_T[N+1]: Post-stage gate drive signal

T1, T2: time interval

U2D: first scan direction signal

VGH: Gate High Voltage

XDONB: reference ground voltage

FIG. 1 is a schematic diagram of a gate driving circuit according to an embodiment of the present invention.

FIG. 2 is a schematic diagram of a shift register circuit according to another embodiment of the present invention.

FIG. 3 is a schematic diagram of a shift register circuit according to another embodiment of the present invention.

FIG. 4 is an operation waveform diagram of the shift register circuit according to the embodiment of the present invention.

The term "coupled (or connected)" as used throughout this specification (including the scope of the application) may refer to any direct or indirect means of connection. For example, if it is described in the text that a first device is coupled (or connected) to a second device, it should be interpreted that the first device can be directly connected to the second device, or the first device can be connected to the second device through another device or some other device. indirectly connected to the second device by a connecting means. Also, where possible, elements/components/steps using the same reference numerals in the drawings and embodiments represent the same or similar parts. Elements/components/steps that use the same reference numerals or use the same terminology in different embodiments may refer to relative descriptions of each other.

Please refer to FIG. 1 , which is a schematic diagram of a gate driving circuit according to an embodiment of the present invention. The gate driving circuit includes a plurality of shift register circuits coupled in series, wherein the shift register circuit 100 of the Nth stage includes a direction selection circuit 110 , a voltage adjustment circuit 120 , a pull-down circuit 130 and an output stage circuit 140 . The direction selection circuit 110 is coupled to the first driving terminal DE1. The direction selection circuit 110 can receive the front-stage gate driving signal SR_T[N-1], the back-stage gate driving signal SR_T[N+1], the first scanning direction signal U2D and the second scanning direction signal D2U, and according to the previous-stage gate driving signal SR_T[N+1] The gate driving signal SR_T[N-1] and the subsequent gate driving signal SR_T[N+1] are used to select the first scanning direction signal U2D or the second scanning direction signal D2U to generate the first driving on the first driving terminal DE1 signal DS1.

It is worth mentioning that, in this embodiment, the first scanning direction signal U2D is used to indicate that the scanning direction of the gate driving circuit is the first direction (for example, scanning from the top of the display panel (not shown) to the bottom of the display panel). ), and the second scanning direction signal D2U is used to indicate that the scanning direction of the gate driving circuit is the second direction (eg, scanning from the bottom of the display panel to the top of the display panel). In addition, in this embodiment, the front-stage gate driving signal SR_T[N-1] and the rear-stage gate driving signal SR_T[N+1] may be the shift of the N-1th stage and the N+1th stage, respectively. The gate drive signal generated by the bit temporary storage circuit, or the front-stage gate drive signal SR_T[N-1] and the latter-stage gate drive signal SR_T[N+1] can also be the N-1th and The auxiliary gate drive signal generated by the N+1 stage shift temporary storage circuit. The generation of the auxiliary gate driving signal will be described in detail in the following embodiments.

On the other hand, the voltage adjustment circuit 120 is coupled to the second driving terminal DE2. The voltage adjustment circuit 120 can receive the clock signals CK3 and CK5, the gate high voltage VGH, the first scanning direction signal U2D and the second scanning direction signal D2U. The voltage adjustment circuit 120 can be used for pulling up the voltage value of the second driving signal DS2 on the second driving terminal DE2 based on the clock signals CK3 and CK5, and according to the first scanning direction signal U2D and the second scanning direction signal D2U as the gate electrode. High voltage VGH.

The pull-down circuit 130 is coupled to the first driving terminal DE1 and the second driving terminal DE2. The pull-down circuit 130 can receive the preceding gate driving signal SR_T[N-1], the succeeding gate driving signal SR_T[N+1], the first scanning direction signal U2D, the second scanning direction signal D2U and the reference ground voltage XDONB. The pull-down circuit 130 can be used based on the front-stage gate driving signal SR_T[N-1] and the back-stage gate driving signal SR_T[N+1], and according to the first scanning direction signal U2D or the second scanning direction signal D2U, the voltage value of the second driving signal DS2 on the second driving terminal DE2 is pulled down as the reference ground voltage XDONB.

On the other hand, the output stage circuit 140 is coupled to the first driving terminal DE1 and the second driving terminal DE2. The output stage circuit 140 can receive the clock signal CK1, the gate high voltage VGH, the first driving signal DS1 and the second driving signal DS2. The output stage circuit 140 can be used to generate the Nth stage gate driving signal SR[N] based on the clock signal CK1, the first driving signal DS1 and the second driving signal DS2.

It is worth noting that the above N is a positive integer, and the gate driving circuit of the embodiment of the present invention can be applied to a 6-phase (phase) shift register circuit (that is, 6 groups of shift register circuits), However, the present invention is not limited to this. In addition, in this embodiment, the clock signals CK1 , CK3 and CK5 may be generated by a clock signal generator (not shown). Wherein, under the design requirement of the 6-phase shift register circuit, the clock signal generator can be used to generate sequentially enabled clock signals CK1-CK6, and provide these clock signals CK1-CK6 to the corresponding clock signals CK1-CK6 in the shift register circuit. The number of the above-mentioned clock signals is not limited to 6, and the clock signal generator can generate different numbers of clock signals according to the design requirements of the gate driving circuit.

According to the above description, since the pull-down circuit 130 of this embodiment has the function of bidirectional driving, no matter which scanning method (eg, the first direction or the second direction) the scanning direction of the gate driving circuit is, the pull-down circuit 130 can be driven according to the first direction or the second direction. A state of the scanning direction signal U2D or the second scanning direction signal D2U, and through the front gate The driving signal SR_T[N-1] and the subsequent gate driving signal SR_T[N+1] are used to effectively pull down the voltage value of the second driving signal DS2 on the second driving terminal DE2, so as to raise and pull down the second driving terminal DE2 capability on the second drive signal DS2.

In addition, since there is no additional leakage path in the pull-down circuit 130 of this embodiment, the transistor inside the shift register circuit is in a degraded state (for example, the transistor has low mobility (low mobility). ) or/and high threshold voltage), when the signal of the previous stage is written, the pull-down circuit 130 can quickly pull down the second driving signal DS2 on the second driving terminal DE2 to a low voltage level , and the first driving signal DS1 on the first driving terminal DE1 can be normally pulled up to a high voltage level. In this way, the gate driving circuit of the present embodiment is not affected by the competition phenomenon in the circuit, and thus the reliability of the shift register circuit 100 is effectively improved.

Please refer to FIG. 2 below. FIG. 2 is a schematic diagram of a shift register circuit according to another embodiment of the present invention. In FIG. 2 , the shift register circuit 200 of the Nth stage includes a direction selection circuit 210 , a voltage adjustment circuit 220 , a pull-down circuit 230 and an output stage circuit 240 . In this embodiment, the direction selection circuit 210 includes transistors M11 and M12. The first terminal of the transistor M11 is coupled to the first driving terminal DE1, the second terminal of the transistor M11 receives the first scanning direction signal U2D, and the control terminal of the transistor M11 receives the front-stage gate driving signal SR_T[N-1] . The first terminal of the transistor M12 is coupled to the first driving terminal DE1, the second terminal of the transistor M12 receives the second scanning direction signal D2U, and the control terminal of the transistor M12 receives the subsequent gate driving signal SR_T[N+1] . One of the transistors M11 and M12 can be based on the front-stage gate driving signal SR_T[N-1] or the back-stage gate driving signal SR_T[N-1] The pole driving signal SR_T[N+1] is turned on, and the first scanning direction signal U2D or the second scanning direction signal D2U is transmitted to the first driving terminal DE1 to generate the first driving signal DS1.

In this embodiment, the voltage adjustment circuit 220 includes transistors M21 ˜ M23 . The second end of the transistor M21 receives the clock signal CK3, and the control end of the transistor M21 receives the first scanning direction signal U2D. The first end of the transistor M22 is coupled to the first end of the transistor M21, the second end of the transistor M22 receives the clock signal CK5, and the control end of the transistor M22 receives the second scanning direction signal D2U. The first terminal of the transistor M23 is coupled to the second driving terminal DE2, the second terminal of the transistor M23 receives the gate high voltage VGH, and the control terminal of the transistor M23 is coupled to the first terminal of the transistor M21.

Specifically, in the voltage adjustment circuit 220, one of the transistors M21 and M22 can be turned on according to the first scanning direction signal U2D or the second scanning direction signal D2U, and transmits the second clock signal CK3 or the third The clock signal CK5 is sent to the control terminal of the transistor M23. Next, when the transistor M23 is turned on according to the enabled second clock signal CK3 or the third clock signal CK5, the voltage adjustment circuit 220 can adjust the voltage value of the second driving signal DS2 on the second driving terminal DE2 Pulled up to the gate high voltage VGH.

In this embodiment, the pull-down circuit 230 includes a signal selector 231, a signal transmitter 232 and a pull-down transistor MD1. The signal selector 231 includes transistors M31 and M32. The first terminal of the transistor M31 is coupled to the signal output terminal PD, the second terminal of the transistor M31 receives the front-stage gate driving signal SR_T[N-1], and the control terminal of the transistor M31 receives the first scanning direction signal U2D. The first end of the transistor M32 is coupled to To the signal output terminal PD, the second terminal of the transistor M32 receives the gate driving signal SR_T[N+1] of the subsequent stage, and the control terminal of the transistor M32 receives the second scanning direction signal D2U.

The signal transmitter 232 includes transistors M33 and M34. The first terminal of the transistor M33 receives the reference ground voltage XDONB, the second terminal of the transistor M33 is coupled to the second driving terminal DE2 and receives the second driving signal DS2, and the control terminal of the transistor M33 is coupled to the signal output terminal PD. The first terminal of the transistor M34 receives the reference ground voltage XDONB, the second terminal of the transistor M34 is coupled to the second driving terminal DE2 and receives the second driving signal DS2, and the control terminal of the transistor M34 is coupled to the first driving terminal DE1 and receive the first driving signal DS1.

In addition, the first end of the pull-down transistor MD1 receives the reference ground voltage XDONB, the second end of the pull-down transistor MD1 is coupled to the first driving end DE1 and receives the first driving signal DS1, and the control end of the pull-down transistor MD1 is coupled to The second driving terminal DE2 receives the second driving signal DS2.

Specifically, in the pull-down circuit 230, the signal selector 231 can select the front-stage gate driving signal SR_T[N-1] or the back-stage gate driving signal SR_T[N-1] according to the first scanning direction signal U2D or the second scanning direction signal D2U The driving signal SR_T[N+1] is transmitted to the signal output terminal PD. Then, the signal transmitter 230 can pull down the second driving signal according to one of the front-stage gate driving signal SR_T[N-1] and the back-stage gate driving signal SR_T[N+1] and the first driving signal DS1 DS2.

For example, when the first scan direction signal U2D is set to be enabled (eg, a high voltage level) and the second scan direction signal D2U is set to be disabled (eg, a low voltage level), the transistor M31 may According to the first scanning direction signal U2D, is turned on and the transistor M32 can be turned off according to the second scanning direction signal D2U. At this time, the signal selector 231 can transmit the front-stage gate driving signal SR_T[N-1] to the signal output terminal PD. Next, when the transistor M33 is turned on according to the front-stage gate driving signal SR_T[N-1] and/or the transistor M34 is turned on according to the first driving signal DS1, the pull-down circuit 230 can pull down the pull-down circuit 230 through the signal transmitter 232 The second driving signal DS2 on the second driving terminal DE2 reaches the reference ground voltage XDONB.

Conversely, when the first scan direction signal U2D is set to be disabled (eg, a low voltage level) and the second scan direction signal D2U is set to be enabled (eg, a high voltage level), the transistor M31 can The first scanning direction signal U2D is turned off and the transistor M32 can be turned on according to the second scanning direction signal D2U. At this time, the signal selector 231 can transmit the post-stage gate driving signal SR_T[N+1] to the signal output terminal PD. Then, when the transistor M33 is turned on according to the subsequent gate driving signal SR_T[N+1] and/or the transistor M34 is turned on according to the first driving signal DS1, the pull-down circuit 230 can pull down the pull-down circuit 230 through the signal transmitter 232 The second driving signal DS2 on the second driving terminal DE2 reaches the reference ground voltage XDONB.

In addition, in this embodiment, when the pull-down transistor MD1 is turned on according to the second driving signal DS2, the pull-down transistor MD1 can pull down the first driving signal DS1 to the reference ground voltage XDONB according to the second driving signal DS2.

In this embodiment, the output stage circuit 240 includes transistors M42 to M44 and a capacitor C1. The second terminal of the transistor M42 is coupled to the first driving terminal DE1 and receives the first driving signal DS1, and the control terminal of the transistor M42 receives the gate high voltage VGH and is maintained in an on state. In addition, the first end of the transistor M43 is coupled to The output terminal OUT1 of the shift register circuit 200 and the output terminal OUT1 of the shift register circuit 200 generate the Nth stage gate driving signal SR[N]. The second terminal of the transistor M43 receives the clock signal CK1, and the control terminal of the transistor M43 is coupled to the first terminal of the transistor M42.

In addition, the first terminal of the transistor M44 receives the reference ground voltage XDONB, the second terminal of the transistor M44 is coupled to the output terminal OUT1, and the control terminal of the transistor M44 is coupled to the second driving terminal DE2 and receives the second driving signal DS2 . The first terminal of the capacitor C1 is coupled to the control terminal of the transistor M43, and the second terminal of the capacitor C1 is coupled to the output terminal OUT1.

It is worth mentioning that when the first driving signal DS1 is at a high voltage level (eg, equal to the gate high voltage VGH), the first driving signal DS1 will be transmitted to the second terminal of the transistor M42. In addition, through the on-voltage provided by the transistor M42, the voltage on the gate of the transistor M43 is substantially equal to the gate-high voltage VGH minus an on-voltage. In this way, the attenuation of the voltage value transmitted to the gate of the transistor M43 is effectively reduced, thereby increasing the operational margin of the circuit.

On the other hand, in this embodiment, when the first driving signal DS1 is equal to the gate high voltage VGH, the second driving signal DS2 may be the reference ground voltage XDONB. In this case, the transistor M43 may be correspondingly turned on, and the output stage circuit 240 may pull up the Nth stage gate driving signal SR[N] based on the enabled clock signal CK1. In addition, through the turned-on transistor M43, according to the pulled-up clock signal CK1, the voltage on the control terminal of the transistor M43 can be pumped to a higher voltage value by the capacitor C1, and the voltage of the transistor M43 is increased. degree of conduction.

According to the above, in the present embodiment, since the pull-down circuit 230 can use the signal selector 231 and the signal transmitter 232 to effectively pull down the second driving signal DS2 on the second driving terminal DE2, the pull-down circuit 230 does not The competition phenomenon occurs. Therefore, when the first driving terminal DE1 is about to perform a charging operation, the first driving terminal DE1 will be smoothly charged to a high voltage level without being affected by the second driving signal DS2 on the second driving terminal DE2. In this way, the pull-down circuit 230 of this embodiment can effectively improve the ability to pull down the second driving signal DS2 on the second driving terminal DE2, and improve the reliability of the circuit.

Please refer to FIG. 3 below. FIG. 3 is a schematic diagram of a shift register circuit according to another embodiment of the present invention. In FIG. 3 , the shift register circuit 300 of the Nth stage includes a direction selection circuit 310 , a voltage adjustment circuit 320 , a pull-down circuit 330 and an output stage circuit 340 . Different from the foregoing embodiments, in this embodiment, the shift register circuit 300 of the Nth stage may further include a pull-down driver 350 and a resistive leakage element 360 .

In the embodiment of FIG. 3 , the pull-down driver 350 includes transistors M52 and M53. The second terminal of the transistor M52 is coupled to the first driving terminal DE1 and receives the first driving signal DS1. The first terminal of the transistor M53 receives the reference ground voltage XDONB, the second terminal of the transistor M53 is coupled to the first terminal of the transistor M52, and the control terminals of the transistor M53 and the transistor M52 are jointly coupled to the second driving terminal DE2 and receives the second driving signal DS2. The transistors M52 and M53 can be simultaneously turned on according to the second driving signal DS2, and pull down the first driving signal DS1 to the reference ground voltage XDONB.

It is worth noting that the first end of the transistor M52 and the first end of the transistor M53 The two terminals may be commonly coupled to the leakage resistance element 360 . In this embodiment, the leakage resistance element 360 includes transistors M61 and M62. The second end of the transistor M61 is coupled to the first end of the transistor M52, and the control end of the transistor M61 receives the first driving signal DS1. In addition, the first terminal and the control terminal of the transistor M62 are coupled to each other and jointly receive the gate off signal GOFF, and the second terminal of the transistor M62 is coupled to the first terminal of the transistor M61.

In the leakage resistance element 360 of this embodiment, the transistor M62 may be coupled in a diode configuration, wherein the first terminal and the control terminal of the transistor M62 form the anode of the diode, and the second terminal of the transistor M62 forms the anode of the diode. The two terminals form the cathode of the diode.

Further, the leakage resistance element 360 can prevent the leakage current on the pull-down driver 350 according to the first driving signal DS1 and the gate-off signal GOFF. The gate off signal GOFF in this embodiment is used to indicate whether the gate driving circuit stops outputting the enabled gate driving signal. For example, when the gate-off signal GOFF is set to a high voltage level (for example, equal to the gate-high voltage VGH), it means that the gate driving circuit stops outputting the gate driving signal. At this time, the N-th gate driving signal is SR[N] is equal to the reference ground voltage XDONB. Conversely, when the gate-off signal GOFF is set to a low voltage level (eg, equal to the reference ground voltage XDONB), it means that the gate driving circuit can normally output the gate driving signal.

Please note here that when the first driving terminal DE1 is being charged and the gate-off signal GOFF is a low voltage value (eg equal to the reference ground voltage XDONB), the voltage on the first driving terminal DE1 may pass through the transistor that is turned on M61 to discharge the action. In this case, the leakage resistance element 360 can pass through the transistor M62 The diode is formed to block the possible discharge path between the power transistor M61 and the gate-off signal GOFF, so as to maintain the charging efficiency of the first driving terminal DE1. In addition, the leakage resistance element 360 can increase the voltage value on the first end of the transistor M52 according to the gate off signal GOFF, and reduce the leakage current generated on the coupling path of the transistors M52 and M53.

On the other hand, with regard to the configuration of the voltage adjustment circuit 320 , different from the foregoing embodiments, in this embodiment, the second end of the transistor M21 can receive the clock signal CK5 , and the second end of the transistor M22 can receive the clock signal CK5 . Receive clock signal CK1. In addition, the voltage adjustment circuit 320 may further include a transistor M24. The first terminal of the transistor M24 is coupled to the second driving terminal DE2, the second terminal of the transistor M24 receives the gate high voltage VGH, and the control terminal of the transistor M24 can receive the reset signal RST.

Specifically, when the shift register circuit 300 needs to reset the first drive signal DS1 on the first drive terminal DE1, the transistor M24 can be turned on according to the enabled reset signal RST to pull The voltage value of the high second driving signal DS2 is the gate high voltage VGH. At this time, the transistors M52 and M53 can be simultaneously turned on according to the pulled second driving signal DS2, so that the pull-down driver 350 can pull down the voltage value of the first driving signal DS1 to the reference ground voltage XDONB, so as to complete the reset set action.

On the other hand, the output stage circuit 340 of the embodiment of FIG. 3 includes transistors M45 ˜ M51 . The second terminal of the transistor M45 is coupled to the first driving terminal DE1 and receives the first driving signal DS1 , and the control terminal of the transistor M45 receives the gate high voltage VGH and is maintained in an on state. The first terminal of the transistor M48 is coupled to the shift register circuit 300 The output terminal OUT1 of the shift temporary storage circuit 300 generates the Nth gate driving signal SR[N]. The second end of the transistor M48 receives the clock signal CK3, and the control end of the transistor M48 is coupled to the first end of the transistor M45. In this embodiment, the transistor M49 is coupled in a capacitor configuration, wherein the control terminal of the transistor M49 forms the first terminal of the capacitor and is coupled to the control terminal of the transistor M48, and the first terminal of the transistor M49 The terminal and the second terminal are coupled to each other and form the second terminal of the capacitor and are coupled to the first terminal of the transistor M48.

In addition, the first terminal of the transistor M50 receives the reference ground voltage XDONB, the second terminal of the transistor M50 is coupled to the output terminal OUT1, and the control terminal of the transistor M50 receives the second driving signal DS2. The first terminal of the transistor M51 receives the reference ground voltage XDONB, the second terminal of the transistor M51 is coupled to the output terminal OUT1, and the control terminal of the transistor M51 receives the gate off signal GOFF.

In particular, in this embodiment, the shift register circuit 300 has an auxiliary output terminal OUT2 to generate the Nth stage auxiliary gate driving signal SR_T[N]. The first end of the transistor M46 is coupled to the auxiliary output end OUT2, the second end of the transistor M46 receives the clock signal CK3, and the control end of the transistor M46 is coupled to the first end of the transistor M45. The first terminal of the transistor M47 receives the reference ground voltage XDONB, the second terminal of the transistor M47 is coupled to the auxiliary output terminal OUT2, and the control terminal of the transistor M47 receives the second driving signal DS2.

Further, in this embodiment, the N-th gate driving signal SR[N] can be used to only connect to the gates of the thin film transistors of the corresponding display pixels. The Nth stage auxiliary gate drive signal SR_T[N] can be used to connect to the shift buffers of other stages on the circuit. In this way, the N-th gate driving signal SR[N] can provide sufficient driving capability to turn on the thin film transistors of the corresponding display pixels to ensure display quality.

On the other hand, in the output stage circuit 340 of this embodiment, when the second driving signal DS2 is equal to the gate high voltage VGH, the first driving signal DS1 may be the reference ground voltage XDONB. At this time, the transistor M47 and the transistor M50 can be turned on according to the pulled second driving signal DS2, and make the Nth stage gate driving signal SR[N] and the Nth stage auxiliary gate driving signal SR_T[N ] is pulled down to the reference ground voltage XDONB.

In addition, the transistor M51 of the output stage circuit 340 can be turned on according to the gate off signal GOFF, and when the shift register circuit 300 stops outputting the enabled N-th gate driving signal SR[N], the transistor M51 The gate driving signal SR[N] of the Nth stage can be pulled down to the reference ground voltage XDONB according to the enabled gate off signal GOFF.

Regarding the direction selection circuit 310 , the voltage adjustment circuit 320 , the pull-down circuit 330 and the output stage circuit 340 in this embodiment, reference may be made to the direction selection circuit 210 , the voltage adjustment circuit 220 , the pull-down circuit 230 and the output stage circuit 240 mentioned in FIG. 2 . Related descriptions to analogy. In addition, the pull-down circuit 330 of the present embodiment includes a signal selector 331 and a signal transmitter 332, wherein the signal selector 331 and the signal transmitter 332 can also refer to the correlation of the signal selector 231 and the signal transmitter 232 mentioned in FIG. 2. The description is analogous, so it will not be repeated.

Please refer to FIG. 4 below. FIG. 4 is an operation waveform diagram of the shift register circuit according to the embodiment of the present invention. The following takes the embodiment of FIG. 2 as an example for description, please also Referring to FIG. 2 and FIG. 4 , in the present embodiment, when the shift register circuit 200 operates in the time interval T1, the transistor M11 of the direction selection circuit 210 can be based on the enabled front-stage gate driving signal SR_T[N -1] is turned on, and the first scanning direction signal U2D is transmitted to the first driving terminal DE1 to generate the first driving signal DS1 with a high voltage level. At this time, the signal selector 231 transmits the front-stage gate driving signal SR_T[N-1] to the signal transmitter 232 according to the first scanning direction signal U2D, so that the signal transmitter 232 can make the signal transmitter 232 according to the first driving signal DS1 and the previous-stage gate driving signal SR_T[N-1]. The gate driving signal SR_T[N-1] is used to pull down the second driving signal DS2.

Next, when the shift register circuit 200 operates in the time interval T2, the transistor M11 of the direction selection circuit 210 can be turned on according to the enabled post-stage gate driving signal SR_T[N+1], and transmits the second The scanning direction signal D2U is sent to the first driving terminal DE1 to generate the first driving signal DS1 with a high voltage level. At this time, the signal selector 231 transmits the post-stage gate driving signal SR_T[N+1] to the signal transmitter 232 according to the second scanning direction signal D2U, so that the signal transmitter 232 according to the first driving signal DS1 and the post-stage gate driving signal SR_T[N+1] The gate driving signal SR_T[N+1] is used to pull down the second driving signal DS2.

In this way, the pull-down circuit 230 of this embodiment can effectively pull down the second driving signal DS2 on the second driving terminal DE2 by using the signal selector 231 and the signal transmitter 232, and the first driving signal DS2 on the first driving terminal DE1 The driving signal DS1 can be smoothly charged to a high voltage level, thereby improving the reliability of the circuit.

To sum up, the shift register circuit of the gate driving circuit according to the embodiments of the present invention can effectively pull down the first pull-down circuit through the pull-down circuit with bidirectional driving function. The second driving signal on the two driving terminals prevents competition from occurring in the circuit. In this way, when the first driving terminal is about to perform a charging operation, the first driving terminal will not be affected by the second driving signal on the second driving terminal and will be smoothly charged to a high voltage level, thereby improving the reliability of the circuit. .

100: The shift temporary storage circuit of the Nth stage

110: Direction selection circuit

120: Voltage adjustment circuit

130: pull-down circuit

140: Output stage circuit

CK1, CK3, CK5: clock signal

D2U: Second scan direction signal

DE1: The first drive end

DS1: The first drive signal

DE2: The second drive end

DS2: The second drive signal

SR[N]: Nth gate drive signal

SR_T[N-1]: Front stage gate drive signal

SR_T[N+1]: Post-stage gate drive signal

U2D: first scan direction signal

VGH: Gate High Voltage

XDONB: reference ground voltage

Claims (14)

A gate drive circuit, comprising: a plurality of shift temporary storage circuits, the shift temporary storage circuits are coupled in series, wherein the shift temporary storage circuit of the Nth stage includes; a direction selection circuit, coupled to a first a driving terminal, which selects a first scanning direction signal or a second scanning direction signal according to a front-stage gate driving signal and a rear-stage gate driving signal to generate a first driving signal on the first driving terminal; a A voltage adjustment circuit, coupled to a second driving terminal, pulls up a second driving signal on the second driving terminal according to the first scanning direction signal or the second scanning direction signal; a pull-down circuit is coupled to The first driving terminal and the second driving terminal receive the front-stage gate driving signal and the back-stage gate driving signal, and the pull-down circuit is based on the front-stage gate driving signal and the back-stage gate driving signal, and pulls down the second driving signal on the second driving terminal according to the first scanning direction signal or the second scanning direction signal, wherein the pull-down circuit includes: a signal selector, which has a signal output terminal and is used for according to the first scanning direction signal or the second scanning direction signal to select and transmit the front-stage gate driving signal or the back-stage gate driving signal to the signal output terminal; and a signal transmitter coupled to the signal The output terminal, the first driving terminal and the second driving terminal are used for pulling down the second driving terminal according to one of the front-stage gate driving signal and the rear-stage gate driving signal and the first driving signal signal; and an output stage circuit, coupled to the first driving terminal and the second driving terminal, and generating an N-stage gate driving signal according to the first driving signal and the second driving signal. The gate driving circuit of claim 1, wherein the pull-down circuit further comprises: a pull-down transistor, the first end of which receives a reference ground voltage, the second end of which is coupled to the first driving end, and the control end of which is The second driving signal is received. The gate drive circuit of claim 1, wherein the signal selector comprises: a first transistor, the first end of which is coupled to the signal output end, and the second end of which receives the front-stage gate drive signal, Its control end receives the first scanning direction signal; and a second transistor, the first end of which is coupled to the signal output end, the second end of which receives the post-stage gate drive signal, and the control end of which receives the second A scanning direction signal, wherein the signal transmitter includes: a third transistor, the first end of which receives a reference ground voltage, the second end of which is coupled to the second driving end, and the control end of which is coupled to the signal output end ; and a fourth transistor, the first terminal of which receives the reference ground voltage, the second terminal of which is coupled to the second driving terminal, and the control terminal of which receives the first driving signal. The gate drive circuit of claim 1, wherein the direction selection circuit comprises: a first transistor, the first end of which is coupled to the first drive end, the second end of which receives the first scanning direction signal, and the control end of which receives the front-stage gate drive signal; and a second transistor, The first terminal is coupled to the first driving terminal, the second terminal receives the second scanning direction signal, and the control terminal receives the rear gate driving signal. The gate drive circuit of claim 1, wherein the voltage adjustment circuit comprises: a first transistor, the second terminal of which receives a second clock signal or a third clock signal, and the control terminal of which receives the first transistor a scanning direction signal; a second transistor, the first end of which is coupled to the first end of the first transistor, the second end of which receives the third clock signal or a first clock signal, and its control end receiving the second scanning direction signal; and a third transistor, the first end of which is coupled to the second driving end, the second end of which receives a gate high voltage, and the control end of which is coupled to the first transistor the first end. The gate drive circuit of claim 5, wherein the voltage adjustment circuit further comprises: a fourth transistor, the first end of which is coupled to the second drive end, and the second end of which receives the gate voltage, Its control terminal receives a reset signal. The gate driving circuit of claim 1, wherein the output stage circuit comprises: a first transistor, the second terminal of which receives the first driving signal, and the control terminal of which receives a gate high voltage; a second transistor, the first end of which generates the N-th gate driving signal, the second end of which receives a first clock signal, and the control end of which is coupled to the first end of the first transistor; a first Three transistors, the first terminal of which receives a reference ground voltage, the second terminal of which is coupled to the first terminal of the second transistor, and the control terminal of which receives the second driving signal; and a capacitor, the first terminal of which is coupled to is connected to the control terminal of the second transistor, and the second terminal thereof is coupled to the first terminal of the second transistor. The gate driving circuit of claim 1, wherein the output stage circuit comprises: a first transistor, the second terminal of which is coupled to the first driving terminal, the control terminal of which receives a gate high voltage; a first transistor Two transistors, the first terminal of which is coupled to an auxiliary output terminal, the second terminal of which receives a second clock signal, and the control terminal of which is coupled to the first terminal of the first transistor, wherein the auxiliary output terminal generates an auxiliary N-th gate driving signal; a third transistor, the first terminal of which receives a reference ground voltage, the second terminal of which is coupled to the auxiliary output terminal, and the control terminal of which receives the second driving signal; a first Four transistors, the first terminal of which generates the N-th gate driving signal, the second terminal of which receives the second clock signal, and the control terminal of which is coupled to the first terminal of the first transistor; a capacitor whose third One end is coupled to the control end of the fourth transistor, and the second end is coupled to the first end of the fourth transistor; a fifth transistor, the first end of which receives the reference ground voltage, the second end of which is coupled to the first end of the fourth transistor, and the control end of which receives the second driving signal; and a sixth transistor, Its first end receives the reference ground voltage, its second end is coupled to the second end of the fifth transistor, and its control end receives a gate closing signal. The gate driving circuit of claim 1, further comprising: a pull-down driver, coupled between the first driving terminal and the second driving terminal, for pulling down the first driving signal according to the second driving signal a driving signal; and a resistive leakage element coupled to the pull-down driver for providing a gate closing signal to the pull-down driver according to the first driving signal. The gate driving circuit of claim 9, wherein the pull-down driver comprises: a first transistor, the second terminal of which is coupled to the first driving terminal, and the control terminal of which is coupled to the second driving terminal; and A second transistor, the first end of which receives a reference ground voltage, the second end of which is coupled to the first end of the first transistor, and the control end of which is coupled to the second driving end. The gate driving circuit of claim 9, wherein the leakage resistance element comprises: a first transistor, the first end of which receives the gate close signal, the second end of which is coupled to the pull-down driver, and the control end of which is The first driving signal is received. The gate drive circuit as claimed in claim 11, wherein the resistance-leakage element further comprises: a diode coupled between the paths of the first transistor receiving the gate-off signal, wherein the anode of the diode receives the gate-off signal, and the cathode of the diode is coupled to the first transistor the first end of the crystal. The gate driving circuit of claim 12, wherein the diode is a second transistor, wherein the first end of the second transistor and the control end of the second transistor are commonly coupled and received together The gate off signal, the second end of the second transistor is coupled to the first end of the first transistor. The gate driving circuit of claim 1, wherein the front-stage gate driving signal is the N-1 th gate driving signal, and the latter stage gate driving signal is the N+1 th stage gate driving signal.

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