TWI761750B - Automatic performance analysis system and method thereof for analog circuits - Google Patents

Automatic performance analysis system and method thereof for analog circuits Download PDF

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TWI761750B
TWI761750B TW109100660A TW109100660A TWI761750B TW I761750 B TWI761750 B TW I761750B TW 109100660 A TW109100660 A TW 109100660A TW 109100660 A TW109100660 A TW 109100660A TW I761750 B TWI761750 B TW I761750B
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circuit
analog circuit
netlist
simulation
analog
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TW202127294A (en
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郭柏佑
吳志中
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國立雲林科技大學
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Abstract

An automatic performance analysis method includes: providing a computer-aided analysis tool, with selecting and inputting a target analog circuit therein; loading a topology corresponding to the selected target analog circuit; inputting a circuit specification corresponding to the selected target analog circuit and judging whether the circuit specification to meet original conditions; returning to input a new circuit specification if failing to meet the original conditions; or, generating a calculated circuit netlist if meeting the original conditions; inputting the calculated circuit netlist to a simulation software to generate a simulation result; judging whether the simulation result to meet the original conditions; returning to input an adjusted transistor specification to the circuit netlist if failing to meet the original conditions; generating a simulated circuit netlist if meeting the original conditions.

Description

類比電路效能自動化分析系統及其方法 Analog circuit performance automatic analysis system and method

本發明係關於一種類比電路〔analog circuit〕效能自動化分析〔automatic performance analysis〕系統及其方法;更特別是關於一種簡化〔simplified〕類比電路效能自動化分析系統及其方法。 The present invention relates to an analog circuit performance automatic analysis system and method; more particularly, to a simplified analog circuit performance automatic analysis system and method.

舉例而言,習用電路設計模擬方法及其系統,如中華民國專利公開第TW-201610733號〝估計電路的自熱特徵之模擬系統以及其之設計方法〞之發明專利申請案,其揭示一種電路設計模擬方法及其系統,其為利用由電腦執行的一電路模擬工具設計一半導體電路之方法。 For example, conventional circuit design simulation methods and systems, such as the invention patent application of the Republic of China Patent Publication No. TW-201610733 "Simulation System for Estimating Self-heating Characteristics of Circuits and Design Method Therefor", discloses a circuit design A simulation method and a system thereof, which are methods for designing a semiconductor circuit using a circuit simulation tool executed by a computer.

承上,前述第TW-201610733號之該模擬方法包含:藉由該電路模擬工具計算半導體電路之元件之功率消耗;利用該等功率消耗及該等元件中每一者之幾何形狀資訊,進行建置關於該半導體電路之一熱網路連線表;利用該電路模擬工具來以該熱網路連線表進行該半導體電路之模擬,以偵測該等元件中每一者之溫度;及該熱網路連線表包括該等元件中每一者之熱容資訊。 Continuing from the above, the simulation method of the aforementioned No. TW-201610733 includes: calculating the power consumption of the components of the semiconductor circuit by the circuit simulation tool; set up a thermal network connection table for the semiconductor circuit; use the circuit simulation tool to simulate the semiconductor circuit with the thermal network connection table to detect the temperature of each of the components; and the The thermal network connection table includes thermal capacitance information for each of these components.

另一習用電路設計模擬方法及其系統,如中華民國專利公開第TW-201145061號〝Hspice相容等效電路模擬系統及方法〞之發明專利申請案,其亦揭示一種電路設計模擬方法及其系統。該模擬系統包含一資料獲取模組、一電腦資料儲存單元、一參數檢查模組、一函數產生 模組及一等效電路產生模組。 Another conventional circuit design simulation method and system, such as the invention patent application of the Republic of China Patent Publication No. TW-201145061 "Hspice Compatible Equivalent Circuit Simulation System and Method", which also discloses a circuit design simulation method and system . The simulation system includes a data acquisition module, a computer data storage unit, a parameter checking module, a function generation The module and an equivalent circuit generating module.

承上,前述第TW-201145061號之該模擬方法包含:該資料獲取模組用於自該電腦資料儲存單元內讀取一Touchstone格式之N埠電路系統資料檔案,及自該N埠電路系統資料檔案內獲取一S參數矩陣;該參數檢查模組用於檢查該S參數矩陣內的所有S參數是否滿足電路被動特性;該函數產生模組用於設定產生S參數之有理數函數所需之極值-殘值數量與系統誤差;該等效電路產生模組用於基於極值-殘值數量執行向量擬合演算法產生S參數之有理數函數矩陣;及根據該有理數函數矩陣模擬合成一Hspice相容等效電路。 Continuing from the above, the simulation method of the aforementioned No. TW-201145061 includes: the data acquisition module is used for reading an N-port circuit system data file in Touchstone format from the computer data storage unit, and obtaining the N-port circuit system data from the computer data storage unit. Obtain an S-parameter matrix from the file; the parameter checking module is used to check whether all the S-parameters in the S-parameter matrix meet the passive characteristics of the circuit; the function generation module is used to set the extremum required to generate the rational number function of the S-parameter - the number of residual values and the systematic error; the equivalent circuit generation module is used to perform a vector fitting algorithm based on the number of extrema-residual values to generate a rational number function matrix of S-parameters; and simulate and synthesize an Hspice compatible matrix according to the rational number function matrix Equivalent Circuit.

另一習用電路設計模擬方法及其系統,如中華民國專利公告第TW-I620082號〝具數位輸出之溫度感測電路設計之行為模擬方法及其系統〞之發明專利,其亦揭示一種溫度感測電路設計之行為模擬方法。 Another conventional circuit design simulation method and system, such as the invention patent of the Republic of China Patent Publication No. TW-I620082 "Behavior Simulation Method and System for Design of Temperature Sensing Circuit with Digital Output", which also discloses a temperature sensing Behavioral simulation methods for circuit design.

承上,前述第TW-I620082號之該溫度感測電路設計之行為模擬方法包含:建構一溫度感測電路數學架構,而該溫度感測電路數學架構適用於一行為模擬軟體〔例如:Simulink〕之執行,且該溫度感測電路數學架構包含數個元件數學架構;於該溫度感測電路數學架構中選擇至少一指定元件數學架構;再選擇利用一進階模擬軟體〔例如:Hspice〕或一實測資料執行模擬計算該溫度感測電路數學架構之指定元件數學架構,以獲得一指定元件溫度模型;及該行為模擬軟體利用該指定元件溫度模型結合於該溫度感測電路數學架構執行行為模擬計算,以便快速獲得一初步模擬資料及其數位輸出。 Continuing from the above, the behavioral simulation method of the design of the temperature sensing circuit in the aforementioned No. TW-I620082 includes: constructing a mathematical structure of the temperature sensing circuit, and the mathematical structure of the temperature sensing circuit is suitable for a behavioral simulation software (eg Simulink) is executed, and the mathematical structure of the temperature sensing circuit includes a mathematical structure of several components; select at least one mathematical structure of a specified component in the mathematical structure of the temperature sensing circuit; and then select to use an advanced simulation software (for example: Hspice) or a Performing a simulation calculation on the measured data to obtain a specified element mathematical structure of the mathematical structure of the temperature sensing circuit to obtain a specified element temperature model; and the behavioral simulation software uses the specified element temperature model in combination with the temperature sensing circuit mathematical structure to perform a behavioral simulation calculation , in order to quickly obtain a preliminary simulation data and its digital output.

然而,前述中華民國專利公開第TW-201610733號、公開第TW-201145061號及公告第TW-I620082號之電路設計模擬方法未揭示如何進一步簡 化其模擬作業及減少其模擬時間,因此其必然存在簡化半導體電路設計模擬作業及減少模擬時間之需求。前述專利申請案僅為本發明技術背景之參考及說明目前技術發展狀態而已,其並非用以限制本發明之範圍。 However, the circuit design simulation methods of the aforementioned ROC Patent Publication No. TW-201610733, Publication No. TW-201145061, and Publication No. TW-I620082 do not disclose how to further simplify In order to simplify the simulation work and reduce the simulation time, there must be a need to simplify the simulation work of the semiconductor circuit design and reduce the simulation time. The aforementioned patent application is only for reference of the technical background of the present invention and to illustrate the current state of technological development, and is not intended to limit the scope of the present invention.

有鑑於此,本發明為了滿足上述技術問題及需求,其提供一種類比電路效能自動化分析系統及其方法,其提供至少一電腦輔助分析工具,並選擇輸入至少一目標類比電路;選擇輸入至少一電路拓撲,且該電路拓撲對應於該目標類比電路;選擇輸入至少一電路規格,而該電路規格對應於該目標類比電路,且判斷該目標類比電路之電路規格是否符合原訂條件;若未達該原訂條件時,則返回重新輸入至少一新電路規格;若達成該原訂條件時,則產生至少一已計算電路網表;將該已計算電路網表輸入至一模擬軟體進行模擬,並產生至少一模擬結果;判斷該模擬結果是否符合原訂規格;若未達該原訂規格時,則返回重新輸入至少一已調整電晶體規格至該電路網表;若未達該原訂規格時,則產生至少一已模擬網表,因此相對於習用電路設計模擬方法及其系統可達成類比電路效能自動化分析、簡化半導體電路設計模擬作業及減少模擬作業時間之目的。 In view of this, in order to meet the above-mentioned technical problems and needs, the present invention provides an analog circuit performance automatic analysis system and method thereof, which provides at least one computer-aided analysis tool, and selects and inputs at least one target analog circuit; selects and inputs at least one Circuit topology, and the circuit topology corresponds to the target analog circuit; select and input at least one circuit specification, and the circuit specification corresponds to the target analog circuit, and determine whether the circuit specification of the target analog circuit meets the original conditions; When the original condition is met, return to re-input at least one new circuit specification; if the original condition is met, generate at least one calculated circuit netlist; input the calculated circuit netlist into a simulation software for simulation, and Generate at least one simulation result; determine whether the simulation result meets the original specification; if it does not meet the original specification, return and re-enter at least one adjusted transistor specification into the circuit netlist; if it does not meet the original specification , then at least one simulated netlist is generated, so compared with the conventional circuit design simulation method and the system thereof, the purpose of automatic analysis of analog circuit performance, simplification of semiconductor circuit design simulation operation and reduction of simulation operation time can be achieved.

本發明之主要目的係提供一種類比電路效能自動化分析系統及其方法,其提供至少一電腦輔助分析工具,並選擇輸入至少一目標類比電路;選擇輸入至少一電路拓撲,且該電路拓撲對應於該目標類比電路;選擇輸入至少一電路規格,而該電路規格對應於該目標類比電路,且判斷該目標類比電路之電路規格是否符合原訂條件;若未達該原訂條件時,則返回重新輸入至少一新電路規格;若達成該原訂條件時,則產生至少一已計算電路網表;將 該已計算電路網表輸入至一模擬軟體進行模擬,並產生至少一模擬結果;判斷該模擬結果是否符合原訂規格;若未達該原訂規格時,則返回重新輸入至少一已調整電晶體規格至該電路網表;若未達該原訂規格時,則產生至少一已模擬網表,以便達成類比電路效能自動化分析、簡化半導體電路設計模擬作業及減少模擬作業時間之功效。 The main purpose of the present invention is to provide an analog circuit performance automatic analysis system and method thereof, which provide at least one computer-aided analysis tool, and select and input at least one target analog circuit; select and input at least one circuit topology, and the circuit topology corresponds to the target analog circuit; select to input at least one circuit specification, and the circuit specification corresponds to the target analog circuit, and judge whether the circuit specification of the target analog circuit meets the original condition; if the original condition is not met, return to the new Input at least one new circuit specification; if the original condition is met, at least one calculated circuit netlist will be generated; The calculated circuit netlist is input to a simulation software for simulation, and at least one simulation result is generated; it is judged whether the simulation result conforms to the original specification; if it does not meet the original specification, it returns to re-input at least one adjusted transistor The specification is added to the circuit netlist; if the original specification is not met, at least one simulated netlist is generated, so as to achieve the effects of automatic analysis of analog circuit performance, simplification of semiconductor circuit design simulation operations, and reduction of simulation operation time.

為了達成上述目的,本發明較佳實施例之類比電路效能自動化分析方法包含: In order to achieve the above-mentioned purpose, the method for automatic analysis of the performance of the analog circuit according to the preferred embodiment of the present invention includes:

提供至少一電腦輔助分析工具,並選擇輸入至少一目標類比電路; Provide at least one computer-aided analysis tool, and select to input at least one target analog circuit;

選擇輸入至少一電路拓撲,且該電路拓撲對應於該目標類比電路; selecting and inputting at least one circuit topology, and the circuit topology corresponds to the target analog circuit;

選擇輸入至少一電路規格,而該電路規格對應於該目標類比電路,且判斷該目標類比電路之電路規格是否符合原訂條件; Select and input at least one circuit specification, and the circuit specification corresponds to the target analog circuit, and determine whether the circuit specification of the target analog circuit meets the original condition;

若未達該原訂條件時,則返回重新輸入至少一新電路規格;或 If the original condition is not met, go back and re-enter at least one new circuit specification; or

若已達成該原訂條件時,則產生至少一已計算電路網表; If the original condition has been met, at least one calculated circuit netlist is generated;

將該已計算電路網表輸入至一模擬軟體進行模擬,並產生至少一模擬結果; inputting the calculated circuit netlist to a simulation software for simulation, and generating at least one simulation result;

判斷該模擬結果是否符合原訂規格;及 determine whether the simulation result conforms to the original specification; and

若未達該原訂規格時,則返回重新輸入至少一已調整電晶體規格至該電路網表;或 If the original specification is not met, go back and re-enter at least one adjusted transistor specification into the circuit netlist; or

若已達成該原訂規格時,則產生至少一已模擬網表。 If the original specification has been met, at least one simulated netlist is generated.

為了達成上述目的,本發明較佳實施例之類比電路效能自動化分析系統包含: In order to achieve the above-mentioned purpose, the analog circuit performance automatic analysis system of the preferred embodiment of the present invention includes:

一電腦輔助分析工具,其用以選擇輸入至少一 目標類比電路; A computer-aided analysis tool for selecting input at least one target analog circuit;

至少一電路拓撲,其選擇輸入至該電腦輔助分析工具,且該電路拓撲對應於該目標類比電路; at least one circuit topology that is selected for input to the computer-aided analysis tool, and the circuit topology corresponds to the target analog circuit;

至少一電路規格,其選擇輸入至該電腦輔助分析工具,而該電路規格對應於該目標類比電路,且判斷該目標類比電路之電路規格是否符合原訂條件;及 at least one circuit specification, which is selected and input to the computer-aided analysis tool, and the circuit specification corresponds to the target analog circuit, and it is judged whether the circuit specification of the target analog circuit meets the original conditions; and

一模擬軟體,其用以將至少一已計算電路網表輸入及進行模擬,並產生至少一模擬結果; a simulation software for inputting and simulating at least one calculated circuit netlist, and generating at least one simulation result;

其中判斷該目標類比電路之電路規格是否符合原訂條件時,若未達該原訂條件時,則返回重新輸入至少一新電路規格;或,若已達成該原訂條件時,則產生該已計算電路網表;及 When judging whether the circuit specification of the target analog circuit meets the original condition, if the original condition is not met, return to re-input at least one new circuit specification; or, if the original condition has been met, generate the Calculate the circuit netlist; and

其中若未達該原訂規格時,則返回重新輸入至少一已調整電晶體規格至該電路網表;或,若已達成該原訂規格時,則產生至少一已模擬網表。 If the original specification is not reached, return and re-enter at least one adjusted transistor specification into the circuit netlist; or, if the original specification has been achieved, generate at least one simulated netlist.

本發明較佳實施例之該類比電路可選自low-dropout regulator類比電路、folded-cascode amplifier類比電路、buck-converter類比電路、boost-converter類比電路或其它類比電路。 The analog circuit of the preferred embodiment of the present invention can be selected from a low-dropout regulator analog circuit, a folded-cascode amplifier analog circuit, a buck-converter analog circuit, a boost-converter analog circuit or other analog circuits.

本發明較佳實施例之該已計算電路網表由C程式語言或其它具類似模擬功能之程式語言進行計算。 The calculated circuit netlist of the preferred embodiment of the present invention is calculated by the C programming language or other programming language with similar analog functions.

本發明較佳實施例之該模擬軟體選自Hspice或其它具類似模擬功能之軟體。 The simulation software of the preferred embodiment of the present invention is selected from Hspice or other software with similar simulation functions.

本發明較佳實施例採用至少一工具命令語言〔TCL〕。 The preferred embodiment of the present invention employs at least one Tool Command Language [TCL].

S1‧‧‧第一步驟 S1‧‧‧First step

S2‧‧‧第二步驟 S2‧‧‧Second step

S3‧‧‧第三步驟 S3‧‧‧The third step

S4‧‧‧第四步驟 S4‧‧‧The fourth step

S5‧‧‧第五步驟 S5‧‧‧Step 5

S6‧‧‧第六步驟 S6‧‧‧Sixth step

S7‧‧‧第七步驟 S7‧‧‧Seventh step

第1圖:本發明較佳實施例之類比電路效能自動化分析方法之流程方塊示意圖。 Fig. 1 is a schematic block diagram of the flow chart of the method for automatic analysis of the performance of the analog circuit according to the preferred embodiment of the present invention.

第2圖:本發明較佳實施例採用類比電路效能自動化分析方法之流程示意圖。 Fig. 2 is a schematic flow chart of a method for automatically analyzing the performance of analog circuits according to a preferred embodiment of the present invention.

第3圖:本發明較佳實施例之類比電路效能自動化分析系統及其方法適用於模擬第一電路之電路示意圖。 Figure 3: A schematic diagram of a circuit for simulating a first circuit, the system for automatically analyzing the performance of an analogous circuit and the method thereof according to the preferred embodiment of the present invention.

第4圖:本發明較佳實施例之類比電路效能自動化分析系統及其方法適用於模擬第二電路之電路示意圖。 FIG. 4 : a schematic diagram of a circuit for simulating a second circuit by the analog circuit performance automatic analysis system and the method thereof according to the preferred embodiment of the present invention.

第5圖:本發明較佳實施例之類比電路效能自動化分析系統及其方法適用於模擬第三電路之電路示意圖。 Fig. 5: a schematic diagram of a circuit for simulating a third circuit, the system for automatically analyzing the performance of an analogous circuit and the method thereof according to the preferred embodiment of the present invention.

為了充分瞭解本發明,於下文將舉例較佳實施例並配合所附圖式作詳細說明,且其並非用以限定本發明。 In order to fully understand the present invention, preferred embodiments will be exemplified below and described in detail in conjunction with the accompanying drawings, which are not intended to limit the present invention.

本發明較佳實施例之類比電路效能自動化分析系統及其方法適合應用於各種類比電路效能自動化分析,例如:低壓降穩壓器之類比電路效能分析,類比低通濾波器之類比電路效能分析,放大器之類比電路效能分析或其它類比電路效能分析,但其並非用以限制本發明之應用範圍。 The analog circuit performance automatic analysis system and the method thereof according to the preferred embodiment of the present invention are suitable for automatic performance analysis of various analog circuits, such as: analog circuit performance analysis of low-dropout voltage regulators, analog circuit performance analysis of analog low-pass filters, The performance analysis of analog circuits such as amplifiers or the performance analysis of other analog circuits is not intended to limit the scope of application of the present invention.

第1圖揭示本發明較佳實施例之類比電路效能自動化分析方法之流程方塊示意圖;第2圖揭示本發明較佳實施例採用類比電路效能自動化分析方法之流程示意圖。請參照第1及2圖所示,本發明較佳實施例之類比電路效能自動化分析方法包含步驟S1:舉例而言,首先,在開始模擬作業時,以適當技術手段提供至少一電腦輔助分析工具〔computer-aided analysis tool〕,並以適當技術手段選擇輸入至少一目標類比電路〔target circuit〕。 FIG. 1 shows a block diagram of the flow chart of the method for automatically analyzing the performance of the analog circuit according to the preferred embodiment of the present invention; FIG. 2 shows the schematic flow chart of the method for automatically analyzing the performance of the analog circuit according to the preferred embodiment of the present invention. Referring to Figures 1 and 2, the method for automatically analyzing the performance of an analog circuit according to a preferred embodiment of the present invention includes step S1: For example, when starting the simulation operation, at least one computer-aided analysis tool is provided by appropriate technical means. [computer-aided analysis tool], and select and input at least one target analog circuit with appropriate technical means.

請再參照第1及2圖所示,該類比電路可選自low-dropout regulator類比電路、folded-cascode amplifier類比電路、buck-converter類比電路、boost-converter類比電路或其它類比電路。 Referring again to Figures 1 and 2, the analog circuit can be selected from a low-dropout regulator analog circuit, a folded-cascode amplifier analog circuit, a buck-converter analog circuit, a boost-converter analog circuit, or other analog circuits.

請再參照第1及2圖所示,本發明較佳實施例之類比電路效能自動化分析方法包含步驟S2:舉例而言,接著,以適當技術手段選擇輸入〔loading〕至少一電路拓撲〔topology of selected circuit〕,且該電路拓撲對應於該目標類比電路。 Referring again to Figures 1 and 2, the method for automatically analyzing the performance of analog circuits according to a preferred embodiment of the present invention includes step S2: for example, then, selecting input (loading) at least one circuit topology (topology of selected circuit], and the circuit topology corresponds to the target analog circuit.

請再參照第1及2圖所示,本發明較佳實施例之類比電路效能自動化分析方法包含步驟S3:舉例而言,接著,以適當技術手段選擇輸入至少一電路規格〔specification〕,而該電路規格對應於該目標類比電路,且判斷該目標類比電路之電路規格是否符合〔reachable〕原訂條件。 Referring to Figures 1 and 2 again, the method for automatically analyzing the performance of an analog circuit according to a preferred embodiment of the present invention includes step S3: for example, then, selecting and inputting at least one circuit specification by appropriate technical means, and the The circuit specification corresponds to the target analog circuit, and it is determined whether the circuit specification of the target analog circuit complies with the original condition of [reachable].

請再參照第1及2圖所示,本發明較佳實施例之類比電路效能自動化分析方法包含步驟S4:舉例而言,接著,若未達該原訂條件時,則返回重新輸入至少一新電路規格,如第2圖之上虛線框體右側標示No;或,若已達成該原訂條件時,則產生至少一已計算電路網表,如第2圖之上虛線框體中間標示Yes。 Referring to Figures 1 and 2 again, the method for automatically analyzing the performance of an analog circuit according to a preferred embodiment of the present invention includes step S4: for example, if the original condition is not met, return to re-enter at least one new The circuit specification, such as the right side of the dashed box in Figure 2, indicates No; or, if the original condition is met, at least one calculated circuit netlist will be generated, such as the middle of the dashed box in Figure 2 indicates Yes.

請再參照第1及2圖所示,舉例而言,本發明較佳實施例之該已計算電路網表或其相關電路網表〔circuit netlist〕由C程式語言或其它具類似模擬功能之程式語言進行適當計算。 Referring again to Figures 1 and 2, for example, the calculated circuit netlist or its related circuit netlist (circuit netlist) of the preferred embodiment of the present invention is written in C programming language or other programs with similar analog functions. Language is properly calculated.

請再參照第1及2圖所示,本發明較佳實施例之類比電路效能自動化分析方法包含步驟S5:舉例而言,接著,以適當技術手段將該已計算電路網表輸入至一模擬軟體進行模擬,並產生至少一模擬結果,如第2圖之下虛線框體所示。 Referring again to Figures 1 and 2, the method for automatically analyzing the performance of an analog circuit according to a preferred embodiment of the present invention includes step S5: for example, then, inputting the calculated circuit netlist to a simulation software by appropriate technical means The simulation is performed, and at least one simulation result is generated, as shown by the dashed box in the lower part of FIG. 2 .

請再參照第1及2圖所示,舉例而言,本發明較佳實施例之該模擬軟體選自Hspice或其它具類似模擬功能之軟體。 Referring again to Figures 1 and 2, for example, the simulation software in the preferred embodiment of the present invention is selected from Hspice or other software with similar simulation functions.

請再參照第1及2圖所示,本發明較佳實施例之類比電路效能自動化分析方法包含步驟S6:舉例而言,接著,判斷該模擬結果是否符合原訂規格,即所需規格〔required specification〕。 Referring to Figures 1 and 2 again, the method for automatically analyzing the performance of an analog circuit according to a preferred embodiment of the present invention includes step S6: for example, then, it is determined whether the simulation result complies with the original specification, that is, the required specification. specification].

請再參照第1及2圖所示,本發明較佳實施例之類比電路效能自動化分析方法包含步驟S7:舉例而言,接著,若未達該原訂規格時,則返回重新輸入至少一已調整電晶體規格至該電路網表,如第2圖之下虛線框體左側標示No;或,若已達成該原訂規格時,則產生至少一已模擬網表,如第2圖之下虛線框體中間標示Yes;最後,可選擇結束模擬作業。 Referring to Figures 1 and 2 again, the method for automatically analyzing the performance of an analog circuit according to a preferred embodiment of the present invention includes step S7: for example, if the original specification is not reached, then return to re-input at least one Adjust the transistor specifications to the circuit netlist, as indicated by No on the left side of the frame with the dotted line in Figure 2; or, if the original specification has been met, generate at least one simulated netlist, as shown by the dotted line in Figure 2 The middle of the box is marked with Yes; finally, you can choose to end the simulation job.

請再參照第1及2圖所示,本發明較佳實施例之類比電路效能自動化分析系統及其方法可採用至少一工具命令語言〔Tool Command Language,TCL〕,其用以呼叫C程式語言或其它具類似模擬功能之程式語言,或其用以呼叫Hspice或其它具類似模擬功能之軟體。 Referring again to Figures 1 and 2, the analog circuit performance automatic analysis system and method thereof according to the preferred embodiment of the present invention can use at least one tool command language (Tool Command Language, TCL), which is used to call C programming language or Other programming languages with similar simulation functions, or their use to call Hspice or other software with similar simulation functions.

第3圖揭示本發明較佳實施例之類比電路效能自動化分析系統及其方法適用於模擬第一電路之電路示意圖。請參照第3圖所示,本發明較佳實施例之類比電路效能自動化分析系統及其方法適用於模擬boost-converter類比電路。 FIG. 3 discloses a circuit schematic diagram of the analog circuit performance automatic analysis system and the method for simulating the first circuit according to the preferred embodiment of the present invention. Please refer to FIG. 3 , the analog circuit performance automatic analysis system and the method thereof according to the preferred embodiment of the present invention are suitable for simulating boost-converter analog circuits.

第4圖揭示本發明較佳實施例之類比電路效能自動化分析系統及其方法適用於模擬第二電路之電路示意圖。請參照第4圖所示,本發明較佳實施例之類比電路效能自動化分析系統及其方法適用於模擬buck-converter類比電路。 FIG. 4 discloses a circuit schematic diagram of the analog circuit performance automatic analysis system and the method thereof applicable to the simulation of the second circuit according to the preferred embodiment of the present invention. Referring to FIG. 4 , the analog circuit performance automatic analysis system and the method thereof according to the preferred embodiment of the present invention are suitable for simulating a buck-converter analog circuit.

第5圖揭示本發明較佳實施例之類比電路效能自動化分析系統及其方法適用於模擬第三電路之電路示意圖。請參照第5圖所示,本發明較佳實施例之類比電路效 能自動化分析系統及其方法適用於模擬low dropout類比電路。 FIG. 5 discloses a circuit schematic diagram of the analog circuit performance automatic analysis system and the method for simulating the third circuit according to the preferred embodiment of the present invention. Referring to FIG. 5, the analog circuit of the preferred embodiment of the present invention is effective An automated analysis system and method thereof are suitable for simulating low dropout analog circuits.

前述較佳實施例僅舉例說明本發明及其技術特徵,該實施例之技術仍可適當進行各種實質等效修飾及/或替換方式予以實施;因此,本發明之權利範圍須視後附申請專利範圍所界定之範圍為準。本案著作權限制使用於中華民國專利申請用途。 The aforementioned preferred embodiment is only an example of the present invention and its technical features, and the technology of this embodiment can still be implemented in various substantially equivalent modifications and/or alternative ways; therefore, the scope of the right of the present invention is subject to the appended patent application The scope defined by the scope shall prevail. The copyright in this case is restricted to be used for the purposes of the ROC patent application.

S1‧‧‧第一步驟 S1‧‧‧First step

S2‧‧‧第二步驟 S2‧‧‧Second step

S3‧‧‧第三步驟 S3‧‧‧The third step

S4‧‧‧第四步驟 S4‧‧‧The fourth step

S5‧‧‧第五步驟 S5‧‧‧Step 5

S6‧‧‧第六步驟 S6‧‧‧Sixth step

S7‧‧‧第七步驟 S7‧‧‧Seventh step

Claims (10)

一種類比電路效能自動化分析方法,其包含:提供至少一電腦輔助分析工具,並選擇輸入至少一目標類比電路;選擇輸入至少一電路拓撲,且該電路拓撲對應於該目標類比電路;選擇輸入至少一電路規格,而該電路規格對應於該目標類比電路,且判斷該目標類比電路之電路規格是否符合原訂條件;若未達該原訂條件時,則返回重新輸入至少一新電路規格;若已達成該原訂條件時,則產生至少一已計算電路網表;將該已計算電路網表輸入至一模擬軟體進行模擬,並產生至少一模擬結果;判斷該模擬結果是否符合原訂規格;若未達該原訂規格時,則返回重新輸入至少一已調整電晶體規格至該電路網表;及若已達成該原訂規格時,則產生至少一已模擬網表。 An automatic analysis method for analog circuit performance, comprising: providing at least one computer-aided analysis tool, and selecting and inputting at least one target analog circuit; selecting and inputting at least one circuit topology, and the circuit topology corresponds to the target analog circuit; selecting and inputting at least one A circuit specification, and the circuit specification corresponds to the target analog circuit, and it is judged whether the circuit specification of the target analog circuit meets the original condition; if the original condition is not met, return and re-enter at least one new circuit specification; if When the original condition has been met, generate at least one calculated circuit netlist; input the calculated circuit netlist to a simulation software for simulation, and generate at least one simulation result; determine whether the simulation result conforms to the original specification; If the original specification is not reached, return to re-input at least one adjusted transistor specification into the circuit netlist; and if the original specification is achieved, generate at least one simulated netlist. 依申請專利範圍第1項所述之類比電路效能自動化分析方法,其中該目標類比電路選自low-dropout regulator類比電路、folded-cascode amplifier類比電路、buck-converter類比電路或boost-converter類比電路。 According to the automatic analysis method of analog circuit performance as described in item 1 of the claimed scope, the target analog circuit is selected from a low-dropout regulator analog circuit, a folded-cascode amplifier analog circuit, a buck-converter analog circuit or a boost-converter analog circuit. 依申請專利範圍第1項所述之類比電路效能自動化分析方法,其中該已計算電路網表由C程式語言或其它具類似模擬功能之程式語言進行計算。 According to the automatic analysis method of analog circuit performance described in item 1 of the scope of the patent application, the calculated circuit netlist is calculated by C programming language or other programming languages with similar analog functions. 依申請專利範圍第1項所述之類比電路效能自動化分析方法,其中該模擬軟體選自Hspice或其它具類似模擬功能之軟體。 According to the automatic analysis method of analog circuit performance described in item 1 of the scope of application, wherein the simulation software is selected from Hspice or other software with similar simulation functions. 依申請專利範圍第1項所述之類比電路效能自動化分 析方法,其中採用至少一工具命令語言。 According to the automatic analysis of analog circuit performance described in item 1 of the scope of application analysis method, wherein at least one tool command language is used. 一種類比電路效能自動化分析系統,其包含:一電腦輔助分析工具,其用以選擇輸入至少一目標類比電路;至少一電路拓撲,其選擇輸入至該電腦輔助分析工具,且該電路拓撲對應於該目標類比電路;至少一電路規格,其選擇輸入至該電腦輔助分析工具,而該電路規格對應於該目標類比電路,且判斷該目標類比電路之電路規格是否符合原訂條件;及一模擬軟體,其用以將至少一已計算電路網表輸入及進行模擬,並產生至少一模擬結果;其中判斷該目標類比電路之電路規格是否符合原訂條件時,若未達該原訂條件時,則返回重新輸入至少一新電路規格;或,若已達成該原訂條件時,則產生該已計算電路網表;及其中若未達該原訂規格時,則返回重新輸入至少一已調整電晶體規格至該電路網表;或,若已達成該原訂規格時,則產生至少一已模擬網表。 An analog circuit performance automatic analysis system, which includes: a computer-aided analysis tool, which is used to select and input at least one target analog circuit; at least one circuit topology, which is selected and input to the computer-aided analysis tool, and the circuit topology corresponds to the target analog circuit; at least one circuit specification, which is selected and input to the computer-aided analysis tool, and the circuit specification corresponds to the target analog circuit, and it is judged whether the circuit specification of the target analog circuit meets the original conditions; and a simulation software , which is used to input and simulate at least one calculated circuit netlist, and generate at least one simulation result; when judging whether the circuit specification of the target analog circuit meets the original condition, if it does not meet the original condition, then Return to re-enter at least one new circuit specification; or, if the original condition is met, generate the calculated circuit netlist; and if the original specification is not met, return to re-enter at least one adjusted transistor specification to the circuit netlist; or, if the original specification has been met, generate at least one simulated netlist. 依申請專利範圍第6項所述之類比電路效能自動化分析系統,其中該目標類比電路選自low-dropout regulator類比電路、folded-cascode amplifier類比電路、buck-converter類比電路或boost-converter類比電路。 According to the automatic analysis system of analog circuit performance described in item 6 of the patent application scope, the target analog circuit is selected from a low-dropout regulator analog circuit, a folded-cascode amplifier analog circuit, a buck-converter analog circuit or a boost-converter analog circuit. 依申請專利範圍第6項所述之類比電路效能自動化分析系統,其中該已計算電路網表由C程式語言或其它具類似模擬功能之程式語言進行計算。 According to the automatic analysis system of analog circuit performance as described in item 6 of the scope of the patent application, the calculated circuit netlist is calculated by C programming language or other programming languages with similar analog functions. 依申請專利範圍第6項所述之類比電路效能自動化分析系統,其中該模擬軟體選自Hspice或其它具類似模擬功能之軟體。 According to the automatic analysis system for analog circuit performance described in item 6 of the patent application scope, the simulation software is selected from Hspice or other software with similar simulation functions. 依申請專利範圍第6項所述之類比電路效能自動化分析系統,其中採用至少一工具命令語言〔TCL〕。 According to the automatic analysis system of analog circuit performance as described in item 6 of the scope of the patent application, at least one tool command language (TCL) is used.
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TWI369620B (en) * 2008-07-30 2012-08-01 Faraday Tech Corp Method and technique for analogue circuit synthesis
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