TWI759833B - Burn-in apparatus with functional testing for processor - Google Patents

Abstract

The present invention provides a processor burn-in device with functional testing, comprising: a burn-in carrier board with a plurality of test slots and a sub-system module, the sub-system module is used for receiving a signal, and the signal is associated with a test parameter setting; and a signal test board coupled to the burn-in carrier board to form a signal connection with a part of the burn-in carrier board of the plurality of test slots and the subsystem module; wherein the signal According to the signal, the test board controls the part of the burn-in carrier board of the plurality of test slots that are communicatively connected with the signal test board to perform a test procedure.

Description

Processor burn-in device with functional test

The present invention relates to a device for burn-in carrier board, in particular to a burn-in device that can be installed on the burn-in carrier board and can control the input high-frequency signal of the burn-in carrier board.

In the semiconductor or PCB industry, burn-in is a process of testing wafers or chips. Multiple wafers or chips will be correspondingly installed on the test seat on the burn-in board to test various parameters. Such as temperature, stress, frequency, etc., to detect any failures in subsequent processes due to design, material, process or manufacturing defects.

The burn-in boards used by various manufacturers today are customized according to the needs of customers' products. Therefore, each time there are different product burn-in test requirements, it is necessary to re-manufacture the burn-in boards with different test conditions. Moreover, according to different test items or parameters, the wafers or chips must be separately configured on the corresponding burn-in boards for testing, so the overall testing process is time-consuming. How to effectively solve the above problems and reduce the manufacturing cost of the burn-in board is the subject to be solved by the present invention when a customer needs to test a wide range of frequencies for a product within a certain period of time.

FIG. 7 illustrates a conventional burn-in carrier board 710, which has a signal interface 140 and a power interface 150, which respectively receive test signals (eg, 10MHz signals) for burn-in testing and power signals for the entire burn-in board operation. . The burn-in carrier board 710 is further provided with a plurality of test sockets 120 in an array, and each socket 120 is used for accommodating a device under test (DUT), such as a chip. The signal interface 140 and the power interface 150 are a combination of various connectors and electronic components, and are configured to transmit signals to each test socket 120 through specific conductive paths. However, this configuration suffers from certain deficiencies that affect test consistency. The burn-in board 710 usually has a considerable area, and the signal interface 140 and the power interface 150 are usually arranged on the side of the burn-in board 710 . The position of the slot 120 relative to the burn-in carrier 710 is determined. Therefore, the time for the same signal to reach different test sockets 120 may be inconsistent, and a longer conduction path may cause signal loss, thereby affecting the test quality. Furthermore, a single burn-in carrier in this configuration can only provide a single test for all the devices under test at the same time, so that other test schedules that can improve test efficiency are limited and cannot be applied.

Therefore, it is necessary to develop an improved burn-in carrier configuration with the goal of reducing signal loss and overcoming test scheduling limitations.

In order to solve the above problem, the present invention utilizes a subsystem module configured on the burn-in carrier board and a signal test board that can be installed on the burn-in carrier board, so that the signal test board can use the subsystem module. Groups are used to control different parameters of the burn-in carrier board, so that the DUT can be tested with a large number of different parameters.

In order to achieve the above object, the present invention provides a processor burn-in device with functional testing, comprising: a burn-in carrier board with a plurality of test slots and a sub-system module, the sub-system module is used for receiving a signal, the signal is associated with a test parameter setting; and a signal test board coupled to the burn-in carrier board to form a signal connection with a part of the plurality of test slots and the subsystem module; Wherein the signal test board controls the part of the plurality of test sockets which are in communication with the signal test board to perform a test procedure according to the signal.

In order to achieve the above-mentioned purpose, the present invention further provides a signal test board with function test installed on a burn-in carrier board, comprising: a signal test board, coupled to the burn-in carrier board, so that the signal is connected to the The burn-in carrier board; wherein the signal test board has a subsystem module for receiving a signal, the signal is associated with a test parameter setting, and the signal test board controls the burn-in carrier board to perform a test procedure according to the signal.

The above-mentioned processor burn-in device with function test is further electrically connected to a test device, the test device provides a control signal to the signal test board, and the control signal is used to trigger the signal test board to execute the plurality of The portion of the test socket is subjected to a test procedure.

The above-mentioned processor burn-in device with function test and signal test board, wherein each of the subsystem module and the signal test board includes a field programmable logic gate array, wherein the field programmable logic gate array is provided with a Burn program.

The above-mentioned processor burn-in device and signal test board with function test, wherein the signal test board updates the burn-in program of the field programmable logic gate array according to the signal of the subsystem module.

The above-mentioned processor burn-in device with function test and signal test board, wherein the signal test board further includes at least one connector, and the at least one connector is configured to be communicatively coupled to the burn-in carrier board.

In the above processor signal test board with function test, the signal test board is further provided with a plurality of objects to be tested, and the signal test board can test the plurality of objects to be tested.

Various embodiments of the invention are described hereinafter with reference to schematic illustrations of idealized embodiments of the invention. The shapes and arrangements in these illustrations may vary due to manufacturing techniques, designs and/or tolerances. Therefore, the embodiments described herein should not be construed as limiting the invention to any particular element or shape, which is to include any variation in shape caused by manufacture.

In order to facilitate the understanding of the present invention, the configuration of the processor burn-in device with function test of the present invention is briefly described first. As shown in FIG. 1 , the processor burn-in device with function test 100 mainly has a burn-in carrier board 110 . The burn-in carrier board 110 is configured with a plurality of test sockets 120 (Socket), and each test socket 120 accommodates an object to be tested for testing. The burn-in carrier board 110 is also configured with a signal interface 140 and a power interface 150 for respectively receiving test signals for burn-in testing and supplying power signals for operating the burn-in carrier board 110 . The configuration of the burn-in test board described so far is a common configuration method for those skilled in the art. Compared with the above-mentioned burn-in test board, the present invention utilizes a signal test board 200 that can be detachably disposed on the burn-in carrier board 110 . , and connected to an external signal control system 300 , so that the burn-in carrier board 110 can control different parameters of the signal test board 200 to perform burn-in test through the input settings of the signal control system 300 . In one example, the signal test board 200 is a circuit configuration for providing high frequency test signals. The specific connection method of the signal test board 200 of the present invention will be described later. In addition, for the convenience of understanding, this paper only uses frequency parameters for description, so the signal test board 200 is not limited to controlling only the frequency, but also refers to other parameters to be tested such as temperature and stress, and also includes a plurality of parameters to be tested that can be controlled.

The following describes the manner in which the signal test board 200 is disposed on the burn-in carrier board 110 . Referring to the bottom view and side view of the connector of the processor burn-in device with functional test in FIGS. 2a and 2b, the signal test board 200 has a communication interface for communicating with the control system 300 and a circuit assembly for outputting test signals , which can be distributed on the top surface of the signal test board 200 . At least one connector 210 is fixed on the bottom surface of the signal test board 200 (ie, the side facing the burn-in carrier board 110 ), and the connector or socket (not shown in the figure) corresponding to the connector 210 is provided in FIG. 1 A top surface of the burn-in carrier board 110 (ie, the surface shared with the test socket 120 ) is, for example, a board-to-board connector. The choice of the setting method is determined by the circuit configuration of the burn-in carrier board 110 . The configuration of the connector 210 enables the signal test board 200 to be disposed on the burn-in carrier board 110 in the form of a mezzanine board to form electrical connection and signal connection. With the arrangement of the interlayer board, the test socket 120 can pass between the burn-in carrier board 110 and the signal test board 200 . Although only one signal test board 200 is illustrated in the figure, a larger number of signal test boards 200 are also possible. Each signal test board 200 is connected to a specific test slot 120 for testing part of the device under test. The configuration of the connector 210 may depend on how to form an electrical connection and a signal connection with the burn-in carrier board 110. Therefore, the configuration as shown in FIGS. 2a and 2b is not limited, but a single connector 210 disposed in the middle can be used. , and also does not limit the arrangement direction of the connector 210 .

The following is a detailed description of the processor burn-in device 100 with function test of the present invention. Please refer to FIG. 3 and FIG. 4 at the same time. FIG. 3 is a schematic diagram of the configuration of the processor burn-in device with function test 100 of the present invention. , and FIG. 4 is a schematic diagram of the configuration of the processor burn-in device with functional testing of the present invention in the burn-in test machine. The burn-in carrier board 110 is further provided with a subsystem module 130 , and the signal is connected between the signal test board 200 and the signal control system 300 , and the signal test board 200 is used to integrate the The data of the signal test board 200 is sent back to the signal control system 300, wherein the signal test board 200 contains a field programmable gate array (Field Programmable Gate Array, FPGA), which is mainly used to generate the high voltage required for testing. frequency program. The signal control system 300 is an external computer device, and transmits signals with the subsystem module 130 through a common interface, such as using Ethernet. In addition, the processor burn-in device 100 with functional test is connected to the test machine 400 outside the test chamber 500 of FIG. 4 . Referring to FIG. 3 , the test machine 400 provides a signal through the signal interface 140 of the burn-in carrier board 110 , and the signal is transmitted to the signal test board 200 . In more detail, the narrower control signal path P1 in FIG. 3 is for the test equipment 400 to send/receive control signals to the FPGA in each signal test board 200 . The test machine 400 transmits a 10MHz signal to trigger the signal test board 200 to perform a burn-in procedure for each burn-in module. In addition, various burn-in modules (such as high temperature modules and high-voltage modules) installed on the burn-in carrier board 110 can be changed. The test board 200 controls each burn-in module by the signal test board 200 , and the test parameter setting signal (the thicker test parameter setting signal path P2 in FIG. 3 ) is controlled through the graphic user interface (GUI) on the signal control system 300 ) to set the subsystem module 130, the subsystem module 130 can make the following function settings on each signal test board 200, (1) update the signal test board 200 to test the high frequency program settings, (2) update the signal test board 200 FPGA firmware. The test machine 400 has a power supply 410 , and the required power is provided to the burn-in board 110 through the power interface 150 of the burn-in board 110 .

The configuration between the signal test board 200 and the DUT D will be described below. Please refer to FIG. 5 , which is a schematic diagram of the configuration of the burn-in carrier board and the DUT of the processor burn-in device with functional testing of the present invention, wherein M1 To M3 are different illustrations of the relationship between the signal test board 200 and the DUT D in the slot. The embodiment of M1 is the configuration described above in FIGS. 2a and 2b, using a signal test board 200 to be fixed on the burn-in carrier board 110 and signally connected to a plurality of DUTs D, so that a signal test board 200 can test a plurality of DUTs D Perform a burn-in test. In the M2 embodiment, the DUT D and the signal test board 200 are disposed on the same carrier board, and then mounted on the burn-in carrier board 110 together to perform the burn-in test. The M3 embodiment is that a signal test board 200 is clamped to a test object D (the test object D is set in the test slot 120 and is located between the signal test board 200 and the burn-in carrier board 110 , so the M3 embodiment The DUT D is not shown to perform a burn-in test, so it can be known that M3 can be connected to a signal test board 200 customized for each DUT D. According to the above, the signal test board 200 can be customized on the burn-in carrier board 110 in different sizes and ways according to the needs of customers, without redesigning the burn-in carrier board 110, so as to reduce the manufacturing cost and Wiring is complicated.

Next, please refer to the configuration diagram of the burn-in carrier board of the processor burn-in device with functional test of the present invention in FIG. 6 . The following describes in detail how the connector 210 of the signal test board 200 is disposed on the burn-in carrier board 110 . This embodiment is configured according to the above-mentioned M1 method. In the figure, the area showing the DUT is the DUT disposed in the test slot 120 (hereinafter referred to as the DUT), and the area showing the signal test board 200 is the DUT. The signal test board 200 has been installed on the test slot 120, so each signal test board 200 in FIG. 6 will simultaneously control the frequency of two DUTs, such as the signal test board of GROUP#0 shown in FIG. 6 200 adjust the frequency of DUT#0 and DUT#8 at the same time to test. The user operates the signal control system 300 to transmit a signal of parameter setting to the subsystem module 130, and the subsystem module 130 transmits a set parameter signal to the individual signal test board 200 according to the signal, and each signal is tested. The FPGA of the board 200 will update the burn-in program according to the set parameters, so that each signal test board 200 can control its corresponding DUT to perform the burn-in test. When the burn-in test is in progress, the individual signal test boards 200 will return the current test information to the subsystem module 130, and the subsystem module 130 collects the returned test signal uniformly and transmits it to the subsystem module 130. The signal control system 300 provides the user with the real-time test situation of the individual DUT under test, so that the user can adjust the individual test parameters in time according to the test situation.

According to the above, those with ordinary knowledge in the technical field can apply the teachings of the present invention to various burn-in test items. The following is a detailed description of the various burn-in test items applicable to the present invention: /Short TEST) is used to check whether the signal pins used for testing are in contact with the wafer or chip, and to detect whether the signal pins are short-circuited relative to the normal signal pins. (2) DC Parametric Test, to test whether the DC parameters of the wafer or chip meet the designed specifications, and its parameters can be such as: Output Drive Current, Current Leakage, Power ( Power Current), Threshold Level, etc. (3) Functional Test, which is used to check whether the wafer or chip can correctly operate its expected logic function, and can create a test vector or truth table to detect faults in the wafer or chip. (4) AC Parametric Test, to ensure whether the wafer or chip can meet its timing specification, its parameters can be such as: propagation delay (Propagation delay), setup time and hold time (setup time and hold time) , Access time, Refresh time, Raise/Fall times, etc. (5) Data binning, wafers or wafers are classified according to the above test results. (6) Pattern programming, editing the microcode of the Logic Algorithm Test Vector Generator (ALPG) to handle the test pattern. (7) Socket programming, edit parallel test settings. The above description sequence and test content are not limited to actual various burn-in tests, so the configuration of the present invention can be applied to other undisclosed burn-in test items.

To sum up, compared with the prior art, the main advantages of the processor burn-in device with functional test of the present invention are: (1) Customers do not need to purchase a new high frequency or have more burn-in devices at present. Under the test equipment that tests the function of the project, it can continue to be used in the original burn-in device and at the same time meet the ever-changing test technology of future semiconductors, so as to prolong the service life of the burn-in device. In addition, it can also meet the high-frequency test requirements of the DUT and the increase of test items. For example, the signal test board provides a higher frequency test signal to test the DUT, replacing the 10MHz signal provided by the original test equipment. (2) On the firmware, the sequence of steps in the traditional burn-in process (for example, step 1 is high temperature test, step 2 is low temperature test, step 3 is the sequence of full-speed test), using methods such as FPGA, etc. The machine flow is modified and integrated to perform the above three steps or other steps synchronously, and various burn-in test items such as paragraph [0028] can be integrated to shorten the test time. According to the above, the burn-in device of the present invention can improve the test efficiency, provide a higher number/density of test signals, optimize the PCB wiring, flexibly adjust the setting method, flexibly control the setting parameters, and can adapt to novel or new test technologies, and finally can Achieving a reduction in the testing cost of the DUT.

100 with functional test Processor burn-in device 110 Burn-in carrier board 120 test slots 130 Subsystem modules 140 Signal Interface 150 Power Interface 200 signal test board 210 Connector 300 Signal Control System 400 test equipment 410 Power 500 chambers 710 Burn-in carrier board DUT/D DUT M1~M3 configuration mode P1 Control signal path P2 Test parameter setting signal

FIG. 1 is a schematic diagram of the burn-in device of the present invention.

FIG. 2a shows a top view of the burn-in device and the connector of the present invention.

Figure 2b shows a side view of the burn-in device and connector of the present invention.

FIG. 3 shows a schematic diagram of the signal path of the present invention.

FIG. 4 is a schematic diagram showing the configuration of the burn-in device of the present invention on a burn-in test machine.

FIG. 5 is a schematic diagram showing the configuration of the signal test board and the DUT of the present invention.

FIG. 6 shows the configuration diagram of the burn-in carrier board of the present invention.

FIG. 7 shows a block diagram of a conventional burn-in device.

100 Processor burn-in device with functional test 110 Burn-in carrier board 120 test slots 140 Signal Interface 150 Power Interface 200 signal test board 300 Signal Control System

Claims (7)

A processor burn-in device with function test, comprising: a burn-in carrier board with a plurality of test slots and a sub-system module, the sub-system module is used for receiving a signal, the signal is related to a test parameter setting; and at least one signal test board, coupled to the burn-in carrier board, to form a signal connection with a part of the plurality of test slots and the subsystem module; wherein the signal test board according to the signal, Control the portion of the plurality of test slots communicatively connected with the signal test board to perform a test procedure. The processor burn-in device with functional test as described in claim 1 is further electrically connected to a test device, the test device provides a control signal to the signal test board, and the control signal is used to trigger the signal test board to execute the test. Wait for the portion of the plurality of test slots to perform a test procedure. The processor burn-in device with function test as claimed in claim 1, wherein the subsystem module and the signal test board each comprise a field programmable logic gate array, wherein the field programmable logic gate array is provided with a burn-in machine program. The processor burn-in device with function test as claimed in claim 3, wherein the signal test board updates the burn-in program of the field programmable logic gate array according to the signal of the subsystem module. The processor burn-in device with function test as claimed in claim 1, wherein the signal test board further comprises at least one connector, and the at least one connector is configured to be communicatively coupled to the burn-in carrier board. A signal test board with function test installed on a burn-in carrier board with a plurality of test slots, comprising: at least one signal test board, coupled to the burn-in carrier board, so that the signal is connected to the burn-in machine A part of the plurality of test slots of the carrier board; wherein the signal test board has a subsystem module for receiving a signal, the signal is associated with a test parameter setting, and the signal test board controls the burn-in according to the signal A portion of the plurality of test sockets of the carrier board is subjected to a test procedure. The processor burn-in device with functional testing according to claim 6, wherein the signal test board is further provided with a plurality of objects to be tested, and the signal test board can test the plurality of objects to be tested.

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