TWI759632B - Display panel and display panel menufacturing method - Google Patents

Abstract

A display panel includes a substrate, a film layer, a seed pattern layer, a first conductive structure, a pattern film and a second conductive structure. The film layer with a plurality of openings is disposed on a first surface of the substrate. A plurality of blind holes penetrating the substrate respectively communicate with the openings. The seed pattern layer disposed on the film layer fills the openings. The first conductive structure disposed on the seed pattern layer fills the openings. The blind holes are overlapped with the first conductive structure. The pattern film overlaps the second surface of the substrate and the blind holes. The second conductive structure disposed on the pattern film fills the blind holes so as to be electrically connected to the first conductive structure or the seed pattern layer, which serves as a stopper layer of the second conductive structure.

Description

Display panel and display panel manufacturing method

The present invention relates to an electronic device and a manufacturing method of the electronic device, and more particularly, to a display panel and a manufacturing method of the display panel.

In general, a display panel may have a display area and a non-display area surrounding the display area. The non-display area may include a wiring area for wiring and a driving circuit area for driving circuits used to drive active elements in the display panel, such as source driver circuits or gate driver circuits. Therefore, the non-display area of the display panel cannot be used. Display images and affect the appearance design of the display panel.

Specifically, when the area of the non-display area is reduced, the display area occupies a larger area of the display panel, and accordingly more pixels are set, so that the resolution of the display panel can be improved. When the area of the non-display area is reduced, the border of the display area is closer to the outer edge of the display panel, so that a narrow border design can be realized. For a large-scale display panel formed by splicing, the non-display area forms a splicing gap where the image cannot be displayed, resulting in discontinuity of the overall image and affecting the display quality. Therefore, the existing display panels still need to be improved.

In one embodiment of the present invention, a display panel is provided, the structure of which is helpful for reducing the size of the display panel and improving the yield.

An embodiment of the present invention provides a display panel, which includes a substrate, a film layer, a seed pattern layer, a first conduction structure, a pattern coating, and a second conduction structure. The substrate has a first surface and a second surface. The film layer is disposed above the first surface of the substrate, the film layer has a plurality of openings, and a plurality of blind holes penetrating the substrate are respectively connected to the openings. The seed crystal pattern layer is disposed above the film layer, and the seed crystal pattern layer fills the opening. The first conduction structure is disposed above the seed pattern layer, the first conduction structure fills the opening, and the blind hole overlaps the first conduction structure. The pattern coating film overlaps the second surface of the substrate and the blind hole. The second conducting structure is disposed above the pattern coating film, and the second conducting structure fills the blind hole to be electrically connected to the first conducting structure.

An embodiment of the present invention provides a method for fabricating a display panel, including forming a film layer over a first surface of a substrate, forming a seed layer over the film layer, forming a first conduction structure over the seed layer, Forming a plurality of blind holes, forming a surface treatment film, forming a second conduction structure over the surface treatment film, and patterning the seed layer and the surface treatment film to form a seed pattern layer and a pattern film. The membrane layer has a plurality of openings. A seed layer fills the opening. The first conduction structure fills the opening. The blind holes penetrate through the substrate and are respectively communicated with the openings. The blind hole overlaps the first conduction structure. The surface treatment coating covers a second surface of the substrate and the blind holes. The second conductive structure is filled in the blind hole to be electrically connected to the first conductive structure.

In the display panel of the embodiment of the present invention, the first conduction structure can be The blind holes passing through the substrate are coupled to the second conductive structure, so that the elements located on the upper surface of the substrate can be coupled to the elements located on the lower surface of the substrate. In this way, size miniaturization can be achieved. The first conduction structure and the support layer of the display panel are formed before the blind holes, so the first conduction structure and the support layer can improve the structural strength of the substrate, which is beneficial to the drilling of the blind holes, and can improve the yield. In addition, since the supporting layer and the substrate cover the elements and film layers in the display area on the first surface of the substrate, subsequent processes can avoid damaging the elements and film layers in the display area, thereby improving yield.

In order to make the above-mentioned features and advantages of the present invention more obvious and easy to understand, the following embodiments are given and described in detail with the accompanying drawings as follows.

10, 10': Display panel

100, 1700: substrate

100B: Second surface

100S: Carrier substrate

100T: first surface

110: pixel array structure layer

111~115: film layer

116: Connect the conductor layer

220: seed layer

220N: Seed pattern layer

330: First photoresist pattern

330P: The first cylinder

410: Alignment mark

640S1~640S4: The first conduction structure

770: Support Layer

920: Surface treatment film

920N: Pattern Lamination

1030: Second photoresist pattern

1030P: Second cylinder

1140S1~1140S3: Second conduction structure

1140T: Top surface

1140B: Bottom surface

1301: The first conductor layer

1302: Second Conductor Layer

1601: First masking layer

1602: Second masking layer

AA: display area

BR1~BR3: The second groove

CP1: Conductor Pattern

d1, d2, a1: column diameter

D1: Drain pattern

DD1: Dimensions

G1: Gate pattern

HL1~HL3: Contact holes

LN1: Lighting unit

NAA: non-display area

PG1, PG2: opening

S1: source pattern

SE1: Semiconductor layer

T1: Active element

TH1, TH1', TH2: Thickness

TR1~TR4: The first groove

V1, V2, V1', V2': blind vias

X, Y, Z: direction

1A to FIG. 17 are schematic diagrams of a manufacturing process of a partial area of a display panel according to an embodiment of the present invention in sequence.

18 is a schematic cross-sectional view of a partial region of a display panel according to another embodiment of the present invention.

Directional terms mentioned in the embodiments, such as "up", "down", "front", "rear", "left", "right", etc., only refer to the directions of the drawings. Accordingly, the directional terms used are intended to illustrate rather than limit the present invention. In the accompanying drawings, various figures depict the generality of the methods, structures and/or materials used in particular exemplary embodiments sexual characteristics. These drawings, however, should not be construed to define or limit the scope or nature of the scope or nature encompassed by these exemplary embodiments. For example, the relative sizes, thicknesses and positions of various layers, regions and/or structures may be reduced or exaggerated for clarity.

In the embodiments, the same or similar elements will be given the same or similar reference numerals, and repeated descriptions thereof will be omitted. In addition, the features of the different exemplary embodiments may be combined with each other without conflict, and simple equivalent changes and modifications made in accordance with the present specification or the scope of the claims are still within the scope of the present patent. In addition, terms such as "first" and "second" mentioned in this specification or the scope of the patent application are only used to name discrete elements or to distinguish different embodiments or ranges, and are not used to limit the number of elements. The upper limit or the lower limit is not intended to limit the manufacturing order or the arrangement order of the elements.

1A to FIG. 17 are schematic diagrams of a manufacturing process of a partial area of a display panel 10 according to an embodiment of the present invention, wherein, FIG. 1A , FIG. 2 , FIG. 3 , FIGS. 5 to 17 are schematic cross-sectional views, and FIG. 1B is a 1A is a schematic top view of the display panel 10 in a manufacturing stage, and FIG. 4 is a top schematic view of the display panel 10 in another manufacturing stage.

Referring to FIGS. 1A and 1B , in this embodiment, a carrier substrate 100S is provided first, and then a substrate 100 is provided on the carrier substrate 100S. In some embodiments, the setting of the carrier substrate 100S may also be omitted, and the substrate 100 may be directly provided. The substrate 100 is suitable for carrying other components, and may have a first surface 100T and a second surface 100B opposite to each other, and the normal directions of the first surface 100T and the second surface 100B of the substrate 100 may be parallel to the direction Z. In some embodiments, the substrate 100 It can be a flexible substrate, for example, a flexible substrate such as a polyimide (Polyimide, PI) substrate; in other embodiments, the substrate 100 can also be a rigid substrate. In some embodiments, the carrier substrate 100S may be a rigid substrate, such as a glass substrate or a plastic-steel substrate, to provide a smooth surface. In some embodiments, as shown in FIG. 1B , the size of the carrier substrate 100S may be larger than that of the substrate 100 , and the substrate 100 may be divided into a display area AA and a non-display area NAA around the display area AA.

As shown in FIG. 1A , after that, a pixel array structure layer 110 is formed on the first surface 100T of the substrate 100 . In some embodiments, the pixel array structure layer 110 is located in the display area AA, but not limited thereto. The pixel array structure layer 110 may include film layers 111 - 115 , an active element T1 , a conductor pattern CP1 and a connection conductor layer 116 . The active element T1 may include a semiconductor layer SE1, a source pattern S1, a drain pattern D1 and a gate pattern G1. In some embodiments, the formation process of the pixel array structure layer 110 may include sequentially forming the film layer 111 , the semiconductor layer SE1 , the film layer 112 , the gate pattern G1 and the film layer 113 , and then forming the source electrode together or sequentially The pattern S1 , the drain pattern D1 and the conductor pattern CP1 are then sequentially formed with the film layers 114 , 115 and the connection conductor layer 116 , but not limited to this. In some embodiments, the formation method of the pixel array structure layer 110 may involve a physical vapor deposition method or a chemical vapor deposition method; in some embodiments, the formation method of the pixel array structure layer 110 may involve a patterning process. In addition, the number of the film layers or elements of the present invention is not limited thereto, and can be appropriately adjusted according to different design considerations, and the film layers or elements may be a single-layer structure or a multi-layer stacked composite structure.

The film layer 111 is disposed on the substrate 100, which can be a buffer layer. The material constituting the buffer layer can usually be an insulating material, and can be composed of inorganic materials. Inorganic thin films. The film layer 112 is disposed on the film layer 111 , which can be a gate insulating layer (GI), and the material of the gate insulating layer is, for example, silicon oxide, silicon nitride or other insulating materials. The film layer 113 is disposed on the film layer 112 , which may be an inter-layer dielectric (ILD), and the material of the inter-layer dielectric layer may include inorganic materials, organic materials, or a combination thereof.

The film layer 114 is disposed on the film layer 113 , which may be a planarization layer (PL), and the materials constituting the planarization layer may include various suitable organic materials. The film layer 115 is disposed on the film layer 114, and its material can include various suitable inorganic materials to improve the bonding degree with the subsequent conductor material or metal material. The film layer 114 has a plurality of openings PG1 and PG2 to expose the film layer 111 , and the film layer 114 has a plurality of contact holes HL1 to HL3 to expose the conductor pattern CP1 , the source electrode pattern S1 and the drain electrode pattern D1 . The material used to form the film layer 115 fills the openings PG1, PG2 and the contact holes HL1-HL3, but does not fill the openings PG1, PG2 and the contact holes HL1-HL3, that is to say, part of the film layer 115 is located in the openings PG1, PG2 and contact holes HL1~HL3. In some embodiments, the sidewalls of the openings PG1 and PG2 defined by the film layer 114 may be inclined planes, so the cross-sectional areas of the openings PG1 and PG2 parallel to the XY plane may vary; The bottom end is tapered, that is, tapered toward the direction close to the substrate 100 or fan out toward the direction away from the substrate 100 (ie, the direction Z); in some embodiments, the openings PG1, PG2 Conical or horn hole.

Active elements (eg, active elements T1 ) are disposed on the first surface 100T of the substrate 100 and are arranged in an array. The active element T1 can be a bottom gate type thin film transistor body (bottom gate TFT), top gate type thin film transistor (top gate TFT) or other suitable type of thin film transistor. The semiconductor layer SE1 is disposed on the film layer 111, and the material of the semiconductor layer SE1 is, for example, polysilicon (eg, low temperature crystalline silicon (LTPS)), amorphous silicon (amorphous silicon), and metal oxide semiconductor (eg, indium gallium zinc). oxide (Indium Gallium Zinc Oxide, IGZO)) or other semiconductor materials. Part of the source pattern S1 and the drain pattern D1 are disposed on the film layer 113 , while the other part of the source pattern S1 and the drain pattern D1 penetrate through the film layers 112 and 113 and respectively contact the semiconductor layer SE1 .

In some embodiments, the material of the conductor pattern CP1, the source pattern S1, the drain pattern D1 and the gate pattern G1 can be a single-layer or multi-layer stacked conductive material; in some embodiments, based on the consideration of conductivity, the conductor The materials of the pattern CP1 , the source pattern S1 , the drain pattern D1 and the gate pattern G1 are generally other conductive materials such as metal materials or alloys, nitrides of metal materials, oxides of metal materials, oxynitrides of metal materials. The connecting conductor layer 116 is disposed on the film layer 115 and is electrically connected to the conductor pattern CP1 , the source pattern S1 and the drain pattern D1 through a plurality of contact holes HL1 to HL3 respectively.

Next, referring to FIG. 2 , a seed layer 220 is comprehensively formed on the first surface 100T of the substrate 100 , that is, the seed layer 220 completely overlaps with the substrate 100 or the carrier substrate 100S. The seed layer 220 covers the film layers 111 and 115 and the connection conductor layer 116 . The material for forming the seed layer 220 fills the openings PG1 and PG2, but does not fill the openings PG1 and PG2, that is, a part of the seed layer 220 is located in the openings PG1 and PG2. In some embodiments, the seed layer 220 may be a layer of conductive material; in some implementations In an embodiment, the material of the seed layer 220 is generally other conductive materials such as metal materials or alloys, nitrides of metal materials, oxides of metal materials, oxynitrides of metal materials, and the like. In some embodiments, the method of forming the seed layer 220 may include physical vapor deposition or chemical vapor deposition. In some embodiments, the seed layer 220 is located at least in the display area AA; in some embodiments, the seed layer 220 is located in the display area AA and the non-display area NAA. In some embodiments, the thickness of the seed layer 220 is approximately between 1 and 2 microns.

Next, referring to FIG. 3 , a first photoresist pattern 330 is formed on the seed layer 220 , in other words, the first photoresist pattern 330 is located above the first surface 100T of the substrate 100 . In some embodiments, the material of the first photoresist pattern 330 may be positive photoresist or negative photoresist; in some embodiments, the first photoresist pattern 330 may be liquid photoresist or dry film . The first photoresist pattern 330 partially overlaps the seed layer 220 in the direction Z and partially exposes the seed layer 220 . The first photoresist pattern 330 has a plurality of first trenches TR1 ˜ TR4 . The first trenches TR1 ˜ TR4 respectively expose the openings PG1 , PG2 or the contact holes HL1 ˜HL3 and communicate with the openings PG1 , PG2 or the contact holes HL1 respectively ~HL3. In some embodiments, the first photoresist pattern 330 does not overlap with the openings PG1, PG2 or the contact holes HL1-HL3 in the direction Z; in some embodiments, the first photoresist pattern 330 does not overlap in the direction Z The contact holes HL1-HL3 completely overlap; in some embodiments, the first trenches TR1-TR4 overlap with the openings PG1, PG2 or the contact holes HL1-HL3 in the direction Z respectively; in some embodiments, the first trenches TR1 ~TR4 overlaps the connecting conductor layer 116 in the direction Z. The first photoresist pattern 330 may include a plurality of pillars, eg, the first pillars 330P. in some implementations In an example, the sidewall of the first columnar body 330P may be inclined, and the cross-sectional area of the first columnar body 330P parallel to the XY plane may vary; in some embodiments, the first columnar body 330P gradually changes from the bottom end to the top end. Thin, meaning tapered in a direction away from the seed layer 220 (ie, direction Z) or fan out in a direction close to the seed layer 220 ; in some embodiments, the first columnar The body 330P is tapered. In order to improve the manufacturing precision of the first photoresist material pattern 330, in some embodiments, the first columnar body 330P is defined by a large substrate yellow light pattern, and further, is formed in a high-precision yellow light process; In some embodiments, the first pillars 330P of the first photoresist pattern 330 may be formed by patterning the photoresist through an exposure development process.

Next, referring to FIG. 4 , a plurality of alignment marks 410 are formed on the substrate 100 . The alignment mark 410 is located in the non-display area NAA, which can be used as a reference point for positioning or alignment in subsequent processes. In some embodiments, the alignment mark 410 can be a through hole that penetrates through the substrate 100 . In this way, whether it is the fabrication of components or film layers on the first surface 100T side of the substrate 100 or the second surface 100B side of the substrate 100 For the fabrication of the components or film layers, the alignment marks 410 can be used as the basis to ensure the production yield. In some embodiments, setting the alignment mark 410 may be omitted. Next, referring to FIG. 5 , the carrier substrate 100S is removed from the substrate 100 , that is, a release process is performed. In some embodiments, the release process may be performed by laser or physical stripping.

Next, referring to FIG. 6 , a plurality of first conductive structures 640S1 to 640S4 are formed on the first surface 100T of the substrate 100 . In some embodiments, based on the consideration of electrical conductivity, the materials of the first conductive structures 640S1 to 640S4 are generally metal materials or alloys, nitrides of metal materials, oxides of metal materials, and oxynitrides of metal materials. In some embodiments, the material of the first conductive structures 640S1 to 640S4 is copper. In some embodiments, the method for forming the first conductive structures 640S1 ˜ 640S4 may include thick film forming techniques such as electroplating; chemical vapor deposition. In some embodiments, the seed layer 220 facilitates the formation of the first conductive structures 640S1 ˜ 640S4 , or can improve the formation uniformity of the first conductive structures 640S1 ˜ 640S4 (meaning that the copper plating is uniform on the entire surface), or can enhance the first conductive structures 640S1 ˜ 640S4 The combination of the conduction structures 640S1 to 640S4 with the substrate 100 . The first conduction structures 640S1-640S4 cover part of the seed layer 220, and the first trenches TR1-TR4 of the first photoresist pattern 330 and the opening PG1 of the film layer 114 are filled with the material for forming the first conduction structures 640S1-640S4 , PG2 to fabricate the first conduction structures 640S1 to 640S4. The film layer 114 , the seed layer 220 and the first conducting structures 640S1 - 640S4 all fill the openings PG1 and PG2 , and the first conducting structures 640S1 - 640S4 fill the openings PG1 and PG2 . In addition, the first conduction structures 640S1 ˜ 640S4 fill the first trenches TR1 ˜ TR4 of the first photoresist pattern 330 and are fitted with the first trenches TR1 ˜ TR4 , that is, the first photoresist pattern 330 can be The blocking seed layer 220 contacts the electroplating solution, so that the first conductive structures 640S1 to 640S4 have a patterned structure. In some embodiments, since the sidewalls of the first column 330P and the openings PG1 and PG2 of the first photoresist pattern 330 are inclined planes, the sidewalls of the first conducting structures 640S1 to 640S4 are also inclined planes, that is, the first conducting structure 640S1 The cross-sectional areas of the ~640S4 parallel to the XY plane may vary; in some embodiments, the first conductive structures 640S1 to 640S4 gradually become thicker from the bottom to the top, that is, in a direction away from the first surface 100T of the substrate 100 (ie, the direction Z) is fan out or tapered in a direction close to the first surface 100T of the substrate 100 ; in some embodiments, the first conductive structures 640S1 - 640S4 are tapered. In this way, the first conduction structures 640S1 - 640S4 can ensure the yield and manufacturing efficiency of the subsequent micro bonding process (eg, micro bump bonding or micro light emitting diode bonding, etc.). In some embodiments, the column diameter d1 of the first conduction structure 640S1 (ie, the column diameter near the bottom end of the substrate 100 ) is approximately between 30 micrometers (μm) and 80 micrometers; in some embodiments, the first The column diameter d1 of the conduction structure 640S1 is approximately less than 150 μm, wherein the column diameter may be a diameter, a diagonal length, an edge width or other geometric features. In some embodiments, the thickness TH1 of the first conducting structures 640S1-640S4 is greater than 10 microns; in some embodiments, the thickness TH1 of the first conducting structures 640S1-640S4 is greater than 20 microns; in some embodiments, The thicknesses TH1 of the first conducting structures 640S1 - 640S4 are much larger than the thickness of the seed layer 220 ; in some embodiments, the thicknesses TH1 ′ of the first conducting structures 640S1 and 640S3 are greater than 10 μm. The thicker thickness TH1 of the first conductive structures 640S1 to 640S4 can reduce the resistance of the traces on the first surface 100T of the substrate 100 , and can carry a large current, thereby realizing high current density driving. In addition, the thicker thickness TH1 of the first conducting structures 640S1 ˜ 640S4 is helpful for the subsequent micro-bonding process, because the first conducting structures 640S1 ˜ 640S4 form relative protruding points, which is beneficial to alignment.

Next, referring to FIG. 7 , a support layer 770 is formed on the first surface 100T of the substrate 100 . In some embodiments, the support layer 770 covers the seed layer 220 and the first conduction structures 640S1-640S4. In some embodiments, the support layer 770 to It is less located in the display area AA. In this case, since the supporting layer 770 and the substrate 100 cover the elements and film layers (such as the pixel array structure layer 110 ) located in the display area AA, subsequent processes can prevent damage to the display area AA. components and membranes. In some embodiments, the support layer 770 can be used as a protective film layer to facilitate backside processes, such as copper plating. In some embodiments, the support layer 770 can improve the structural strength of the substrate 100 while improving the problem of insufficient stress or stiffness.

Next, referring to FIG. 8 , a plurality of blind vias V1 and V2 are formed. The plurality of blind vias V1 and V2 overlap the first conductive structures 640S1 and 640S3. The blind holes V1 and V2 are drilled from the second surface 100B of the substrate 100 to the first surface 100T, that is, along the direction Z. In some embodiments, the method for forming the blind vias V1 and V2 may include laser or etching (eg, dry etching). The support layer 770 and the first conductive structures 640S1 to 640S4 can improve the structural strength and hardness of the substrate 100 and facilitate the drilling process of the blind holes V1 and V2. Therefore, the support layer 770 and the first conductive structures 640S1 to 640S4 are in the blind holes V1 and V2. The holes V1, V2 are formed before the drilling process. Moreover, after the blind holes V1 and V2 are drilled, there are still other elements or film layers above the blind holes V1 and V2, that is to say, the blind holes V1 and V2 do not completely penetrate the holes above the first surface 100T of the substrate 100 . All components or layers, and further, there are components or layers on the surface of the blind vias V1 and V2, which are different from the through holes, which not only helps to improve the resolution, but also avoids the problem of metal reflection. The blind holes V1 and V2 communicate with the openings PG1 and PG2 respectively, that is to say, the blind holes V1 and V2 overlap the openings PG1 and PG2 in the direction Z. As shown in FIG. In this case, the placement positions of the blind vias V1 and V2 are related to the placement positions of the openings PG1 and PG2. Therefore, when the first conductive structures 640S1 and 640S3 are formed, the placement positions of the blind vias V1 and V2 have been determined. Word, The positions of the blind vias V1 and V2 are determined together when the front side is copper-plated. In some embodiments, the first conductive structures 640S1-640S4, the blind vias V1, V2, and the openings PG1, PG2 are located in the display area AA (ie, the image display area), and the surrounding non-display area NAA does not require wiring (eg, connecting metal line), but not limited thereto. In some embodiments, the blind vias V1 and V2 penetrate through the substrate 100 and the film layer 111 to expose the seed layer 220 located above the first surface 100T of the substrate 100 . In some embodiments, the laser stops at the seed layer 220 . The top surfaces of the blind vias V1 and V2 are the bottom surfaces of the seed layer 220 . Therefore, the top surfaces of the blind vias V1 and V2 are not coplanar with the first surface 100T of the substrate 100 , but are higher than the first surface 100T of the substrate 100 . That is to say, the distance along the direction Z between the top surface of the blind via V1 (or the blind via V2 ) and the first surface 100T of the substrate 100 is smaller than the distance between the top surface of the blind via V1 (or the blind via V2 ) and the first surface 100T of the substrate 100 The distance between the two surfaces 100B along the direction Z; in some embodiments, by appropriately designing the blind holes V1 and V2 , the back electrode formed subsequently will extend beyond the substrate 100 . In some embodiments, the sidewalls of the blind holes V1 and V2 are inclined planes, that is, the cross-sectional areas of the blind holes V1 and V2 parallel to the XY plane can vary; The bottom end of the two surfaces 100B to the top (adjacent to the first conductive structures 640S1 and 640S3 ) taper gradually, which means that it tapers in the direction close to the first conductive structures 640S1 and 640S3 (that is, the direction Z) or away from the first conductive structure. The structures 640S1 and 640S3 fan out in the direction; in some embodiments, the blind holes V1 and V2 are tapered or are horn holes or large and small holes. In this way, the column diameter (eg, the diameter) of the top ends of the blind vias V1 and V2 (adjacent to the first conductive structures 640S1 and 640S3 ) can be ensured to be small, which helps to improve the resolution. In addition, in some embodiments, the dimension DD1 of the first conduction structure 640S1 (eg, the cross-sectional area is wide degree) is approximately between 100 microns and 120 microns, therefore, the first conductive structure 640S1 can completely shield the blind via V1; in some embodiments, the dimension DD1 of the first conductive structure 640S1 is less than 200 microns.

Next, referring to FIG. 9 , a surface treatment coating 920 is formed. The surface treatment film 920 is located on the second surface 100B side of the substrate 100 and completely covers the substrate 100 . For example, the surface treatment film 920 covers the second surface 100B and the blind holes V1 and V2 of the substrate 100 . In some embodiments, the surface treatment coating 920 may be a conductive material layer. In some embodiments, the surface treatment film 920 may be formed by a surface metallization process; in some embodiments, the entire surface of the substrate 100 is conductive. In some embodiments, the surface ring opening of the substrate 100 may be performed by plasma treatment or strong chemical alkali treatment, that is, to open the heterocyclic ring of the substrate 100 or to open weaker bonds, and then, to the substrate 100 The surface of the substrate 100 is subjected to metal ion exchange, and then the metal is reduced to the surface of the substrate 100 to form a surface treatment coating 920 . In some embodiments, the substrate 100 (and the film layer thereon) is immersed in a chemical solution, so that the surface treatment coating 920 fully coats the substrate 100 . In some embodiments, the surface treatment coating 920 can be used as a seed layer, which is beneficial to the subsequent electroplating process and can avoid the phenomenon of film peeling. Since the supporting layer 770 and the substrate 100 cover the elements and film layers (such as the pixel array structure layer 110 ) located in the display area AA on the first surface 100T of the substrate 100 , damages in the process of forming the surface treatment coating 920 can be avoided. Elements and film layers of the display area AA. That is to say, the substrate 100 and the supporting layer 770 cover the entire display area AA on both sides, so the subsequent process will not cause process damage to the display area AA. For example, the strong alkali used to conduct the substrate 100 will not damage the front surface. of In the display area AA, in contrast, if the double-sided copper electroplating process is performed at one time, the front display area AA may be damaged.

Next, referring to FIG. 10 , a second photoresist pattern 1030 is formed on the surface treatment coating 920 , in other words, the second photoresist pattern 1030 is located on the second surface 100B side of the substrate 100 . The material of the second photoresist pattern 1030 may be the same as or different from that of the first photoresist pattern 330 . The second photoresist pattern 1030 partially overlaps the surface treatment film 920 in the direction Z and partially exposes the surface treatment film 920 . In some embodiments, the second photoresist pattern 1030 does not overlap with the blind holes V1 and V2 in the direction Z; in some embodiments, the second photoresist pattern 1030 has a plurality of second trenches BR1˜BR3, The second trenches BR1 and BR3 respectively expose the blind holes V1 and V2 and communicate with the blind holes V1 and V2 respectively; in some embodiments, the second trenches BR1 and BR3 respectively overlap with the blind holes V1 and V2 in the direction Z . The second photoresist pattern 1030 may include a plurality of pillars, eg, the second pillars 1030P. In some embodiments, the sidewall of the second columnar body 1030P may be inclined, and the cross-sectional area of the second columnar body 1030P parallel to the XY plane may vary; in some embodiments, the second columnar body 1030P is formed from (adjacent to the substrate) The bottom end of the second surface 100B of the substrate 100 is tapered to the top end (away from the second surface 100B of the substrate 100 ), which means that it tapers in a direction away from the substrate 100 or in a direction closer to the substrate 100 (ie, the direction Z). Upper fan-out; in some embodiments, the second column 1030P is tapered. In some embodiments, the second pillars 1030P of the second photoresist pattern 1030 can be formed by patterning, wherein the fabrication precision of the first pillars 330P of the first photoresist pattern 330 is higher than that of the second The fabrication accuracy of the second pillars 1030P of the photoresist pattern 1030 .

11 , a plurality of second conductive structures 1140S1 ˜ 1140S3 are formed on the surface treatment film 920 , in other words, the second conductive structures 1140S1 ˜ 1140S3 are located on the second surface 100B side of the substrate 100 . The second conductive structures 1140S1 to 1140S3 contact the seed layer 220 through the blind holes V1 and V2. In some embodiments, the bottom surface of the second conductive structure 1140S1 (or the second conductive structure 1140S3 ) is not coplanar with the first surface 100T of the substrate 100 , but is higher than the first surface 100T of the substrate 100 ; in some embodiments , the bottom surface of the second conduction structure 1140S1 (or the second conduction structure 1140S3 ) is located above the first surface 100T of the substrate 100 . The materials of the second conducting structures 1140S1 ˜ 1140S3 may be the same as or different from those of the first conducting structures 640S1 ˜ 640S4 . In some embodiments, the method for forming the second conductive structures 1140S1 ˜ 1140S3 may include thick film forming techniques such as electroplating; in some embodiments, the method for forming the second conductive structures 1140S1 ˜ 1140S3 may include physical vapor deposition or chemical vapor deposition. In some embodiments, the surface treatment coating 920 facilitates the formation of the second conductive structures 1140S1 ˜ 1140S3 , or can improve the formation uniformity of the second conductive structures 1140S1 ˜ 1140S3 , or can strengthen the second conductive structures 1140S1 ˜ 1140S3 and the substrate 100 . In some embodiments, the second conductive structure 1140S1 can be formed between the seed layer 220 or the first conductive structures 640S1 to 640S4 and the adjacent but not directly contacted surface treatment film 920 by jump plating. ~1140S3. The second conductive structures 1140S1-1140S3 cover part of the surface treatment film 920, and the second trenches BR1-BR3 and the blind holes V1, V2 of the second photoresist pattern 1030 are filled with the material for forming the second conductive structures 1140S1-1140S3 to fabricate the second conduction structures 1140S1 to 1140S3. Among them, the surface treatment film 920 and the first The two conductive structures 1140S1 to 1140S3 are all filled with the blind vias V1 and V2, while the second conductive structures 1140S1 to 1140S3 are filled with the blind vias V1 and V2. In addition, the second conductive structures 1140S1 ˜ 1140S3 fill up the second trenches BR1 ˜ BR3 of the second photoresist pattern 1030 and are fitted with the second trenches BR1 ˜ BR3 , that is, the second photoresist pattern 1030 can be The blocking surface treatment film 920 contacts the electroplating solution, so that the second conductive structures 1140S1 to 1140S3 have a patterned structure. In some embodiments, since the sidewalls of the second columnar body 1030P and the blind holes V1 and V2 of the second photoresist pattern 1030 are inclined planes, the sidewalls of the second conducting structures 1140S1 - 1140S3 are also inclined planes, that is, the second conducting structures The cross-sectional areas of the 1140S1-1140S3 parallel to the XY plane may vary; in some embodiments, the second conductive structures 1140S1-1140S3 gradually become thicker from the bottom end (bottom surface 1140B) to the top (top surface 1140T), which means that the second conductive structures 1140S1 to 1140S3 are gradually thickened away from the substrate. The direction of the second surface 100B of the substrate 100 is fanned out or tapered toward the direction close to the second surface 100B of the substrate 100 (ie, the direction Z). In some embodiments, the second conductive structures 1140S1 to 1140S3 are tapered. In this way, the second conductive structures 1140S1 - 1140S3 can ensure the yield and manufacturing efficiency of the subsequent bonding process. In some embodiments, the column diameter d2 of the second conducting structure 1140S1 (ie, the column diameter near the bottom ends of the first conducting structures 640S1 and 640S3 ) is approximately between 1 micrometer (μm) and 20 micrometers; in some implementations In an example, the diameter d2 of the pillars of the second conduction structure 1140S1 is approximately between 10 μm and 20 μm; in some embodiments, the diameter d2 of the pillars of the second conduction structure 1140S1 is different from the diameter d1 of the pillars of the first conduction structure 640S1; In some embodiments, the column diameter d2 of the second conductive structure 1140S1 is smaller than the column diameter d1 of the first conductive structure 640S1. In some embodiments, the thickness of the second conduction structures 1140S1 - 1140S3 TH2 is greater than 20 microns; in some embodiments, the thicknesses TH2 of the second conductive structures 1140S1-1140S3 are much larger than the thickness of the surface treatment coating 920; in some embodiments, the thicknesses TH1 of the first conductive structures 640S1-640S4 are different In some embodiments, the thicknesses of the front and back copper are different; in some embodiments, the thickness TH1 of the first conductive structures 640S1 ~ 640S4 is smaller than that of the second conductive structures 1140S1 ~ 1140S3 Thickness TH2; In some embodiments, the thickness TH1 of the first conducting structures 640S1 ˜ 640S4 is the same as the thickness TH2 of the second conducting structures 1140S1 ˜ 1140S3 . The thicker thickness TH2 of the second conduction structures 1140S1 to 1140S3 can reduce the resistance value of the traces on the second surface 100B of the substrate 100 , and can carry a large current, thereby realizing high current density driving, so as to ensure the external quantum efficiency (EQE, External Quantum Efficiency) and the chromaticity of the light-emitting unit.

Next, referring to FIG. 12 , the support layer 770 is removed. 13, a first conductor layer 1301 is formed on the first conduction structures 640S1-640S4, and a second conductor layer 1302 is formed on the second conduction structures 1140S1-1140S3. In other words, the first conductor layer 1301 is located on the The substrate 100 is on the first surface 100T side, and the second conductor layer 1302 is located on the second surface 100B side of the substrate 100 . In some embodiments, the first conductor layer 1301 and the second conductor layer 1302 are formed together in the same process. More specifically, the front and back surfaces are a one-time process, that is, double-sided tinning is completed at one time; in some cases In the embodiment, the first conductor layer 1301 and the second conductor layer 1302 are formed in different processes. In some embodiments, based on the consideration of electrical conductivity, the materials of the first conductor layer 1301 and the second conductor layer 1302 are generally metal materials or alloys, Other conductive materials such as nitrides of metal materials, oxides of metal materials, oxynitrides of metal materials, etc.; in some embodiments, the material of the first conductor layer 1301 and the second conductor layer 1302 is tin. The conductor layer 1301 and the second conductor layer 1302 are formed by a tinning process, so as to prevent surface oxidation. In some embodiments, the material of the first conductor layer 1301 and the second conductor layer 1302 is gold. In some embodiments, the thickness of the first conductor layer 1301 or the second conductor layer 1302 is approximately between 3 microns and 4 microns; in some embodiments, the thickness of the first conductor layer 1301 or the second conductor layer 1302 is approximately between 1 micron and 2 microns.

Next, referring to FIG. 14 , the first photoresist pattern 330 and the second photoresist pattern 1030 are removed. In some embodiments, the first photoresist pattern 330 and the second photoresist pattern 1030 are removed together in the same process. More specifically, the front and back surfaces are a one-time process, that is, the photoresist on both sides is removed. The agent is a one-time process; in some embodiments, the first photoresist pattern 330 and the second photoresist pattern 1030 are removed in different processes. The present invention removes the first photoresist pattern 330 and the second photoresist pattern 1030 after the first conductor layer 1301 and the second conductor layer 1302 are formed, so that the first conductor layer 1301 and the second photoresist pattern 1030 are removed. The second conductor layer 1302 is formed at the positions where the first photoresist pattern 330 and the second photoresist pattern 1030 are located, so that the sides of the first conducting structures 640S1-640S4 or the second conducting structures 1140S1-1140S3 are also covered with tin, and further affect the process accuracy.

Next, referring to FIG. 15 , a patterning step is performed to pattern the seed layer 220 and the surface treatment coating 920 to form a seed pattern layer 220N and a pattern coating 920N. In some embodiments, the seed layer 220 and the surface treatment coating 920 are They are patterned together in the same process, that is, a one-time patterning process; in some embodiments, the seed layer 220 and the surface treatment film 920 are patterned in different processes. Wherein, the patterning step involves an exposure process, a development process or an etching process. The projections of the seed crystal pattern layer 220N and the pattern coating film 920N along the direction Z on the substrate 100 substantially overlap the projections of the first conducting structures 640S1 - 640S4 and the second conducting structures 1140S1 - 1140S3 along the direction Z on the substrate 100 . In some embodiments, based on the height H1 of the first conduction structure 640S2 (or the first conduction structure 640S3 ) greater than 20 μm, the column diameter a1 is approximately between 4 μm and 6 μm, and the ratio between the height and the column diameter is greater than 3. In some embodiments, based on the aspect ratio of the first conductive structures 640S2 and 640S3, the first conductive structures 640S2 and 640S3 can be defined as pillars or copper pillars; in some embodiments, the copper pillars are formed by the A conduction structure 640S1-640S4 and the seed pattern layer 220N are formed, but there is an interface between the first conduction structures 640S1-640S4 and the seed pattern layer 220N, or the copper pillars are covered by the second conduction structures 1140S1-1140S3 and the pattern. The film 920N is formed, but there is an interface between the second conductive structures 1140S1-1140S3 and the pattern coating film 920N; in some embodiments, the first conductive structures 640S1-640S4 are compared with the seed pattern layer 220N (or the seed layer 220) The components are different, or the degree of impurity doping or film quality is different, so there is an interface between the first conduction structures 640S1-640S4 and the seed pattern layer 220N. Similarly, the second conduction structures 1140S1-1140S3 are compared with the pattern coating The composition of 920N (or the surface treatment film 920) is different, or the degree of impurity inclusion or the film quality is different.

Next, referring to FIG. 16, a first shielding layer 1601 is formed on the first conductor layer 1301, and a second shielding layer 1602 is formed on the second conductor layer 1302. In other words, the first shielding layer 1601 is located on the side of the first surface 100T of the substrate 100 , and the second shielding layer 1602 is located on the side of the second surface 100B of the substrate 100 . The first shielding layer 1601 partially overlaps the first conductor layer 1301 in the direction Z, and partially exposes the first conductor layer 1301 and the first conductive structures 640S2 and 640S3 thereunder to serve as bonding regions. The second shielding layer 1602 partially overlaps the second conductor layer 1302 in the direction Z, and partially exposes the second conductor layer 1302 and the second conductive structure 1140S3 thereunder to serve as a bonding area. In some embodiments, the first conduction structures 640S2, 640S3 and the first conductor layer 1301 thereon can be used as pads or bonding pads; similarly, the second conduction structures 1140S3 and the second conductor layer 1302 thereon can be used as the connection pads. pad or solder pad. In some embodiments, the material of the first shielding layer 1601 or the second shielding layer 1602 includes black ink; in some embodiments, the first shielding layer 1601 or the second shielding layer 1602 can be used as an anti-reflection layer or Solder Mask layer; in some embodiments, the front side only exposes the area for bonding the light-emitting unit LN1, and the back side only exposes the area for bonding the integrated circuit, therefore, the first shielding layer 1601 and the second The shielding layer 1602 can be used to shield light, or avoid the problem of metal reflection, so as to achieve seamless splicing.

Next, referring to FIG. 17 , the light emitting unit LN1 is disposed on the first conductor layer 1301 , in other words, the light emitting unit LN1 is located on the side of the first surface 100T of the substrate 100 . In some embodiments, the light-emitting unit LN1 may be a light-emitting diode (LED) or a micro-LED (micro LED), but the invention is not limited thereto. In some embodiments, the light-emitting unit LN1 is first formed on a growth substrate, and then transferred to another light-emitting unit substrate using a mass transfer technique. In some embodiments, the light-emitting unit LN1 is formed by, for example, an adhesive layer or soldering The material is bonded to the first conductor layer 1301, and further coupled to the first conductive structures 640S2 and 640S3; in some embodiments, the miniature light-emitting diodes are bonded to the copper pillars through a micro-bonding process. In some embodiments, the first conducting structure 640S2 may be coupled to one end of the light-emitting unit LN1, for example, coupled to the cathode (Cathode) or the anode (Anode) of the light-emitting unit LN1; in some embodiments, the first conducting structure 640S3 Can be coupled to system low voltage (VSS).

On the other hand, as shown in FIG. 17 , the substrate 1700 is provided on the second conductor layer 1302 , in other words, the substrate 1700 is located on the second surface 100B side of the substrate 100 . The substrate 1700 is used for disposing a driving circuit. The driving circuit can provide driving signals to the active elements (not shown) of the pixel unit, and the driving circuit can be coupled to the second conducting structure 1140S3 through the second conductor layer 1302 . Here, the fabrication of the display panel 10 can be completed. In some embodiments, an encapsulant or a cover glass or a black matrix may be further provided to complete the fabrication of the display panel 10 .

As can be seen from the above, the elements located on the first surface 100T of the substrate 100 can be coupled to the first conducting structures (eg, the first conducting structures 640S1 and 640S3 ), and the first conducting structures can be coupled to the first conducting structures through the blind vias V1 and V2 The second conduction structure, the second conduction structure (the second conduction structure 1140S1 , 1140S3 ) can be coupled to the elements located on the second surface 100B of the substrate 100 . That is, the elements located on the second surface 100B of the substrate 100 can be coupled to the elements located on the first surface 100T of the substrate 100 through the first conduction structure and the second conduction structure. Blind holes V1 and V2 are connected up and down. In this way, the space of the first surface 100T and the second surface 100B of the substrate 100 can be fully utilized for wiring, and the size of the display panel 10 can be reduced. size, thereby achieving size miniaturization. In addition, arranging part of the wiring on the second surface 100B of the substrate 100 can reduce the area of the wiring area (ie, the non-light-emitting area) on the first surface 100T of the substrate 100 . In this case, the display panel 10 can realize a narrow frame design or a seamless splicing design.

In addition, the first conductive structures 640S1 - 640S4 are formed before the blind vias V1 and V2 . Therefore, the first conductive structures 640S1 - 640S4 can improve the structural strength of the substrate 100 and facilitate the drilling of the blind vias V1 and V2 . In addition, the blind vias V1 and V2 extend to the first conductive structures 640S1 to 640S4 without passing through the first conductive structures 640S1 to 640S4. Thereafter, the second conductive structures 1140S1 to 1140S3 are filled into the blind vias V1 and V2, and the electrical connected to the first conduction structures 640S1 to 640S4. That is to say, the copper plating can be divided into the front side and the back side twice. In this way, the panel manufacturing process (as shown in Fig. 1A to Fig. 4 ) with higher precision and the wiring process with higher precision (as shown in Fig. 4) can be combined. 6 to FIG. 17 ) are carried out separately, which is different from the one-time copper plating process technology on the front and back. In addition, when the front side is copper-plated, the substrate has no blind holes, but when the backside laser drilling is used, there is a front side hardness support, and the drilling stops at the front copper layer. In this case, the structure of the blind hole is conducive to improving the resolution. . Moreover, since the supporting layer 770 and the substrate 100 cover the elements and film layers (such as the pixel array structure layer 110 ) located in the display area AA on the first surface 100T of the substrate 100 , subsequent processes (such as the open loop shown in FIG. 9 ) can be avoided. procedures) damage the components and film layers located in the display area AA. Since the first conductor layer 1301 and the second conductor layer 1302 are formed in the same process, the first photoresist pattern 330 and the second photoresist pattern 1030 are removed together in the same process, and the seeds are Layer 220 and surface treatment coating 920 are combined in the same process patterning, thus simplifying the process and shortening the process time.

The depths of the blind holes V1 and V2 may be adjusted according to different design considerations. For example, please refer to FIG. 18, which is a schematic cross-sectional view of a partial area of a display panel 10' according to another embodiment of the present invention. As shown in FIG. 18 , the difference between the display panel 10 ′ and the display panel 10 is that the blind holes V1 ′ and V2 ′ of the display panel 10 ′ penetrate through the substrate 100 , the film layer 111 and the seed layer 220 , and are exposed on the substrate 100 . The first conductive structures 640S1 and 640S3 above the first surface 100T of the 100 , that is, the drilling process of the blind holes V1 ′ and V2 ′ is terminated at the first conductive structures 640S1 and 640S3 . In some embodiments, the laser stops at the first conduction structures 640S1, 640S3 (or thick copper layers). The top surfaces of the blind vias V1' and V2' are the bottom surfaces of the first conductive structures 640S1 and 640S3. Therefore, the top surfaces of the blind vias V1' and V2' are not coplanar with the first surface 100T of the substrate 100, but are higher than the substrate. 100 of the first surface 100T. The second conduction structures 1140S1 and 1140S3 contact the first conduction structures 640S1 and 640S3 through the blind holes V1' and V2', so that the first conduction structures 640S1 and 640S3 serve as termination layers of the second conduction structures 1140S1 and 1140S3. In some embodiments, the front side copper layer is a termination layer for the back side copper layer.

To sum up, the display panel of the present invention has blind holes penetrating through the substrate, the first conductive structure can be coupled to the second conductive structure through the blind holes, so the components on the upper surface of the substrate can be coupled to the components on the substrate. The components on the lower surface, in this way, can be miniaturized in size. The first conduction structure and the support layer of the display panel are formed before the blind holes, so the first conduction structure and the support layer can improve the structural strength of the substrate, which is beneficial to the drilling of the blind holes, and can improve the yield. In addition, since the support layer and the substrate cover the elements and film layers in the display area on the first surface of the substrate, it is possible to avoid Subsequent processes damage components and film layers in the display area, thereby improving yield.

Although the present invention has been disclosed above by the embodiments, it is not intended to limit the present invention. Anyone with ordinary knowledge in the technical field can make some changes and modifications without departing from the spirit and scope of the present invention. Therefore, The protection scope of the present invention shall be determined by the scope of the appended patent application.

10: Display panel

100, 1700: substrate

111~115: film layer

220: seed layer

640S1~640S4: The first conduction structure

1140S1~1140S3: Second conduction structure

1301: The first conductor layer

1302: Second Conductor Layer

1601: First masking layer

1602: Second masking layer

CP1: Conductor Pattern

D1: Drain pattern

G1: Gate pattern

LN1: Lighting unit

S1: source pattern

SE1: Semiconductor layer

X, Y, Z: direction

Claims (14)

A display panel, comprising: a substrate having a first surface and a second surface; a pixel array structure layer disposed on the first surface of the substrate, wherein the pixel array structure layer has an opening, and A blind hole passing through the substrate is communicated with the opening of the pixel array structure layer; a seed crystal pattern layer is arranged on the pixel array structure layer, wherein the seed crystal pattern layer is filled into the pixel array structure layer. the opening; a first conducting structure disposed on the seed pattern layer, wherein the first conducting structure is coupled to the pixel array structure layer and fills the opening of the pixel array structure layer, the substrate The blind hole overlaps the first conduction structure, and the ratio between the thickness of the first conduction structure and the column diameter is greater than 3; a light-emitting unit is disposed on the first conduction structure and coupled to the first conduction structure ; a pattern coating, disposed on the second surface of the substrate and a side wall of the blind hole of the substrate, wherein the pattern coating is another seed pattern layer; and a second conduction structure, disposed on the On the pattern coating, wherein the second conducting structure fills the blind hole of the substrate to be electrically connected to the first conducting structure. The display panel of claim 1, wherein a bottom surface of the second conduction structure is located above the first surface of the substrate. The display panel of claim 1, wherein the thickness of the first conduction structure is smaller than the thickness of the second conduction structure. The display panel as claimed in claim 1, wherein the blind hole is tapered toward a direction close to the first conduction structure, and the opening is tapered toward a direction close to the substrate. The display panel of claim 1, wherein a column diameter at the bottom end of the first conducting structure is different from a column diameter at the bottom end of the second conducting structure. The display panel of claim 1, wherein an interface exists between the second conducting structure and the first conducting structure. A method for manufacturing a display panel, comprising: forming a pixel array structure layer on a first surface of a substrate, the pixel array structure layer having an opening; forming a seed layer on the pixel array structure layer, wherein The seed layer fills the opening of the pixel array structure layer; a first conductive structure is formed on the seed layer, wherein the first conductive structure is coupled to the pixel array structure layer and fills the pixel the opening of the array structure layer; a blind hole is formed, the blind hole penetrates the substrate and is connected to the opening of the pixel array structure layer, the blind hole overlaps the first conduction structure; a surface treatment coating is formed, the The surface treatment film covers a second surface of the substrate and the blind hole, wherein the surface treatment film is used as another seed layer; a second conduction structure is formed on the surface treatment film, and the second conduction structure fills entering the blind hole into the substrate to be electrically connected to the first conduction structure; patterning the seed layer and the surface treatment coating to form a seed pattern layer and a pattern coating; and A light-emitting unit is disposed on the first conducting structure, and the light-emitting unit is coupled to the first conducting structure. The method for fabricating a display panel as described in item 7 of the claimed scope further comprises, before forming the first conduction structure, forming a first photoresist pattern on the seed layer, the first photoresist pattern having a a first trench, the first conductive structure fills the first trench, and the first trench communicates with the opening of the pixel array structure layer. The method for fabricating a display panel as described in item 7 of the claimed scope further includes forming a plurality of alignment marks, the alignment marks are located in a non-display area of the substrate and penetrate through the substrate. The method for fabricating a display panel as described in item 8 of the claimed scope further includes forming a support layer on the first conduction structure and the first photoresist pattern before forming the blind hole. The method for fabricating a display panel as described in item 7 of the claimed scope further comprises, before forming the second conduction structure, forming a second photoresist pattern on the surface treatment coating, the second photoresist pattern having a second trench, the second conductive structure fills the second trench, and the second trench communicates with the blind hole. The method for fabricating a display panel as described in item 7 of the claimed scope further comprises forming a first conductor layer on the first conduction structure and a second conductor layer on the second conduction structure. The method for manufacturing a display panel as described in item 7 of the claimed scope further comprises removing a first photoresist pattern and a second photoresist together before patterning the seed layer and the surface treatment coating pattern. The method for fabricating a display panel as described in item 7 of the claimed scope further comprises: forming a first conductor layer on the first conducting structure and a second conducting layer on the second conducting structure together; forming a first conducting layer on the first conducting structure. a shielding layer over the first conductor layer and a second shielding layer on the second conductor layer, the first shielding layer exposing a part of the first conductor layer as a first bonding area; and the light emitting The unit is bonded to the first conductor layer at the first bonding area.

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