TWI759197B - Display panel - Google Patents

Abstract

A display panel includes data lines, a control switch, and pixel circuits. A terminal of the control switch is connected to one of the data lines, and another terminal of the control switch is connected to a direct current (DC) voltage. Each pixel circuit includes a light emitting unit, multiple switches and a capacitor. The display may be operated in a normal mode and a skip mode. In at least one stage of the skip mode, the control switch is turned on, such that the light emitting units of the pixel circuits are reset through the DV voltage. Accordingly, power consumption is reduced.

Description

display panel

The present disclosure relates to a display panel with an omission mode.

The existing display panel can be operated in the normal mode and the omitted mode, and the displayed picture will not change in the omitted mode, so as to achieve the purpose of saving power. However, in the omission mode, if some characteristics of the pixels are changed, for example, the frequency is changed, the light-emitting diodes are not reset, etc., a flickering phenomenon will occur to the human eye. Therefore, how to avoid the phenomenon that is uncomfortable for human eyes when switching between the normal mode and the omitted mode and achieve the purpose of power saving at the same time, is a topic of concern to those skilled in the art.

Embodiments of the present disclosure provide a display panel having a display area and a non-display area. The display panel includes a plurality of data lines, a control switch and a plurality of pixel circuits. The control switch has a control end, a first end and a second end, the first end of the control switch is connected to the DC voltage, and the second end of the control switch is connected to the data line. Each pixel circuit is connected to a data line. The pixel circuit includes the following elements. The light-emitting unit has a first end and a second end, and the first end of the light-emitting unit is connected to the first operating voltage. The first switch has a first end, a second end and a control end, the first end of the first switch is connected to the second end of the light emitting unit, and the control end of the first switch is connected to the first control signal. The second switch has a first terminal, a second terminal and a control terminal, and the first terminal of the second switch is connected to the second terminal of the first switch. The third switch has a first terminal, a second terminal and a control terminal, the first terminal of the third switch is connected to the second terminal of the second switch, the second terminal of the third switch is connected to the second operating voltage, and the The control end is connected to the second control signal. The fourth switch has a first end, a second end and a control end, the first end of the fourth switch is connected to the reference signal, the second end of the fourth switch is connected to the second end of the light-emitting unit and the first end of the first switch , the control terminal of the fourth switch is connected to the third control signal. The capacitor has a first end and a second end, the first end of the capacitor is connected to the second end of the light-emitting unit, the first end of the first switch and the second end of the fourth switch, and the second end of the capacitor is connected to the second switch the control terminal. The fifth switch has a first end, a second end and a control end, the first end of the fifth switch is connected to the second end of the second switch and the first end of the third switch, and the second end of the fifth switch is connected to the capacitor The second end of the switch and the control end of the second switch, the control end of the fifth switch is connected to the third control signal. The sixth switch has a first end, a second end and a control end, the first end of the sixth switch is connected to the second end of the first switch and the first end of the second switch, and the second end of the sixth switch is connected to the A data line, the control end of the sixth switch is connected to the fourth control signal. In the first mode, the control switch is off. During at least one phase of the second mode, the control switch is turned on.

In some embodiments, the control switch is disposed in the non-display area, the control terminal of the control switch is connected to the test switch pad in the test phase, and the first terminal of the control switch is connected to the test data pad in the test phase.

In some embodiments, after the test phase is performed, the test switch pads and the test data pads are removed.

In some embodiments, the pixel circuit is configured to sequentially operate in the first stage, the second stage, the third stage and the fourth stage in the first mode. In the first stage, the first switch and the sixth switch are turned off, and the second switch, the third switch, the fourth switch and the fifth switch are turned on. In the second stage, the first switch and the third switch are turned off, and the second switch, the fourth switch, the fifth switch and the sixth switch are turned on. In the third stage, the first switch and the second switch are turned on, and the third switch, the fourth switch, the fifth switch and the sixth switch are turned off. In the fourth stage, the first switch, the second switch and the third switch are turned on, and the fourth switch, the fifth switch and the sixth switch are turned off.

In some embodiments, the pixel circuit is configured to sequentially operate in the first omission stage, the second omission stage and the third omission stage in the second mode. In the first omitted stage, the first switch, the third switch, the fourth switch, the fifth switch and the sixth switch are turned off. In the second omitted stage, the first switch, the sixth switch and the control switch are turned on, and the third switch, the fourth switch and the fifth switch are turned off. In the third omitted stage, the first switch, the second switch and the third switch are turned on, and the fourth switch, the fifth switch and the sixth switch are turned off.

In some embodiments, the light-emitting unit is a light-emitting diode, and the DC voltage is lower than the threshold voltage of the light-emitting unit.

In some embodiments, the first to sixth switches are N-type transistors, and the first operating voltage is lower than the second operating voltage. In the first omission stage, the first control signal, the second control signal, the third control signal and the fourth control signal are at a low level. In the second omission stage, the first control signal and the fourth control signal are at a high level, and the second control signal and the third control signal are at a low level. In the third omission stage, the first control signal and the second control signal are at a high level, and the third control signal and the fourth control signal are at a low level.

In some embodiments, in the first stage, the first control signal and the fourth control signal are at a low level, and the second control signal and the third control signal are at a high level. In the second stage, the first control signal and the second control signal are at a low level, and the third control signal and the fourth control signal are at a high level. In the third stage, the first control signal is at a high level, and the second control signal, the third control signal and the fourth control signal are at a low level. In the fourth stage, the first control signal and the second control signal are at a high level, and the third control signal and the fourth control signal are at a low level.

In some embodiments, the first mode is the normal mode and the second mode is the skip mode.

In the above-mentioned display panel, in the second mode, the light-emitting unit is reset by the DC voltage, which can save power consumption.

The terms "first", "second", etc. used in this document do not mean a particular order or order, but are only used to distinguish elements or operations described in the same technical terms.

FIG. 1 is a schematic diagram illustrating a display panel in a testing stage according to an embodiment. Referring to FIG. 1 , the display panel 100 includes a display area 110 , a non-display area 120 and a test area 130 . The display area 110 includes a plurality of sub-pixels 111 (for simplicity, not all sub-pixels are shown), data lines 151-158, gate lines (not shown), and the like. The sub-pixels 111 are arranged in a matrix, and the sub-pixels on the same row are connected to the same data line. Control switches 141 - 148 are disposed in the non-display area 120 , each of the control switches has a first end, a second end and a control end, wherein the second ends are respectively connected to the data lines 151 - 158 . A plurality of pads are disposed in the test area 130 , such as the test switch pad 131 and the test data pads 132 - 134 . The control terminals of the control switches 141 to 148 are connected to the test switch pads 131 through wires. The first ends of the control switches 141 to 148 are connected to the test data pads 132 to 134 through wires. For example, the first ends of the control switches 141 , 144 and 147 are connected to the test data pads 132 . The first end of 148 is connected to the test data pad 133 , and the first ends of the control switches 143 and 146 are connected to the test data pad 134 .

In the testing stage, the display panel 100 has not been provided with gate drivers, source drivers, and the like. The control switches 141 - 148 can be turned on by applying a high-level voltage to the test switch pads 131 . At this time, applying pixel data to the test data pads 132 - 134 can test whether the corresponding sub-pixels 111 are normal. After the test phase is completed, the test area 130 is cut off by, for example, a laser, so the test switch pads 131 and the test data pads 132 to 134 are removed from the display panel.

FIG. 2 is a schematic diagram illustrating a display panel according to an embodiment. Referring to FIG. 2 , after the test phase is completed, a gate driver (not shown), a multiplexer 210 , a source driver 220 , a timing controller (not shown), etc. can be set on the display panel 100 . The multiplexer 210 is connected to the source driver 220 through wires (not shown), and the source driver 220 can transmit signals to the data lines 151-158. For simplicity, all components of the display panel are not shown in FIG. 2 . The source driver 220 may be disposed on a tape carrier package (Tape Carrier Package, TCP), a chip on film (COF), a glass substrate, or other locations, which are not limited in the present disclosure. In particular, the control terminals of the control switches 141-148 are connected to the gate driver or the source driver 220, and the first terminals of the control switches 141-147 are connected to a DC voltage (which can be provided by any circuit on the display panel) . Each sub-pixel 111 has a pixel circuit therein. The display panel 100 can operate in the normal mode and the skip mode, and the DC voltages on the first terminals of the control switches 141 - 148 can be supplied to the pixel circuits in the skip mode.

FIG. 3 is a circuit diagram illustrating a pixel circuit according to an embodiment. Please refer to FIG. 2 and FIG. 3 . Here, a pixel circuit 300 and a control switch 141 are used as an example for illustration. The pixel circuit 300 is, for example, disposed in one of the sub-pixels in the first row of the display area, and the pixel circuit 300 passes through the data line 151 Connected to the control switch 141 and the source driver 220 . The pixel circuit 300 includes a first switch T1 to a sixth switch T6, a light emitting unit 310 and a capacitor C1. The first to sixth switches T1 to T6 are, for example, N-type transistors. The light emitting unit 310 is, for example, a light emitting diode. The light-emitting unit 310 has a first terminal 310-1 and a second terminal 310-2, and the first terminal 310-1 of the light-emitting unit 310 is connected to the operating voltage OVSS. The first switch T1 has a first terminal T1-1, a second terminal T1-2 and a control terminal T1-3, the first terminal T1-1 of the first switch T1 is connected to the second terminal 310-2 of the light emitting unit 310, A control terminal T1-3 of a switch T1 is connected to the control signal EM[N]. The second switch T2 has a first terminal T2-1, a second terminal T2-2 and a control terminal T2-3. The first terminal T2-1 of the second switch T2 is connected to the second terminal T1-2 of the first switch T1. The third switch T3 has a first terminal T3-1, a second terminal T3-2 and a control terminal T3-3, the first terminal T3-1 of the third switch T3 is connected to the second terminal T2-2 of the second switch T2, The second terminal T3-2 of the third switch T3 is connected to the operating voltage OVDD, and the control terminal T3-3 of the third switch T3 is connected to the control signal EM[N+1].

The fourth switch T4 has a first terminal T4-1, a second terminal T4-2 and a control terminal T4-3, the first terminal T4-1 of the fourth switch T4 is connected to the reference signal ref, and the second terminal of the fourth switch T4 T4-2 is connected to the second terminal 310-2 of the light-emitting unit 310 and the first terminal T1-1 of the first switch T1, and the control terminal T4-3 of the fourth switch T4 is connected to the control signal S1[N]. The capacitor C1 has a first terminal C1-1 and a second terminal C1-2, and the first terminal C1-1 of the capacitor C1 is connected to the second terminal 310-2 of the light emitting unit 310 and the first terminal T1-1 of the first switch T1 As well as the second terminal T4-2 of the fourth switch T4, the second terminal C1-2 of the capacitor C1 is connected to the control terminal T2-3 of the second switch T2. The fifth switch T5 has a first terminal T5-1, a second terminal T5-2 and a control terminal T5-3, wherein the first terminal T5-1 of the fifth switch T5 is connected to the second terminal T2-2 of the second switch T2 and the first terminal T3-1 of the third switch T3 and the second terminal T5-2 of the fifth switch T5 are connected to the second terminal C1-2 of the capacitor C1 and the control terminal T2-3 of the second switch T2, the fifth switch The control terminal T5-3 of T5 is connected to the control signal S1[N]. The sixth switch T6 has a first terminal T6-1, a second terminal T6-2 and a control terminal T6-3. The first terminal T6-1 of the sixth switch T6 is connected to the second terminal T1-2 of the first switch T1 and The first terminal T2-1 of the second switch T2 and the second terminal T2-2 of the sixth switch T6 are connected to the source driver 220 and the second terminal 141-2 of the control switch 141 through the data line 151. The control terminal T6-3 is connected to the control signal S2[N]. The control switch 141 has a first terminal 141-1, a second terminal 141-2 and a control terminal 141-3. The first terminal 141-1 of the control switch 141 is connected to the DC voltage V _dc , and the control switch 141 has a control terminal 141-3. Connect to control signal SW.

The normal mode will be described first. FIG. 4 is a timing diagram illustrating control signals in a normal mode according to an embodiment. Referring to FIG. 3 and FIG. 4 , the pixel circuit 300 operates in a first stage 401 , a second stage 402 , a third stage 403 and a fourth stage 404 in sequence. In each stage 401-404 in the normal mode, the control switch 141 is kept off.

FIG. 5 is a schematic diagram illustrating switching of a pixel circuit in a first stage according to an embodiment. 4 and FIG. 5, in the first stage 401, the control signals S1[N] and EM[N+1] are at the high level VGH, and the control signals S2[N] and EM[N] are at the low level VGL. Therefore, the first switch T1 and the sixth switch T6 are turned off, and the second switch T2 , the third switch T3 , the fourth switch T4 and the fifth switch T5 are turned on. In the first stage 401, the potentials of the node A and the node C are the same as the operating voltage OVDD, and the potential of the node B is the same as the reference signal ref.

FIG. 6 is a schematic diagram illustrating the switching of the pixel circuit in the second stage according to an embodiment. 4 and 6, in the second stage 42, the control signals S1[N], S2[N] are at the high level VGH, the control signals EM[N], EM[N+1] are at the low level VGL, The _data voltage Vdata represents the brightness to be displayed. Therefore, the first switch T1 and the third switch T3 are turned off, and the second switch T2 , the fourth switch T4 , the fifth switch T5 and the sixth switch T6 are turned on. In the second stage, the potential of node C is the data voltage V _data , the potential of node B is the reference signal ref, and the potential of node A gradually drops to V _data +V _t2 , where V _t2 is the threshold voltage of the second switch T2 .

FIG. 7 is a schematic diagram illustrating switching of a pixel circuit in a third stage according to an embodiment. 4 and 7, in the third stage 403, the control signals S1[N], S2[N], EM[N+1] are at the low level VGL, and the control signal EM[N] is at the high level VGH. Therefore, the first switch T1 and the second switch T2 are turned on, and the third switch T3, the fourth switch T4, the fifth switch T5 and the sixth switch T6 are turned off. In the third stage 403 , the potentials of the nodes B and C are V _LED +OVSS, where V _LED is the threshold voltage of the light-emitting unit 310 . Since the potential of node B changes from ref in the second stage to VLED + _OVSS in the third stage by VLED + _OVSS -ref, the potential of node A changes from _Vdata + _Vt2 in the second stage 402 to V _data + V _t2 + V _LED + OVSS-ref for the third stage 403 .

FIG. 8 is a schematic diagram illustrating switching of a pixel circuit in a fourth stage according to an embodiment. 4 and FIG. 8 , in the fourth stage 404, the control signals EM[N], EM[N+1] are at the high level VGH, and the control signals S1[N], S2[N] are at the low level VGL. Therefore, the first switch T1 , the second switch T2 and the third switch T3 are turned on to generate the current I _d , and the fourth switch T4 , the fifth switch T5 and the sixth switch T6 are turned off. The magnitude of the above current I _d is represented by the following equation 1. [Mathematical formula 1]

Where K is a constant, VA is the potential of node _A , and _VC is the potential of node C. It is worth noting that in the formula 1, the threshold voltage V _t2 and the operating voltage OVSS cancel each other due to compensation, so the current I _d is not affected by the threshold voltage V _t2 and the operating voltage OVSS.

Next, the omission mode will be described. The omission mode appears after the normal mode. For example, one or more pictures can be set to be in normal mode, and the next one or more pictures can be set to omit mode. The brightness of the pixel remains unchanged. Since the brightness of the sub-pixels needs to be kept unchanged in the omission mode, the potential of the node A also needs to be kept unchanged. However, in the third stage 403 of the normal mode, the light-emitting unit 310 is reset. Therefore, the light-emitting unit 310 must also be reset in the omitted mode, otherwise a flickering phenomenon will occur. In the prior art, the source driver transmits the data voltage V _data in a certain stage of the skip mode to reset the light-emitting unit 310 , but this will increase the power consumption of the source driver. In the following embodiments, the light-emitting unit 310 is reset by the DC voltage V _dc , so the source driver does not need to transmit other signals to the light-emitting unit 310, so that power consumption can be saved. Specifically, FIG. 9 is a timing diagram illustrating a control signal in an omission mode according to an embodiment. In the omission mode, the pixel circuit operates in the first omission stage 901 , the second omission stage 902 , and the third omission stage 903 in sequence.

FIG. 10 is a schematic diagram of a switch illustrating a first omitted stage according to an embodiment. Referring to FIG. 9 and FIG. 10 , in the first omitted stage 901 , the control signals S1[N], S2[N], EM[N], EM[N+1], and SW are all at the low level VGL. Therefore, the first switch T1, the third switch T3, the fourth switch T4, the fifth switch T5, the sixth switch T6 and the control switch 141 are turned off. The first omitted stage 901 follows the fourth stage 404 of the normal mode, so the potential of node A is V _data +V _t2 +V _LED +OVSS-ref, and the second switch T2 is turned on.

FIG. 11 is a schematic diagram of a switch illustrating a second omitted stage according to an embodiment. Referring to FIG. 9 and FIG. 11 , in the second omitted stage 902, the control signals S1[N] and EM[N+1] are at the low level VGL, and the control signals S2[N], EM[N], and SW are at the high level bit. Therefore, the first switch T1, the second switch T2, the sixth switch T6 and the control switch 141 are turned on, and the third switch T3, the fourth switch T4 and the fifth switch T5 are turned off. In the second omission stage 902, the potential of node A remains unchanged, the potential of node C and node B is the same as the DC voltage V _dc , which is less than the threshold voltage of the light-emitting unit 310 (in some embodiments, the DC voltage V _{dc dc} can also be a ground voltage), so the light-emitting unit 310 is not turned on to emit light, and at this time, the light-emitting unit 310 is reset. The data voltage V _data remains unchanged, that is to say, the source driver 220 does not need to provide additional signals to the pixel circuit, which can save power consumption.

FIG. 12 is a schematic diagram illustrating a switch in a third omitted stage according to an embodiment. Referring to FIG. 9 and FIG. 12, in the third omitted stage 903, the control signals S1[N], S2[N], and SW are at the low level VGL, and the control signals EM[N], EM[N+1] are at the high level bit VGH. Therefore, the first switch T1 , the second switch T2 and the third switch T3 are turned on to generate the current I _d , and the fourth switch T4 , the fifth switch T5 , the sixth switch T6 and the control switch 141 are turned off. The magnitude of the current I _d is calculated as in the above-mentioned formula 1. Since the potential of the node A does not change, the magnitude of the current I _d does not change either.

In this embodiment, the control switch 141 is turned on in the second omitted stage 902 and turned off in other stages. However, since the sixth switch T6 can also decide when to apply the DC voltage V _dc to the light-emitting unit 310, in some implementations In the example, the control switch 141 may also be turned on during the first to third omitted stages 901 to 903 .

The above-mentioned embodiment uses the data line 151 as an example, and it is understood that the above-mentioned embodiment can also be applied to other data lines. In addition, the pixel circuits on the same data line can receive the DC voltage V _dc through the data line. In the above-mentioned display panel, since the DC voltage V _dc is used to reset the light-emitting unit 310 , the source driver does not need to provide additional signals, which can save power consumption. In addition, the control switches 141 to 148 already exist in the testing stage, so there is no need to add additional switches.

Although the present invention has been disclosed as above with examples, it is not intended to limit the present invention. Anyone with ordinary knowledge in the technical field can make some changes and modifications without departing from the spirit and scope of the present invention. The protection scope of the present invention shall be determined by the scope of the appended patent application.

100: Display panel 110: Display area 111: Sub-pixel 120: Non-display area 130: Test area 131: Test switch pads 132~134: Test data pads 141~148: Control switches 151~158: Data lines 210: Multi Worker 220: Source driver 300: Pixel circuit 310: Light-emitting units T1~T6: Switch C1: Capacitor 310-1, C1-1, T1-1, T2-1, T3-1, T4-1, T5-1 , T6-1, 141-1: first end 310-2, C1-2, T1-2, T2-2, T3-2, T4-2, T5-2, T6-2, 141-2: second end T1-3 , T2-3, T3-3, T4-3, T5-3, T6-3, 141-3: control terminal OVSS, OVDD: operating voltage EM[N], EM[N+1], S1[N], S2[ N], SW: Control signal ref: Reference signal V _data : Data voltage V _dc : DC voltage A, B, C: Node 401: First stage 402: Second stage 403: Third stage 404: Fourth stage VGH: High level VGL: Low level 901: The first omission stage 902: The second omission stage 903: The third omission stage GND: Ground voltage

In order to make the above-mentioned features and advantages of the present invention more obvious and easy to understand, the following embodiments are given and described in detail with the accompanying drawings as follows. FIG. 1 is a schematic diagram illustrating a display panel in a testing stage according to an embodiment. FIG. 2 is a schematic diagram illustrating a display panel according to an embodiment. FIG. 3 is a circuit diagram illustrating a pixel circuit according to an embodiment. FIG. 4 is a timing diagram illustrating control signals in a normal mode according to an embodiment. FIG. 5 is a schematic diagram illustrating switching of a pixel circuit in a first stage according to an embodiment. FIG. 6 is a schematic diagram illustrating the switching of the pixel circuit in the second stage according to an embodiment. FIG. 7 is a schematic diagram illustrating switching of a pixel circuit in a third stage according to an embodiment. FIG. 8 is a schematic diagram illustrating switching of a pixel circuit in a fourth stage according to an embodiment. FIG. 9 is a timing diagram illustrating control signals in an omission mode according to an embodiment. FIG. 10 is a schematic diagram of a switch illustrating a first omitted stage according to an embodiment. FIG. 11 is a schematic diagram of a switch illustrating a second omitted stage according to an embodiment. FIG. 12 is a schematic diagram illustrating a switch in a third omitted stage according to an embodiment.

300: Pixel circuit

310: Lighting unit

T1~T6: switch

141: Control switch

151: data line

C1: Capacitor

310-1, C1-1, T1-1, T2-1, T3-1, T4-1, T5-1, T6-1, 141-1: first end

310-2, C1-2, T1-2, T2-2, T3-2, T4-2, T5-2, T6-2, 141-2: second end

T1-3, T2-3, T3-3, T4-3, T5-3, T6-3, 141-3: Control terminal

OVSS, OVDD: operating voltage

EM[N],EM[N+1],S1[N],S2[N],SW: Control signal

ref: reference signal

V _data : data voltage

V _dc : DC voltage

A,B,C: Nodes

Claims (9)

A display panel has a display area and a non-display area, the display panel includes: multiple data lines; a control switch, the control switch has a control end, a first end and a second end, the first end of the control switch is connected to a DC voltage, and the second end of the control switch is connected to the data lines one of them; and a plurality of pixel circuits, each of the pixel circuits comprising: a light-emitting unit having a first end and a second end, the first end of the light-emitting unit is connected to a first operating voltage; A first switch has a first end, a second end and a control end, wherein the first end of the first switch is connected to the second end of the light-emitting unit, and the control end of the first switch is connected to the first control signal; a second switch, having a first end, a second end and a control end, wherein the first end of the second switch is connected to the second end of the first switch; A third switch has a first end, a second end and a control end, wherein the first end of the third switch is connected to the second end of the second switch, the second end of the third switch The terminal is connected to a second operating voltage, and the control terminal of the third switch is connected to a second control signal; A fourth switch has a first end, a second end and a control end, wherein the first end of the fourth switch is connected to a reference signal, and the second end of the fourth switch is connected to the light-emitting unit The second end of the first switch and the first end of the first switch, the control end of the fourth switch is connected to a third control signal; A capacitor has a first end and a second end, wherein the first end of the capacitor is connected to the second end of the light-emitting unit, the first end of the first switch and the first end of the fourth switch Two terminals, the second terminal of the capacitor is connected to the control terminal of the second switch; A fifth switch has a first end, a second end and a control end, wherein the first end of the fifth switch is connected to the second end of the second switch and the first end of the third switch terminal, the second terminal of the fifth switch is connected to the second terminal of the capacitor and the control terminal of the second switch, and the control terminal of the fifth switch is connected to the third control signal; and A sixth switch has a first end, a second end and a control end, wherein the first end of the sixth switch is connected to the second end of the first switch and the first end of the second switch terminal, the second terminal of the sixth switch is connected to one of the data lines, the control terminal of the sixth switch is connected to a fourth control signal, wherein in a first mode, the control switch is turned off, Wherein, in at least one stage of a second mode, the control switch is turned on. The display panel of claim 1, wherein the control switch is disposed in the non-display area, the control end of the control switch is used to connect to a test switch pad in a testing stage, and the first end of the control switch is in the The test stage is connected to a test data pad. The display panel of claim 2, wherein the test switch pad and the test data pad are removed after the test phase is performed. The display panel of claim 1, wherein each of the pixel circuits is configured to operate a first stage, a second stage, a third stage and a fourth stage in sequence in the first mode, In the first stage, the first switch and the sixth switch are turned off, the second switch, the third switch, the fourth switch and the fifth switch are turned on, In the second stage, the first switch and the third switch are turned off, the second switch, the fourth switch, the fifth switch and the sixth switch are turned on, In the third stage, the first switch and the second switch are turned on, the third switch, the fourth switch, the fifth switch and the sixth switch are turned off, In the fourth stage, the first switch, the second switch and the third switch are turned on, and the fourth switch, the fifth switch and the sixth switch are turned off. The display panel of claim 4, wherein each of the pixel circuits is configured to sequentially operate a first omission stage, a second omission stage and a third omission stage in the second mode, wherein in the first omission stage, the first switch, the third switch, the fourth switch, the fifth switch and the sixth switch are turned off, Wherein in the second omission stage, the first switch, the sixth switch and the control switch are turned on, the third switch, the fourth switch and the fifth switch are turned off, In the third omitted stage, the first switch, the second switch and the third switch are turned on, and the fourth switch, the fifth switch and the sixth switch are turned off. The display panel of claim 5, wherein the light-emitting unit is a light-emitting diode, and the DC voltage is lower than a threshold voltage of the light-emitting unit. The display panel of claim 5, wherein the first to sixth switches are N-type transistors, the first operating voltage is lower than the second operating voltage, wherein in the first omitted stage, the first control signal, the second control signal, the third control signal and the fourth control signal are at a low level, wherein in the second omission stage, the first control signal and the fourth control signal are at a high level, the second control signal and the third control signal are at the low level, In the third omitted stage, the first control signal and the second control signal are at the high level, and the third control signal and the fourth control signal are at the low level. A display panel as described in claim 7, Wherein in the first stage, the first control signal and the fourth control signal are at the low level, the second control signal and the third control signal are at the high level, Wherein in the second stage, the first control signal and the second control signal are at the low level, the third control signal and the fourth control signal are at the high level, Wherein in the third stage, the first control signal is at the high level, the second control signal, the third control signal and the fourth control signal are at the low level, In the fourth stage, the first control signal and the second control signal are at the high level, and the third control signal and the fourth control signal are at the low level. The display panel of claim 1, wherein the first mode is a normal mode, and the second mode is an omitted mode.

Images