TWI758681B - Integrated circuit, memory, and memory array - Google Patents

Abstract

Fin-based well straps are disclosed for improving performance of memory arrays, such as static random access memory arrays. An exemplary well strap cell includes a p-well, a first n-well, and a second n-well disposed in a substrate. The p-well, the first n-well, and the second n-well are configured in the well strap cell such that a middle portion of the well strap cell is free of the first n-well and the second n-well along a gate length direction. The well strap cell further includes p-well pick up regions to the p-well and n-well pick up regions to the first n-well, the second n-well, or both. The p-well has an I-shaped top view along the gate length direction.

Description

Integrated circuits, memories and memory arrays

The present disclosure relates to a memory structure, and more particularly, to a fin ribbon cell structure.

Static random access memory (SRAM) generally refers to any memory or storage that retains stored data when power is applied. As integrated circuit (IC) technology evolves toward smaller technologies, SRAMs often incorporate fin structures, such as fin field effect transistors (FinFETs), into SRAM cells to increase performance, where each A SRAM cell can store one bit of data. Since the performance of SRAM cells is layout dependent (for example, it has been observed that the performance of internal SRAM cells of an SRAM array is not the same as the performance of edge SRAM cells of an SRAM array), well strap cells The system is used to stabilize the well potential and promote the uniform distribution of charges in the entire SRAM array, so that the performance between the SRAM cells of the SRAM array is uniform. However, as fin structures shrink in size, fin well strip cells have been observed to increase pick-up resistance and/or reduce the latch-up performance of SRAM arrays. Thus, while existing well strip cells for SRAM arrays are generally adequate for their intended purpose, they are not entirely satisfactory in all respects.

The present disclosure provides many different embodiments. Disclosed herein are fin wells for memory array (eg, SRAM array) performance and methods of making the same. An exemplary integrated circuit has a first doping configuration including a first well, a second well, and a third well disposed in a substrate. The second well region is disposed between the first well region and the third well region, and the first well region and the third well region are doped with a first type dopant, and the second well region is doped with a The second type dopant is doped. The integrated circuit further includes a well band cell disposed adjacent to the memory cell. The well zone cell has a first well zone zone, a second well zone zone, and a third well zone zone, and the second well zone zone is arranged between the first well zone zone and the third well zone zone. The first well zone and the third well zone have a first well doping configuration. The second well region has a second doping configuration including a fourth well region doped with the first type dopant. The well zone cell includes a first well pickup area connected to a fourth well area, and a second well pickup area connected to the second well area.

The present disclosure further discloses a well band cell disposed between a first memory cell and a second memory cell. The well strip cell includes a P-type well, a first N-type well, and a second N-type well in a substrate. The P-type well, the first N-type well, and the second N-type well are arranged in the well zone cell, so that a middle part of the well zone cell does not have the first N-type well and the second N-type well in the length direction of a gate. Two N-type wells. The well zone cell further includes a P-well pickup area connected to a P-type well, an N-type well pickup area connected to a first N-type well, a second N-type well, or both.

The present disclosure further discloses a memory array including a first memory cell row and a second memory cell row. Each memory cell of the first memory cell row has a first well doping configuration. Each memory cell of the second row of memory cells has a first well doping configuration. The memory array includes a well with a cell row disposed between the first memory cell row and the second memory cell row. Each well zone cell within the well zone cell row includes a P-type well zone disposed between a first N-type well zone and a second N-type well zone, wherein the first N-type well zone and the second N-type well strip has a first well doping configuration, and the P-type well strip has a second well doping configuration different from the first well doping configuration.

The following disclosure provides many different embodiments or examples for implementing different features of the present invention. The following disclosure describes specific examples of various components and their arrangements to simplify the description. Of course, these specific examples are not intended to be limiting. For example, if the present disclosure describes that a first feature is formed on or over a second feature, it may include embodiments in which the first feature and the second feature are in direct contact, and may also include embodiments where additional features are formed. An embodiment in which the first feature and the second feature may not be in direct contact between the first feature and the second feature. In addition, different examples of the following disclosure may reuse the same reference symbols and/or signs. These repetitions are for the purpose of simplicity and clarity and are not intended to limit the specific relationship between the various embodiments and/or structures discussed.

Furthermore, the present disclosure may repeat reference numerals and/or letters in various instances. The above repetition is for simplicity and clarity, and is not by itself indicative of the various embodiments discussed and/or relationships between. In the present disclosure below, a feature is on top of another feature, a feature is connected to another feature, and/or a feature is coupled to another feature may include embodiments formed in direct contact, and also Embodiments formed by sandwiching additional features between features may be included so that the features may not be in direct contact. Additionally, spatially related terms such as "lower", "higher", "horizontal", "vertical", "over", "overlays", "under" ", "downward," "above," "below," "top," "bottom," and derivatives thereof (eg, "horizontal," "downward," "upward") are used for convenience Relationship of one feature of the present disclosure to another. Spatially relative terms are intended to cover different orientations of the device, including functional components.

For advanced integrated circuit technology, fin field effect transistors (FinFETs), also known as non-planar transistors, have become popular and promising candidates for high performance and low leakage applications. Memory arrays, such as static random access memory (SRAM) arrays, often include fin field effect transistors (FinFETs) in memory cells to improve performance, where each memory cell can Stores one bit of data. The performance of memory cells is largely dependent on layout. For example, it has been observed that the internal memory cells of a memory array behave differently than the edge memory cells of the memory array. In some implementations, internal memory cells and edge memory cells exhibit different threshold voltages (V _t ), different on-currents (I _on ), and/or different off-currents (I _off ). Fin-well strip cells have thus been implemented to stabilize the well potential, promoting uniform charge distribution throughout the memory array, resulting in uniform performance among the memory cells of the memory array. A fin well tie (also referred to as an electrical tie) electrically connects a well region of a fin field effect transistor corresponding to a memory cell to a voltage node (or voltage line). For example, a fin N-well strip electrically connects an N-well corresponding to a P-type finFET to a voltage node (eg, a voltage node associated with the P-type transistor), and a fin The P-type well strip electrically connects a P-type well region corresponding to an N-type FinFET to a voltage node (eg, a voltage node associated with the N-type transistor).

As finFET technology progresses to smaller technology nodes (eg, 20 nm, 16 nm, 10 nm, 7 nm, and smaller), it is observed to reduce pin pitch and reduce fin The width (pin width) reduces the benefits provided by the fin well. For example, it has been observed that reducing fin width to increase well pick-up resistance makes the one-well pick-up resistance of finned (non-planar) well strips much higher than that of planar well strips. Such increased well pickup resistance has been observed to reduce the latch-up performance of memory arrays using fin well straps. The present disclosure therefore proposes modifications to fin wells that can achieve improved performance. For example, as described herein, it has been observed to modify a well doping configuration of the fin well strip cell such that the well doping configuration of the fin well strip cell is different from that of the fin memory cell One well doping configuration, which significantly improves memory performance. In some embodiments, removing the N-type well from the P-type well strip of the fin well strip cell does not affect the desired characteristics (eg, voltage threshold) and/or the corresponding fin field effect transistor (FinFET) thereof. Or where significant modifications to existing manufacturing techniques are required, the well pickup resistance associated with this P-type well zone is reduced. In some embodiments, the P-type well zone includes only one P-type well, whereas the N-type well zone includes an N-type well disposed between the P-type wells. In some embodiments, the well doping configuration of such an N-type well strip is the same as the well doping configuration within the fin cell. In some embodiments, a fin well zone includes a P-type well zone disposed between a plurality of N-type well zones, wherein the P-type well of the P-type well zone and the P-type well of the N-type well zone Combined into a type I p-well in the fin-well strip cell. In some embodiments, the N-type well zone is an edge portion of the fin well zone cell, and the P-type well zone is a middle portion of the fin well zone cell. In some embodiments, the disclosed fin well strip cell is disposed between a plurality of memory cells. The proposed fin well strip cell structure for improving memory performance is described below. Different embodiments may have different advantages, and no particular advantage is required for any embodiment.

FIG. 1 is a schematic plan view of a memory 10 that can implement the configuration well strip described herein according to an embodiment of the present disclosure. The memory 10 is configured as a static random access memory (SRAM). However, the present disclosure contemplates embodiments in which the memory 10 is configured as another type of memory, such as a dynamic random access memory (DRAM), a non-volatile random access memory (NVRAM), a flash memory , or other suitable memory. The memory 10 may be included in a microprocessor, a memory, and/or other integrated circuit (IC) device. In some implementations, memory 10 may be part of an integrated circuit chip, a single chip (SOC), or a portion thereof, and includes various passive and active microelectronic devices such as resistors, capacitors, inductors, two Polar Body, P-Type Field Effect Transistor (PFET), N-Type Field Effect Transistor (NFET), Metal-Oxide-Semi-Field-Effect Transistor (MOSFET), Complementary Metal-Oxide-Semi-Field Effect Transistor (CMOS), Bipolar Junction Type Transistor (BJT), Laterally Diffused Metal Oxide Transistor (LDMOS), High Voltage Transistor, High Frequency Transistor, other suitable components, or a combination thereof. Depending on the design requirements of the memory 10, the various transistors may be planar transistors or multi-gate transistors, such as fin field effect transistors (FinFETs). For clarity, Figure 1 has been simplified to better understand the inventive concepts of the present disclosure. Additional features may be added to memory 10 , and some of the features below may be replaced, changed, or excluded in other embodiments of memory 10 .

Memory 10 includes a memory array 12A and a memory array 12B, where each of memory array 12A and memory array 12B includes memory cells 20, such as SRAM cells (also referred to as SRAM cells) for storing data. bit cells). The memory cell 20 includes various transistors, such as P-type FinFET and/or N-type FinFET, configured to facilitate reading and writing of data from the memory cell 20 into memory cell 20. The memory cells 20 are arranged in row 1 (C1) to row N (CN) along a first direction (here, the y direction), and along a second direction (here, the x direction) ) are set in the 1st column (R1) to the Mth column (RM), where N and M are positive integers. Each of rows 1 to N includes a bit line pair along the first direction, such as a bit line (BL) and a complementary bit line bar (BLB), which helps Data is read from and/or written to the corresponding memory cells 20 in true form and complementary form on a row-by-row basis. Each of row 1 ( R1 ) to row M (RM) includes a word line (WL) to facilitate row-by-row access to the corresponding memory cell 20 . Each memory cell 20 is electrically connected to a respective bit line (BL), a respective complementary bit line (BLB), and a respective word line (WL), and these bit lines ( BL), a complementary bit line (BLB) and a word line (WL) are electrically connected to the controller 60 . Controller 60 is configured to generate one or more signals to select at least one word line and at least one pair of bit lines (here, bit lines and complementary bit lines) for use in read operations and/or Or at least one memory cell 20 is accessed during a write operation. Controller 60 includes any circuitry suitable for facilitating reading data from or writing data to memory cells 20, including a row decode circuit, a column decode circuit, a row select circuit, a column select circuit, a read /Write circuitry (eg, configured to read data from and/or write data to memory cell 20, which corresponds to a selected bit line pair ( In other words, a selected row)), other suitable circuits, or a combination thereof. In some embodiments, the controller 60 includes at least one sense amplifier configured to detect and/or amplify the voltage difference of the selected bit line pair, but the present disclosure is not limited thereto. In some embodiments, the sense amplifier is configured to latch or otherwise store the data value of the voltage difference.

A plurality of dummy cells, such as edge dummy cells and well strap cells, are arranged around the memory 10 to ensure uniform performance of the memory cells 20 . Dummy cells are configured to be physically and/or structurally similar to memory cells 20, but do not store data. For example, dummy memory cells may include P-wells, N-wells, fin structures (including one or more fins), gate structures, source/drain features, and/or contact features. Well strip cells generally refer to an N-type well configured to electrically connect a voltage to the memory cell 20, a P-type well of the memory cell 20, or a dummy cell of both. In the depicted embodiment, memory 10 includes edge dummy cells disposed along a first direction (here, the y-direction) within an edge dummy cell row 35A and an edge dummy cell row 35B cell 30 in which each of the 1st to Mth columns of the memory cell 20 is arranged in an edge dummy cell 30 in edge dummy cell row 35A and in an edge dummy cell 30 in edge dummy cell row 35B An edge is placed between cells 30 . In the process of the described embodiment, each of rows 1 through M of memory cells 20 are disposed between edge dummy cells 30 . In some embodiments, edge dummy cell row 35A and/or edge dummy cell row 35B are along at least a pair of bit lines (here bit lines and complementary bit lines) that are substantially parallel to memory 10 line) extension. In some embodiments, edge dummy cells 30 are configured to connect respective memory cells 20 to respective word lines. In some embodiments, edge dummy cells 30 include circuitry for driving word lines. In some embodiments, the edge dummy cell 30 is electrically connected to a power supply voltage V _DD (eg, a positive power supply voltage) and/or a power supply voltage V _SS (eg, an electrical ground).

In the course of the described embodiment, a wellstrip row 40 includes wellstrip cells 50 disposed along the first direction (here, the y-direction). Well strip rows 40 are disposed between memory array 12A and memory array 12B such that each column series of memory cells 20 within memory array 12A is disposed on a respective edge dummy cell 30 and a respective Between a well strip cell 50 and each row of memory cells 20 within the memory array 12B is disposed between a respective one well strip cell 50 and a respective one edge dummy pack cell 30 . In some embodiments, well row 40 extends along at least a pair of bit lines (here, bit lines and complementary bit lines) that are substantially parallel to memory 10 . In the described embodiment, the well cell 50 includes an N-type well, a P- well, or a combination thereof. In some embodiments, well zone cell 50 includes a P-type well zone disposed between N-type well zones. The N-well strip is configured to electrically couple an N-well corresponding to at least one P-type FFET of the memory cell 20 to a voltage source. The P-well is configured to electrically couple a P-well corresponding to at least one N-type FinFET of the memory cell 20 to a voltage source. As described herein, well strap cells are configured to significantly reduce well pickup resistance, improving the latch-up performance of memory 10 .

FIGS. 2A to 2G are partial schematic diagrams of part or all of a one-well strip cell, such as the well strip cell 50 implemented in the memory 10 in FIG. 1 , according to various parts of the present disclosure. FIG. 2A is a simplified top view of the well cell 50; FIG. 2B is a schematic cross-sectional view of the well cell 50 along line BB of FIG. 2A (eg, in an xy plane); FIG. 2C is along the Figure 2A is a schematic cross-sectional view of the well cell 50 along line CC (eg, at a yz plane); Figure 2D is a schematic cross-sectional view of the well cell 50 along line 2A DD (eg, at a yz plane). xz plane); FIG. 2E is a schematic cross-sectional view of the well cell 50 along line EE of FIG. 2A (eg, in an xz plane); FIG. 2F is the well cell along line FF of FIG. 2A 50 is a schematic cross-sectional view (eg, in an xz plane); and FIG. 2G is a schematic cross-sectional view (eg, in an xz plane) of well zone cell 50 along line GG of FIG. 2A. The well band cell 50 is disposed between an SRAM cell 20A of the memory cell 20 and an SRAM cell 20B of the memory cell 20 . In some embodiments, the width of the well strip cell (here along a y-direction) is substantially equal to the width of the memory cell 20 (here SRAM cells 20A, 20B). The well zone cell 50 includes a P-type well zone 50A disposed between an N-type well zone 50B and an N-type well zone 50C along the length of the well zone cell 50 (here, along an x-direction). In such a configuration, N-type well strips 50B are disposed adjacent to a respective memory cell 20, such as SRAM cell 20A, and N-type well strips 50C are disposed adjacent to a respective one of memory cells 20, such as SRAM cell 20B. In some embodiments, the P-type well zone 50A is disposed along the length of a fin between the N-type well zone 50B and the N-type well zone 50C. The P-well strip 50A is configured to electrically connect the P-well of the memory cell 20 to a first power supply voltage, such as a power supply voltage V _SS . Each of N-well strip 50B and N-well strip 50C is configured to electrically connect the N-well of memory cell 20 to a second power supply voltage, such as a power supply voltage V _DD . In some embodiments, the power supply voltage V _DD is a positive power supply voltage, and the power supply voltage V _SS is an electrical ground. For clarity, Figures 2A to 2G have been simplified to better understand the inventive concepts of the present disclosure. Additional features may be added to well strip cell 50, and in other embodiments of well strip cell 50, some of the features described below may be replaced, modified, or eliminated.

Well strip cell 50 is configured to be physically and/or structurally similar to memory cell 20 . For example, the well strip cell 50 includes a substrate (wafer) 110 . In the described embodiment, the substrate 110 is a bulk substrate comprising silicon. Alternatively or additionally, the bulk substrate includes another elementary semiconductor, such as germanium; a compound semiconductor, such as silicon carbide, phosphorus silicide, gallium arsenide, gallium phosphide, indium phosphide, indium arsenide, Indium antimonide, zinc oxide, zinc selenide, zinc sulfide, zinc telluride, cadmium selenide, cadmium sulfide, and/or cadmium telluride; alloy semiconductors such as silicon germanium (SiGe), silicon titanium cyanine (SiPC), phosphorus Gallium Arsenide (GaAsP), Indium Aluminum Arsenide (AlInAs), Gallium Aluminum Arsenide (AlGaAs), Gallium Indium Arsenide (GaInAs), Gallium Indium Phosphide (GaInP), and/or Gallium Indium Arsenide Phosphide (GaInAsP) ; other Group III-V materials; other Group II-IV materials; or a combination thereof. Alternatively, the substrate 110 is a semiconductor-on-insulator (semiconductor-on-insulator) substrate, such as a silicon-on-insulator (SOI) substrate, a silicon germanium-on-insulator (SGOI) substrate , or a germanium-on-insulator (GOI) substrate. The semiconductor-on-insulator substrate may be fabricated by separation by implantation of oxygen (SIMOX), wafer bonding, and/or other suitable methods. The substrate 110 includes doped regions, such as an N-row doped region 112A, an N-type doped region 112B, an N-type doped region 112C, an N-type doped region 112D, a P-type doped region 114A, and a P-type doped region 112A. Type doped region 114B, a P-type doped region 114C (hereinafter referred to as N-type wells 112A-112D and P-type wells 114A-114C). N-type doped regions, such as N-type wells 112A-112D, are doped with N-type dopants, such as phosphorus, arsenic, other N-type dopants, or a combination thereof. P-type doped regions, such as P-type wells 114A-114C, are doped with P-type dopants, such as boron, indium, other P-type dopants, or combinations thereof. In some embodiments, the substrate 110 includes a doped region composed of a combination of P-type dopants and N-type dopants. Various doped regions can be formed directly on and/or in the substrate 110, eg, to provide a P-well structure, an N-type well structure, a dual-well structure, a bump structure, or a combination thereof. An ion implantation process, a diffusion process, and/or other suitable doping processes may be performed to form various doped regions.

The various doped regions are configured according to the design requirements of the memory 10 . Each of the SRAM cells 20A, 20B includes an N-type well region disposed between the P-type wells. For example, SRAM cell 20A includes N-type well 112A and P-type well 114A, and SRAM cell 20B includes N-type well 112B and P-type well 114B. The N-type wells 112A, 112B are configured for a P-type metal oxide semi-fin field effect transistor (PMOS FinFET), such as a pull-up (PU) FinFET, and the P-type wells 114A, 114B are Configured for use with N-type metal oxide semi-fin field effect transistors (NMOS FinFETs), such as pull-down (PD) fin field effect transistors. P-type well 114A includes a P-type well sub-region 114A-1 and a P-type well sub-region 114A-2, and P-type well 114B includes a P-type well sub-region 114B-1 and a P-type well sub-region 114B-2 . The N-type well 112A is disposed along the y direction (here along a gate length direction) between the P-type well sub-region 114A-1 and the P-type well sub-region 114A-2, and the N-type well 112B is along the It is disposed between the P-type well sub-region 114B-1 and the P-type well sub-region 114B-2 along the y direction. N-well 112A, P-well sub-region 114A-1, and P-well sub-region 114A-2 extend along an entire length of SRAM cell 20A such that N-well 112A, P-well sub-region 114A-1 And the length of the P-well sub-region 114A-2 is substantially equal to the length of the SRAM cell 20A (here along the x-direction). N-well 112B, P-well sub-region 114B-1, and P-well sub-region 114B-2 extend along the entire length of SRAM cell 20B such that N-well 112B, P-well sub-region 114B-1 , and the length of the P-well subregion 114B-2 is substantially equal to the length of the SRAM cell 20B (here along the x-direction). The N-type wells 112A, 112B have a width W1, the P-type well sub-regions 114A-1, 114B-1 have a width W2, and the P-type well sub-regions 114A-2, 114B-2 have a width W3. The widths W1, W2, and W3 are smaller than the widths of the SRAM cells 20A, 20B. In the described embodiment, the sum of width W1, width W2, and width W3 is substantially equal to the width of SRAM cells 20A, 20B (in other words, W1+W2+W3=width of SRAM cells 20A, 20B ). In some embodiments, width W1, width W2, and width W3 are the same. In some embodiments, width W1, width W2, and width W3 are not the same. In some implementations, width W2 and width W3 are the same, but different from width W1. The present disclosure contemplates any configuration of width Wl, width W2, and width W3.

The present disclosure proposes a well doping configuration within well strip cell 50 that significantly reduces well pick-up resistance, especially in relation to P-type well strip 50A. In FIGS. 2A-2G, the well strip cell 50 includes an N-type well 112C, an N-type well 112D, and a P-type well 114C. P-well 114C is I-shaped in plan view along the width of wellstrip cell 50 (here along the y-direction), and in plan view along the length of wellstrip cell 50 (here along the x-direction) See it as an H shape. For example, P-well 114C includes a P-well sub-region 114C-1, a P-well sub-region 114C-2, and a P-well sub-region 114C-3. The N-type well 112C is located between the P-type well sub-region 114C-1 and the P-type well sub-region 114C-2 in the N-type well zone 50B, and the N-type well 112D is located in the P-type well zone 50C in the N-type well zone 50C. Type well sub-region 114C-1 and P-type well sub-region 114C-2. N-type well 112C extends uninterrupted into N-type well 112A, and N-type well 112D extends uninterrupted into N-type well 112B. In some embodiments, no actual interface is observed between N-type well 112C and N-type well 112A, and no actual interface is observed between N-type well 112D and N-type well 112B. The N-type well 112C has a length L1 and a width W4. The N-well 112D has a length L2 and a width W5. The length L1 is less than the length of the well zone cell 50 and is substantially equal to a length of the N-type well zone 50B. The length L2 is less than the length of the well zone cell 50 and is substantially equal to a length of the well zone cell 50C. The widths W4 and W5 are substantially equal to the widths W1 of the N-type wells 112A and 112B of the SRAM cells 20A and 20B. Although width W4 is larger or smaller than width W5 in embodiments contemplated by the present disclosure, in the described embodiment, width W4 is substantially equal to width W5.

The P-well sub-regions 114C-1, 114C-2 extend along the entire length of the well zone cell 50. The P-well sub-zones 114C-1, 114C-2 thus span the P-well zone 50A, the N-well zone 50B, and the N-well zone 50C. The P-well sub-region 114C-1 extends uninterrupted into the respective P-well sub-region 114A-1, 114B-1 of the P-wells 114A, 114B. In some embodiments, no actual interface can be observed between the P-well sub-region 114C-1 and the P-well sub-regions 114A-1, 114B-1. The P-well sub-region 114C-2 extends uninterrupted into the respective P-well sub-region 114A-2, 114B-2 of the P-wells 114A, 114B. In some embodiments, no actual interface can be observed between the P-well sub-region 114C-2 and the P-well sub-regions 114A-2, 114B-2. The P-well sub-region 114C-1 has a length L3 and a width W6. The P-well sub-region 114C-2 has a length L4 and a width W7. The lengths L3 and L4 are substantially equal to the length of the well zone cell 50 . The widths W6 and W7 are smaller than the width of the well strip cell 50 . In the depicted embodiment, the width W6 is substantially equal to the width W2 of the respective P-well sub-regions 114A-1, 114B-1 in the P-wells 114A, 114B, and the width W7 is substantially equal to the P-wells 114A, 114A, Width W3 of the respective P-well sub-regions 114A-2, 114B-2 in 114B. Although width W6 is larger or smaller than width W7 in embodiments contemplated by the present disclosure, in the described embodiment, width W6 is substantially equal to width W7.

P-well sub-region 114C-3 is disposed between P-well sub-region 114C-1 and P-well sub-region 114C-2 along the width of well zone cell 50 in P-well zone 50A such that P The P-well sub-region 114C-3, the P-well sub-region 114C-2, and the P-well sub-region 114C-1 are combined to span the entirety of the P-well zone 50A. The P-well sub-region 114C-3 is further disposed along the length of the well zone cell 50 between the N-well 112C and the N-well 112D. The P-well sub-region 114C-3 thus forms the well zone cell 50 and an intermediate portion of the P-well zone 50A. In some embodiments, the axis of symmetry of P-well sub-region 114C-3 along the width (here y) direction is substantially aligned with the axis of symmetry of P-well sub-region 114C-1 along the width direction and The axis of symmetry of the P-well sub-region 114C-2 along the width direction. In such an embodiment, the axes of symmetry of the P-type well sub-regions 114C-1, 114C-2, and 114C-3 are aligned with an axis of symmetry. The P-well sub-region 114C-3 has a length L5 and a width W8. The length L5 is less than the length of the well zone cell 50 and is substantially equal to a length of the P-type well zone 50A. The width W8 is smaller than the width of the well strip cell 50 . In the described embodiment, width W8 is substantially equal to width W4 of N-type well 112C and/or width W5 of N-type well 112D (and thus substantially equal to N-type well 112A in SRAM cells 20A, 20B , the width W1 of 112B). In the described embodiment, the sum of width W6, width W7, and width W8 is substantially equal to the width of well zone cell 50 (in other words, W6+W7+W8=width of well zone cell 50, And W8=width of well strip cell 50-(W6+W7)).

By implementing an I-shaped P-well 114C in well strip cell 50, the one-well doping configuration of P-well strip 50A is different from that of memory cell 20 (here, SRAM cells 20A, 20B) A well-doped configuration, and the well-doped configuration of the N-type well strips 50B, 50C is equivalent to the well-doped configuration of the memory cell 20 . For example, P-type well strip 50A includes only one P-type well and no N-type wells, N-type well strips 50B, 50C include an N-type well disposed between the P-type wells, and SRAM cells 20A, 20B include an N-type well disposed between the P-type wells An N-type well between the P-type wells. In such a configuration, the well pick-up resistance associated with P-type well strip 50A is not limited because the P-type wells of P-type well strip 50 are not divided into discrete sections like conventional well strips, but are instead Uninterrupted continuous extension into the P-well zone 50 . This enables the P-type well strip 50A to achieve perfect well pickup resistance and to block noise wells from N-type wells (eg, N-type well strips 50B, 50C). For example, it has been observed that eliminating the p-n junction of P-well 50A (so that the p-n depletion region can increase resistance when P-well 50A is connected to a voltage) to significantly reduce the wellness of P-well 50A pick-up resistance, resulting in an improvement in the performance of the memory 10 .

The well strip cell 50 further includes a fin 120 (also referred to as a fin structure or an active fin region) disposed on the substrate 110, wherein the fin 120 is configured to be equal to or similar to the N-type fins of the SRAM cells 20A, 20B The fins of the fin field effect transistor and/or the p-type fin field effect transistor. The fins 120 are substantially parallel to each other, and each of the fins 120 has a length defined in the x-direction, a width defined in the y-direction, and a height defined in a z-direction. Each of the fins 120 has at least one channel region, at least one source region, and at least one drain region defined along their length in the x-direction, wherein a channel region is disposed in a source region and a drain region. between the electrode regions (often referred to as source/drain regions). The channel region includes a top portion defined between the sidewall portions, wherein the top portion and the sidewall portion engage a gate structure (as described below) so that current can flow between the source/drain regions during operation. The source/drain regions also include a top portion defined between the sidewall portions. In some embodiments, the fins 120 are part of the substrate 110 (eg, part of a material layer of the substrate 110). For example, the substrate 110 includes silicon, and the fins 120 include silicon. Alternatively, in some embodiments, the fins 120 are defined in a layer of material, such as one or more layers of semiconductor material overlying the substrate 110 . For example, the fin 120 may include a semiconductor layer stack having various semiconductor layers (eg, a heterostructure) disposed over the substrate 110 . The semiconductor layer may comprise any suitable semiconductor material, such as silicon, germanium, silicon germanium, other suitable semiconductor materials, or combinations thereof. The semiconductor layers may comprise the same or different materials, etch rates, composition atomic percentages, compositional weight percentages, thicknesses, and/or configurations. In some embodiments, the semiconductor layer stack includes alternate semiconductor layers, such as a semiconductor layer composed of a first material and a semiconductor layer composed of a second material. For example, the semiconductor layer stack is an alternate stack of silicon layers and silicon germanium layers (eg, silicon germanium (SiGe), silicon (Si)...)). In some embodiments, the semiconductor layer stack includes semiconductor layers of the same material but with alternate composition atomic percentages, eg, a semiconductor layer having a first atomic percent composition and a semiconductor layer having a second atomic percent composition. For example, the semiconductor layer stack includes silicon and/or germanium atomic percentages with alternating (eg, Si _a Ge _b /Sic Ge _d /..., where a, _c are different silicon atomic percentages, and b, d is the different atomic percent germanium) of the silicon germanium layers.

The fins 120 are formed on the substrate 110 by any suitable process. In some embodiments, a combination of doping, lithography, and/or etching processes are performed to define the fins 120 extending from the substrate 110 . For example, forming fins 120 includes performing a lithography process to form a patterned mask layer on substrate 110 (or a layer of material disposed over substrate 110, such as a heterostructure), and performing an etching process Used to transfer the pattern defined in the patterned mask layer to the substrate 110 (or the material layer disposed on the substrate 110, such as the heterostructure). The lithography process may include forming a photoresist layer (eg, by spin coating) on a photomask layer disposed over the substrate 110, and performing a pre-exposure bake process , using a mask to perform an exposure process, perform a post-exposure baking process, and perform a developing process. In the exposure process, the photoresist layer is exposed to radiation (eg, ultraviolet (UV)), deep ultraviolet (DUV), or extreme ultraviolet (EUV), wherein the mask block is based on the mask reticle pattern and/or reticle type (eg, binary reticle, phase-shift reticle, or EUV reticle) to block, emit, and/or reflect radiation to the photoresist layer such that the reticle corresponds to An image of the pattern is projected on the photoresist layer. Since the photoresist layer is sensitive to radiation energy, the exposed part of the photoresist layer undergoes chemical changes, and the exposed (or unexposed) part of the photoresist layer depends on the characteristics of the photoresist layer and the conditions in the development process. The characteristics of a developer used are eliminated during the development process. After development, the patterned photoresist layer includes a photoresist pattern corresponding to the photomask. The etch process uses the patterned photoresist layer as an etch mask to remove portions of the mask layer, and then uses the patterned mask layer to remove portions of the substrate 110 (or a layer over the substrate 110 ). material layer). The etching process may include a dry etching process (eg, a reactive ion etching (RIE)), a wet etching process, other suitable etching processes, or a combination thereof. The patterned photoresist layer is removed during or after the etch process by, for example, a photoresist removal process. Alternatively, or even worse, the fins 120 are formed by a multiple patterning process, such as a double patterning lithography (DPL) process (eg, a lithography-etch-lithography-etch) -etch-lithography-etch: LELE) process, a self-aligned double patterning (SADP) process, a spacer-is-dielectric patterning (SIDP) process, other double patterning process, or a combination thereof), a triple patterning process (eg, a lithography-etch-lithography-etch-lithography-etch: LELELE) process, a self- self-aligned triple patterning (SATP) process, other triple patterning process, or a combination thereof), other multi-patterning process (eg, self-aligned quadruple patterning: SAQP) ) process), or a combination thereof. Typically, dual patterning processes and/or multi-patterning processes combine lithography and self-alignment processes, allowing the creation of patterns with pitches smaller than that obtainable using a single direct lithography process. For example, in some embodiments, a mandrel layer is used as an etch mask to remove portions of the mask layer, the mandrel layer being formed using a spacer patterning technique form. For example, forming the mandrel layer includes forming a patterned sacrificial layer (the patterned sacrificial layer including sacrificial features having a first pitch), forming a spacer layer over the patterned sacrificial layer, etching the spacer layer to form spacers along the sidewalls of each sacrificial feature (eg, removing the spacer layer from the sacrificial feature) A top surface of the feature and a portion of the top surface of the reticle layer are removed), and the patterned sacrificial layer is removed, leaving a second pitch (which may be referred to as a patterned spacer layer, the patterned spacer layer) The layer includes a spacer that exposes the openings of the portion of the reticle layer. The mandrel layer and its mandrel system can thus be referred to as a spacer layer and spacer, respectively. In some embodiments, the spacer layer is conformally formed over the patterned sacrificial layer such that the thickness of the spacer layer is substantially uniform. In some embodiments, the spacers are trimmed before or after removal of the patterned sacrificial layer. In some embodiments, a direct self-assembly (DSA) technique is performed while forming the fins 120 .

An isolation feature 122 is formed on and/or within the substrate 110 for isolating various regions of the IC device 100, such as various device regions. For example, isolation features 122 separate and isolate active device regions and/or passive device regions (eg, various FinFETs of memory 10 ) from each other. The isolation features 122 further separate and isolate the fins 120 from each other. In the depicted embodiment, isolation feature 122 includes a bottom of fin 120 . The isolation features 122 include silicon oxide, silicon nitride, silicon oxynitride, other suitable isolation materials (eg, including silicon, oxygen, nitrogen, carbon, and/or other suitable isolation compositions), or combinations thereof. The isolation features 122 may include different structures, such as shallow trench isolation (STI), deep trench isolation (DTI), and/or local oxidation of silicon (LOCOS) structures. In some embodiments, shallow trench isolation (STI) features are formed by etching a trench in substrate 110 (eg, by using a dry etch process and/or a wet etch process) and filled with insulating material The trenches (eg, by using a chemical vapor deposition process or a spin-on glass process). A chemical mechanical polishing (CMP) may be performed to remove excess insulating material and/or to planarize a top surface of the isolation features 122 . In some embodiments, after the fins 120 are formed, shallow trench isolation (STI) features are formed by depositing an insulating material on the substrate 110 (in some embodiments, such that the insulating material layer fills the fins 120 ) the trench between), and the insulating material layer is etched back to form isolation features 122. In some embodiments, isolation features 122 comprise a multi-layer structure filling trenches, such as a bulk dielectric layer disposed over a liner dielectric layer, wherein the bulk dielectric layer and the The liner dielectric layer includes materials according to design requirements (eg, includes a bulk dielectric layer that includes silicon nitride disposed over a liner dielectric layer, and the liner dielectric layer includes thermal oxide ). In some embodiments, isolation features 122 include a dielectric layer disposed over a doped liner layer including, for example, boron silicate glass (BSG) or phosphosilicate glass (PSG).

The well strip cell 50 further includes a gate structure 130 disposed over the fins 120 and the isolation features 122, wherein the gate structure 130 is configured to be the same or similar to the N-type FinFETs of the SRAM cells 20A, 20B and/or the gate structure of the P-type fin field effect transistor. The gate structures 130 extend along the y-direction (eg, substantially perpendicular to the fins 120 ) across the respective fins 120 such that the gate structures 130 cover upper portions of the respective fins 120 . The gate structure 130 is disposed on the channel region of the fin 120 and covers the channel region of the fin 120 so that the fin 120 is sandwiched between the respective source/drain regions. The gate structures 130 engage the respective channel regions of the fins 120 such that current can flow between the respective source/drain regions of the fins 120 during operation. The gate structure 130 in the well cell 50 is a dummy gate structure, while the gate structure in the memory cell 20 is an active gate structure (the gate structure 130 is configured the same as that in the memory cell 20). gate structure of the fin field effect transistor in element 20). The "active gate structure" is usually referred to as an electrical functional gate structure, and the "dummy gate structure" is usually referred to as an electrical non-functional gate structure. For example, the gate structure 130 mimics the physical properties of the active gate structure of the FFET in the memory cell 20, such as the physical size of the active gate structure, and still cannot be electrically operated (in other words, cannot so that current flows between the source/drain regions). In some embodiments, gate structure 130 achieves a substantially uniform process environment, eg, allowing epitaxial material to grow uniformly within the source/drain regions of fin 120 (eg, when forming epitaxial source/drain regions) region features), uniform etch rates in the source/drain regions of fin 120 (eg, when forming source/drain grooves), and/or uniformize a substantially flat surface (eg, by reducing Minimize (or avoid) CMP-induced dishing effects). In the depicted embodiment, gate structure 130 includes the same gate stack as the gate stack of the FinFET gate structure within memory cell 20 . For example, a gate stack of each gate structure 130 includes a gate dielectric 132, a gate dielectric 132 along gate spacers 138 disposed adjacent to the gate stack (eg, along sidewalls of the gate stack) electrode 134, and a hard mask layer 136. Gate dielectric 132 , gate electrode 134 , and/or hard mask layer 136 may include the same or different layers and/or the same or different materials in gate structure 130 . Since the gate structure 130 spans the P-type well zone 50A, the N-type well zone 50B, and the N-type well zone 50C, the gate structure 130 has the P-type well zone 50A, the N-type well zone 50B, and the N-type well zone Different layers in multiple regions corresponding to 50C. For example, the number, configuration, and/or material of layers of gate dielectric 132 and/or gate electrode 134 corresponding to P-well zone 50A are different from those corresponding to N-type well zone 50B and/or N-type well zone 50C The number, configuration and/or material of the layers of gate dielectric 132 and/or gate electrode 134 .

The gate stack of gate structure 130 is fabricated according to a gate last process, a gate first process, or a hybrid gate last/first process. In a post-gate process embodiment, the one or more gate structures 130 include dummy gate stacks that are subsequently replaced by metal gate stacks. The dummy gate stack, for example, includes an interface layer (including, for example, silicon oxide) and a dummy gate electrode layer (including, for example, polysilicon). In such an embodiment, the dummy gate electrode layer is removed to form openings (trenches) in which gate dielectrics 132 and/or gate electrodes 134 are subsequently formed. In some embodiments, a dummy gate stack of the at least one gate structure 130 is replaced by a metal gate stack, but a dummy gate stack of the at least one gate structure 130 remains. For example, some or all of gate structures 130 may include polysilicon gate stacks. The gate-last process and/or the gate-first process may implement deposition processes, lithography processes, etching processes, other suitable processes, or a combination thereof. The deposition process includes chemical vapor deposition (CVD), physical vapor deposition (PVD), atomic layer deposition (ALD), high density plasma chemical vapor deposition (high density) plasma CVD: HDPCVD), metal organic chemical vapor deposition (metal organic CVD: MOCVD), remote plasma chemical vapor deposition (remote plasma CVD: RPCVD), plasma enhanced chemical vapor deposition (plasma enhanced CVD: PECVD) , low-pressure chemical vapor deposition (low-pressure CVD: LPCVD), atomic layer chemical vapor deposition (atomic layer CVD: ALCVD), atmospheric pressure chemical vapor deposition (atmospheric pressure CVD: APCVD), electroplating, other suitable methods, or a combination thereof. The lithography patterning process includes photoresist coating (eg, spin-on coating), soft baking, mask aligning, exposure, post-exposure bake Post-exposure baking, developing photoresist, rinsing, drying (eg, hard baking), other suitable processes, or a combination thereof. Alternatively, the lithographic exposure process may be assisted, implemented or replaced by other methods, such as maskless lithography, e-beam writing, or ion-beam writing . The etching process includes a dry etching process, a wet etching process, other etching processes, or a combination thereof. A chemical mechanical planarization (CMP) process may be performed to remove any excess material of gate dielectric 132 , gate electrode 134 , and/or hard mask layer 136 to planarize gate structure 130 .

The gate dielectric 132 is disposed over the fins 120 and the isolation features 122 such that the gate dielectric 132 has a substantially uniform thickness. The gate dielectric 132 includes a dielectric material such as silicon oxide, a high-k dielectric material, other suitable dielectric materials, or a combination thereof. In the depicted embodiment, gate dielectric 132 includes one or more high-k dielectric layers including, for example, chromium, aluminum, zirconium, lanthanum, tantalum, titanium, yttrium, oxygen, nitrogen, other suitable compositions, or its combination. In some embodiments, the one or more high-k dielectric layers include hafnium dioxide (HfO ₂ ), hafnium silicon oxide (HfSiO), hafnium oxysilicon oxynitride (HfSiON), hafnium tantalum oxide (HfTaO), titanium oxide Hafnium (HfTiO), Zirconium Hafnium Oxide (HfZrO), Zirconium Dioxide (ZrO ₂ ), Alumina (Al ₂ O ₃ ), Hafnium Dioxide-Alumina (HfO ₂ -Al ₂ O ₃ ), Titanium Dioxide (TiO ₂ ) , tantalum oxide (Ta ₂ O ₅ ), lanthanum oxide (La ₂ O ₃ ), yttrium oxide (Y ₂ O ₃ ), other suitable high-k dielectric materials, or a combination thereof. A high-k dielectric material is generally referred to as a dielectric material with a high dielectric constant, for example, a dielectric constant greater than that of silicon oxide (k≒3.9). In some embodiments, the gate dielectric 132 further includes an interface layer (including a dielectric material such as silicon oxide) disposed between the high-k dielectric layer and the fins 120 and isolation features 122 .

A gate electrode 134 is disposed over the gate dielectric 132 . The gate electrode 134 includes a conductive material. In some embodiments, gate electrode 134 includes multiple layers, such as one or more capping layers, work function layers, glue/barrier layers, and/or metal fill (bulk) layers. A capping layer may include materials that avoid or eliminate compositional diffusion and/or reaction between the gate dielectric 132 and other layers of the gate structure 130 (in particular, the gate layer includes metal). In some embodiments, the capping layer includes a metal and nitrogen, such as titanium nitride (TiN), tantalum nitride (TaN), tungsten nitride (W ₂ N), titanium silicon nitride (TiSiN), tantalum nitride Silicon (TaSiN), or a combination thereof. A work function layer includes a conductive material, such as N-type work function material and/or P-type work function material, tuned to have a desired work function (eg, an N-type work function or a P-type work function). P-type work function materials include titanium nitride (TiN), tantalum nitride (TaN), ruthenium (Ru), molybdenum (Mo), aluminum (Al), tungsten nitride (WN), zirconium disilicide (ZrSi ₂ ), Molybdenum disilicide (MoSi ₂ ), tantalum disilicide (TaSi ₂ ), nickel disilicide (NiSi ₂ ), tungsten nitride (WN), other P-type work function materials, or combinations thereof. N-type work function materials include titanium (Ti), aluminum (Al), silver (Ag), manganese (Mn), zirconium (Zr), titanium aluminide (TiAl), titanium aluminide carbon (TiAlC), tantalum carbide (TaC) ), tantalum nitride nitride (TaCN), tantalum silicide nitride (TaSiN), tantalum aluminide (TaAl), tantalum aluminide carbon (TaAlC), titanium aluminum nitride (TiAlN), other N-type work function materials, or combinations thereof. A glue/barrier layer may include a material that promotes adhesion between adjacent layers, such as the work function layer and the metal fill layer, and/or between blocking and/or reducing gate layers (such as the work function layer) layer and the metal filling layer) diffusion of a material. For example, the glue/barrier layer includes metals (eg, tungsten, aluminum, tantalum, titanium, nickel, copper, cobalt, other suitable metals, or combinations thereof), metal oxides, metal nitrides (eg, titanium nitride) ), or a combination thereof. A metal fill layer may include a suitable conductive material, such as aluminum, tungsten, and/or copper. A hard mask layer 136 is disposed over gate electrode 134 and gate electrode 132 and includes any suitable material, such as silicon, nitrogen, and/or carbon (eg, silicon nitride or silicon carbide).

The gate spacer 138 is formed by any suitable process and includes a dielectric material. The dielectric material may include silicon, oxygen, carbon, nitrogen, other suitable materials, or combinations thereof (eg, silicon oxide, silicon nitride, silicon oxynitride, or silicon carbide). For example, in the described embodiment, a dielectric layer including silicon and nitrogen, such as a silicon nitride layer, may be deposited over the substrate 110 and subsequently etched out of phase to form the gate spacers 138 . In some embodiments, the gate spacer 138 includes a multi-layer structure, such as a first dielectric layer including silicon nitride and a second dielectric layer including silicon oxide. In some embodiments, gate spacers 138 include sets of spacers, such as seal spacers, offset spacers, sacrificial spacers, dummy spacers, and/or main spacers formed adjacent to the gate stack spacer. In such an embodiment, the various sets of spacers may include materials with different etch characteristics. For example, a first dielectric layer of silicon and oxygen may be disposed over substrate 110 and subsequently etched out of phase to form a first set of spacers adjacent to the gate stack, including silicon A second dielectric layer of nitrogen and nitrogen is disposed on the substrate 110, and is subsequently etched heterogeneously to form a second set of spacers adjacent to the first set of spacers. Implantation, diffusion, and/or annealing processes may be performed to form lightly doped source and Lightly doped source and drain (LDD) features and/or heavily doped source and drain (HDD) features (neither are disclosed in Figures 2A-2G).

The well cell 50 further includes source features and drain features (referred to as source/drain features) disposed in the source/drain regions of the fin 120 . The source/drain features are configured to be equal to or similar to the source/drain features of the N-type finFETs and/or the source/drain features of the P-type finFETs of the SRAM cells 20A, 20B. Drain characteristics. For example, semiconductor material is epitaxially grown on fins 120 to form epitaxial source/drain features 140A on fins 120 over N-type wells 112C, 112D (in other words, well-striped cells Regions of cell 50 are configured similar to the P-type finFET regions including the P-type finFETs of SRAM cells 20A, 20B and fin 120 over P-type well 114C Epitaxial source/drain features 140B are formed thereon (in other words, regions of well strip cell 50 are configured to be similar to the N type fin field effect transistor region). In some embodiments, a fin recess process (eg, an etch back process) is performed on the source/drain regions of the fin 120 so that the epitaxial source/drain features 140A, 140B are Grows at the bottom. In some embodiments, the source/drain regions of the fin 120 are not affected by the fin recessing process, so that the epitaxial source/drain features 140A, 140B are removed from at least the upper fin active region of the fin 120 . A portion grows and covers at least a portion of the upper fin-type active region of the fin 120 . The epitaxial source/drain features 140A, 140B may extend (grow) laterally (in some embodiments, substantially perpendicular to the fin 120) along the y-direction such that the epitaxial source/drain features 140A, 140B are Source/drain features across multiple fins 120 are merged. In some embodiments, epitaxial source/drain features 140A and/or epitaxial source/drain features 140B include partially merged portions (with discontinuities between epitaxial material grown from adjacent fins 120 (or gaps)) and/or fully merged portions (no interruptions (or gaps) between epitaxial material grown from adjacent fins 120).

An epitaxial process can implement chemical vapor deposition (CVD) techniques (eg, vapor-phase epitaxy (VPE), ultra-high vacuum CVD (UHV-CVD), low pressure Chemical Vapor Deposition (LPCVD), and/or Plasma Advanced Chemical Vapor Deposition (PECVD), molecular beam epitaxy, other suitable selective epitaxial growth process, or its Combined. The epitaxial process may use gaseous and/or liquid precursors that interact with the composition of the fin 120. The epitaxial source/drain features 140A, 140B use N-type doping Doping with impurities and/or P-type dopants. In some embodiments, the N-type well strips 50B, 50C and the P-type finFETs of the memory cell 20 have the same dopant epitaxial source. P-type well 50A and N-type finFETs of memory cell 20 have the same doped epitaxial source/drain characteristics. For example, the N-type of memory cell 20 The epitaxial source/drain features 140A of well strips 50B, 50C and the epitaxial source/drain features of the P-type finFETs may include epitaxial layers containing silicon and/or germanium, including epitaxial layers The silicon germanium is doped with boron, carbon, other P-type dopants, or a combination thereof (eg, to form a silicon:germanium:boron (Si:Ge:B) epitaxial layer or a silicon:germanium:carbon (Si:Ge:C) epitaxial layer). To further illustrate, the epitaxial source/drain features 140B of the P-well strip 50A and the epitaxial N-type finFET in the memory cell 20 The source/drain features may include epitaxial layers including silicon and/or carbon, wherein the epitaxial layer including silicon or the epitaxial layer including silicon carbon is doped with phosphorus, arsenic, other N-type dopants, or a combination thereof Doping (for example, forming a silicon:phosphorus (Si:P) epitaxial layer, a silicon:carbon (Si:C) epitaxial layer, a silicon:arsenic (Si:As) epitaxial layer, or a silicon: carbon:phosphorus (Si:C:P) epitaxial layers). In some embodiments, the N-type well strips 50B, 50C and P-type finFETs of the memory cell 20 have oppositely doped epitaxial sources And the P-type well 50A and N-type finFETs of the memory cell 20 have oppositely doped epitaxial source/drain characteristics. In some embodiments, the epitaxial source/drain The pole features 140A, 140B include materials and/or dopants that can achieve the desired tensile and/or compressive stress in the channel region. In some embodiments, the epitaxial source/drain features 140A, 140B are Doping is done during doping by adding impurities to a source material of the epitaxial process. In some embodiments, the epitaxial source/drain features 140A, 140B are doped by an ion implantation process after the deposition process .In some embodiments, an annealing process is performed to Epitaxial source/drain features 140A, epitaxial source/drain features 140B, and/or other source/drain features of memory 10 activate dopants, such as heavily doped source and drain (HDD ) regions and/or lightly doped source and drain (LDD) regions.

A multilayer interconnect (MLI) feature 150 is disposed over the substrate 110 . The multilayer interconnect feature 150 is electrically coupled to various devices (eg, P-type finFET in memory cell 20, N-type finFET in memory cell 20, N-type well strip 50B) N-type well strips, P-type well strips within P-type well strips 50A, transistors, resistors, capacitors, and/or inductors) and/or components (eg, the P-type finFETs of memory cell 20 and /or gate structure of N-type FinFET), source/drain features (eg, epitaxial source/drain features 140A, 140B and/or P-type FinFET of memory cell 20 ) epitaxial source/drain features of crystals and/or N-type finFETs), and/or doped wells of well strip cell 50 (eg, N-type wells 112C, 112D and/or P-type well 114C) , so that these various devices and/or components can operate according to the design requirements of the memory 10 . The multilayer interconnect feature 150 includes a combination of dielectric and conductive layers configured to form various interconnect structures. The conductive layers are configured to form vertical interconnect features, such as device-level contacts and/or vias, and/or horizontal interconnect features, such as wires. Vertical interconnect features are typically connected to horizontal interconnect features at different layers (or different planes) in multi-layer interconnect features 150 . During operation, the interconnect feature is configured to route signals between the device and/or the element of memory 10 and/or distribute signals (eg, clock signals, voltage signals, and/or ground signals) to memory The device and/or the element of the body 10 . For example, the multilayer interconnect feature 150 includes interconnect features configured to route a power supply or ground voltage to the P-well strips 50A and/or the N-well strips 50B, 50C. Notably, although the multi-layer interconnect features 150 are described with a given number of dielectric and conductive layers, the present disclosure contemplates multi-layer interconnect features 150 having more or fewer dielectric and/or conductive layers.

Multilayer interconnect features 150 include one or more dielectric layers, such as interlayers disposed over substrate 110 (especially over epitaxial source/drain features 140A, 140B, gate structures 130, and fins 120). A dielectric layer 152 (ILD-0), and an interlayer dielectric layer 154 (ILD-1) disposed on the interlayer dielectric layer 152. The interlayer dielectric layers 152 and 154 include a dielectric material including, for example, silicon oxide, silicon nitride, silicon oxynitride, oxides formed from tetraethoxysilane (TEOS), phosphosilicate glass (PSG), borophosphosilicate Glass (BPSG), low-k dielectric materials, other suitable dielectric materials, or a combination thereof. Exemplary low-k dielectric materials include fluorinated glass (FSG), carbon-doped silicon oxide, Black Diamond (Applied Materials of Santa Clara, CA), xerogel, aerogel ( aerogel), amorphous fluorinated carbon, parylene, benzocyclobutene (BCB), SiLK (Michigan, Midland, Dow Chemical), polyimide ), other low-k dielectric materials, or a combination thereof. In the depicted embodiment, the interlayer dielectric layers 152, 154 are dielectric layers comprising a low-k dielectric material (commonly referred to as low-k dielectric layers). In some implementations, a low-k dielectric layer is referred to as a material having a dielectric constant (k) of less than 3. The interlayer dielectric layers 152, 154 may comprise a multi-layered structure having a plurality of dielectric materials. The multilayer interconnect feature 150 may further include one or more contact etch stop layers (CESL) disposed between the interlayer dielectric layers 152 , 154 , such as between the interlayer dielectric layer 152 and the interlayer dielectric layer 154 of an etch stop layer at a contact. In some embodiments, a contact etch stop layer is disposed between the substrate 110 and/or the isolation features 122 and the interlayer dielectric layer 152 . The contact etch stop layer includes a material different from the interlayer dielectric layers 152 , 154 , eg, a dielectric material different from the dielectric material of the interlayer dielectric layers 152 , 154 . For example, where the interlayer dielectric layers 152 and 154 include a low-k dielectric material, the contact etch stop layer includes silicon and nitrogen, such as silicon nitride or silicon oxynitride. The interlayer dielectric layers 152, 154 are formed on the substrate 110 by a deposition process such as chemical vapor deposition (CVD), physical vapor deposition (PVD), atomic layer deposition (ALD), high density plasma chemical Vapor Deposition (HDPCVD), Metal Organic Chemical Vapor Deposition (MOCVD), Remote Plasma Chemical Vapor Deposition (RPCVD), Plasma Advanced Chemical Vapor Deposition (PECVD), Low Pressure Chemical Vapor Deposition (LPCVD), Atomic Layer chemical vapor deposition (ALCVD), atmospheric pressure chemical vapor deposition (APCVD), electroplating, other suitable methods, or a combination thereof. In some embodiments, the interlayer dielectric layers 152 and 154 are formed by a flowable chemical vapor deposition (FCVD) process. The flow chemical vapor deposition process includes, for example, depositing a flowable material (eg, a liquid composition) on the substrate 110 and converting the flowable material to a solid state material by a suitable technique, such as thermal annealing and/or UV light Light radiation treatment. After deposition of the interlayer dielectric layer 152 and/or the contact etch stop layer, a chemical mechanical planarization (CMP) process and/or other planarization processes are performed until the gate stack of the gate structure 130 is reached (exposed). a top. After deposition of the interlayer dielectric layer 154 and/or the contact etch stop layer, a chemical mechanical planarization (CMP) process and/or other planarization processes may be performed.

In FIGS. 2A-2G, device-level contacts (eg, N-well contact 160A and P-well contact 160B), vias, and/or wires (collectively referred to as a first metal ( M1) layer) is disposed on one or more interlayer dielectric layers 152, 154 for forming interconnection structures. Device-level contacts (eg, N-well contact 160A and P-well contact 160B), vias, and/or wire systems include any suitable conductive material, such as tantalum, titanium, aluminum, copper, cobalt, tungsten, nitride Titanium, tantalum nitride, other suitable conductive materials, or combinations thereof. Various conductive materials can be combined to provide device-level contacts (eg, N-well contact 160A and P-well contact 160B), vias, and/or wires with various layers, such as a barrier layer , an adhesive layer, a backing layer, a block layer, other suitable layers, or a combination thereof. In some embodiments, device-level contacts (eg, N-well contact 160A and P-well contact 160B) include titanium, titanium nitride, and/or cobalt, and vias include titanium, titanium nitride, and/or Tungsten, and wires include copper, cobalt, and/or ruthenium. Device-level contacts (eg, N-well contacts 160A and P-well contacts 160B), vias, and/or wires are formed by patterning the interlayer dielectric layers 152 , 154 . The patterning of the interlayer dielectric layers 152, 154 may include a lithography process and/or an etching process to form openings (trenches), such as contact openings, via openings, and/or within the respective interlayer dielectric layers 152, 154 line opening. In some embodiments, the lithography process includes forming a photoresist layer on the respective interlayer dielectric layers 152, 154, exposing the photoresist layer to patterning radiation, and developing the exposed photoresist layer, thereby forming a A patterned photoresist layer that can be used as a mask element for etching openings in the respective interlayer dielectric layers 152, 154. The etching process includes a dry etching process, a wet etching process, other etching processes, or a combination thereof. Afterwards, the opening is filled with one or more conductive materials. The conductive material can be deposited by chemical vapor deposition (CVD), physical vapor deposition (PVD), atomic layer deposition (ALD), electroplating, electroless plating, other suitable deposition processes, or a combination thereof. Thereafter, any excess conductive material is removed through a planarization process, such as a chemical mechanical planarization (CMP) process, thereby planarizing a top surface of the interlayer dielectric layers 152, 154, device level contacts (eg, N-type Well contact 160A and P-well contact 160B), pilot holes, and/or wires.

N-well contacts 160A (also referred to as N-well pick-up areas) are disposed over respective N-wells 112C, 112D such that N-well contacts 160A electrically connect N-wells 112C, 112D to a power source Supply voltage, such as power supply voltage V _DD . P-well contact 160B (also referred to as P-well pickup area) is disposed on P-well 114C such that P-well contact 160B electrically connects P-well 114C to a power supply voltage, such as a power supply voltage _VSS . N-well contact 160A and P-well contact 160B extend through interlayer dielectric layer 152 , interlayer dielectric layer 154 , and isolation feature 122 , although this disclosure contemplates embodiments in which N-well contact 160A and /or P-well contacts 160B extend through more or less interlevel dielectric layers and/or contact etch stop layers of more or less multilayer interconnect features 150 . In some embodiments, the one or more N-well contacts 160A and/or P-well contacts 160B do not electrically connect the N-wells 112C, 112D and/or P-well 114A to the multilayer interconnect feature 150 another conductive feature, such as vias. In such an embodiment, the one or more N-well contacts 160A and/or P-well contacts 160B are dummy contacts whose physical properties are similar to non-dummy contacts, To achieve a substantially consistent process environment.

In the described embodiment, the P-well contact 160B is disposed within the P-well zone 50A, and the N-well zones 50B, 50C do not have the P-well contact 160B. Because the P-well zone 50A does not have an N-type well, the P-well contact 160B (P-well pick-up zone) has lower well pick-up resistance compared to the conventional P-well zone, which The strips typically have a similar doping configuration to the N-well strips 50B, 50C, such that a P-well junction is provided between two P-wells separated by an N-well. In the described embodiment, the P-type wells 50A have more junctions than the N-type wells 50B, 50C. For example, P-well strip 50A includes 9 P-well contacts 160B, while N-well strips 50B, 50C each include 3 N-well contacts 160A. The present disclosure contemplates any configuration of N-well contact 160A and/or P-well contact 160B. For example, FIG. 3 is a simplified schematic top view of another embodiment of a portion or all of a well-band cell that may be implemented in the memory 10 of FIG. 1 in accordance with various portions of the present disclosure. In Figure 3, N-well contact 160A is disposed within an N-well zone, such as N-well zone 50B. In such an embodiment, the N-type well strip 50C is devoid of the N-type contact 160A.

FIG. 4 is a partial top view of a portion 300 of a well strip row 40 in accordance with various portions of the present disclosure. In FIG. 4, three well strip cells 50 are arranged between rows of memory cells 20 (eg, one row of memory array 12A and one row of memory array 12B). Well strip row 40 includes an N-type well 312 and a P-type well 314 . The N-type well 312 represents the combined N-type well of the SRAM cell and the well-band cell 50 (eg, the N-type wells 112A, 112B as described above with reference to FIGS. 2A-2G ), and the P-type well 314 represents Merged P-wells of SRAM cells and well-band cells (eg, P-wells 114A-114C as described above with reference to Figures 2A-2G). In FIG. 4, N-well 312 extends from memory cell 20 to N-well strips 50B, 50C, but does not extend to P-well strip 50A. P-well 314 extends from memory cell 20 to N-well strips 50B, 50C and P-well strip 50A. Because the P-well 314 is I-shaped in the wells cell 50, the wells row 40 includes an intermediate portion that does not have a central portion along an entire length of the wells row 40 (here along the y-direction) N-type wells. For clarity, FIG. 4 has been simplified to better understand the inventive concept of the present disclosure. Additional features may be added to the portion 300 of the wells row 40, and in other embodiments of the portion 300 of the wells row 40, some of the features described below may be replaced, modified, or removed.

FIG. 5 is a circuit diagram of a port memory cell 400 that may be implemented in an SRAM memory in accordance with various portions of the present disclosure. For example, the port SRAM cell 400 is implemented as the memory cell 20 of one or more of the memory 10 (FIG. 1). The port SRAM cell 400 includes 6 transistors: a pass-gate transistor PG-1, a pass-gate transistor PG-2, a pull-up transistor PU-1, an upper Pull-up transistor PU-2, pull-down transistor PD-1, and pull-down transistor PD-2. The port SRAM cell 400 is therefore also referred to as a 6T SRAM cell. In operation, on-gate transistor PG-1 and on-gate transistor PG-2 provide access to a storage portion of SRAM cell 400, which includes a cross-coupled pair of inverters, a Inverter 410 and an inverter 420. The inverter 410 includes a pull-up transistor PU-1 and a pull-down transistor PD-1, and the inverter 420 includes a pull-up transistor PU-2 and a pull-down transistor PD-2. For clarity, FIG. 5 has been simplified to better understand the inventive concepts of the present disclosure. Additional features may be added to the port SRAM cell 400, and in other embodiments of the port SRAM cell 400, some of the features described below may be replaced, modified, or removed.

In some embodiments, the pull-up transistors PU-1, PU-2 are configured as P-type FinFETs. For example, each of the pull-up transistors PU-1, PU-2 includes a gate structure disposed over a channel region of an N-type fin structure (including one or more N-type fins) such that The gate structure is sandwiched between P-type source/drain regions (eg, P-type epitaxial source/drain features) of the N-type fin structure, wherein the gate structure and the N-type fin structure The structure is disposed over an N-type well area. Each of the pull-down transistors PD-1, PD-2 includes a gate structure disposed over a channel region of a P-type fin structure (including one or more P-type fins) such that the gate The structure is sandwiched between N-type source/drain regions of the P-type fin structure (eg, N-type epitaxial source/drain features), wherein the gate structure and the P-type fin structure are disposed in Above a P-type well area. In some embodiments, the on-gate transistors PG-1, PG-2 are also configured as N-type FinFETs. For example, each of the on-gate transistors PG-1, PG-2 includes a gate structure disposed over a channel region of a P-type fin structure (including one or more P-type fins) , so that the gate structure is sandwiched between the N-type source/drain regions (eg, N-type epitaxial source/drain features) of the P-type fin structure, wherein the gate structure and the P-type The fin structure is disposed on a P-type well area.

A gate of the pull-up transistor PU-1 is sandwiched between a source (electrically coupled to a voltage supply voltage (V _DD )) and a first common drain (CD1), and the pull-down transistor PD- A gate of 1 is sandwiched between a source (electrically coupled to a power supply voltage (V _SS )) and the first common drain. A gate of the pull-up transistor PU-2 is sandwiched between a source (electrically coupled to a voltage supply voltage (V _DD )) and a second common drain (CD2), and the pull-down transistor PD- A gate of 2 is sandwiched between a source (electrically coupled to a power supply voltage (V _SS )) and the second common drain. In some embodiments, the first common drain (CD1) is a storage node (SN) that stores data in true form, and the second common drain (CD2) is a storage node (SN) that stores data in complementary form. SNB). The gate of the pull-up transistor PU-1 and the gate of the pull-down transistor PD-1 are coupled to the second common drain, and the pull-up transistor PU-2 and the pull-down transistor PD-2 are connected to the second common drain. The first common drains are coupled to each other. A gate of the on-gate transistor PG-1 is sandwiched between a source (electrically coupled to a bit line BL) and a drain, and the drain is electrically coupled to the first common drain pole. A gate of the on-gate transistor PG-2 is sandwiched between a source (electrically coupled to a complementary bit line BLB) and a drain, and the drain is electrically coupled to the second common Drain extremely. The gates of the on-gate transistors PG-1 and PG-2 are electrically coupled to a word line WL. In some embodiments, on-gate transistors PG-1, PG-2 provide access to the storage node during read operations and/or write operations. For example, the on-gate transistors PG-1 and PG-2 are respectively coupled to the storage nodes to the bit lines BL and BLB in response to the voltages applied to the gates of the on-gate transistors in response to the word lines.

6 is a partial top view of a portion or all of an SRAM array 500 in accordance with various portions of the present disclosure. In some embodiments, SRAM array 500 represents a portion of memory 10 , such as a portion of SRAM cell 20 . In FIG. 6, the SRAM array 500 includes a substrate 510 having various doped regions disposed therein, such as an N-type well 512A, an N-type well 512B, a P-type well 514A, a P-type well 514B , and P-well 514C. Substrate 510, N-type wells 512A, 512B, and P-type wells 514A-514C are similar to substrate 110, N-type wells 112A, 112B, and P-type wells 114A-114C, respectively, above with reference to FIGS. 2A-2G. SRAM array 500 further includes various features disposed over N-type wells 512A, 512B and P-type wells 514A-514C, wherein the various features are configured to achieve desired functions. For example, the SRAM array 500 includes fins 520 (similar to the fins 120 , please refer to the aforementioned FIGS. 2A to 2G ), isolation features (similar to the isolation features 222 , please refer to the aforementioned FIGS. 2A to 2G ) , a gate structure 530 (similar to the gate structure 130, please refer to the aforementioned Figures 2A to 2G) (including, for example, a gate dielectric, a gate electrode, and a hard mask (similar to the gate dielectric 132) Gate spacer, gate electrode 134, hard mask 136, and/or gate spacer 138, please refer to the aforementioned Figures 2A to 2G), epitaxial source/drain features (similar to epitaxial Source/drain features 140A, 140B, please refer to the aforementioned Figures 2A-2G), a multi-level interconnect (MLI) feature (similar to the MLI feature 150, please refer to the aforementioned Figures 2A-2G) Figure 2G), interlayer dielectric layer (similar to the interlayer dielectric layers 152, 154, please refer to the aforementioned Figures 2A to 2G), device level contacts (similar to the device level contacts of Figures 2A to 2G) , vias (similar to the vias of Figures 2A-2G), and wires (similar to the wires of Figures 2A-2G). The various features are configured to form an SRAM cell region, the SRAM The cell area includes an SRAM cell 560A, an SRAM cell 560B, an SRAM cell 560C, and an SRAM cell 560D. The SRAM cells 560A-560D may be implemented within the SRAM cell 20 of the memory 10. In some In embodiments, SRAM cell 560B or SRAM cell 560D may be implemented as SRAM cell 20A adjacent to well strip cell 50 in Figure 2. In some embodiments, SRAM cell 560A or SRAM cell 560C may be Implemented as SRAM cell 20B adjacent to well strip cell 50 in Figure 2. Figure 6 has been simplified for clarity to better understand the inventive concepts of the present disclosure. Additional features may be added to the SRAM array 500, and in other embodiments of the SRAM array 500, some of the features described below may be replaced, modified, or removed.

The SRAM cells 560A-560D include a port SRAM, a dual port SRAM, other types of SRAM, or a combination thereof. In the depicted embodiment, SRAM cells 560A-560D include 6 transistors: an on-gate transistor PG-1, an on-gate transistor PG-2, and a pull-up transistor PU-1 , a pull-up transistor PU-2, a pull-down transistor PD-1, and a pull-down transistor PD-2. Each of the SRAM cells 560A-560D includes an N-type well disposed between the P-type wells. For example, each of SRAM cells 560A, 560B includes N-type well 512A disposed between P-type well 514A and P-type well 514B, with pull-up resistors PU-1, PU-2 disposed in N-type well 512A Above, and on-gate transistors PG-1, PG-2 and pull-down transistors PD-1, PD-2 are disposed above P-well 514A or P-well 514B. Each of SRAM cells 560C, 560D includes an N-type well 512B disposed between P-type well 514B and P-type well 514C, with pull-up transistors PU-1, PU-2 disposed between N-type well 512B and the on-gate transistors PG-1, PG-2 and the pull-down transistors PD-1, PD-2 are disposed above the P-type well 514B or the P-type well 514C. The pull-up resistors PU-1 and PU-2 are P-type fin field effect transistors, the on-gate transistors PG-1 and PG-2 are N-type fin field effect transistors, and the pull-down transistors PD-1 and PD are -2 is a P-type transistor. In some embodiments, the pull-up resistors PU-1, PU-2 are configured as P-type fin field effect transistors, while the on-gate transistors PG-1, PG-2 and the pull-down transistors PD-1, PD The -2 series is configured as an N-type FinFET. For example, each of the on-gate transistors PG-1, PG-2 and/or the pull-down transistors PD-1, PD-2 includes a fin structure (including a or a plurality of fins 520), and a respective gate structure 430 disposed on a channel region of the fin structure, so that the gate structure 430 is sandwiched between the source/drain regions of the fin structure . The fin structures of the on-gate transistors PG-1, PG-2 and the pull-down transistors PD-1, PD-2 include P-type dopants and are electrically connected to the P-type well. The fin structures of on-gate transistors PG-1, PG-2 and pull-down transistors PD-1, PD-2 further include N-type epitaxial source/drain features (in other words, on-gate The epitaxial source/drain features of transistors PG-1, PG-2 and/or pull-down transistors PD-1, PD-2 include N-type dopants). The epitaxial source/drain features of gate structure 430 and/or on-gate transistors PG-1, PG-2 and/or pull-down transistors PD-1, PD-2 are through the multi-level interconnect (MLI ) features, such as the multilayer interconnect feature 150, are electrically connected to a voltage source (eg, V _SS ). To further illustrate, each of the pull-up resistors PU-1, PU-2 includes a fin structure (including one or more fins 520) disposed over a respective N-type well, and disposed on the fin structure A respective gate structure 530 above a channel region of the fin structure, so that the respective gate structure 530 is sandwiched between the source/drain regions of the fin structure. The gate structures of the pull-up resistors PU-1 and PU-2 include N-type dopants and are electrically connected to the N-type well. The gate structures of the pull-up resistors PU-1 and PU-2 further include P-type epitaxial source/drain features (in other words, the epitaxial source/drain features of the pull-up resistors PU-1 and PU-2 including P-type dopants). The gate structure 530 and/or the epitaxial source/drain features of the pull-up resistors PU-1, PU-2 are electrically connected to a voltage source (eg, V _DD ) through the multi-level interconnect (MLI) feature . In some embodiments, the pull-up resistors PU-1, PU-2, the on-gate transistors PG-1, PG-2 and the pull-down transistors PD-1, PD-2 are single-fin fin field effect transistors (In other words, the fin structure includes a fin), although this disclosure contemplates embodiments in which one or more pull-up resistors PU-1, PU-2, on-gate resistors The transistors PG-1, PG-2 and the pull-down transistors PD-1, PD-2 are multi-fin fin field effect transistors (in other words, the fin structure includes multiple fins).

The present disclosure provides many different embodiments. Disclosed herein are fin wells for memory array (eg, SRAM array) performance and methods of making the same. An exemplary integrated circuit has a first doping configuration including a first well, a second well, and a third well disposed in a substrate. The second well region is disposed between the first well region and the third well region, and the first well region and the third well region are doped with a first type dopant, and the second well region is doped with a The second type dopant is doped. The integrated circuit further includes a well band cell disposed adjacent to the memory cell. The well zone cell has a first well zone zone, a second well zone zone, and a third well zone zone, and the second well zone zone is arranged between the first well zone zone and the third well zone zone. The first well zone and the third well zone have a first well doping configuration. The second well region has a second doping configuration including a fourth well region doped with the first type dopant. The well zone cell includes a first well pickup area connected to a fourth well area, and a second well pickup area connected to the second well area. In some embodiments, the third well region and the fourth well region combine to form an I-shaped well region within the well strip cell doped with the first type dopant. In some embodiments, the first-type dopant is a P-type dopant, and the second-type dopant is an N-type dopant.

In some embodiments, the first well region, the second well region, the third well region, and the fourth well region extend along a direction perpendicular to a gate length direction. In some embodiments, the fourth well region has a width substantially equal to the width of the well strip cell. In some embodiments, the second well pick-up zone is provided in the second well zone only within the first well zone zone or the third well zone zone. In some embodiments, the first well pickup is connected to a first voltage, and the second well pickup is connected to a second voltage that is different from the first voltage. In some embodiments, the well cell includes a fin configured as a dummy fin field effect transistor (FinFET), a gate structure, and epitaxial source/drain features.

The present disclosure further discloses a well band cell disposed between a first memory cell and a second memory cell. The well strip cell includes a P-type well, a first N-type well, and a second N-type well in a substrate. The P-type well, the first N-type well, and the second N-type well are arranged in the well zone cell, so that a middle part of the well zone cell does not have the first N-type well and the second N-type well in the length direction of a gate. Two N-type wells. The well zone cell further comprises that the P-type well pick-up area is connected to the P-type well, the N-type well pick-up area is connected to the first N-type well or the second N-type well, or is simultaneously connected to the first N-type well and the second N-type well well. In some embodiments, the P-type well exhibits an I-shape along the length of the gate in a plan view. In some embodiments, the width of the first N-type well, the width of the second N-type well, and an intermediate portion of the well zone cell along the gate length without the first and second N-type wells The sum of the lines is substantially equal to the width of the well band cell. In some embodiments, the well strip cell is a fin well strip cell, and the fin well strip cell includes fins extending in a direction perpendicular to the length of the gate.

In some embodiments, a middle portion of the well zone cell is disposed on a first edge portion of the well zone cell and a second edge portion of the well zone cell, wherein the middle portion includes a first edge portion of the P-type well one time zone. The first edge portion includes a first N-type well disposed between a second sub-region of the P-type well and a third sub-region of the P-type well along the gate length direction; wherein the second sub-region of the P-type well And the third sub-region of the P-type well extends from the first sub-region of the P-type well. The second edge portion includes a second N-type well disposed along the gate length between a fourth sub-region of the P-type well and a fifth sub-region of the P-type well; wherein the fourth sub-region of the P-type well And the fifth sub-region of the P-type well extends from the first sub-region of the P-type well. In some embodiments, the middle portion corresponds to a P-type well zone, the first edge portion corresponds to a first N-type well zone, and the second edge portion corresponds to a second N-type well zone; wherein the P-type well zone The system is arranged between the first N-type well zone and the second N-type well zone.

In some embodiments, the first gate structure is disposed in the middle portion of the well-strip cell, such that the first gate structure is disposed over the P-type well; the second gate structure is disposed at the first gate of the well-strip cell the edge part, so that the second gate structure is arranged on the first N-type well, the second sub-region of the P-type well, and the third sub-region of the P-type well; the third gate structure is arranged on the well band cell The second edge portion of the cell, so that the third gate structure is arranged in the second N-type well, the fourth sub-region of the P-type well, and the fifth sub-region of the P-type well. In some embodiments, the P-well pick-up zone is disposed in the middle of the well zone cell along the length of the gate without the first N-well and the second N-well. At least one of the P-type well pickup regions is disposed between the first N-type well and the second N-type well along a direction perpendicular to the length of the gate.

The present disclosure further discloses a memory array including a first memory cell row and a second memory cell row. Each memory cell of the first memory cell row has a first well doping configuration. Each memory cell of the second row of memory cells has a first well doping configuration. The memory array includes a well with a cell row disposed between the first memory cell row and the second memory cell row. Each well zone cell within the well zone cell row includes a P-type well zone disposed between a first N-type well zone and a second N-type well zone, wherein the first N-type well zone and the second N-type well strip has a first well doping configuration, and the P-type well strip has a second well doping configuration different from the first well doping configuration. In some embodiments, the first well doping configuration includes an N-type well, and the second well doping configuration lacks an N-type well. In some embodiments, the P-type well zone includes a P-type well pickup zone disposed between an N-type well of the first N-type well zone and an N-type well of the second N-type well zone. The P-type well zone includes a P-type well pickup zone disposed between an N-type well of the first N-type well zone and an N-type well of the second N-type well zone.

The foregoing outlines the features of several embodiments so that those skilled in the art may better understand the present disclosure. Those skilled in the art should appreciate that the present disclosure may be readily utilized as a basis for designing or modifying other processes and structures for carrying out the same purposes and/or achieving the same advantages of the embodiments introduced in the present disclosure. Those skilled in the art should realize that such equivalent constructions do not depart from the spirit and scope of the present disclosure, and that various changes, substitutions and alterations may be made herein without departing from the spirit and scope of the present disclosure.

10: memory 20: memory cell 30: edge dummy cell 40: well strip row 50: well strip cell 60: controller 12A, 12B: memory array C1: row 1 CN: row N R1 : column 1 RM: column M WL: word line BL: bit line BLB: complementary bit line V _DD , V _SS : power supply voltage 35A, 35B: dummy cell row x, y, x: direction xy, yx, xz: plane BB, CC, EE, FF, GG: line 20A, 20B: SRAM cell 50A: P-well strip 50B, 50C: N-well strip 110: Substrate 112A, 112B, 112C, 112D: N-type doped regions (N-type wells) 114A, 114B, 114C: P-type doped regions (P-type wells) 114A-1, 114A-2, 114B-1, 114B-2: P-type well sub-regions W1, W2, W3 : Width 114C-1, 114C-2, 114C-3: P-well sub-area W4, W5, W6, W7, W8: Width L1, L2, L3, L4, L5: Length 120: Fin 122: Isolation feature 130: Gate Pole Structure 132: Gate Dielectric 134: Gate Electrode 136: Hard Mask Layer 138: Gate Spacers 140A, 140B: Epitaxial Source/Drain Features 150: Multilayer Interconnect Features 152, 154: Interlayer Dielectric Layer 160A:N Type Well Contact 160B: P Type Well Contact 300: Part 312: N Type Well 314: P Type Well 400: Port Memory Cell (SRAM Cell) PG-1, PG-2: On-Gate Voltage Crystals PU-1, PU-2: pull high transistors PD-1, PD-2: pull low transistors 410, 420: inverter 430: gate structure CD1: first common drain CD2: second common drain 500 : SRAM array 510: Substrate 512A, 512B: N-well 514A, 514B, 514C: P-well 520: Fin 530: Gate structure 560A, 560B, 560C, 560D: SRAM cell

The present disclosure is best understood from the following detailed description when read in conjunction with the drawings. It is further emphasized that, in accordance with standard industry practice, the various features are not drawn to scale and are used for illustration purposes only. In fact, the dimensions of the various features may be arbitrarily increased or decreased for clarity of discussion. FIG. 1 is a partial schematic plan view of a memory according to an embodiment of the present disclosure. Figures 2A, 2B, 2C, 2D, 2E, 2F, and 2G illustrate a well-band cell that can be implemented in the memory of Figure 1 according to embodiments of the present disclosure Part or all of a partial schematic plan. FIG. 3 is a simplified schematic top view of another embodiment of part or all of the well strip cell that may be implemented in the memory of FIG. 1 according to embodiments of the present disclosure. FIG. 4 is a partial top view of a portion of a column of wells that may be implemented in the memory of FIG. 1 according to an embodiment of the present disclosure. FIG. 5 is a circuit diagram of a port SRAM cell that may be implemented in the memory of FIG. 1 according to an embodiment of the present disclosure. FIG. 6 is a partial top view of an SRAM array that may be partially or fully implemented in the memory of FIG. 1 according to an embodiment of the present disclosure.

10: Memory

20: Memory Cell

30: Edge dummy cells

40: Well Belt Row

50: Well Band Cell

60: Controller

12A, 12B: Memory array

C1: line 1

CN: row N

R1: column 1

RM: column M

BL: bit line

BLB: Complementary Bit Line

35A, 35B: Dummy cell rows

Claims (17)

An integrated circuit includes: a memory cell having a first doping configuration including a first well, a second well, and a third well disposed in a substrate region, wherein the second well region is disposed between the first well region and the third well region, and the first well region and the third well region are doped with a first-type dopant, and the second well region is doped with a second type dopant; and a well band cell disposed adjacent to the memory cell, wherein: the well band cell has a first well band region, A second well zone and a third well zone, the second well zone is arranged between the first well zone and the third well zone; the first well zone and the third well zone The well region has a first well doping configuration; the second well region has a second doping configuration including a fourth well region doped with the first type dopant; and The well zone cell includes a plurality of first well pickup areas connected to the fourth well area, and a plurality of second well pickup areas connected to the second well area. The integrated circuit of claim 1, wherein the third well region and the fourth well region are combined to form an I-shaped well region in the well strip cell doped with the first type dopant; the first The four-well region has a width that is substantially equal to the width of the well strip cell. The integrated circuit of claim 1, wherein the first-type dopant is a P-type dopant, and the second-type dopant is an N-type dopant. The integrated circuit of claim 1, wherein the first well region, the second well region, the third well region, and the fourth well region extend along a direction perpendicular to a gate length direction. The integrated circuit of claim 1, wherein the second well pick-up area is provided only in the the first well zone or the second well zone within the third well zone; the first well pick-up zones are connected to a first voltage, and the second well pick-up zones are connected to a second voltage, the second voltage is different from the first voltage. The integrated circuit of claim 1, wherein the well band cell includes a fin configured as a dummy fin field effect transistor (FinFET), a gate structure, and epitaxial source/drain features. A memory, comprising: a well band cell disposed between a first memory cell and a second memory cell, wherein the well band cell comprises: a P-type well in a substrate, A first N-type well, and a second N-type well, wherein the P-type well, the first N-type well, and the second N-type well are arranged in the well zone cell, so that the well zone A middle portion of the cell is devoid of the first N-type well and the second N-type well in a gate length direction; a plurality of P-type well pick-up regions connected to the P-type well; and a plurality of N-type well pick-up regions, Connected to the first N-type well, or to the second N-type well, or to both the first N-type well and the second N-type well. The memory of claim 7, wherein the P-type well presents an I-shape along the gate length direction in a plan view. The memory of claim 7, wherein a middle portion of the wellstrip cell is disposed between a first edge portion of the wellstripe cell and a second edge portion of the wellstripe cell, wherein the wellstripe cell The middle portion includes a first sub-region of the P-type well; the first edge portion includes a second sub-region and a third sub-region of the P-type well disposed along the gate length direction between the first N-type well, wherein the second zone of the P-type well and The third sub-region of the P-type well extends from the first sub-region of the P-type well; and the second edge portion includes a fourth sub-region disposed in the P-type well along the gate length direction and The second N-type well between a fifth sub-region of the P-type well, wherein the fourth sub-region of the P-type well and the fifth sub-region of the P-type well are from the first sub-region of the P-type well A zone extension. The memory of claim 9, wherein the middle portion corresponds to a P-type well zone, the first edge portion corresponds to a first N-type well zone, and the second edge portion corresponds to a second N-type well zone belt; wherein, the P-type well belt is arranged between the first N-type well belt and the second N-type well belt. The memory of claim 9, further comprising: a plurality of first gate structures disposed in the middle portion of the well band cell, so that the first gate structures are disposed on the P-type well; a plurality of second gate structures a pole structure disposed on the first edge portion of the well strip cell, so that the second gate structures are disposed on the first N-type well, the second subregion of the P-type well, and the P-type well above the third subregion of the well; and a plurality of third gate structures disposed on the second edge portion of the well band cell, so that the third gate structures are disposed on the second N-type well, The fourth sub-region of the P-type well, and above the fifth sub-region of the P-type well. The memory of claim 7, wherein the width of the first N-type well, the width of the second N-type well, and the absence of the first N-type well and the second N-type well along the gate length The sum of a middle portion of the well zone cell is substantially equal to the width of the well zone cell. The memory of claim 7, wherein the P-well pick-up zones are disposed in the middle of the well zone cells along the gate length without the first N-well and the second N-well part; at least one of the pick-up regions of the P-type wells is arranged in the No. 1 along a direction perpendicular to the length of the gate between an N-type well and the second N-type well. The memory of claim 7, wherein the well strip cell is a fin well strip cell, and the fin well strip cell includes fins extending in a direction perpendicular to the gate length direction. A memory array, comprising: a first memory cell row, wherein each memory cell of the first memory cell row has a first well doping configuration; a second memory cell row, Wherein each memory cell of the second memory cell row has the first well doping configuration; and a well band cell row disposed between the first memory cell row and the second memory cell between cell rows, wherein each well zone cell within the well zone cell row includes a P-type well zone disposed between a first N-type well zone and a second N-type well zone, the The first N-type well strip and the second N-type well strip have the first well doping configuration, and the P-type well strip has a second well doping configuration different from the first well doping configuration. The memory array of claim 15, wherein the first well doping configuration includes an N-type well, and the second well doping configuration is devoid of an N-type well. The memory array of claim 15, wherein the P-type well zone includes a plurality of P-type wells disposed between an N-type well of the first N-type well zone and an N-type well of the second N-type well zone Well pick-up area.

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