CN117276269A

CN117276269A - Semiconductor structure and method for manufacturing semiconductor device

Info

Publication number: CN117276269A
Application number: CN202310973058.3A
Authority: CN
Inventors: 黄一珊
Original assignee: Taiwan Semiconductor Manufacturing Co TSMC Ltd
Current assignee: Taiwan Semiconductor Manufacturing Co TSMC Ltd
Priority date: 2022-08-30
Filing date: 2023-08-03
Publication date: 2023-12-22

Abstract

According to some embodiments, embodiments of the present invention provide a semiconductor structure. The semiconductor structure includes a semiconductor substrate having a first circuit region and a second circuit region, a first transistor including a first gate stack disposed in the first circuit region, a second transistor including a second gate stack disposed in the second circuit region, and a guard ring structure disposed between the first circuit region and the second circuit region. The first gate stack and the second gate stack have different material compositions. The guard ring structure completely surrounds the second circuit region. Embodiments of the present invention also provide methods of manufacturing semiconductor devices.

Description

Semiconductor structure and method for manufacturing semiconductor device

Technical Field

Embodiments of the present invention relate to semiconductor structures and methods of fabricating semiconductor devices.

Background

The semiconductor Integrated Circuit (IC) industry has experienced an exponential growth. Technological advances in IC materials and design have resulted in multi-generation ICs, where each generation has smaller and more complex circuitry than the previous generation. During the development of ICs, functional density (i.e., the number of interconnected devices per chip area) has generally increased, while geometry (i.e., the smallest component (or line) that can be created using a manufacturing process) has decreased. Such scaled down processes generally provide benefits by improving production efficiency and reducing associated costs. Such scaling down also increases the complexity of processing and manufacturing ICs.

For example, modern ICs include millions or billions of transistors formed on a semiconductor substrate (e.g., silicon). Depending on the application of the IC, the IC may use many different types of transistors. In recent years, the increasing market for cellular and RF (radio frequency) devices has led to a significant increase in the use of RF transistors. As the IC industry advances to advanced technologies with smaller feature sizes (such as 7nm, 5nm, and 3 nm), miniaturized processes have led to various developments in IC designs that integrate RF transistors and logic transistors. Integrated circuit structures face various challenges including noise coupling, shorting, leakage, wiring resistance, alignment margin, layout flexibility, and packing density. Accordingly, structures and methods of transistors are needed to address these issues to enhance circuit performance and reliability.

Disclosure of Invention

Some embodiments of the present invention provide a semiconductor structure comprising: a semiconductor substrate having a first circuit region and a second circuit region; a first transistor including a first gate stack disposed in the first circuit region; a second transistor including a second gate stack disposed in the second circuit region, wherein the first gate stack and the second gate stack have different material compositions; and a guard ring structure disposed between the first circuit region and the second circuit region, wherein the guard ring structure completely surrounds the second circuit region.

Other embodiments of the present invention provide a semiconductor structure comprising: a semiconductor substrate having a logic circuit region and a Radio Frequency (RF) circuit region; a first transistor including a first gate stack disposed in the logic circuit region; a second transistor including a second gate stack disposed in the radio frequency circuit region; and a guard ring structure disposed between the logic circuit region and the radio frequency circuit region, wherein the guard ring structure includes an inner guard ring completely surrounding the radio frequency circuit region and an outer guard ring completely surrounding the inner guard ring and the radio frequency circuit region.

Still further embodiments of the present invention provide a method of manufacturing a semiconductor device, the method comprising: forming a first gate stack in a first circuit region of a substrate; forming a second gate stack in a second circuit region of the substrate; forming a third gate stack in the guard ring region between the first circuit region and the second circuit region, wherein the first gate stack, the second gate stack, and the third gate stack each comprise the same material composition, and wherein the third gate stack completely surrounds the second circuit region in a top view; depositing a patterned mask layer covering the guard ring region and the second circuit region; performing an etching process to remove the first metal filling layer in the first gate stack, wherein the etching process also partially etches the third gate stack to form a gap; depositing a second metal fill layer in the second gate stack and in the gaps of the third gate stack; and planarizing the semiconductor device to expose the first metal fill layer in the second gate stack.

Drawings

Aspects of the disclosure may be best understood from the following detailed description when read in connection with the accompanying drawings. It is noted that the various components are not drawn to scale according to standard practice in the industry. In fact, the dimensions of the various features may be arbitrarily increased or reduced for clarity of discussion.

Fig. 1 is a top view of an Integrated Circuit (IC) structure constructed in accordance with various aspects of the disclosure.

Fig. 2 is a cross-sectional view of the IC structure of fig. 1 constructed in accordance with various aspects of the present disclosure.

Fig. 3, 4, 5, 6, 7, 8, 9, 10, 11, 12, 13, 14, 15, 16, 17, 18, 19, 20, and 21 illustrate perspective and cross-sectional views of intermediate stages in forming an IC structure according to aspects of the present disclosure.

Fig. 22 illustrates a layout of an IC structure having one or more guard rings surrounding an RF circuit area in accordance with various aspects of the disclosure.

Fig. 23, 24, 25, 26, 27, 28, 29, 30 and 31 illustrate cross-sectional views of intermediate stages in forming the IC structure of fig. 22, in accordance with aspects of the present disclosure.

Fig. 32 and 33 illustrate alternative layouts of an IC structure having one or more guard rings surrounding an RF circuit area in accordance with aspects of the present disclosure.

Fig. 34A, 34B, 34C, and 34D illustrate some transistor structures that may be used as logic transistors and RF transistor devices in accordance with aspects of the present disclosure.

Fig. 35 illustrates a process flow of forming an IC structure including a logic circuit region and an RF circuit region in accordance with various aspects of the disclosure.

Detailed Description

The following disclosure provides many different embodiments, or examples, of the different components used to implement the present disclosure. Specific examples of components and arrangements are described below to simplify the present disclosure. Of course, these are merely examples and are not intended to be limiting. For example, in the following description, forming a first component over or on a second component may include embodiments in which the first component and the second component are formed in direct contact, and may also include embodiments in which additional components may be formed between the first component and the second component, such that the first component and the second component may not be in direct contact.

In addition, the present disclosure may repeat reference numerals and/or characters in the various examples. This repetition is for the purpose of simplicity and clarity and does not in itself dictate a relationship between the various embodiments and/or configurations discussed. Moreover, in the present disclosure below, forming an element on, connecting to, and/or coupling to another element may include embodiments in which the elements are formed in direct contact, and may also include embodiments in which additional elements may be formed between the elements such that the elements may not be in direct contact. In addition, to facilitate describing the relationship between one component of the present disclosure and another component, spatially relative terms are used, such as "lower," "upper," "horizontal," "vertical," "above …," "above …," "below …," "below …," "upper," "lower," "top," "bottom," and the like, as well as derivatives thereof (e.g., "horizontally," "downwardly," "upwardly," and the like). Spatially relative terms are intended to encompass different orientations of the device in which the component is included. Still further, when a value or range of values is recited with "about," "approximately," etc., the term is intended to encompass values within a reasonable range including the recited value, such as values within +/-10% of the recited value or other values understood by those of skill in the art. For example, the term "about 5nm" encompasses a size range from 4.5nm to 5.5 nm.

The present disclosure relates generally to semiconductor circuit structures having Field Effect Transistors (FETs) and processes for their fabrication, and more particularly to semiconductor circuit structures including a combination of a first type of transistor and a second type of transistor having one or more guard rings surrounding the first type of transistor for isolation from the second type of transistor. According to some embodiments of the present disclosure, the first type of transistor is a transistor for Radio Frequency (RF) applications (also referred to as an RF transistor), and the second type of transistor is a transistor for logic applications (also referred to as a logic transistor). The RF transistor operates in the high frequency band, such as in the range between about 100kHz and about 300GHz, or in the range between about 1GHz and about 300 GHz. The logic transistor operates at a lower frequency band than the radio frequency transistor. Those of ordinary skill in the art will appreciate that other types of transistors other than RF transistors and/or logic transistors, such as a combination of a first type of transistor for memory applications and a second type of transistor for input/output (I/O) applications, may be readily devised or modified using the present disclosure as a basis for designing or modifying other processes and structures for carrying out the same purposes and/or achieving the same advantages of the embodiments described herein.

Further, the present disclosure provides various embodiments of Integrated Circuits (ICs) formed on a semiconductor substrate. Integrated circuits have a design layout that can be combined with various standard cells. Standard cells are pre-designed IC structures to be reused in a single IC design. An effective IC design layout includes various pre-designed standard cells and predefined rules for placing the standard cells to enhance circuit performance and reduce circuit area. According to an embodiment, the concepts of the present disclosure are explained using forming fin field effect (FinFET) transistors as examples. Other types of transistors, such as planar transistors, nanoplate or nanowire transistors, full-gate-all-around (GAA) transistors, and the like, may also employ the concepts of the present disclosure. According to some embodiments, intermediate stages of forming a FinFET transistor are shown. Some variations of some embodiments are discussed. Like reference numerals are used to designate like elements throughout the various views and illustrative embodiments. Although method embodiments may be discussed as being performed in a particular order, other method embodiments may be performed in any logical order.

Reference is now made jointly to fig. 1 and 2. In one embodiment, fig. 1 is a top view of a semiconductor structure (or semiconductor device) 100 constructed in accordance with various aspects of the present disclosure, and fig. 2 is a cross-sectional view of the semiconductor structure 100 along the dashed line X-X of fig. 1. In some embodiments, the semiconductor structure 100 is formed on a planar active area and includes a Field Effect Transistor (FET). In some embodiments, the semiconductor structure 100 is formed on the fin active region and includes a FinFET. In some embodiments, the semiconductor structure 100 includes FETs (also referred to as GAA transistors) formed on vertically stacked channels. An IC structure and method of making the same are generally described with reference to semiconductor structure 100 as an example.

In various embodiments, the semiconductor structure 100 includes various circuit modules integrated on the same substrate. Those circuit blocks (or simply circuits) may have different functions or different circuit characteristics. Those circuit modules are placed on different circuit areas of the substrate, either adjacent or spaced apart, or have different surrounding environments. For example, the semiconductor structure 100 includes a first circuit region 120 and a second circuit region 122 disposed on a semiconductor substrate (or simply substrate) 102. The semiconductor structure 100 may include additional circuit regions similar to or different from the first circuit region and the second circuit region. For example, the semiconductor structure 100 includes other logic circuit regions, other RF circuit regions, other circuit regions, such as a memory region, an image sensor region, an analog circuit region, or a combination thereof. In some embodiments, the first circuit formed in the first circuit region 120 is a logic circuit and the second circuit formed in the second circuit region 122 is a Radio Frequency (RF) circuit. Radio frequency circuits typically require high frequency and high speed, and correspondingly less parasitic capacitance. In some embodiments, the IC structure further includes a third circuit formed in the third circuit region, where the third circuit is a memory circuit including individual memory devices, such as Static Random Access Memory (SRAM) cells, configured in an array.

Those circuit areas may include one or more standard cells placed into the IC layout according to a predetermined rule. Those standard cells are reused in the integrated circuit design and are thus pre-designed according to the manufacturing technique and stored in a standard cell library. The IC designer may retrieve those standard cells, incorporate those standard cells into his IC design, and place them into the IC layout according to predefined placement rules. For example, the logic standard cells may include various basic circuit devices such as inverters, AND, NAND, OR, XOR and NOR, flip-flop circuits, latches, or combinations thereof, which are popular in applications of digital circuit designs such as Central Processing Units (CPUs), graphics Processing Units (GPUs), and system on a chip (SOC) chip designs.

The substrate 102 comprises silicon. Alternatively, the substrate 102 may comprise an elemental semiconductor, such as silicon or germanium in a crystalline structure; compound semiconductors such as silicon germanium, silicon carbide, gallium arsenide, gallium phosphide, indium arsenide, and/or indium antimonide; or a combination thereof. Possible substrates 102 also include silicon-on-insulator (SOI) substrates. SOI substrates are fabricated using separation by implantation of oxygen (SIMOX), wafer bonding, and/or other suitable methods.

The substrate 102 also includes various isolation features 104, such as isolation features formed on the substrate 102 and thereby defining respective active regions 106 on the substrate 102. Isolation feature 104 employs an isolation technique, such as Shallow Trench Isolation (STI), to define and electrically isolate the various active regions. Each active region 106 is surrounded by a continuous spacer element to separate from other adjacent active regions. The isolation feature 104 comprises silicon oxide, silicon nitride, silicon oxynitride, other suitable dielectric material, or a combination thereof. The spacer 104 is formed by any suitable process. As one example, forming the STI feature includes a photolithography process to expose portions of the substrate, etching trenches in the exposed portions of the substrate (e.g., by using dry and/or wet etching), filling the trenches with one or more dielectric materials (e.g., by using a chemical vapor deposition process), and planarizing the substrate and removing excess portions of the dielectric material by a polishing process, such as a Chemical Mechanical Polishing (CMP) process. In some examples, the filled trench may have a multi-layer structure, such as a thermal oxide liner layer and a filling layer of silicon nitride or silicon oxide.

Active region 106 is a region having a semiconductor surface in which various doped features are formed and configured to one or more devices, such as diodes, transistors, and/or other suitable devices. The active region 106 may comprise a semiconductor material similar to the semiconductor material of the bulk semiconductor material of the substrate 102, such as silicon, or may comprise a different semiconductor material, such as silicon germanium (SiGe), silicon carbide (SiC), or multiple layers of semiconductor material formed on the substrate 102 by epitaxial growth, such as alternating layers of silicon and silicon germanium, for performance enhancement, such as a strain effect to improve carrier mobility.

In some embodiments, the active region 106 is three-dimensional, such as a fin active region extending over the isolation feature. The fin active region 106 protrudes from the substrate 102 over the isolation feature 104 and has a three-dimensional profile for more efficient coupling between the channel and gate electrodes of the FET. In particular, the substrate 102 has a top surface, and the fin active region 106 has a top surface 106A that is located above the top surface of the substrate 102. The fin active region 106 may be formed by selective etching to recess the isolation feature, or by selective epitaxial growth to grow an active region having the same or a different semiconductor than that of the substrate 102, or a combination thereof.

The substrate 102 also includes various doped features such as n-type doped wells, p-type doped wells, source and drain features, other doped features, or combinations thereof configured to form various devices or components of devices such as source and drain features of field effect transistors. In the present example shown in fig. 1, semiconductor structure 100 includes a negatively doped well (also referred to as an N-well) 108 and a positively doped well (also referred to as a P-well) 110. The N-well 108 includes a negative dopant, such as phosphorus. And P-well 110 includes a positive dopant such as boron. The N-well 108 and the P-well 110 are formed by suitable techniques such as ion implantation, diffusion, or a combination thereof. In the present embodiment, one active region 106 is formed in an N-well 108, and another active region 106 is formed in a P-well 110.

The semiconductor structure 100 also includes various gate stacks (or gates for short) 112 having elongated shapes oriented in a first direction (Y-direction). In this embodiment, the X-direction and the Y-direction are orthogonal and define the top surface of the substrate 102. The gate stack includes a gate dielectric layer and a gate electrode. The gate stack is a component of the FET and works with other components, such as source/drain (S/D) components and a channel, where the channel is the portion of the active region directly underneath the gate stack; and the S/D features are located in the active region and disposed on both sides of the gate stack. In the present embodiment, the gate stacks in the first circuit region 120 and the second circuit region 122 are referred to as a gate stack 112A and a gate stack 112B, respectively. It should be noted that the gate stack should not be confused with logic gates, such as NOR logic gates.

The semiconductor structure 100 may also include some dummy gate stacks disposed on the substrate 102. The dummy gate is not a functional gate. Instead, dummy gates are provided for other purposes, such as adjusting pattern density and/or isolation. The dummy gate may have a similar structure to the functional gate 112. Alternatively, in some cases, the dummy gate may have a different structure, or may even be a dielectric component (also referred to as a dielectric gate) that includes one or more dielectric materials and that serves as an isolation component.

The dummy gate is similar in formation to gate 112. In some embodiments, the gate 112 and the dummy gate are formed together through a process such as a back gate process. In a further embodiment, the initial dummy gate is first formed by deposition and patterning, wherein the patterning further comprises a photolithography process and etching. Thereafter, a subset of the initial dummy gates are replaced by depositing a gate dielectric layer and gate electrode to form gates 112, while the remaining initial dummy gates are replaced by depositing a dielectric material to form dielectric gates. Further, the dummy gate is differently set and configured, and thus the dummy gate functions differently. In the depicted embodiment, some dielectric gates are placed on the border areas between circuit blocks or on the borders of standard cells to act as spacers to separate one standard cell from an adjacent standard cell, and some dielectric gates are placed inside standard cells or inside circuit blocks in the circuit area in consideration of one or more considerations, such as isolation between adjacent FETs and adjusting pattern density. Thus, the dummy gate provides isolation functions between adjacent IC devices and additionally provides pattern density adjustment to improve fabrication, such as etching, deposition, and CMP.

In this embodiment, the semiconductor structure 100 includes a first circuit region 120 for logic circuitry and a second circuit region 122 for RF circuitry. The two circuit regions 120 and 122 may be placed adjacent to each other or separated by a distance by a dummy region including a plurality of dummy gates.

In the depicted embodiment, the semiconductor structure 100 includes a first active region 106 in an N-well 108 and a second active region 106 in a P-well 110. The gate 112A in the first circuit region 120 may extend continuously along the Y-direction from the first active region 106 (in the N-well 108) to the second active region 106 (in the P-well 110). Similarly, the gate 112B in the second circuit region 122 may extend continuously from the first active region 106 (in the N-well 108) to the second active region 106 (in the P-well 110) along the Y-direction.

With the source/drain regions 126 and channel 130 formed for each transistor associated with a respective gate, a respective active region, and a respective circuit region, the first circuit region 120 includes one P-type FET (pFET) 132 located in the N-well 108 and one N-type FET (nFET) 133 located in the P-well 110; and second circuit region 122 includes one pFET 134 located in N-well 108 and one nFET 135 located in P-well 110. In this embodiment, the pFET 132, the nFET 133, and other FETs in the first circuit region 120 are integrated to form a functional circuit block, such as a logic circuit; and the pfets 134, nfets 135 and other FETs in the second circuit region 122 are integrated to form another functional circuit block, such as an RF circuit.

Fig. 1 and 2 provide an exemplary semiconductor structure 100 having a first circuit region 120 and a second circuit region 122 for illustration. However, it should be understood that the semiconductor structure 100 may include additional circuit regions and some dummy regions (or fill regions) added in various configurations. In some embodiments, each circuit region is surrounded by a corresponding dummy region. For example, additional circuit regions and dummy regions may be added to the left, right, upper and/or lower edges of fig. 1 in similar configurations, depending on the individual designs. The IC structures in other figures, such as those discussed below, should be similarly understood.

In particular, the gate stacks 112A in the first circuit region 120 and the gate stacks 112B in the second circuit region 122 have different pitches. Pitch is defined as the periodic distance of an array of gates, such as the center-to-center distance of two adjacent gates in an array of gates. In the present embodiment, the gate stack 112A has a first pitch P1, and the gate stack 112B has a second pitch P2 greater than the first pitch P1. For example, the first pitch P1 is smaller than the reference pitch, and the second pitch P2 is larger than the reference pitch. The reference pitch is determined according to the fabrication techniques and characteristics of the first transistor and the second transistor. In the depicted embodiment, the reference pitch may be approximately 100nm. For example, the first pitch P1 is less than 100nm and the second pitch P2 is greater than 100nm. In some embodiments, the ratio P2/P1 is large enough, such as greater than 1.5, to achieve the desired circuit performance enhancement with a corresponding gate profile. In some embodiments, P2/P1 is in the range between 1.2 and 2. The first pitch P1 and the second pitch P2 may be adjusted for corresponding circuit performance, respectively. Accordingly, the RF circuits in the second circuit region 122 may have a larger pitch, smaller parasitic capacitance, and high frequency performance, while the logic circuits in the first circuit region 120 may have a smaller pitch and higher packing density without degrading overall circuit performance. In addition, the gate stacks 112A and 112B may differ in gate pitch, gate size, gate structure, gate profile, gate orientation, gate configuration, gate composition, gate environment, dummy gate design, or combinations thereof.

In the above example, only two circuit areas (120 and 122) are shown. However, the semiconductor structure 100 may include a plurality of circuit regions, each designed for a respective function, such as a first circuit region for a logic circuit having a first gate pitch, a second circuit region for an RF circuit having a second gate pitch, a third circuit region for a memory circuit having a third gate pitch, a fourth circuit region for an I/O device having a fourth gate pitch, and so on. Those gate pitches are different from each other and are individually tuned for corresponding circuit characteristics and performance enhancements. Further, each circuit region may include a dummy gate surrounding the functional gate. The dummy gate is further tuned to have different designs (such as gate pitch, gate size, and gate group) to compensate for pattern density so that process defects are eliminated while circuit performance is enhanced. The region for the dummy gate is referred to as a dummy region, and the region for the functional gate is referred to as an active device region (or active circuit region). Since the dummy gates in the dummy region are not part of the circuit, they are designed to enhance fabrication and circuit performance and thus have greater freedom of adjustment such as gate material, gate pitch, gate size, gate orientation, and gate pattern density. In addition, the location and size of the dummy area is also a factor for adjusting the process. For example, a dummy region will be placed near the edge of the circuit region where the gate pattern density is relatively far from the average.

Referring now to fig. 3-21, fig. 3-21 illustrate perspective and cross-sectional views of intermediate stages in forming RF transistors and logic transistors in the semiconductor device 100 of fig. 1 and 2, in accordance with some embodiments of the present disclosure. The process shown in these figures is also schematically reflected in the process flow 200 shown in fig. 35.

Referring to fig. 3, a substrate 102 is provided. The substrate 102 may be a semiconductor substrate, such as a bulk semiconductor substrate, a semiconductor-on-insulator (SOI) substrate, or the like, which may be doped (e.g., with a p-type or n-type dopant) or undoped. The substrate 102 may be part of a wafer, such as a silicon wafer. Typically, the SOI substrate is a layer of semiconductor material formed on an insulator layer. The insulator layer may be, for example, a Buried Oxide (BOX) layer, a silicon oxide layer, or the like. An insulator layer, typically a silicon substrate or a glass substrate, is provided over the substrate. Other substrates, such as a multilayer substrate or a gradient substrate, may also be used. In some embodiments, the semiconductor material of the substrate 102 may include silicon; germanium; a compound semiconductor including carbon-doped silicon, gallium arsenide, gallium phosphide, indium arsenide, and/or indium antimonide; an alloy semiconductor comprising SiGe, gaAsP, alInAs, alGaAs, gaInAs, gaInP and/or GaInAsP; or a combination thereof.

With further reference to fig. 3, a well region 108 is formed in the substrate 102. The corresponding process is shown as process 202 in process flow 200 shown in fig. 35. Well region 108 is an n-type well region formed by implanting n-type dopants into substrate 102, which may be phosphorus, arsenic, antimony, etc., in accordance with some embodiments of the present disclosure. According to other embodiments of the present disclosure, the well region is a p-type well region formed by implanting p-type dopants into the substrate 102, which may be boron, indium, or the like. The resulting well region 108 may extend to the top surface of the substrate 102. The n-type or p-type dopant concentration may be equal to or less than 10 ¹⁸ cm ^-3 Such as at about 10 ¹⁷ cm ^-3 About 10 ¹⁸ cm ^-3 Within a range between. The substrate 102 also includes a first circuit region 120 where logic transistors are to be formed and a second circuit region 122 where RF transistors are to be formed.

Referring to fig. 4, isolation regions 104 are formed to extend into substrate 102 from the top surface of substrate 102. The isolation region 104 is alternatively referred to as a Shallow Trench Isolation (STI) region. The corresponding process is shown as process 204 in process flow 200 shown in fig. 35. The portion of the substrate 102 between adjacent STI regions 104 is referred to as a semiconductor strip 105. To form the STI region 104, a pad oxide layer 116 and a hard mask layer 118 are formed on the semiconductor substrate 102, and then the pad oxide layer 116 and the hard mask layer 118 are patterned. Pad oxide layer 116 may be a thin film formed of silicon oxide. According to some embodiments of the present disclosure, the pad oxide layer 116 is formed in a thermal oxidation process, wherein a top surface layer of the substrate 102 is oxidized. The pad oxide layer 116 serves as an adhesion layer between the substrate 102 and the hard mask layer 118. Pad oxide layer 116 may also serve as an etch stop layer for etching hard mask layer 118. The hard mask layer 118 is formed from silicon nitride, for example, using Low Pressure Chemical Vapor Deposition (LPCVD), in accordance with some embodiments of the present disclosure. According to other embodiments of the present disclosure, the hard mask layer 118 is formed by thermal nitridation of silicon or plasma-enhanced chemical vapor deposition (PECVD). A photoresist (not shown) is formed on the hard mask layer 118, and then a photoresist etch is patterned. The hard mask layer 118 is then patterned using the patterned photoresist as an etch mask to form the patterned hard mask layer 118 as shown in fig. 4.

Next, the pad oxide layer 116 and the substrate 102 are etched using the patterned hard mask layer 118 as an etch mask, followed by filling the resulting trenches in the substrate 102 with a dielectric material. A planarization process, such as a Chemical Mechanical Polishing (CMP) process or a mechanical polishing process, is performed to remove the excess portion of the dielectric material, and the remaining portion of the dielectric material is STI region 104.STI region 104 may include a liner dielectric (not shown) which may be a thermal oxide formed by thermal oxidation of a surface layer of substrate 102. The liner dielectric may also be a deposited silicon oxide layer, silicon nitride layer, or the like formed using, for example, atomic Layer Deposition (ALD), high Density Plasma Chemical Vapor Deposition (HDPCVD), or Chemical Vapor Deposition (CVD). STI region 104 may also include a dielectric material over the liner oxide, wherein the dielectric material may be formed using Flowable Chemical Vapor Deposition (FCVD), spin coating, or the like. According to some embodiments, the dielectric material over the liner dielectric may comprise silicon oxide.

The top surface of the patterned hard mask layer 118 and the top surface of the STI region 104 may be substantially flush with each other. Semiconductor strips 105 are located between adjacent STI regions 104. According to some embodiments of the present disclosure, the semiconductor strips 105 are part of the original substrate 102, and thus the material of the semiconductor strips 105 is the same as the material of the substrate 102. According to an alternative embodiment of the present disclosure, the semiconductor strips 105 are replacement strips formed by etching portions of the substrate 102 between the STI regions 104 to form recesses, and performing epitaxy to regrow another semiconductor material in the recesses. Accordingly, the semiconductor stripe 105 is formed of a semiconductor material different from that of the substrate 102. According to some embodiments, the semiconductor strips 105 are formed of silicon germanium, silicon carbon, or III-V compound semiconductor material. The patterned hard mask layer 118 is then removed.

Referring to fig. 5, the STI region 104 is recessed such that a top portion of the semiconductor strip 105 protrudes above the top surface 104A of the remaining portion of the STI region 104 to form a protruding fin 106. The corresponding process is shown as process 206 in process flow 200 shown in fig. 35. The pad oxide layer 116 and the patterned hard mask layer 118 are also removed. Etching may be performed using a dry etching process, wherein HF is used, for example ₃ And NH ₃ As an etching gas. During the etching process, a plasma may be generated. Argon may also be included. In accordance with an alternative embodiment of the present disclosure, the recessing of STI region 104 is performed using a wet etch process. The etching chemistry may include, for example, HF.

In the above embodiments, the fins may be patterned by any suitable method. For example, the fins may be patterned using one or more photolithographic processes, including a double patterning process or a multiple patterning process. Typically, a double patterning process or a multiple patterning process combines a lithographic process and a self-aligned process, allowing for the creation of patterns with, for example, a smaller pitch than is obtainable using a single direct lithographic process. For example, in one embodiment, a sacrificial layer is formed over a substrate and patterned using a photolithographic process. Spacers are formed beside the patterned sacrificial layer using a self-aligned process. The sacrificial layer is then removed and the remaining spacers or mandrels may then be used to pattern the fins.

Referring to fig. 6, dummy gate stack 138 is formed to extend over the top surface and sidewalls of (protruding) fin 106. The corresponding process is shown as process 208 in process flow 200 shown in fig. 35. The dummy gate stack 138 may include a dummy gate dielectric 140 and a dummy gate electrode 142 over the dummy gate dielectric 140. The dummy gate dielectric 140 may be formed of silicon oxide or similar materials. The dummy gate electrode 142 may be formed using polysilicon, for example, and other materials may also be used. Each dummy gate stack 138 may also include a hard mask layer(s) 144 over the dummy gate electrode 142. The hard mask layer 144 may be formed of silicon nitride, silicon oxide, silicon carbonitride, or a plurality of layers thereof. The dummy gate stack 138 may span single or multiple protruding fins 106 and/or STI regions 104. The dummy gate stack 138 also has a longitudinal direction perpendicular to the longitudinal direction of the fin 106.

Next, gate spacers 146 are formed on sidewalls of the dummy gate stack 138. The corresponding process is shown as process 208 in process flow 200 shown in fig. 35. According to some embodiments of the present disclosure, the gate spacer 146 is formed of a low-k dielectric material such as porous silicon oxynitride, porous silicon carbonitride, porous silicon nitride, or the like, and the gate spacer 146 may have a single-layer structure or a multi-layer structure including a plurality of dielectric layers. The gate spacer 146 may have a dielectric constant (k value) below 3.8 and may be below about 3.0, for example, in a range between about 2.5 and about 3.0.

Referring to fig. 7, an etching process is then performed to etch portions of fin 106 not covered by dummy gate stack 138 and gate spacers 146. The corresponding process is shown as process 210 in process flow 200 shown in fig. 35. The recess may be anisotropic and thus the portions of the fin 106 directly under the dummy gate stack 138 and gate spacers 146 are protected and not etched. According to some embodiments, the top surface of the recessed semiconductor strips 105 may be lower than the top surface 104A of the STI regions 104. The grooves 148 are formed accordingly. The recess 148 includes portions on opposite sides of the dummy gate stack 138 and portions between the remaining portions of the fin 106.

Referring to fig. 8, epitaxial features (or referred to as source/drain features or source/drain regions) 126 are formed by selectively growing (by epitaxy) semiconductor material in recesses 148. The corresponding process is shown as process 212 in process flow 200 shown in fig. 35. For example, when the resulting FinFET is a p-type FinFET, boron doped silicon germanium (SiGeB), boron doped silicon (sibs), or the like may be grown; when the resulting FinFET is an n-type FinFET, phosphorus doped Silicon (SiP), arsenic doped Silicon (SiAs), or the like may be grown. According to an alternative embodiment of the present disclosure, the source/drain regions 126 comprise a III-V compound semiconductor, such as GaAs, inP, gaN, inGaAs, inAlAs, gaSb, alSb, alAs, alP, gaP, combinations thereof, or multilayers thereof. After the recess 148 is filled with the source/drain regions 126, further epitaxial growth of the source/drain regions 126 causes the source/drain regions 126 to expand horizontally and may form facets. Further growth of the source/drain regions 126 may also cause adjacent source/drain regions 126 to merge with one another. A void (air gap) 128 may be created. The source/drain regions may refer to sources or drains, either individually or collectively depending on the context.

Referring to fig. 9 and 10, fig. 9 shows a perspective view of the structure after formation of a Contact Etch Stop Layer (CESL) 150 and an interlayer dielectric (ILD) layer 152, and fig. 10 shows a cross-sectional view along line X-X of fig. 9. The corresponding process is shown as process 214 in process flow 200 shown in fig. 35. The CESL 150 may be formed of silicon nitride, silicon oxide, silicon, carbonitride, or the like, and the CESL 150 may be formed using CVD, ALD, or the like. ILD layer 152 may comprise a dielectric material formed using, for example, FCVD, spin-on, CVD, or another deposition method. ILD layer 152 may be formed of an oxygen-containing dielectric material, which may be a silicon oxide-based material such as silicon oxide, phosphosilicate glass (PSG), borosilicate glass (BSG), boron doped phosphosilicate glass (BPSG), and the like. A planarization process (such as a CMP process or a mechanical polishing process) may be performed to level the top surfaces of ILD layer 152, dummy gate stack 138, and gate spacers 146 with each other. In fig. 10, the top surface 104A of the STI region 104 is shown to be horizontal, and the fin 106 is higher than the top surface 104A.

Referring to fig. 11 and 12, fig. 11 shows a perspective view of the structure after removal of dummy gate stack 138, and fig. 12 shows a cross-sectional view along line X-X of fig. 11. In some embodiments, the removal of the dummy gate stack 138 includes one or more etching processes that remove the hard mask 144, the dummy gate electrode 142, and the dummy gate dielectric 140 in the dummy gate stack 138, resulting in the gate trench 154. For example, the removal of the dummy gate stack 138 may be performed using a selective etching process such as selective wet etching, selective dry etching, or a combination thereof. The corresponding process is shown as process 216 in process flow 200 shown in fig. 35. The top surface and sidewalls of fin 106 are exposed in gate trench 154. The gate trench 154 in the first circuit region 120 for the logic circuit is denoted as gate trench 154A and the gate trench in the second circuit region 122 for the RF circuit is denoted as gate trench 154B. The gate trenches 154A and 154B may have different dimensions due to different applications of the logic transistors and the RF transistors. Accordingly, subsequently formed gates stacked in the gate trenches 154A and 154B may have different sizes. For example, the gate trench 154A in the first circuit region 120 for the logic circuit has a first width D1 (also the gate width of the logic transistor formed in the gate trench 154A) that is less than a reference dimension (such as 40nm in some examples), and the gate trench 154B in the second circuit region 122 for the RF circuit has a second width D2 (also the gate width of the RF transistor formed in the gate trench 154B) that is greater than the reference dimension. In some embodiments, the ratio D2/D1 is in the range between 1.2 and 3. In some embodiments, the ratio D2/D1 is greater than 2.

Referring to fig. 13, a gate dielectric layer 160 is formed in both gate trenches 154A and 154B, and the gate dielectric layer 160 contacts the top surface and sidewalls of fin 106. The corresponding process is shown as process 218 in process flow 200 shown in fig. 35. According to some embodiments of the present disclosure, the gate dielectric layer 160 includes an Interface Layer (IL) 162, the Interface Layer (IL) 162 being formed on exposed top and sidewall surfaces of the fin 106. The IL 162 may include an oxide layer, such as a silicon oxide layer, formed by a thermal oxidation, chemical oxidation process, or deposition process of the fin 106. Gate dielectric layer 160 may also include a high-k dielectric layer 164 over IL 162. The high-k dielectric layer 164 may be formed of a high-k dielectric material including Si, hf, zr, pb, sb, la and the like. For example, the high-k dielectric layer 164 may be formed of hafnium oxide, lanthanum oxide, aluminum oxide, zirconium oxide, combinations thereof, multilayers thereof, or the like, or the high-k dielectric layer 164 may include hafnium oxide, lanthanum oxide, aluminum oxide, zirconium oxide, combinations thereof, multilayers thereof, or the like. The thickness of high-k dielectric layer 164 may range between about 10 angstroms and about 40 angstroms. The high-k dielectric material has a dielectric constant (k value) above 3.9 and may be above about 7.0, or higher. The high-k dielectric layer 164 is over the respective underlying IL 162 and may contact the respective underlying IL 162. The high-k dielectric layer 164 is formed as a conformal layer and extends over the sidewalls of the fin 106 and the top surfaces and sidewalls of the gate spacers 146. According to some embodiments of the present disclosure, high-k dielectric layer 164 is formed using ALD, CVD, or the like.

Referring to fig. 14, a barrier metal layer 166 is formed by deposition in both gate trenches 154A and 154B. The corresponding process is shown as process 220 in process flow 200 shown in fig. 35. A barrier metal layer 166 is deposited on the top surface and sidewalls of high-k dielectric layer 164. In an embodiment, the barrier metal layer 166 comprises a metal nitride, such as TaN, for preventing migration of metal elements in subsequently formed features to the underlying gate dielectric layer 160. The barrier metal layer 166 serves as an etch stop layer in a subsequent etching process. The barrier metal layer 166 is conductive and has a conformal profile. According to some embodiments of the present disclosure, the barrier metal layer 166 is formed using ALD, CVD, or the like.

Referring to fig. 15, a main metal layer 168 is deposited, the main metal layer 168 completely filling the gate trenches 154A and 154B and covering the top surface of the semiconductor structure 100. The corresponding process is shown as process 222 in process flow 200 shown in fig. 35. The main metal layer 168 may be deposited by deposition methods such as ALD, CVD, plasma Enhanced CVD (PECVD), PVD, plating, and the like. The main metal layer 168 may include a homogenous layer having a monolith formed from the same material. Alternatively, the main metal layer 168 may include a plurality of sub-layers formed of materials different from each other. The main metal layer 168 may have an n-type work function or a p-type work function. The main metal layer 168 thus acts as both a work function layer and an overlying filler metal. According to some embodiments, the primary metal layer 168 is formed of tungsten, aluminum, cobalt, or alloys thereof. In some embodiments, a glue layer (not shown) is conformally deposited over barrier metal layer 166 prior to depositing main metal layer 168. The glue layer may be a metal-containing layer, which may comprise TiN or other suitable material, and may be formed along the sidewalls and bottom of the gate trenches 154A and 154B using ALD, CVD, PVD, combinations thereof, or the like.

Referring to fig. 16, a photoresist (resist) layer is deposited over the semiconductor structure 100 and patterned to form a patterned resist layer 170 exposing the first circuit region 120 for the logic circuit. In various embodiments, the optical process for forming patterned resist layer 170 may also include other steps, such as soft baking, mask alignment, exposure, post-exposure baking, development, rinsing, drying (e.g., spin drying and/or hard baking), other suitable lithographic processes, and/or combinations thereof. After forming the patterned resist layer 170, an etching process is performed to remove the main metal layer 168 from the first circuit region 120 for the logic circuit. The corresponding process is shown as process 224 in process flow 200 shown in fig. 35. The barrier metal layer 166 may act as an etch stop layer during the etching process. In some embodiments, the etching process may include a dry etching process, a wet etching process, and/or combinations thereof. In one example, the barrier metal layer 166 comprises TaN, and the etching process is a wet etching process using an etching solution comprising hydrogen peroxide that automatically dissociates in an aqueous solution to form H+ and HO ₂ + ions. In aqueous solution, HO ₂ +and H ₂ O ₂ All react with the main metal layer 168 but substantially not with TaN. Making H+ ions promote H by making the etching solution more acidic ₂ O ₂ To react with the metal element in the main metal layer 168 to increaseMetal etch rate. The etching process releases the gate trench 154A and exposes the barrier metal layer 166 in the first circuit region 120 for the logic circuit. After the etching process, the patterned resist layer 170 may be removed, for example, by solvent, resist stripper, ashing, or other suitable technique.

Referring to fig. 17, a work function layer 172 and a main metal layer 174 over work function layer 172 are deposited on the top surface of semiconductor structure 100. The corresponding process is shown as process 226 in process flow 200 shown in fig. 35. In an embodiment of an n-type transistor, work function layer 172 may include Ti, ag, al, tiAl, tiAlN, tiAlC, taC, taCN, taSiN, taAlC, mn, zr, combinations thereof, and the like, and work function layer 172 may be formed along the sidewalls and bottom of gate trench 154A using ALD, CVD, PVD, combinations thereof, and the like. In an embodiment of a p-type transistor, work function layer 172 may include TiN, WN, taN, ru, co, combinations thereof, and the like, and work function layer 172 may be formed along the sidewalls and bottom of gate trench 154A using ALD, CVD, PVD, combinations thereof, and the like. The main metal layer 174 may include tungsten, aluminum, cobalt, or an alloy thereof, and may fill the gate trench 154A by a deposition method such as ALD, CVD, PECVD, PVD, plating, or the like. A work function layer 172 and a main metal layer 174 are also deposited over the main metal layer 168 in the second circuit region 122 for the RF circuit.

Referring to fig. 18, after forming work function layer 172 and main metal layer 174, a planarization process, such as a Chemical Mechanical Polishing (CMP) process or a mechanical polishing process, is performed to remove an excess portion of the deposited layer. The corresponding process is shown as process 228 in process flow 200 shown in fig. 35. The remaining portions of the layers in gate trench 154A form gate stack 112A in first circuit region 120 for the logic circuit, gate stack 112A including gate dielectric layer 160, barrier metal layer 166, work function layer 172, and main metal layer (or referred to as a metal fill layer) 174. The remaining portions of the layers in gate trench 154B form gate stack 112B in second circuit region 122 for the RF circuit, gate stack 112B including gate dielectric layer 160, barrier metal layer 166, and main metal layer (or referred to as a metal fill layer) 168. Each of the gate stacks 112A and 112B may include other sub-layers, such as one or more cover layers, glue layers, other suitable layers, and combinations thereof, which are not depicted here for simplicity.

According to some embodiments, the main metal layer 168 in the gate stack 112B for the RF transistor and the main metal layer 174 in the gate stack 112A for the logic transistor are formed of the same material but have different grain sizes. For example, each of the main metal layer 168 and the main metal layer 174 is a homogenous layer having a whole formed of the same material, such as tungsten (W). Region 168A in main metal layer 168 has a smaller grain size than region 174A in main metal layer 174. For example, the average grain size of the main metal layer 168 may be less than about 5nm, and the average grain size of the main metal layer 174 may be in a range between about 8nm and about 500 nm. The ratio of the average grain size of the primary metal layer 174 to the average grain size of the primary metal layer 168 is greater than 1.2, or may be greater than about 10. The grain size difference of main metal layer 168 and main metal layer 174 may be due to different deposition processes. For example, the metallic material in main metal layer 168 may be deposited in an ALD process, while the metallic material in main metal layer 174 may be deposited in a CVD process.

Referring to fig. 19, an etch back process is performed to recess the gate stacks 112A and 112B such that a trench is formed between the opposing gate spacers 146. Next, the trench is filled with a dielectric material to form a dielectric region 176. The corresponding process is shown as process 230 in process flow 200 shown in fig. 35. Dielectric region 176 is formed of a dielectric material such as silicon nitride, porous silicon oxynitride, silicon oxycarbide, or the like. Dielectric region 176 is also planarized so that its top surface is coplanar with the top surface of ILD layer 152. Regarding recessed gate stack 112A and gate stack 112B, main metal layer 174 has a width W1 that is less than a width W2 of main metal layer 168, a height H1 that is less than a height H2 of main metal layer 168, and a volume V1 that is less than a volume V2 of main metal layer 168 due to work function layer 172 in one additional layer, gate trench 154A. In some embodiments, the ratio W2/W1 is greater than 1.2, such as in the range of about 1.2 to about 2; the ratio H2/H1 is greater than about 1.1, such as in the range of about 1.1 to about 1.5; and the volume V2/V1 is greater than 1.4, such as in the range of about 1.4 to about 2.

Referring to fig. 20, a second ILD layer 178, a gate contact plug 180, source/drain silicide regions 182, and source/drain contact plugs 184 are formed. The corresponding process is shown as process 232 in process flow 200 shown in fig. 35. ILD layer 178 may be formed of a dielectric material selected from the same set of candidate materials used to form ILD layer 152. The formation of source/drain contact plugs 184 includes forming contact openings by etching ILD layer 178 and ILD layer 152 to expose underlying portions of CESL 150, and then etching the exposed portions of CESL 150 to expose source/drain regions 126. In a subsequent process, source/drain silicide regions 182 are formed by: depositing one or more metals into the contact opening, performing an annealing process on the semiconductor structure 100 to cause a reaction between the one or more metals and the semiconductor material of the exposed portions of the source/drain regions 126 to produce a silicide feature, and removing unreacted portions of the one or more metals, thereby leaving the silicide feature on the bottom of the contact opening. The one or more metals may include titanium (Ti), tantalum (Ta), tungsten (W), nickel (Ni), platinum (Pt), ytterbium (Yb), iridium (Ir), erbium (Er), cobalt (Co), or a combination thereof (e.g., an alloy of two or more metals), and the one or more metals may be deposited using CVD, PVD, ALD or other suitable methods. The source/drain silicide regions 182 may include titanium silicide (TiSi), nickel silicide (NiSi), tungsten silicide (WSi), nickel platinum silicide (NiPtSi), nickel platinum germanium silicide (NiPtGeSi), nickel germanium silicide (NiGeSi), ytterbium silicide (YbSi), platinum silicide (PtSi), iridium silicide (IrSi), erbium silicide (ErSi), cobalt silicide (CoSi), combinations thereof, or other suitable compounds. In some embodiments, the source/drain silicide regions 182 have a thickness in the range of about 1nm to about 15 nm. Subsequently, a filler metal material such as copper, tungsten, aluminum, cobalt, or the like is filled into the contact openings, followed by planarization to remove excess material, thereby obtaining source/drain contact plugs 184. The formation of the gate contact plug 180 may include etching the second ILD 178 and the dielectric region 176 to expose the gate stack 112, and filling a metal material such as copper, tungsten, aluminum, cobalt, etc., in the corresponding opening to form the gate contact plug 180. The gate contact plug 180 may further include a diffusion barrier layer, such as titanium nitride. Some etching and deposition processes, such as deposition to form corresponding openings and metal materials, and planarization processes may be shared to form gate contact plugs 180 and source/drain contact plugs 184.

By performing the process as shown in fig. 3-20, an exemplary semiconductor device 100 is formed that includes a logic transistor having a gate stack 112A in a first circuit region 120 for logic circuitry and an RF transistor having a gate stack 112B in a second circuit region 122 for RF circuitry. As shown, some common formation processes may be shared to form gate stack 112A and gate stack 112B, such as forming dummy gate stacks in both circuit region 120 and circuit region 122, forming source/drain regions, and replacing the dummy gate stacks with a set of components to form gate stack 112B. A separate etching process and deposition process is performed in the first circuit region 120 to replace the barrier metal layer 166 with other metal layers (e.g., work function layer 172 and main metal layer 174) that are more suitable for forming the gate stack 112A for logic circuit applications. Referring back to fig. 16, during the etching process, even though the main metal layer 168 in the second circuit region 122 is covered by the patterned resist layer 170, portions below the edges of the patterned resist layer 170 are eventually exposed to the etching solution applied at process 224 in the process flow 200 shown in fig. 35. The etching solution may first attack this portion of the main metal layer 168 to form a gap between the edge of the patterned resist layer 170 and the underlying barrier metal layer 166, and the etching solution gradually expands the gap into the gate trench of the second circuit region 122. The boundary of such a gap 171 after the etching process is shown in dashed lines in fig. 16. The possible resulting structure after the etching process and removal of the patterned resist layer 170 is further illustrated in fig. 21. As shown in fig. 21, the gate stack 112B of the RF transistor is damaged due to the lateral leakage of the etching liquid to the RF region, and the RF performance of the device may have been impaired.

Fig. 22 is a layout of a partially-structured semiconductor structure 100 in accordance with some embodiments. The semiconductor structure 100 has a layout optimized for enhancing circuit performance of both logic circuits in the first circuit region 120 and RF circuits in the second circuit region 122. The center region of the layout is an exemplary second circuit region 122. The peripheral region of the layout is an exemplary first circuit region 120. In the illustrated embodiment, the first circuit region 120 surrounds the second circuit region 122. Between the first circuit region 120 and the second circuit region 122 is a guard ring region 121. Guard ring region 121 includes one or more guard rings surrounding second circuit region 122.

The first circuit region 120 includes protruding fins 106A and gate stacks 112A for forming logic transistors. In further embodiments, some of the rows and/or columns of transistors closest to the second circuit region 122, such as the illustrated rows indicated in region 120A, may be dummy transistors. The dummy transistor is not a functional transistor, but is configured around a functional block. The dummy transistors are provided for other purposes such as adjusting pattern density and/or isolation. The dummy transistor (including the dummy gate in the dummy transistor) may have a structure similar to that of the functional transistor. For example, a dummy gate in a dummy transistor may include a gate stack 112A as in a functional transistor. The remaining transistors in the rows and columns of the outer circle formed in the first circuit region 120, such as in the illustrated row indicated in region 120B, may be functional transistors, except for dummy transistors.

The second circuit region 122 includes protruding fins 106B and gate stack 112B for forming an RF transistor. In further embodiments, some rows and/or columns of transistors at the edge of the second circuit region 122, such as the illustrated columns indicated in region 122A, may be dummy RF transistors. The dummy RF transistor is not a functional RF transistor but is configured around a functional block. The dummy RF transistors are provided for other purposes such as adjusting pattern density and/or isolation. The dummy RF transistors (including the dummy gates in the dummy RF transistors) may have a similar structure as the functional RF transistors. For example, the dummy gate in the dummy RF transistor may include a gate stack 112B as in a functional RF transistor. The remaining transistors formed in the second circuit region 122 may be functional RF transistors, except for the dummy RF transistors.

The guard ring region 121 includes one or more guard rings. The guard ring is configured and arranged to shield interference, reduce noise, and enhance circuit performance. For example, the guard ring may be configured to bias the substrate to shield interference. In the depicted embodiment, guard ring region 121 includes protruding fin 106C and gate stacks 112C and 112D disposed on fin 106C. The fin 106C may have a different width (measured in the Y direction) than the fins 106A and 106B. For example, each of the fins 106C may have a greater width than the fins 106A and 106B. Further, the width of fin 106C may be non-uniform. In the depicted embodiment, some fins 106C have a greater width than other fins.

Each of the gate stacks 112C and 112D extends continuously to completely surround (or encircle) the second circuit region 122, thereby forming a guard-river-like structure. In the illustrated embodiment, each of gate stack 112C and gate stack 112D is oriented parallel to an adjacent edge of second circuit region 122. The guard ring (or inner guard ring) including the gate stack 112C is configured as a first guard ring. The guard ring-like structure including the gate stack 112D is configured as a second guard ring (or outer guard ring). The gate stacks 112C and 112D may be biased to a supply voltage (e.g., electrically grounded) or the gate stacks 112C and 112D may be left floating by gate contact plugs. Further, gate stack 112C and gate stack 112D are disposed on the same set of fins 106C, and dummy source/drain regions (e.g., epitaxial features) are sandwiched between gate stack 112C and gate stack 112D. The dummy source/drain regions sandwiched between the gate stacks 112C and 112D are electrically grounded through metal lines 113 connected to the corresponding source/drain region contact plugs. In the illustrated embodiment, the metal line 113 is located between the gate stack 112C and the gate stack 112D, and the metal line 113 extends continuously to completely surround (or encircle) the second circuit region 122.

By completely surrounding the second circuit region 122, the guard ring prevents etching solution from leaking into the gate stack in the second circuit region 122, at least at process 224 in process flow 200 shown in fig. 35, among other advantages, such as providing noise interference shielding for high frequency operation of the surrounding RF circuitry, which is further illustrated in fig. 23-31. Fig. 23 to 31 are sectional views taken along the line X '-X' of fig. 22. For clarity, fig. 23-31 have been simplified to better understand the inventive concepts of the present disclosure. For example, source/drain regions, silicide features, CESL, ILD layers, and some other features are omitted, and additional features may be added to semiconductor structure 100, and in other embodiments of semiconductor structure 100, some of the features described below may be replaced, modified, or eliminated. In some embodiments, the semiconductor structure 100 is substantially similar to the semiconductor structure described above with reference to fig. 3-20, but has an outer guard ring and an inner guard ring interposed between logic transistors in the first region 120 and RF transistors in the second region 122.

Referring to fig. 23, at the end of process 222 in process flow 200 shown in fig. 35, a gate dielectric layer 160 (including IL 162, high-k dielectric layer 164), a barrier metal layer 166 (e.g., taN), and a main metal layer 168 (e.g., tungsten) are sequentially deposited in the gate trenches of first circuit region 120, guard ring region 121, and second circuit region 122. In other words, the gate stacks 112A to 112D that span the first circuit region 120, the guard ring region 121, and the second circuit region 122 initially have the same material composition as that in the gate stack 112B of the RF transistor that will be later.

Referring to fig. 24, a patterned resist layer 170 is formed, the patterned resist layer 170 exposing the first circuit region 120 for the logic circuit. The guard ring region 121 and the second circuit region 122 are covered by a patterned resist layer 170. In various embodiments, the optical process for forming patterned resist layer 170 may also include other steps, such as soft baking, mask alignment, exposure, post-exposure baking, development, rinsing, drying (e.g., spin drying and/or hard baking), other suitable lithographic processes, and/or combinations thereof.

Referring to fig. 25, an etching process is performed to remove the main metal layer 168 from the first circuit region 120 for the logic circuit. The barrier metal layer 166 may act as an etch stop layer during the etching process. In one example, the barrier metal layer 166 comprises TaN, and the etching process is a wet etching process using an etching solution comprising hydrogen peroxide that automatically dissociates in an aqueous solution to form H+ and HO ₂ + ions. In aqueous solution, HO ₂ +and H ₂ O ₂ All react with the main metal layer 168 but substantially not with TaN. The etching process releases the gate trench in the first circuit region 120 and exposes the barrier metal layer 166 in the first circuit region 120 for the logic circuit. However, lateral etching of the etching solution may occur such that portions of the main metal layer 168 below the edges of the patterned resist layer 170 may be exposed to the etching solution to be etched away. A gap 171 occurs under the patterned resist layer 170 and extends laterally toward the gate stack 112B in the second circuit region 122. The gate stacks 112D and 112C of the outer and inner guard rings act as barriers to slow down the lateral etch process. Even though lateral leakage of the etching solution into the areas under the patterned resist layer 170 may etch away the main metal layer 168 in the outer guard ring and/or the inner guard ring, the gate stack 112B in the second circuit region 122 remains intact while the gate trench in the first circuit region 120 is released and the etching process is stopped (e.g., by being controlled in a timer mode). In the embodiment shown in fig. 25, the main metal layer 168 in the gate stack 112D of the outer guard ring is etched and the gap 171 extends even to the region between the outer guard ring and the inner guard ring. However, the gate stack 112C in the inner guard ring and the gate stack 112B in the second circuit region 122 remain intact. Due to lateral leakage and/or etch residues (indicated as 190 in fig. 25), some of the etching solution may accumulate in the released gate trench of the outer guard ring, as molecules are difficult to escape through the narrow opening of the gap 171. Etching solution And/or the etching residues 190 are eventually evaporated into the ambient environment or after subsequent removal of the patterned resist layer 170, the etching solution and/or the etching residues 190 are cleaned by a cleaning process. Even if the gate stack 112D of the outer guard ring is damaged due to lateral leakage of the etching solution, the gate stack 112D is not a functional gate stack and the RF performance of the device is not compromised.

Referring to fig. 26, a work function layer 172 and a main metal layer 174 over work function layer 172 are deposited in the gate trenches in the first and outer guard rings 120 and over the remaining main metal layer 168 in the inner and second circuit regions 122. Work function layer 172 adjusts the work function of the logic transistor. The main metal layer 174 may have the same material composition as the main metal layer 168, such as tungsten, but with different grain sizes, as discussed above with reference to fig. 18.

Referring to fig. 27, after the work function layer 172 and the main metal layer 174 are formed, a planarization process such as a Chemical Mechanical Polishing (CMP) process or a mechanical polishing process is performed to remove an unnecessary portion of the deposited layer. The remaining portions of the layers in the gate trench form gate stacks 112A in the logic transistor, gate stacks 112D in the outer guard ring, gate stacks 112C in the inner guard ring, and gate stacks 112B in the RF transistor. Gate stack 112A and gate stack 112D each include a gate dielectric layer 160, a barrier metal layer 166, a work function layer 172, and a main metal layer (or referred to as a metal fill layer) 174. Gate stack 112C and gate stack 112B each include a gate dielectric layer 160, a barrier metal layer 166, and a main metal layer (or referred to as a metal fill layer) 168. Each of the gate stacks 112A-112D may include other sub-layers, such as one or more cover layers, glue layers, other suitable layers, and combinations thereof, which are not depicted here for simplicity.

Referring to fig. 28, an etch back process is performed to recess gate stacks 112A through 112D, dielectric region 176 is formed on recessed gate stacks 112A through 112D, and then gate contact plug 180 and source/drain contact plug 184 are formed. In some embodiments, gate contact plugs 180 on the outer guard ring and the inner guard ring electrically ground gate stack 112D and gate stack 112C, respectively. Alternatively, the gate stacks 112D and 112C of the outer and inner guard rings may be left floating. In some embodiments, source/drain contact plugs 184 landing on dummy source/drain regions (epi features) sandwiched between gate stacks 112D and 112C electrically couple the dummy source/drain regions to metal lines 113 (fig. 22) thereon, metal lines 113 providing an electrical ground. In some embodiments, with respect to recessed gate stack 112D and gate stack 112C, gate width D3 of gate stack 112D may be equal to gate width D4 of gate stack 112C. However, due to the work function layer 172 in one additional layer-gate stack 112D, the main metal layer 174 has a width W3 that is less than the width W4 of the main metal layer 168, a height H3 that is less than the height H4 of the main metal layer 168, and a volume V3 that is less than the volume V4 of the main metal layer 168. In some embodiments, the ratio W4/W3 is greater than 1.2, such as in the range of about 1.2 to about 2; the ratio H4/H3 is greater than about 1.1, such as in the range of about 1.1 to about 1.5; and the volume V4/V3 is greater than 1.4, such as in the range of about 1.4 to about 2. In some embodiments, the guard ring has a gate width that is wider than the gate widths of the RF transistors and logic transistors, and for the main metal layer 168 and the main metal layer 174 in different regions, there is d4=d3 > d2> D1, W4> W3> W2> W1, h4=h2 > h3=h1, and V4> V3> V2> V1.

Fig. 29 shows an alternative embodiment when lateral leakage of the etching solution further removes the main metal layer 168 from the gate trench in the inner guard ring, such as due to overetching with a longer etching time to ensure complete removal of the main metal layer 168 from the gate trench in the first circuit region 120. Even though both the gate stack 112D of the outer guard ring and the gate stack 112C of the inner guard ring are damaged due to lateral leakage of the etching solution, the gate stack 112B in the RF transistor remains intact. Gate stack 112D and gate stack 112C are not functional gate stacks and the RF performance of the device is not compromised.

Referring to fig. 30, a work function layer 172 and a main metal layer 174 over work function layer 172 are deposited in the gate trenches in first circuit region 120, the outer guard ring, and the inner guard ring, and over the remaining main metal layer 168 in second circuit region 122. Work function layer 172 adjusts the work function of the logic transistor. The main metal layer 174 may have the same material composition as the main metal layer 168, such as tungsten, but with different grain sizes, as discussed above with reference to fig. 18.

Referring to fig. 31, after the planarization process removes the excess portion of the deposited layer, an etch back process is performed to recess the gate stacks 112A to 112D, a dielectric region 176 is formed on the recessed gate stacks 112A to 112D, and then a gate contact plug 180 and a source/drain contact plug 184 are formed. The gate stack 112D in the outer guard ring and the gate stack 112C in the inner guard ring comprise the same material layer. In some embodiments, the gate width D3 of the gate stack 112D may be equal to the gate width D4 of the gate stack 112C in some embodiments, and the main metal layer 174 has the same dimensions (e.g., width w3=w4, height h3=h4, and volume v3=v4) in both the gate stack 112D and the gate stack 112C. In some embodiments, the guard ring has a gate width that is wider than the gate width of the RF transistor and the logic transistor, and for the main metal layer 168 and the main metal layer 174 in different regions, there is d4=d3 > d2> D1, w4=w3 > w2> W1, h2> h4=h3=h1, and v4=v3 > v2> V1.

Fig. 32 is an alternative embodiment of a layout of a partially constructed semiconductor structure 100. The top view shown is substantially similar to the top view depicted in fig. 22, but with an additional guard ring in guard ring region 121, the additional guard ring including gate stack 112E formed on protruding fin 106D. An additional guard ring is deposited between the outer guard ring and the first circuit region 120. Unlike the outer and inner guard rings discussed above, the additional guard rings are not continuous but segmented, also referred to as segmented guard rings, as opposed to the merry-go-round guard rings. In particular, the gate stack 112E does not extend continuously around the second circuit region 122, but is segmented and extends longitudinally in the Y-direction. The segmented guard ring biases the substrate to ground, thereby providing additional noise interference shielding at high frequency operation. But the gaps between the segments of the segmented guard ring are not effective in blocking lateral leakage of the etching solution from occurring. Thus, the material composition of the gate stack 112E of the segmented guard ring is substantially similar to the material composition of the gate stack 112A in the first circuit region and possibly the gate stack 112D in the outer guard ring, but is different from the material composition of the protected gate stack 112B in the second circuit region 122.

Fig. 33 is another alternative embodiment of a layout of a partially constructed semiconductor structure 100. The top view shown is substantially similar to the top view depicted in fig. 22, but with an additional guard ring in guard ring region 121, the additional guard ring comprising protruding fins 106D and gate stacks 112E and 112F disposed on fins 106D. The fin 106D may have a different width (measured in the Y direction) than the fins 106A and 106B. For example, some fins 106D may have a width that is greater than any of fins 106A, 106B, and 106C. Further, the width of the fins 106D may be non-uniform, with some fins 106D having a greater width than others.

Each of the gate stacks 112E and 112F extends continuously to completely surround (or encircle) the second circuit region 122. In the illustrated embodiment, each of gate stack 112E and gate stack 112F is oriented parallel to an adjacent edge of second circuit region 122. The guard ring-like structure including the gate stack 112E is configured as a third guard ring (or a second inner guard ring). The guard ring-like structure including the gate stack 112F is configured as a fourth guard ring (or a second outer guard ring). The gate stacks 112E and 112F may be biased to a supply voltage (e.g., electrically grounded) by gate contact plugs, or the gate stacks 112E and 112F may be left floating. Further, gate stack 112E and gate stack 112F are disposed on the same set of fins 106D, and dummy source/drain regions (e.g., epitaxial features) are sandwiched between gate stack 112E and gate stack 112F. The dummy source/drain regions sandwiched between the gate stack 112E and the gate stack 112F are electrically grounded through a metal line 123 connected to the source/drain contact plugs. In the illustrated embodiment, the metal line 123 is located between the gate stacks 112E and 112F, and the metal line 123 extends continuously to completely surround (or encircle) the second circuit region 122. In some embodiments, the gate widths of gate stack 112C and gate stack 112D may be equal to each other, and the gate widths of gate stack 112E and gate stack 112F may be equal to each other, but greater than the gate widths of gate stack 112C and gate stack 112D. In some examples, the ratio of the gate widths of gate stacks 112E and 112F to the gate widths of gate stacks 112C and 112D may be greater than about 1.5. Further, the gate spacing between gate stack 112E and gate stack 112F may be greater than the gate spacing between gate stack 112C and gate stack 112D, such as a ratio of greater than about 1.5 in some examples. In some embodiments, the line width of metal line 123 is greater than the line width of metal line 113.

By having two pairs of guard rings, a first pair of guard rings including dummy gate stack 112C and dummy gate stack 112D and a second pair of guard rings including dummy gate stack 112E and dummy gate stack 112F, the second circuit region 122 is better protected from gate damage caused by lateral leakage of the etching solution. In one example, the lateral leakage reaches the second outer guard ring, and the gate stack 112F of the second outer guard ring has the same metal gate composition as the logic transistors in the first circuit region 120, while the gate stacks 112E, 112D, 112C have the same metal gate composition as the RF transistors in the second circuit region 122. In one example, the lateral leakage reaches the second inner guard ring, and the gate stacks 112F and 112E of the second outer guard ring have the same metal gate composition as the logic transistors in the first circuit region 120, while the gate stacks 112D, 112C have the same metal gate composition as the RF transistors in the second circuit region 122. In one example, the lateral leakage reaches the first outer guard ring, and the gate stack 112F of the second outer guard ring, the gate stack 112E of the second inner guard ring, and the gate stack 112D of the first outer guard ring have the same metal gate composition as the logic transistors in the first circuit region 120, while the gate stack 112C has the same metal gate composition as the RF transistors in the second circuit region 122. In one example, the lateral leakage reaches the first inner guard ring, and the gate stack 112F of the second outer guard ring, the gate stack 112E of the second inner guard ring, the gate stack 112D of the first outer guard ring, and the gate stack 112C of the first inner guard ring have the same metal gate composition as the logic transistors in the first circuit region 120, while the RF transistors in the second circuit region 122 are protected from the lateral leakage and have different metal gate compositions for RF applications.

Fig. 34A-34D illustrate some example transistors in which embodiments of the present disclosure may be applied so that these transistors may be used as logic transistors and/or RF transistors. Fig. 34A shows a cross-sectional view of a dual gate transistor in which two gates are formed on opposite sides of a channel. Fig. 34B shows a perspective view of a FinFET formed on substrate 102. Fig. 34C shows a perspective view of a GAA transistor including two channel layers with a metal gate stack wrapped around each of the two channel layers. Fig. 34D shows a GAA transistor including one channel layer. The gate stacks of these transistors may be formed using embodiments of the present disclosure to improve circuit performance.

The present disclosure provides various embodiments of an IC structure having a plurality of circuit regions with different functions, such as logic circuits and RF circuits. In the various embodiments described above, the RF circuitry is completely surrounded by one or more guard rings, thereby eliminating or reducing process defects due to lateral leakage of the etching solution during the replacement gate process. Accordingly, the overall IC structure has enhanced circuit performance without degrading manufacturing quality.

In one exemplary aspect, the present disclosure provides a semiconductor structure. The semiconductor structure includes a semiconductor substrate having a first circuit region and a second circuit region, a first transistor including a first gate stack disposed in the first circuit region, a second transistor including a second gate stack disposed in the second circuit region, the first gate stack and the second gate stack having different material compositions, and a guard ring structure disposed between the first circuit region and the second circuit region, the guard ring structure completely surrounding the second circuit region. In some embodiments, the second transistor is a high frequency transistor and the first transistor is a logic transistor. In some embodiments, the first circuit region completely surrounds the second circuit region. In some embodiments, the guard ring structure includes at least a dummy gate stack that extends continuously and completely surrounds the second circuit region. In some embodiments, the guard ring structure includes a first dummy gate stack and a second dummy gate stack, wherein each of the first dummy gate stack and the second dummy gate stack extends continuously and completely around the second circuit region. In some embodiments, the first dummy gate stack and the second dummy gate stack are disposed on at least the same active region. In some embodiments, the active region has a fin shape protruding from the semiconductor substrate. In some embodiments, the first gate stack and the first dummy gate stack comprise the same material composition that is different from the second gate stack and the second dummy gate stack. In some embodiments, the first gate stack, the first dummy gate stack, and the second dummy gate stack comprise the same material composition that is different from the second gate stack. In some embodiments, the first gate stack has a first gate pitch that is less than the reference pitch, and the second gate stack has a second gate pitch that is greater than the reference pitch.

In another exemplary aspect, the present disclosure provides a semiconductor structure. The semiconductor structure includes a semiconductor substrate having a logic circuit region and a Radio Frequency (RF) circuit region, a first transistor including a first gate stack disposed in the logic circuit region, a second transistor including a second gate stack disposed in the RF circuit region, and a guard ring structure disposed between the logic circuit region and the RF circuit region, the guard ring structure including an inner guard ring completely surrounding the RF circuit region and an outer guard ring completely surrounding the inner guard ring and the RF circuit region. In some embodiments, the guard ring structure further includes an epitaxial component disposed between the inner guard ring and the outer guard ring, and a metal line electrically coupled to the epitaxial component, and the metal line completely surrounds the RF circuit region. In some embodiments, the outer guard ring includes a first dummy gate stack and the inner guard ring includes a second dummy gate stack, and wherein the first dummy gate stack and the second dummy gate stack are disposed on the same active area. In some embodiments, the outer guard ring comprises a first dummy gate stack and the inner guard ring comprises a second dummy gate stack, and the first dummy gate stack comprises a first material composition that is the same as the first gate stack and the second dummy gate stack comprises a second material composition that is the same as the second gate stack. In some embodiments, the outer guard ring comprises a first dummy gate stack and the inner guard ring comprises a second dummy gate stack, and the first dummy gate stack and the second dummy gate stack comprise the same material composition as the first gate stack but different from the second gate stack. In some embodiments, the inner guard ring includes a first metal fill layer, the outer guard ring includes a second metal fill layer, and the first metal fill layer has a width greater than the second metal fill layer. In some embodiments, the guard ring structure is a first guard ring structure, and the semiconductor structure further includes a second guard ring structure disposed between the logic circuit region and the first guard ring structure.

In yet another exemplary aspect, the present disclosure provides a method of manufacturing a semiconductor device. The method includes forming a first gate stack in a first circuit region of the substrate, forming a second gate stack in a second circuit region of the substrate, forming a third gate stack in a guard ring region between the first circuit region and the second circuit region, each of the first gate stack, the second gate stack, and the third gate stack comprising a same material composition, and in a top view, the third gate stack completely surrounds the second circuit region, depositing a patterned mask layer covering the guard ring region and the second circuit region, performing an etching process to remove the first metal fill layer in the first gate stack, the etching process further partially etching the third gate stack to form a gap, depositing a second metal fill layer in the second gate stack and in the gap of the third gate stack, and planarizing the semiconductor device to expose the first metal fill layer in the second gate stack. In some embodiments, the first metal fill layer and the second metal fill layer comprise the same metal but have different grain sizes. In some embodiments, the first circuit region is a logic circuit region and the second circuit region is a Radio Frequency (RF) circuit region.

The foregoing outlines features of the drop dry embodiment. Those skilled in the art should appreciate that they may readily use the present disclosure as a basis for designing or modifying other processes and structures for carrying out the same purposes and/or achieving the same advantages of the embodiments introduced herein. Those skilled in the art should also realize that such equivalent constructions do not depart from the spirit and scope of the present disclosure, and that they may make various changes, substitutions, and alterations herein without departing from the spirit and scope of the present disclosure.

Claims

1. A semiconductor structure, comprising:

a semiconductor substrate having a first circuit region and a second circuit region;

a first transistor including a first gate stack disposed in the first circuit region;

a second transistor including a second gate stack disposed in the second circuit region, wherein the first gate stack and the second gate stack have different material compositions; and

and a guard ring structure disposed between the first circuit region and the second circuit region, wherein the guard ring structure completely surrounds the second circuit region.

2. The semiconductor structure of claim 1, wherein the second transistor is a high frequency transistor and the first transistor is a logic transistor.

3. The semiconductor structure of claim 1, wherein the first circuit region completely surrounds the second circuit region.

4. The semiconductor structure of claim 1, wherein the guard ring structure comprises at least a dummy gate stack that extends continuously and completely around the second circuit region.

5. The semiconductor structure of claim 1, wherein the guard ring structure comprises a first dummy gate stack and a second dummy gate stack, wherein each of the first dummy gate stack and the second dummy gate stack extends continuously and completely around the second circuit region.

6. The semiconductor structure of claim 5, wherein the first dummy gate stack and the second dummy gate stack are disposed on at least the same active region.

7. The semiconductor structure of claim 6, wherein the active region has a fin shape protruding from the semiconductor substrate.

8. The semiconductor structure of claim 5, wherein the first gate stack and the first dummy gate stack comprise a same material composition that is different from the second gate stack and the second dummy gate stack.

9. A semiconductor structure, comprising:

a semiconductor substrate having a logic circuit region and a Radio Frequency (RF) circuit region;

a first transistor including a first gate stack disposed in the logic circuit region;

a second transistor including a second gate stack disposed in the radio frequency circuit region; and

and a guard ring structure disposed between the logic circuit region and the radio frequency circuit region, wherein the guard ring structure includes an inner guard ring completely surrounding the radio frequency circuit region and an outer guard ring completely surrounding the inner guard ring and the radio frequency circuit region.

10. A method of manufacturing a semiconductor device, comprising:

forming a first gate stack in a first circuit region of a substrate;

forming a second gate stack in a second circuit region of the substrate;

forming a third gate stack in a guard ring region between the first circuit region and the second circuit region, wherein the first gate stack, the second gate stack, and the third gate stack each comprise the same material composition, and wherein the third gate stack completely surrounds the second circuit region in a top view;

Depositing a patterned mask layer covering the guard ring region and the second circuit region;

performing an etching process to remove the first metal fill layer in the first gate stack, wherein the etching process also partially etches the third gate stack to form a gap;

depositing a second metal fill layer in the second gate stack and in the gap of the third gate stack; and

the semiconductor device is planarized to expose the first metal fill layer in the second gate stack.