TWI758084B - Flash memory, flash memory cell and operation method thereof - Google Patents

Abstract

A flash memory, a flash memory cell and an operation method thereof are discussed in this invention. The flash memory cell includes a rectifying device and a transistor. The rectifying device has an input end coupled to a bit line. The transistor has a charge storage structure. The transistor has a first end coupled to an output end of the rectifying device, the transistor has a second end coupled to a source line, and a control end of the transistor is coupled to a word line.

Description

Flash memory, flash memory cell and method of operation

The present invention relates to a flash memory, a flash memory cell and an operation method thereof, and more particularly, to a flash memory with a double-ended access mechanism, a flash memory cell and an operation method thereof.

In the conventional technical field, NOR Flash Memory constructs a single flash memory cell by means of a transistor (1T). Such a form of flash memory cell cannot provide an over-erase action, so that the threshold voltage of the flash memory cell can be a negative voltage. Under such a premise, the conventional NAND flash memory in the technical field needs to provide a higher word line voltage to activate the transistor and read the stored data during the read operation. Therefore, in the prior art, the read speed of the flash memory cells is limited, and high power consumption is required. Correspondingly, when the programming operation is performed, since the threshold voltage of the flash memory cell needs to be raised to a relatively high voltage value, a higher programming voltage is also required, which also results in high power consumption. In addition, it also has a negative impact on leakage current and data reliability.

The present invention provides a flash memory and its flash memory cells, which can reduce the leakage phenomenon of selected memory cells, and can support the functions of over-erase and 0 word line voltage reading.

The flash memory cell of the present invention includes a rectifier element and a transistor. The rectifier element has an input terminal coupled to the bit line. The transistor has a charge storage structure. The transistor has a first end coupled to the output end of the rectifier element, the transistor has a second end coupled to the source line, and the control end of the transistor coupled to the word line.

The flash memory of the present invention includes a plurality of flash memory cells, a plurality of bit lines, a plurality of word lines and a plurality of source lines. The flash memory cells are arranged in a memory cell array, and the memory cell array has a plurality of memory cell rows and a plurality of memory cell columns. The bit lines are respectively coupled to the memory cell rows. The word lines are respectively coupled to the memory cell rows. The source lines are respectively coupled to the memory cell rows. Each of the flash memory cells includes a rectifying element and a transistor. The rectifying element has an input terminal coupled to the corresponding bit line. A transistor has a charge storage structure. The transistor has a first end coupled to the output end of the rectifying element. The transistor has a second end coupled to the corresponding source line. The control end of the transistor is coupled to the corresponding word line.

The operating method of the flash memory of the present invention includes: providing a rectifying element to be coupled between a corresponding bit line and a transistor having a charge storage structure; in the programming action, selecting a selected character corresponding to a selected memory cell The line receives the first voltage; the selected bit line corresponding to the selected memory cell receives the second voltage; the selected source line corresponding to the selected memory cell receives the third voltage, wherein the first voltage is greater than the second voltage, The second voltage is greater than the third voltage.

Based on the above, the flash memory cell proposed by the present invention has a rectifier element to be coupled between the transistor and the bit line, and has a double-terminal access structure. This double-terminal access architecture can avoid leakage of unselected flash memory cells, and can provide over-erase operations and 0-word line voltage reading functions. In addition, the read speed of the flash memory constructed by the flash memory cells of the present invention can be improved, and the circuit layout area required by the memory cell array can also be effectively reduced.

Please refer to FIG. 1 , which is a schematic diagram of a flash memory cell according to an embodiment of the present invention. The flash memory cell 100 includes a rectifier element 110 and a transistor 120 . The rectifying element 110 has an input terminal to be coupled to the bit line BL. The transistor 120 has a charge storage structure. The transistor 120 has a first terminal coupled to the output terminal of the rectifier element 110; the transistor 120 has a second terminal coupled to the source line SL; and a control terminal of the transistor 120 coupled to the word line WL.

In this embodiment, the transistor 120 has a floating gate FG, and the floating gate FG is used to form a charge storage structure. The transistor 120 also has a control gate CG. The control gate CG of the transistor 120 is coupled to the word line WL.

In this embodiment, the rectifying element 110 is turned on when the voltage on the input terminal is greater than a threshold value, and makes the voltage on the output terminal equal to the voltage on the input terminal minus the threshold value. On the contrary, when the voltage on the input terminal of the rectifying element 110 is not greater than the critical value, the rectifying element 110 is equivalently turned off. At this time, the output end of the rectifier element 110 may be in a floating state.

According to the above, when the flash memory cell 100 is set as the unselected flash memory cell in the programming operation, the voltage on the bit line BL and/or the voltage on the word line WL can be lowered by pulling down the voltage on the bit line BL. , so that the flash memory cell 100 is effectively inhibited, thereby reducing the possibility of leakage.

Please refer to FIG. 2 below. FIG. 2 is a schematic diagram of a flash memory cell according to another embodiment of the present invention. The flash memory cell 200 includes a rectifier element 210 and a transistor 220 . The rectifying element 210 has an input terminal to be coupled to the bit line BL. The transistor 220 has a charge storage structure. The transistor 220 has a first end coupled to the output end of the rectifier element 210; the transistor 220 has a second end coupled to the source line SL; and a control end of the transistor 220 coupled to the word line WL.

In this embodiment, the rectifying element 210 is a diode D1. The anode of the diode D1 may be the input end of the rectifying element 210 , and the cathode of the diode D1 may be the output end of the rectifying element 210 . The diode D1 can be turned on when the voltage on the bit line is greater than its turn-on voltage, and when the voltage on the bit line is not greater than its turn-on voltage, the diode D1 can be turned off.

Please refer to FIG. 2 and FIG. 3 synchronously below, wherein FIG. 3 is a cross-sectional view of the structure of the flash memory cell according to the embodiment of FIG. 2 of the present invention. In FIG. 3 , the transistor 220 includes a substrate 221 , doped regions 222 and 223 and a gate structure 224 . The doped regions 222 and 223 are disposed in the substrate 221 and have different conductivity types from the substrate 221 . The gate structure 224 includes a control gate CG, an insulating layer I1, a floating gate FG, and a tunnel oxide layer TO. The tunnel oxide layer TO, the floating gate FG, the insulating layer I1 and the control gate CG sequentially cover between the doped regions 222 and 223 on the substrate 221 .

In this embodiment, the doped region 222 is coupled to the output end of the rectifying element 210 through the conductive structure WIR. The input terminal of the rectifying element 210 is coupled to the bit line BL. The rectifying element 210 may be a diode with a PN junction and is formed on the upper surface of the substrate 221 . The P pole of the diode D1 is coupled to the bit line BL, and the N pole is coupled to the conductive structure WIR. The doped region 223 is coupled to the source line SL. In this embodiment, the source line SL and the conductive structure WIR can be formed by using a metal structure of the same material.

In addition, the substrate 221 in this embodiment can be a P-type substrate, and the doped regions 222 and 223 can be enhanced-type N-type doped regions.

Please note here that in other embodiments, the rectifier element 210 may be replaced by a selector. The selector can be formed by using a back-end of line (BEOL). For details of the selector, please refer to FIG. 4A and FIG. 4B .

FIG. 4A and FIG. 4B are respectively a schematic structural diagram and an electrical characteristic diagram of a selector for constructing a rectifier element according to an embodiment of the present invention. In FIG. 4A , the selector 400 may be formed by overlapping three structures 410 to 430 of different materials. The structure 410 may be a tungsten-plug, and the structure 420 may have a compound material composed of arsenic (As), selenium (Se), and germanium (Ge). The structure 430 may be a titanium nitride (TiN) structure.

In FIG. 4B , the curves C1 to C4 respectively represent the current-voltage (IV) relationship diagram of the selector 400 under different numbers of use cycles. Among them, the curves C1 to C4 respectively correspond to a plurality of service cycles from small to large. Taking curve C4 as an example, when the voltage received by the selector 400 gradually increases and increases to approximately greater than 4 volts, the selector 400 behaves as a diode that is turned on and provides a rapidly increasing output current. When the voltage received by selector 400 increases to approximately equal to 5 volts (or greater), the output current produced by selector 400 may be limited to approximately 10 ⁻³ amps. It should be noted that when the voltage received by the selector 400 drops, if the voltage received by the selector 400 is greater than 2 volts, the selector 400 will maintain an output current of about 10 ⁻³ to 10 ⁻⁴ amps. When the voltage received by selector 400 drops below 2 volts, selector 400 will drop sharply and behave as a diode that is turned off.

Incidentally, the structure of the selector 400 shown in FIG. 4A is only an example for illustration, and is not intended to limit the scope of the present invention. Any structure of the selector 400 that is known to those skilled in the art and that can be implemented through a back-end-of-line (BEOL) process can be applied to the present invention.

Please refer to FIG. 5 below. FIG. 5 is a cross-sectional view of a flash memory cell structure according to another embodiment of the present invention. The flash memory cell 500 includes a rectifier element 510 and a transistor 520 . The rectifying element 510 is formed by overlapping a P-type enhanced (P+) doped region 511 and an N-type enhanced (N+) doped region 512 respectively. The P+ doped region 511 is coupled to the bit line BL, and the N+ doped region 512 is coupled to the transistor 520 . The transistor 520 includes a substrate 525 , a doped region 523 , a polysilicon structure 524 , a memory gate (MG) 521 and a silicon oxide-silicon nitride-silicon oxide (ONO) structure 522 .

In this embodiment, the transistor 520 is a gate-all-around (GAA) transistor. Wherein, the doped region 523 is disposed in the substrate 525 and has a conductivity polarity different from that of the substrate 525 . The polysilicon structure 524 can be a pillar and is disposed on the doped region 523 to form a vertical structure. The memory gate 521 surrounds the polysilicon structure 522 and is coupled to the word line WL. The ONO structure 522 is disposed between the memory gate 521 and the polysilicon structure 524, wherein the ONO structure 522 is used as a charge storage structure.

Incidentally, the transistor 520 may share the doped region 512 with the rectifier element 510 . The doped region 512 can be used as the cathode of the rectifier element 510 and the source of the transistor 520 at the same time.

In this embodiment, the conductivity type of the substrate 525 may be P-type, and the doped region 523 may be an N-type enhanced (N+) doped region.

Please refer to FIG. 6 below. FIG. 6 is a schematic diagram of a flash memory according to an embodiment of the present invention. The flash memory 600 includes multiple flash memory cells MC1 ˜MC(N*M), multiple bit lines BL1 ˜BLM, multiple word lines WL1 ˜WLM, and multiple source lines SL1 ˜SLN. Wherein, each of the flash memory cells MC1 ˜MC(N*M) can be implemented by any one of the flash memory cells 100 , 200 , and 500 of the foregoing embodiments, and the diode in the figure is a rectifying element . The flash memory cells MC1~MC(N*M) are arranged in a memory cell array. The memory cell array has a plurality of memory cell rows and a plurality of memory cell columns. The bit lines BL1 ˜BLM are respectively coupled to a plurality of memory cell rows, the word lines WL1 ˜WLM are respectively coupled to a plurality of memory cell rows, and the source lines SL1 ˜SLN are respectively coupled to a plurality of memory cell rows. The flash memory cells MC1 ˜MC(N*M) can be implemented by using any of the flash memory cells in the foregoing embodiments, and there is no specific limitation.

In terms of layout, the word lines WL1 ˜WLM and the bit lines BL1 ˜BLM may extend in the same first direction, and the source lines SL1 ˜SLN may extend in a second direction different from the first direction. The first direction may be orthogonal to the second direction.

In this embodiment, the flash memory 600 also includes a controller 610 . The controller 610 is coupled to the flash memory cells MC1 ˜MC(N*M), and provides voltage to the flash memory cell MC1 through the word lines WL1 ˜WLM, the bit lines BL1 ˜BLM and the source lines SL1 ˜SLN ~MC(N*M) to perform a program, erase or read operation on each of the flash memory cells MC1~MC(N*M). The controller 610 is also used to execute the operation method of the embodiment of the present invention, and execute each of the flash memory cells MC1 ˜MC(N*M) to execute programming, erasing, or reading operations.

In the details, in the programmed action, the flash memory cell MCA is used as the selected memory cell, and the flash memory cells MCB~MCD are used as the unselected memory cells as an example. The controller 610 can make the word line WLM corresponding to the flash memory cell MCA to be 8 volts; the bit line BLM to be -8 volts; and the source line SL3 to be -8 volts. And make the flash memory cell MCA perform programmed actions through FN tunneling. At the same time, the controller 610 can make the source line SL2 corresponding to the flash memory cell MCB to be 0 volts, so that the word line WLM-1 and the bit line BLM-1 corresponding to the flash memory cells MCC and MCD are both 0 volts. In this way, the non-selected flash memory cells MCB~MCD can be effectively masked without performing programmed actions.

It is worth mentioning that in this embodiment, the flash memory cells MCA to MCD are arranged in the same well region (eg, a P-type well region) in the integrated circuit. In programming, the well region receives a bias voltage of -8 volts, for example.

If the programming operation is performed by channel hot electron injection, the controller 610 can make the word line WLM corresponding to the flash memory cell MCA to be 10 volts; the bit line BLM to be 5 volts; and the source line SL3 to be 0 volts. Meanwhile, the controller 610 sets the source line SL2 corresponding to the flash memory cell MCB to 5 volts, and sets the word line WLM-1 and the bit line BLM-1 corresponding to the flash memory cells MCC and MCD to 0 volts. The well region then receives, for example, a bias voltage of 0 volts. In this way, the flash memory cells MCA can be effectively programmed, and the flash memory cells MCB~MCD can be effectively masked.

During the erase operation, the controller 610 can make the bit lines BLM, BLM-1, the word lines WLM, WLM-1, and the source lines SL2, SL3 to be all 0 volts. The controller 610 also provides an erase voltage (eg, 16 volts) to the well region, so as to execute the block erase operation through FN tunneling for the flash memory cells MCA~MCD.

During the read operation, the controller 610 can make the word line WLM corresponding to the selected flash memory cell MCA to be 0 volts; the bit line BLM to be 1.2 volts; and the source line SL3 to be 0 volts. At the same time, the controller 610 can make the source line SL2 corresponding to the flash memory cell MCB to be 1.2 volts, so that the word line WLM-1 and the bit line BLM-1 corresponding to the flash memory cells MCC and MCD are all 0 volts. In this way, the data of the flash memory cell MCA can be read, and the flash memory cells MCB~MCD can be masked.

During the read operation, the well area shared by the flash memory cells MCA~MCD receives a bias voltage of 0 volts.

Please note that in the architecture of this embodiment, each of the flash memory cells MC1 ˜MC(N*M) may be allowed to perform an over erase operation. That is, the threshold voltage of the erased flash memory cell is made a negative voltage value. Under such conditions, when the read operation is performed, in the embodiment of the present invention, the voltage value of the bias voltage imparted to the flash memory cell can be reduced, thereby reducing the required power consumption. Moreover, under the premise of low-voltage operation, the leakage current that may be generated in the flash memory device 600 of the embodiment of the present invention can be effectively reduced.

It is worth mentioning that, in the above embodiments, the values of the voltages applied to the word line, the bit line, the source line and the well region are only examples for illustration, and are not intended to limit the scope of the present invention. In actual use, the value of the voltage applied to the word line, bit line, source line and well area can be set according to various factors such as the process parameters of the integrated circuit and the voltage value of the operating power supply. There are no fixed limits.

In addition, the controller 610 may be constructed using any form of digital circuitry. In practical use, the controller 610 can be matched with an analog voltage generator to provide various voltages corresponding to the programming action, the erasing action or the reading action to the flash memory cells at an appropriate time. Here, how to control to provide various voltages corresponding to programming actions, erasing actions or reading actions to the flash memory cells is well known to those skilled in the art, and will not be repeated here.

To sum up, in the flash memory cell of the present invention, a rectifying element is arranged between the transistor and the bit line, so that the flash memory cell can provide a mechanism of double-terminal access. In this way, the flash memory cell can perform an over-erase operation, and the threshold voltage can be a negative voltage value. Under such conditions, the bias voltage value required for the access operation of the flash memory cell can be reduced, thereby effectively reducing the power consumption and the possible leakage current phenomenon. At the same time, the read speed of the flash memory can also be improved.

100, 200, 500, MC1~MC(N*M): Flash memory cells 110, 210, 510: Rectifier components 120, 220, 520: Transistor 221, 525: base 222, 223, 511, 512, 523: doped regions 224: Gate structure 400: selector 410~430: Structure 521: Memory gate 522: ONO structure 524: Polysilicon Structure 600: flash memory BL, BL1~BLM: bit lines C1~C4: Curve CG: Control Gate D1: Diode FG: floating gate I1: insulating layer SL, SL1~SLN: source line TO: Tunneling Oxide WIR: Conductive Structure WL, WL1~WLM: word line

FIG. 1 is a schematic diagram of a flash memory cell according to an embodiment of the present invention. FIG. 2 is a schematic diagram of a flash memory cell according to another embodiment of the present invention. FIG. 3 is a cross-sectional view of the structure of the flash memory cell according to the embodiment of FIG. 2 of the present invention. FIG. 4A and FIG. 4B are respectively a schematic structural diagram and an electrical characteristic diagram of a selector for constructing a rectifier element according to an embodiment of the present invention. FIG. 5 is a cross-sectional view of a flash memory cell structure according to another embodiment of the present invention. FIG. 6 is a schematic diagram of a flash memory according to an embodiment of the present invention.

100: Flash Memory Cell

110: Rectifier element

120: Transistor

BL: bit line

SL: source line

WL: word line

FG: floating gate

CG: Control Gate

Claims (17)

A flash memory cell, comprising: a rectifier element having an input end coupled to a bit line; and a transistor having a charge storage structure, the transistor having a first end coupled to an output end of the rectifier element , the transistor has a second end coupled to a source line, and a control end of the transistor coupled to a word line, wherein the transistor is a gate-all-around (GAA) transistor , and has a silicon monoxide-silicon nitride-silicon oxide structure as the charge storage structure. The flash memory cell of claim 1, wherein the transistor has a floating gate for forming the charge storage structure. The flash memory cell of claim 2, wherein the transistor further has a control gate coupled to the word line and covering the floating gate. The flash memory cell of claim 1, wherein the rectifying element is a diode, the anode of the diode is the input end of the rectifying element, and the cathode of the diode is the output end of the rectifying element. The flash memory cell of claim 1, wherein the rectifying element is a selector formed by a back-end of line (BEOL). The flash memory cell of claim 1, wherein the transistor further comprises: a substrate, a first doped region coupled to the source line; and a polysilicon structure disposed on the first doped region ; Silicon monoxide-silicon nitride-silicon oxide structure; a memory gate surrounding the polysilicon structure and coupled to the word line, wherein the silicon oxide-silicon nitride-silicon oxide structure is disposed on the memory gate and the polysilicon structure; a second doping region disposed above the polysilicon structure; and a third doping region disposed above the second doping region and coupled to the bit line, wherein , the first doped region and the second doped region have the same conductivity polarity, and the second doped region and the third doped region have different conductivity polarities. A flash memory, comprising: a plurality of flash memory cells arranged into a memory cell array, the memory cell array has a plurality of memory cell rows and a plurality of memory cell columns; a plurality of bit lines, respectively coupled to the memory cell array some memory cell rows; a plurality of word lines, respectively coupled to the memory cell rows; and a plurality of source lines, respectively coupled to the memory cell rows; wherein each of the flash memory cells includes: a rectifier element , which has an input terminal coupled to the corresponding bit line; and a transistor with a charge storage structure, the transistor has a first terminal coupled to the output terminal of the rectifier element, and the transistor has a second terminal coupled to To the corresponding source line, the control end of the transistor is coupled to the corresponding word line, wherein the rectifying element is a selector formed by a back-end of line (BEOL). The flash memory of claim 7, wherein the transistor has a floating gate and a control gate, the floating gate is used as the charge storage structure, and the control gate is coupled to the word line and cover the floating gate. The flash memory of claim 7, wherein the transistor is a gate-all-around (GAA) transistor and has a silicon monoxide-silicon nitride-silicon oxide structure as the charge storage structure. The flash memory of claim 7, wherein the rectifying element is a diode, the anode of the diode is the input end of the rectifying element, and the cathode of the diode is the output end of the rectifying element. The flash memory of claim 7, further comprising: a controller coupled to the flash memory cells, wherein in a programming action, the controller: makes a corresponding one of the selected memory cells The selected word line receives a first voltage, so that a selected bit line corresponding to the selected memory cell receives a second voltage, and a selected source line corresponding to the selected memory cell receives a third voltage, The first voltage is greater than the second voltage, and the second voltage is greater than the third voltage. The flash memory of claim 11, wherein the controller causes the selected memory cell to perform the programming action by channel hot electron injection or PN tunneling. The flash memory of claim 11, wherein a plurality of first flash memory cells in the flash memory cells are arranged in the same well area, and after erasing During the operation, the controller provides an erase voltage to the well region and executes a block erase operation for the first flash memory cells. The flash memory of claim 13, wherein the controller performs the erase operation in a PN tunneling manner. A method for operating a flash memory, comprising: providing a rectifier element to be coupled between a corresponding bit line and a transistor having a charge storage structure; in a programming action, making a selected memory cell correspond to A selected word line of the selected memory cell receives a first voltage; a selected bit line corresponding to the selected memory cell receives a second voltage; a selected source line corresponding to the selected memory cell receives a third voltage voltage, wherein the first voltage is greater than the second voltage, and the second voltage is greater than the third voltage; and the selected memory cell performs the programming operation in a channel hot electron injection mode or a PN tunneling mode. The operating method of claim 15, further comprising: in an erase operation, supplying an erase voltage to a well region and performing a block erase operation on a plurality of first flash memory cells, wherein the first flash memory cells Flash cells are located in the same well area. The operation method of claim 16, further comprising: performing the erasing action in a PN tunneling manner.

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