TWI755823B - 用以沈積一阻障層之方法及使用其之薄膜封裝結構 - Google Patents

用以沈積一阻障層之方法及使用其之薄膜封裝結構 Download PDF

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TWI755823B
TWI755823B TW109128597A TW109128597A TWI755823B TW I755823 B TWI755823 B TW I755823B TW 109128597 A TW109128597 A TW 109128597A TW 109128597 A TW109128597 A TW 109128597A TW I755823 B TWI755823 B TW I755823B
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barrier layer
thin film
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mhz
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泰景 元
壽永 崔
任東吉
李永東
吳宗凱
尚傑 亞大夫
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美商應用材料股份有限公司
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Abstract

本揭露之數個實施例一般有關於應用於一有機發光二極體裝置中的數種水氣阻障膜。一種水氣阻障膜係在少於約攝氏250度之一溫度、約2MHz至約13.56MHz之一感應耦合電漿功率頻率或約2.45GHz之一微波功率頻率、及約1011cm3至約1012cm3之一電漿密度於一高密度電漿化學氣相沈積腔室中沈積。水氣阻障膜包括選自由氮氧化矽、氮化矽、及氧化矽所組成的群組之一材料。水氣阻障膜具有少於約3,000埃之一厚度、約1.45及1.95之間的一折射率、及在紫外線波長下之約零之一吸收係數。水氣阻障膜可利用於一薄膜封裝結構或一薄膜電晶體中。

Description

用以沈積一阻障層之方法及使用其之薄膜封裝結構
本揭露之數個實施例一般是有關於一有機發光二極體(organic light emitting diode，OLED)裝置，且特別是有關於數種應用於一OLED裝置中的水氣阻障膜。
在製造平面面板顯示器中，許多製程係應用來沈積例如是水氣阻障膜之薄膜於基板上，以形成電子裝置於其上。基板例如是半導體基板、太陽能板基板、液晶顯示器(liquid crystal display，LCD)及/或OLED基板。此些薄膜之沈積一般藉由引入前驅氣體於具有基板之真空腔室中。基板係設置於溫度控制的基板支撐件上。前驅氣體一般係導引通過氣體分佈板，氣體分佈板位於接近真空腔室的頂部的位置。藉由提供來自一或多個射頻(radio frequency，RF)源的RF功率至設置於腔室中的導電噴頭，真空腔室中的前驅氣體可致能(energized)(舉例為激發(excited))成電漿。此一或多個RF源係耦接於腔室。激發之氣體係作用，以形成材料層於基板的表面上。
通常係使用電容耦合電漿(capacitively coupled plasma，CCP)配置，以沈積阻障膜於OLED及LCD基板上。傳統上，電漿係在傳統之腔室中利用CCP配置來離子化氣體原子及形成沈積氣體之自由基(radicals)。離子化氣體原子及形成沈積氣體之自由基係對沈積薄層於基板上有用處。然而，利用CCP配置所沈積的阻障膜一般係相當厚，而具有約7,000埃(angstroms)至約10,000之厚度、在紫外線(ultraviolet，UV)波長具有非零之吸收係數、及具有大於1.7之折射率。
因此，對於沈積用於OLED及LCD結構之阻障膜的改善方法係有需求。
本揭露之數個實施例一般有關於應用於一有機發光二極體裝置中的數種水氣阻障膜。一種水氣阻障膜係在少於約攝氏250度之一溫度、約2MHz至約13.56MHz之一感應耦合電漿功率頻率或約2.45GHz之一微波功率頻率、及約1011cm3至約1012cm3之一電漿密度於一高密度電漿化學氣相沈積腔室中沈積。水氣阻障膜包括選自由氮氧化矽、氮化矽、及氧化矽所組成的群組之一材料。水氣阻障膜具有少於約3,000埃之一厚度、約1.45及1.95之間的一折射率、及在紫外線(UV)波長下之約零之一吸收係數。水氣阻障膜可利用於一薄膜封裝結構或一薄膜電晶體中。
一種用以沈積一阻障層之方法，包括放置一基板於一化學氣相沈積(chemical vapor deposition，CVD)腔室中，CVD腔室包 括一高密度電漿配置；以及在少於約攝氏250度之一溫度、約2MHz至約13.56MHz之一功率頻率、及約1011cm3至約1012cm3之一電漿密度，利用高密度電漿配置沈積阻障層於基板之上方。
一種薄膜封裝結構，包括一第一阻障層，利用一高密度電漿化學氣相沈積(CVD)腔室沈積，第一阻障層包括選自由氮氧化矽、氮化矽、及氧化矽所組成的群組之一材料，其中第一阻障層具有少於約3,000埃之一厚度、約1.45及1.95之間的一折射率、及約零之一吸收係數；一緩衝層，設置於第一阻障層上；以及一第二阻障層，設置於緩衝層上。
一種用以沈積一阻障層之方法，包括放置一基板於一化學氣相沈積(CVD)腔室中，CVD腔室包括一高密度電漿配置；以及在少於約攝氏250度之一溫度、約2MHz至約13.56MHz之一功率頻率、及約1011cm3至約1012cm3之一電漿密度，利用高密度電漿配置沈積阻障層於基板之上方，其中阻障層具有少於約3,000埃之一厚度、約1.45及1.95之間的一折射率、及約零之一吸收係數。為了對本發明之上述及其他方面有更佳的瞭解，下文特舉實施例，並配合所附圖式詳細說明如下：
100:腔室
101:CVD設備
102:壁
104:底部
106:噴頭
108:流量閥開孔
110:真空幫浦
112:背板
114:架狀突出部
116:致動器
118,204:基板支撐件
120,302,402:基板
122:升舉銷
124:加熱及/或冷卻元件
126:射頻(RF)回程帶
128:RF源
130:遠端源
132:氣源
134:噴頭懸架
136:唇部
150:緊固機構
190:匹配網路
200:高密度電漿(HDP)配置
202:電漿腔室
206:氣體擴散器
208:介電板
210:HDP天線線圈
212:終端電容
214:中間電容
216:匹配電路
218:電源
300:顯示裝置
304:發光裝置
306:覆蓋層
308:第一阻障層
310:緩衝層
312:第二阻障層
314:薄膜封裝(TFE)結構
400:薄膜電晶體(TFT)
404:閘極電極
406:閘極絕緣層
408:半導體層
410:保護層
412:汲極
414:源極
為了使本揭露的上述特徵可詳細地瞭解，簡要摘錄於上之本揭露之更特有之說明可參照數個實施例。部分之實施例係繪示於所附之圖式中。然而，值得注意的是，所附之圖式係僅繪示出範例的實施例及因而不視為其範圍的限制，及可承認其他等效實施例。
第1圖係為根據一實施例之化學氣相沈積設備的剖面圖。
第2圖繪示根據一實施例之高密度電漿配置的示意圖。
第3圖係為根據一實施例之具有薄膜封裝結構設置於其上之顯示裝置的剖面圖。
第4圖係為根據另一實施例之應用於顯示裝置中之薄膜電晶體的剖面圖。
為了有助於瞭解，相同的參考編號係在可行之處使用來表示此些圖式之通用的相同元件。將理解的是，一實施例的數個元件及數個特徵可在其他實施例中有利地合併，而無需進一步引述。
本揭露之數個實施例一般有關於應用於一有機發光二極體裝置中的數種水氣阻障膜。一種水氣阻障膜係在少於約攝氏250度之一溫度、約2MHz至約13.56MHz之一感應耦合電漿功率頻率或約2.45GHz之一微波功率頻率、及約1011cm3至約1012cm3之一電漿密度於一高密度電漿化學氣相沈積腔室中沈積。水氣阻障膜包括選自由氮氧化矽、氮化矽、及氧化矽所組成的群組之一材料。水氣阻障膜具有少於約3,000埃之一厚度、約1.45及1.95之間的一折射率、及在紫外線(UV)波長下之約零之一吸收係數。水氣阻障膜可利用於一薄膜封裝結構或一薄膜電晶體中。
第1圖係為化學氣相沈積(chemical vapor deposition，CVD)設備101之剖面圖，CVD設備101可使用以執行此處所述的數個 操作。CVD設備101可為電漿輔助CVD設備。CVD設備101包括腔室100，一或多個膜可在腔室100中沈積於基板120上。腔室100一般包括壁102、底部104、及噴頭106。壁102、底部104、及噴頭106係共同定義出處理空間。此處理空間可為真空環境。基板支撐件118係設置於處理空間中。處理空間係透過流量閥開孔108進出，使得基板120可傳送進入及離開腔室100。基板支撐件118可耦接於致動器116，以升起及降低基板支撐件118。升舉銷122係可移動地穿過基板支撐件118，以移動基板120至基板接收表面及從基板接收表面移動基板120。基板支撐件118亦包括加熱及/或冷卻元件124，以維持基板支撐件118於所需的溫度。基板支撐件118亦包括射頻(RF)回程帶(strap)126，以在基板支撐件118之周圍提供RF回程路徑。
噴頭106藉由緊固機構150耦接於背板112。噴頭106藉由一或多個緊固機構150耦接於背板112，以有助於避免下垂(sag)及/或控制噴頭106之直線度(straightness)/曲率。
氣源132耦接於背板112，以通過噴頭106中之氣體通道提供氣體至噴頭106及基板120之間的處理區域。真空幫浦110耦接於腔室100，以維持處理空間於所需之壓力。RF源128係透過匹配網路190耦接於背板112及/或耦接於噴頭106，以提供RF電流至噴頭106。RF電流在噴頭106及基板支撐件118之間產生電場，使得電漿可從噴頭106及基板支撐件118之間的氣體產生。
遠端源130可亦耦接於氣源132及背板112之間，遠端源130例如是感應耦合遠端電漿源。處理基板期間，清洗氣體可提供 至遠端源130，以產生遠端電漿。來自遠端電漿的自由基可提供至腔室100，以清洗腔室100元件。清洗氣體可更藉由提供至噴頭106的RF源128激發。
噴頭106係藉由噴頭懸架134額外地耦接於背板112。於一實施例中，噴頭懸架134係可彎曲金屬裙部(skirt)。噴頭懸架134具有唇部136，噴頭106可設置於唇部136上。背板112可設置於耦接於壁102之架狀突出部(ledge)114的上表面上，以密封腔室100而形成真空環境。
第2圖繪示根據一實施例之高密度電漿(high density plasma，HDP)配置200的示意圖。HDP配置200可與第1圖之CVD設備101一起使用，以形成HDP CVD腔室(也就是說，CVD設備101包括HDP配置200)。HDP配置200可為感應耦合電漿(inductively coupled plasma，ICP)配置或微波(microwave，MW)配置。HDP配置200包括基板支撐件204，基板支撐件204設置於電漿腔室202中。氣體擴散器206設置於電漿腔室202之上方，及介電板208設置於氣體擴散器206之上方。
一或多個HDP天線線圈210係設置於介電板208上或上方。終端電容212及中間電容214係耦接於此一或多個HDP天線線圈210。終端電容212可接地。中間電容214係耦接於電源218，電源218例如是RF源。電源218包括匹配電路216，或用以調整此一或多個HDP天線線圈210的電性特性之調配能力。對於ICP配置而言，功率頻率可為約2MHz至約13.56MHz。對於MW配置來說， 功率頻率可為約2.4GHz至約2.5GHz之間，例如是約為2.45GHz。
氣體擴散器206係裝配以傳送處理氣體到電漿腔室202。此一或多個HDP天線線圈210之各者係裝配以產生電磁場。在氣體流入氣體擴散器206之下方的電漿腔室202空間中時，電磁場係致能在氣體擴散器206之下方的電漿腔室202中之處理氣體成電漿。電漿接著形成一或多個膜或層於設置於基板支撐件204上的基板上。
HDP配置200係裝配，以藉由利用約1011cm3至約1012cm3之高電漿密度及少於約102eV之低離子轟擊能量來沈積或形成HDP CVD膜於基板上，而產生高離子化效率及低電漿損傷。HDP CVD膜例如是水氣阻障膜。HDP配置200可利用，以在例如是約低於攝氏250度的低溫下形成高品質的膜，及在低電弧可能性下具有高沈積率。HDP配置200之離子/自由基通量及能量係藉由源及偏壓功率獨立地控制。再者，利用HDP配置200來沈積水氣阻障層係致使水氣阻障層具有低折射率(RI)及廣範圍之RI控制。
反過來說，藉由CCP配置所形成或沈積之CVD膜一般具有約109cm3至1010cm3之低電漿密度及大於約102eV之高離子轟擊能量，而產生低離子化效率及高電漿損傷。再者，藉由CCP配置於例如是約低於攝氏250度之低溫下沈積而形成的膜具有低品質，及CCP配置具有在高電弧可能性下之低沈積率。CCP配置之離子/自由基通量及能量係僅藉由電源控制。
第3圖係為根據一實施例之具有薄膜封裝(thin film encapsulation，TFE)結構314設置於其上之顯示裝置300之剖面圖。 顯示裝置300包括基板302。基板302可以含矽材料、玻璃、聚醯亞胺(polyimide)、或塑膠製成。塑膠例如是聚對苯二甲酸乙二酯(polyethyleneterephthalate，PET)或聚萘二酸乙二醇酯(polyethylenenaphthalate，PEN)。發光裝置304係設置於基板302上。發光裝置304可為OLED裝置或量子點(quantum-dot)結構。接觸層(未繪示)可設置於發光裝置304及基板302之間，及接觸層係接觸基板302及發光裝置304。
覆蓋層306係設置於發光裝置304及基板302之上方。覆蓋層306可具有約1.7至約1.8之折射率。薄金屬層(未繪示)可設置於覆蓋層306之上方。第一阻障層308係設置於覆蓋層306或薄金屬層上。緩衝層310係設置於第一阻障層308上。第二阻障層312係設置於緩衝層310上。第一阻障層308、緩衝層310、及第二阻障層312包括TFE結構314。第一阻障層308及第二阻障層312係水氣阻障膜或層。
緩衝層310可包括有機材料，此有機材料具有約1.5之折射率。緩衝層310可包括有機矽化合物，例如是電漿聚合六甲基二矽氧烷(plasma-polymerized hexamethyldisiloxane，pp-HMDSO)、氟化電漿聚合六甲基二矽氧烷(fluorinated plasma-polymerized hexamethyldisiloxane，pp-HMDSO：F)、及六甲基二矽氮烷(hexamethyldisilazane，HMDSN)。或者，緩衝層310可為聚合物材料，由碳氫化合物所組成。聚合物材料可具有化學式CxHyOz，其中x、y及z係為整數。於一實施例中，緩衝層310可選自由聚丙烯酸酯 (polyacrylate)、聚對二甲苯(parylene)、聚醯亞胺(polyimides)、聚四氟乙烯(polytetrafluoroethylene)、氟化乙烯丙烯共聚物(copolymer of fluorinated ethylene propylene)、全氟烷氧基聚合物樹脂(perfluoroalkoxy copolymer resin)、乙烯-四氟乙烯共聚物(copolymer of ethylene and tetrafluoroethylene)及派瑞林(parylene)所組成之群組。於一特定例子中，緩衝層310係為派瑞林。
第一阻障層308可於HDP CVD腔室中利用HDP配置沈積。HDP CVD腔室例如是第1圖之CVD設備101。HDP配置例如是第2圖之HDP配置200。第一阻障層308係由選自由氮化矽(silicon nitride(SiN))、氧化矽(silicon oxide(SiO))、及氮氧化矽(silicon oxynitride(SiON))所組成之群組之材料所構成。此外，TFE結構314之各層可於HDP CVD腔室中利用HDP配置沈積。HDP CVD腔室例如是第1圖之CVD設備101。HDP配置例如是第2圖之HDP配置200。淨化CVD腔室可在數個週期之間執行，以減少污染之風險至最小。
為了利用ICP HDP配置沈積第一阻障層308，功率頻率可為約2MHz至約13.56MHz。為了利用MW HDP配置沈積第一阻障層308，功率頻率可為約2.4GHz至約2.5GHz，例如是約2.45GHz。第一阻障層係利用約1011cm3至約1012cm3之高電漿密度及少於約102eV之低離子轟擊能量來沈積，而產生高離子化效率及低電漿損傷。第一阻障層308在例如是約低於攝氏250度的低溫下沈積成高品質的膜，及在低電弧可能性下具有高沈積率。於包括SiO之第一阻障層308的一實施例中，第一阻障層308可以每分鐘約2000埃之速 率於約攝氏100度之溫度沈積。於包括SiN之第一阻障層308的一實施例中，第一阻障層308可以每分鐘約1,000埃之速率於約攝氏100度之溫度沈積。
再者，利用HDP配置沈積第一阻障層308係致使第一阻障層308具有約1.4至2.1之折射率(refractiveindex(RI))及約零之低吸收係數(absorption coefficient(k))，而產生在UV波長具有零或接近零之吸收的第一阻障層308。利用HDP配置所沈積之第一阻障層308更具有少於約3,000埃之厚度，例如是少於約2,000埃，而減少阻障厚度需求、減少彎曲/摺疊應力(bending/folding stress)、及減少需用以沈積第一阻障層308之總時間。再者，HDP配置係讓第一阻障層308簡易地沈積於側壁上或作為側壁阻障，而不會導致氧化而減少側壁阻障厚度需求。
於一實施例中，第一阻障層308包括SiN，且SiH4及NH3氣體係導引至腔室中來用以沈積SiN之第一阻障層308。舉例來說，可利用約100sccm之SiH4及約600sccm之NH3。約120mTorr之腔室壓力、約2MHz之ICP功率頻率、約3,000W之功率、及約1.725W/cm2之功率密度係可提供約300秒。
當利用HDP配置時，包括SiN之第一阻障層308可具有每分鐘約325埃之濕蝕刻速率(wet etch rate，WER)、約2.52g/cm3之膜密度、約1.91至約1.95之RI、約150GPa至約160GPa之模數(modulus)、在攝氏40度及濕度100%至約500埃之深度下約1x10-4g/m2/天至約3x10-4g/m2/天之水氣穿透率(water vapor transmission rate，WVTR)，及具有少量孔隙(voids)之緊密(dense)的橫截面穿透式電子顯微鏡(XTEM)結構。相較之下，當利用CCP配置時，包括SiN之第一阻障層可具有每分鐘約13,660埃之WER、約2.10g/cm3之模密度、約100GPa之模數、在攝氏40度及濕度100%至約5,000埃之深度下約少於1x10-4g/m2/天的WVTR，及具有數個球形孔隙之XTEM結構。
於另一實施例中，第一阻障層308包括SiON，及SiH4、N2O、及NH3氣體係引入腔室中來用以沈積SiON之第一阻障層308。舉例來說，可利用約100sccm之SiH4、約200sccm至約500sccm之NH3、及約100sccm至約400sccm之N2O。約120mTorr之腔室壓力、約2MHz之ICP功率頻率、約3,000W之功率、及約1.725W/cm2之功率密度係可提供約300秒。
當利用HDP配置時，包括SiON之第一阻障層308可具有每分鐘約3,000埃之WER、約2.13g/cm3至約2.26g/cm3之膜密度、約1.47至約1.84之RI、在攝氏40度及濕度100%至約2,000埃之深度下約1x10-4g/m2/天至約7x10-4g/m2/天之WVTR。相較之下，當利用CCP配置時，包括SiON之第一阻障層可具有每分鐘約20,000埃之WER、約2.04g/cm3之模密度、及在攝氏40度及濕度100%至約10,000埃之深度下約少於1x10-4g/m2/天的WVTR。
於再另一實施例中，第一阻障層308包括SiO，及SiH4及N2O氣體係引入腔室中來用以沈積SiO之第一阻障層308。舉例來說，可利用約30sccm之SiH4及約1,000sccm之N2O。約120mTorr 之腔室壓力、約2MHz之ICP功率頻率、約4,000W之功率、及約2.300W/cm2之功率密度係可提供約130秒。
當利用HDP配置時，包括SiO之第一阻障層308可具有每分鐘約3,400埃之WER、約2.09g/cm3之膜密度、約1.46之RI、在攝氏40度及濕度100%至約2,000埃之深度下約1x10-3g/m2/天之WVTR。相較之下，當利用CCP配置時，包括SiO之第一阻障層可具有每分鐘約20,000埃之WER，且沒有水氣阻障特性。
第二阻障層312係由選自由SiN、SiO、及SiON所組成之群組的材料所構成。第二阻障層312可包括相同於或不同於第一阻障層308的材料。於一些實施例中，第二阻障層312係藉由利用第1圖之CVD設置101及第2圖之HDP配置200以如上所述之相同製程及參數來沈積。如此一來，利用HDP配置於低溫所沈積之第一阻障層308及/或第二阻障層312係為具有低RI及約零之低吸收係數之高品質、薄、緊密之水氣阻障層。
於一實施例中，TFE結構314係藉由放置包括發光裝置304之基板302至HDP CVD腔室中來形成。覆蓋層306可在CVD腔室中沈積於發光裝置304上，或覆蓋層306可在放置到腔室中時已經沈積於發光裝置上。第一阻障層308係在腔室中藉由上述之製程沈積於覆蓋層306上。
緩衝層310係藉由CVD製程在腔室中接著沈積於第一阻障層308之上方。淨化步驟係在沈積第一阻障層308之後、沈積緩衝層310之前執行，因為不同之前驅物係使用於沈積製程。在緩衝層 310係沈積之後，另一淨化步驟係執行。第二阻障層312係沈積於緩衝層310之上方，及第二阻障層312可以相同於第一阻障層308之製程條件沈積。
第4圖係為根據數種實施例之應用於顯示裝置中的薄膜電晶體(thin film transistor，TFT)400之剖面圖。TFT 400可為金屬氧化物TFT。TFT 400包括基板402。基板402可以含矽材料、玻璃、聚醯亞胺(polyimide)、或塑膠製成。塑膠例如是PET或PEN。閘極電極404可設置於基板402上。閘極電極404可包括銅、鎢、鉭、鋁等。閘極絕緣層406設置於閘極電極404及基板402之上方。
半導體層408係設置於閘極絕緣層406之上方。半導體層408可包括金屬氧化物半導體材料、金屬氮氧化物半導體材料、或矽等。金屬氧化物半導體材料例如是氧化銦鎵鋅(indium gallium zinc oxide(IGZO))。矽例如是非晶矽、結晶矽、及多晶矽。汲極412及源極414係設置於半導體層408上。汲極412及源極414係設置半導體層408上。汲極412係與源極414分開且相鄰於源極414。汲極412及源極414可包括銅、鎢、鉭、鋁等。保護層410係設置於半導體層408、汲極412、及源極414之上方。保護層410及閘極絕緣層406係水氣阻障膜或層。
保護層410及閘極絕緣層406可各在HDP CVD腔室中利用HDP配置來沈積。HDP CVD腔室例如是第1圖之CVD設備101。HDP配置例如是第2圖之HDP配置200。閘極絕緣層406係先沈積，接著為半導體層408、接著為保護層410。各保護層410及閘極絕緣 層406可個別地包括相同於第3圖之第一阻障層308的材料。保護層410及閘極絕緣層406可各由選自由SiN、SiO、及SiON所組成之群組之材料所構成。腔室可在各層沈積之間進行淨化。
保護層410及閘極絕緣層406可各利用約1011cm3至約1012cm3之高電漿密度及少於約102eV之低離子轟擊能量來沈積於基板上，而產生高離子化效率及低電漿損傷。針對ICP HDP配置來說，功率頻率可為約2MHz至約13.56MHz。針對MW HDP配置來說，功率頻率可為約2.4GHz至約2.5GHz，例如是約2.45GHz。保護層410及閘極絕緣層406係各在例如是約低於攝氏250度的低溫下沈積成高品質、緊密的膜。於包括SiO之保護層410及/或閘極絕緣層406的一實施例中，保護層410及/或閘極絕緣層406可以每分鐘約2,000埃之速率於約攝氏130度之溫度沈積。於包括SiN之保護層410及/或閘極絕緣層406的一實施例中，保護層410及/或閘極絕緣層406可以每分鐘約1000埃之速率於約攝氏130度之溫度沈積。
再者，利用HDP配置來沈積保護層410及/或閘極絕緣層406係致使保護層410及/或閘極絕緣層406具有約1.4至2.1之折射率及約零之低吸收係數(k)，而讓保護層410及/或閘極絕緣層406具有在UV波長之零或接近零的吸收。利用HDP配置所沈積之保護層410及/或閘極絕緣層406各具有少於約3,000埃之厚度，例如是少於約2,000埃，而減少阻障厚度需求、減少彎曲/摺疊應力、及減少需用以沈積保護層410及/或閘極絕緣層406之總時間。再者，HDP配置係讓保護層410及/或閘極絕緣層406簡易地沈積於側壁上或作為側壁 阻障，而不會導致氧化而減少側壁阻障厚度需求。
於一實施例中，保護層410及/或閘極絕緣層406包括SiN，且SiH4及NH3氣體係導引至腔室中來用以沈積SiN之保護層410及/或SiN之閘極絕緣層406。舉例來說，可利用約100sccm之SiH4及約600sccm之NH3。約120mTorr之腔室壓力、約3,000MHz之ICP功率頻率、及約1.725W/cm2之功率密度係可提供約300秒。
當利用HDP配置時，包括SiN之保護層410及/或閘極絕緣層406可具有每分鐘約325埃之WER、約2.52g/cm3之膜密度、約1.91至約1.95之RI、約150GPa至約160GPa之模數、在攝氏40度及濕度100%至約500埃之深度下約1x10-4g/m2/天至約3x10-4g/m2/天之WVTR，及具有少量孔隙之緊密的XTEM結構。相較之下，當利用CCP配置時，包括SiN之保護層及/或閘極絕緣層可具有每分鐘約13,660埃之WER、約2.10g/cm3之模密度、約100GPa之模數、在攝氏40度及濕度100%至約5000埃之深度下約少於1x10-4g/m2/天的WVTR，及具有數個球形孔隙之XTEM結構。
於另一實施例中，保護層410及/或閘極絕緣層406包括SiON，及SiH4、N2O、及NH3氣體係引入腔室中來用以沈積SiON之保護層410及/或SiON之閘極絕緣層406。舉例來說，可利用約100sccm之SiH4、約200sccm至約500sccm之NH3、及約100sccm至約400sccm之N2O。約120mTorr之腔室壓力、約3,000MHz之ICP功率頻率、及約1.725W/cm2之功率密度係可提供約300秒。
當利用HDP配置時，包括SiON之保護層410及/或閘 極絕緣層406可具有每分鐘約3,000埃之WER、約2.13g/cm3至約2.26g/cm3之膜密度、約1.47至約1.84之RI、在攝氏40度及濕度100%至約2,000埃之深度下約1x10-4g/m2/天至約7x10-4g/m2/天之WVTR。相較之下，當利用CCP配置時，包括SiON之保護層及/或閘極絕緣層可具有每分鐘約20,000埃之WER、約2.04g/cm3之模密度、及在攝氏40度及濕度100%至約10,000埃之深度下約少於1x10-4g/m2/天的WVTR。
於再另一實施例中，保護層410及/或閘極絕緣層406包括SiO，及SiH4及N2O氣體係引入腔室中來用以沈積SiO之保護層410及/或SiO之閘極絕緣層406。舉例來說，可利用約30sccm之SiH4及約1,000sccm之N2O。約120mTorr之腔室壓力、約4,000MHz之ICP功率頻率、及約2.300W/cm2之功率密度係可提供約130秒。
當利用HDP配置時，包括SiO之保護層410及/或閘極絕緣層406可具有每分鐘約3,400埃之WER、約2.09g/cm3之膜密度、約1.46之RI、在攝氏40度及濕度100%至約2,000埃之深度下約1x10-3g/m2/天之WVTR。相較之下，當利用CCP配置時，包括SiO之保護層及/或閘極絕緣層可具有每分鐘約20,000埃之WER，且沒有水氣阻障特性。
TFE結構314及TFT 400係利用HDP配置在低溫下沈積高品質、薄、緊密的水氣阻障膜之兩個範例應用。其他應用包括用於觸控螢幕面板、觸控感應器、聚醯亞/無色聚醯亞胺(poly imide/colorless poly imide(PI/CPI))、活區開孔(hole in active area， HIAA)、及低溫多晶矽(low temperature poly silicon，LTPS)等之水氣阻障層。如此一來，具有低RI及於UV波長下低或零吸收係數之高品質、薄、緊密的水氣阻障膜可利用HDP配置在低溫下沈積。較薄之阻障膜係減少阻障厚度需求、減少彎曲/摺疊應力、及減少需用以沈積阻障層之總時間。具有低光學吸收及廣範圍之RI控制的低RI的阻障層可增加顯示器之發光效率。
綜上所述，雖然本發明已以實施例揭露如上，然其並非用以限定本發明。本發明所屬技術領域中具有通常知識者，在不脫離本發明之精神和範圍內，當可作各種之更動與潤飾。因此，本發明之保護範圍當視後附之申請專利範圍所界定者為準。
300:顯示裝置
302:基板
304:發光裝置
306:覆蓋層
308:第一阻障層
310:緩衝層
312:第二阻障層
314:薄膜封裝(TFE)結構

Claims (22)

  1. 一種用以沈積一阻障層之方法，包括：放置一基板於一化學氣相沈積(chemical vapor deposition，CVD)腔室中，該CVD腔室包括一高密度電漿配置；以及在少於約攝氏250度之一溫度、約2MHz至約13.56MHz之一功率頻率、及約1011cm3至約1012cm3之一電漿密度，利用該高密度電漿配置沈積該阻障層於該基板之上方。
  2. 如請求項1所述之方法，其中該阻障層係為一薄膜封裝結構的一第一阻障層或一第二阻障層。
  3. 如請求項1所述之方法，其中該阻障層係為一薄膜電晶體的一保護層。
  4. 如請求項1所述之方法，其中該阻障層係為一薄膜電晶體的一閘極絕緣層。
  5. 如請求項1所述之方法，其中該阻障層係利用約2MHz至約13.56MHz之一感應耦合電漿功率頻率沈積。
  6. 如請求項1所述之方法，其中該阻障層係利用約2GHz至約3GHz之一微波功率頻率沈積。
  7. 如請求項1所述之方法，其中該阻障層包括選自由氮氧化矽、氮化矽、及氧化矽所組成的群組之一材料，及其中該阻障層具有少於約3,000埃(Angstroms)之一厚度、約1.45及1.95之間的一折射率、及約零之一吸收係數。
  8. 一種薄膜封裝結構，包括：一第一阻障層，在少於約攝氏250度之一溫度、約2MHz至約13.56MHz之一功率頻率、及約1011cm3至約1012cm3之一電漿密度，利用一高密度電漿化學氣相沈積(CVD)腔室沈積，該第一阻障層包括選自由氮氧化矽、氮化矽、及氧化矽所組成的群組之一材料，其中該第一阻障層具有少於約3,000埃(Angstroms)之一厚度、約1.45及1.95之間的一折射率、及約零之一吸收係數；一緩衝層，設置於該第一阻障層上；以及一第二阻障層，設置於該緩衝層上。
  9. 如請求項8所述之薄膜封裝結構，其中該第一阻障層包括氮化矽及具有約1.91及約1.95之間的一折射率。
  10. 如請求項8所述之薄膜封裝結構，其中該第二阻障層包括氮化矽及具有約1.91及約1.95之間的一折射率。
  11. 如請求項8所述之薄膜封裝結構，其中該第一阻障層或該第二阻障層包括氮氧化矽及具有約1.47及約1.84之間的一折射率。
  12. 如請求項8所述之薄膜封裝結構，其中該第一阻障層或該第二阻障層包括氧化矽及具有約1.46之一折射率。
  13. 如請求項8所述之薄膜封裝結構，其中該第二阻障層係利用該高密度電漿CVD腔室沈積，該第二阻障層包括選自由氮氧化矽、氮化矽、及氧化矽所組成之群組的一材料。
  14. 如請求項13所述之薄膜封裝結構，其中該第二阻障層具有少於約3,000埃之一厚度、約1.45及1.95之間的一折射率、及約零之一吸收係數。
  15. 一種用以沈積一阻障層之方法，包括：放置一基板於一化學氣相沈積(CVD)腔室中，該CVD腔室包括一高密度電漿配置；以及在少於約攝氏250度之一溫度、約2MHz至約13.56MHz之一感應耦合電漿功率頻率、及約1011cm3至約1012cm3之一電漿密度，利用該高密度電漿配置沈積該阻障層於該基板之上方，其中該阻障層具有少於約3,000埃(Angstroms)之一厚度、約1.45及1.95之間的一折射率、及約零之一吸收係數。
  16. 如請求項15所述之方法，其中該阻障層包括選自由氮氧化矽、氮化矽、及氧化矽所組成的群組之一材料。
  17. 如請求項15所述之方法，其中該阻障層係沈積於一發光裝置之上方。
  18. 如請求項15所述之方法，其中該阻障層係為一薄膜封裝結構的一第一阻障層或一第二阻障層。
  19. 如請求項15所述之方法，其中該阻障層係為一薄膜電晶體的一保護層。
  20. 如請求項15所述之方法，其中該阻障層係為一薄膜電晶體的一閘極絕緣層。
  21. 如請求項1所述之方法，其中該阻障層係在少於約102eV之低離子轟擊能量，利用該高密度電漿配置沈積於該基板上。
  22. 如請求項15所述之方法，其中該阻障層係在少於約102eV之低離子轟擊能量，利用該高密度電漿配置沈積於該基板上。
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