TWI755744B - Device and method for controlling command sequence - Google Patents
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本發明係指一種控制命令列隊的裝置及方法,尤指一種提高電腦系統之處理命令的效率的控制命令列隊的裝置及方法。 The present invention refers to a device and method for controlling command queuing, especially to a device and method for controlling command queuing which improves the efficiency of processing commands in a computer system.
現有電腦系統的硬體架構於建置完成後,針對輸入裝置(例如,感測器、相機)、影像格式(例如,bmp、png、jpg)、顏色編碼方式(例如,YUV、YCbCr、RGB)、輸出裝置(例如,顯示器、面板或另一電腦系統的硬體架構之輸入裝置)、應用程式或者不同的使用者習慣,皆需要透過電腦系統的一中央處理器調整週邊組件的系統參數。因此,現有的系統的中央處理器除了必須執行龐大的運算之外,同時也需控制並處理來自週邊組件的中斷要求。對於各個週邊組件而言,週邊組件發送一中斷請求至中央處理器回應請求的時間將過於冗長,而降低整個系統的性能。因此,現有技術有改進的必要。 After the hardware structure of the existing computer system is completed, it is suitable for input devices (eg, sensors, cameras), image formats (eg, bmp, png, jpg), and color coding methods (eg, YUV, YCbCr, RGB) , output device (eg, display, panel or input device of another computer system hardware structure), application programs or different user habits, all need to adjust the system parameters of peripheral components through a central processing unit of the computer system. Therefore, the central processing unit of the existing system not only has to perform huge operations, but also needs to control and process interrupt requests from peripheral components. For each peripheral component, the time for the peripheral component to send an interrupt request to the central processing unit to respond to the request will be too long, thereby reducing the performance of the entire system. Therefore, there is a need for improvement in the prior art.
因此,本發明提供一種控制命令列隊的裝置及方法,降低中央處理器的運算量以提升系統的硬體架構的靈活性及彈性,進而提高整個系統的工作效率。 Therefore, the present invention provides an apparatus and method for controlling command queuing, which reduces the calculation amount of the central processing unit to improve the flexibility and flexibility of the hardware architecture of the system, thereby improving the work efficiency of the entire system.
本發明揭露一種用於控制命令列隊的裝置,包含有一內部儲存記憶體,用來儲存複數個命令以及對應於該複數個命令之細節資訊;以及一命令檢查單元,用來檢查該複數個命令之一第一命令之型態;至少一命令執行單元,用來讀取該內部儲存記憶體之該複數個命令,其中該至少一命令執行單元之每一命令執行單元包含有一命令模式切換單元,用來根據該第一命令之型態,決定以一第一模式或一第二模式執行該第一命令;其中,該第一模式係根據該第一命令之操作碼及運算元執行該第一命令,該第二模式係以該第一命令之簡單位址資料格式執行該第一命令。 The invention discloses a device for controlling command queuing, comprising an internal storage memory for storing a plurality of commands and detailed information corresponding to the plurality of commands; and a command checking unit for checking the plurality of commands. A form of a first command; at least one command execution unit for reading the plurality of commands in the internal storage memory, wherein each command execution unit of the at least one command execution unit includes a command mode switching unit, using to decide to execute the first command in a first mode or a second mode according to the type of the first command; wherein, the first mode executes the first command according to the opcode and operand of the first command , the second mode executes the first command in the simple address data format of the first command.
本發明另揭露一種控制命令列隊的方法,用於一控制命令列隊的裝置,其中該裝置包含有一內部儲存記憶體、至少一命令執行單元、一記憶體控制單元、一低延遲介面仲裁單元及一硬體存取管理單元,該方法包含有觸發一命令;確認該內部儲存記憶體是否具有任一命令;當該內部儲存記憶體具有一第一命令時,讀取該內部儲存記憶體之該第一命令;檢查該第一命令之型態;以及根據該第一命令之型態,決定以一第一模式或一第二模式執行該第一命令。 The present invention further discloses a method for controlling command queuing, which is used in a device for controlling command queuing, wherein the device includes an internal storage memory, at least one command execution unit, a memory control unit, a low-latency interface arbitration unit, and a A hardware access management unit, the method includes triggering a command; confirming whether the internal storage memory has any command; when the internal storage memory has a first command, reading the first command of the internal storage memory a command; checking the type of the first command; and determining to execute the first command in a first mode or a second mode according to the type of the first command.
10:電腦系統 10: Computer System
102:外部儲存記憶體 102: External storage memory
104:控制命令列隊裝置 104: Control command queuing device
1042:記憶體控制單元 1042: Memory Control Unit
1044:內部儲存記憶體 1044: Internal storage memory
1044A:命令儲存記憶體 1044A: Command storage memory
1044B:資料儲存記憶體 1044B: Data storage memory
1046:命令檢查單元 1046: Command Check Unit
1048:命令執行單元 1048: Command execution unit
1048_2:命令模式切換單元 1048_2: Command mode switching unit
1048_4:命令解碼單元 1048_4: Command decoding unit
1048_6:時間控制單元 1048_6: Time Control Unit
1048_8:內部暫存器 1048_8: Internal scratchpad
1048_ALU:處理器 1048_ALU: Processor
1050:低延遲介面仲裁單元 1050: Low Latency Interface Arbitration Unit
1052:硬體存取管理單元 1052: Hardware Access Management Unit
106:中央處理器 106: CPU
20:控制命令列隊流程 20: Control the command queuing process
202、204、206、208、210、212、214、216、218:步驟 202, 204, 206, 208, 210, 212, 214, 216, 218: Steps
P0-Pn:外部組件 P0-Pn: External components
R1-R15:暫存器 R1-R15: Scratchpad
第1圖為本發明實施例一電腦系統之示意圖。 FIG. 1 is a schematic diagram of a computer system according to an embodiment of the present invention.
第2圖為本發明實施例一控制命令列隊流程之示意圖。 FIG. 2 is a schematic diagram of a control command queuing process according to an embodiment of the present invention.
請參考第1圖,第1圖為本發明實施例一電腦系統10之示意圖。電腦系統10包含一外部儲存記憶體102、一控制命令列隊裝置104及一中央處理器
106。外部儲存記憶體102可以是用來儲存資料的快閃記憶體,中央處理器106用來執行電腦系統10的運算。控制命令列隊裝置104可以是一積體電路(Integrated Circuit,IC),包含有一記憶體控制單元1042、一內部儲存記憶體1044、一命令檢查單元1046、至少一命令執行單元1048、一低延遲介面仲裁單元1050及一硬體存取管理單元1052。其中,內部儲存記憶體1044另包含有一命令儲存記憶體1044A及一資料儲存記憶體1044B用來儲存複數個命令以及對應於命令之細節資訊,換言之,內部儲存記憶體1044可以作為一緩衝記憶體,以維持外部儲存記憶體102與控制命令列隊裝置104之間的記憶體平衡。舉例而言,內部儲存記憶體1044可決定關於命令的讀寫要求之細節資訊,例如命令的一位址資訊或一資料數量,並且當內部儲存記憶體1044無任何命令時,控制命令列隊裝置104可透過記憶體控制單元1042讀取儲存於外部儲存記憶體102之命令。
Please refer to FIG. 1. FIG. 1 is a schematic diagram of a
命令檢查單元1046用來檢查所有送往命令執行單元1048的命令之型態,例如,檢查命令之長度或格式。命令執行單元1048用來讀取內部儲存記憶體1044之命令,每一命令執行單元1048包含有一命令模式切換單元1048_2、一命令解碼單元1048_4、一時間控制單元1048_6、一內部暫存器1048_8及一處理器1048_ALU。命令模式切換單元1048_2用來根據命令檢查單元1046所確定的命令之型態,決定以一第一模式或一第二模式執行命令。其中,第一模式係根據命令之操作碼及運算元後執行命令,而第二模式係以命令之簡單位址資料格式執行命令。因此,本發明的控制命令列隊裝置104即可根據命令模式切換單元1048_2所切換的模式執行命令,進而減少中央處理器106的負擔,以提升電腦系統10的整體表現。
The
詳細而言,電腦系統10的低延遲介面仲裁單元1050耦接於命令執行
單元1048及中央處理器106,用來接收並處理來自命令執行單元1048或中央處理器106之命令,以決定對內部儲存記憶體1044之資料儲存記憶體1044_B及至少一外部組件P0-Pn之一存取順序。硬體存取管理單元1052耦接於命令執行單元1048及低延遲介面仲裁單元1050,用來管理命令執行單元1048或中央處理器106對外部組件P0-Pn之存取權限,例如存取申請、仲裁存取申請、權限查詢及釋出權限。在一實施例中,當多個命令檢查單元1046及中央處理器106對外部組件P0-Pn中的同一外部組件進行存取動作時,有可能因為命令的存取順序的不同,而造成命令檢查單元1046或中央處理器106在錯誤的時間點向外部組件P0-Pn讀取錯誤的資料。此外,當命令執行單元1048或中央處理器106欲控制資料儲存記憶體1044B讀取記憶體控制單元1042時,需經由低延遲介面仲裁單元1050仲裁後,才可讀取記憶體控制單元1042。
In detail, the low-latency
因此,硬體存取管理單元1052可透過管理不同多個命令檢查單元1046及中央處理器106對外部組件P0-Pn的存取權限,直到任一命令檢查單元1046或中央處理器106所申請的一執行緒完成時,才會釋出存取權限,以避免讀取錯誤資料的情形發生。
Therefore, the hardware
值得注意的,在一實施例中,外部組件P0-Pn的其中之一可以是一資料交換區,以用來儲存命令執行單元1048與中央處理器106之間的訊息,例如命令執行單元1048與中央處理器106的內部單元狀態、外部單元狀態、命令標誌或計數器資料。此外,資料交換區也可用來作為外部儲存記憶體102之一暫存器。因此,本發明的電腦系統10可利用資料交換區儲存多個執行緒的資訊,以避免高延遲而降低電腦系統10的效能,及避免存放於外部儲存記憶體102的資料遺失或錯誤的情形,進而提升系統效能、減少耗能及提高電腦系統10的可靠性。
It should be noted that, in one embodiment, one of the external components P0-Pn may be a data exchange area for storing information between the
另一方面,每一命令執行單元1048的命令解碼單元1048_4用來根據命令模式切換單元1048_2所決定執行命令的第一模式或第二模式,對命令進行解碼。在一實施例中,當命令模式切換單元1048_2決定以第一模式執行命令時,命令解碼單元1048_4可依照一命令集架構(instruction set architecture)解碼命令,其中命令集架構可包含數據處理命令、程序狀態暫存器之處理命令、算數/邏輯運算命令、分支命令、外/內部儲存記憶體存取命令、中斷訊號處理命令、異常產生命令、外部輸入/輸出存取命令等。因此,命令解碼單元1048_4可解碼命令中的操作碼(operation code)及運算元(operand)並據以執行命令。具體而言,操作碼可代表不同的命令類別,例如,ABASE類型描述設定外部組件的高位元位址、WFE類型描述指定一特定組件、中央處理器106或命令執行單元1048執行命令、DONE類型描述命令執行單元1048已完成的命令,並發出中斷要求以告知中央處理器106、BRANCH類型描述包含一條件判斷式的分支命令,及外部儲存記憶體102的一絕對或相對位址、STORE類型描述將一個位元組或是兩個位元組寫入至外部組件P0-Pn、LOAD類型描述將一個位元組、兩個位元組或是四個位元組的資料寫進內部暫存器1048_8、AI類型描述更新內部暫存器1048_8於算數運算之後的資料、LI類型描述將內部暫存器1048_8內的資料做完邏輯運算後更新及擴增之命令集。值得注意的是,命令集架構的操作碼所代表的類別,並不限於上述實施例,其他複雜運算、多項中斷事件處理或將多個命令定義為一巨集命令以減少錯誤產生,皆屬於本發明之範疇。
On the other hand, the command decoding unit 1048_4 of each
當命令模式切換單元1048_2決定以第二模式執行命令時,命令執行單元1048可根據命令之簡單位址資料格式大量填寫連續位址或者循環填寫一相同位址。詳細而言,第二模式為用來解析一無時序、無關作業流程、無複雜運
算之特殊命令,換言之,特殊命令相對於第一模式的命令簡易,並且具有命令資料量較小且無須花費大量運算時間的特色。因此,針對大量填寫連續位址的命令,命令執行單元1048可設定命令具有一最小單位長度(例如,n個m位元組,其中n、m皆為可程式化的數值)以適用於不同週邊暫存器的定址方式。週邊暫存器的控制可以是一二維命令列表,其包含有週邊暫存器的位址及對應的資料,以提升電腦系統10撰寫命令程式碼的速度,進而減少命令所需的儲存空間。
When the command mode switching unit 1048_2 decides to execute the command in the second mode, the
針對循環填寫相同位址的命令,當週邊暫存器為一先進先出(First In,First Out,FIFO)的控制方式,在一回合內寫入暫存器的特定位置,且每回合皆寫入相同位址,於填寫完同一回合的暫存器後,需要處理中斷才會進入下一回合時,命令模式切換單元1048_2可根據命令檢查單元1046所確定命令之型態,以第一模式或第二模式執行命令,進而減化命令撰寫的複雜度及命令所需儲存空間。
For the command that fills in the same address cyclically, when the peripheral register is in a first-in, first-out, FIFO control mode, write to a specific location of the register in one round, and write in each round Enter the same address, after filling in the register of the same round, when an interrupt needs to be processed before entering the next round, the command mode switching unit 1048_2 can use the first mode or the command type determined by the
此外,內部暫存器1048_8另包含有暫存器R1-R15,其中暫存器R1-R13為用來暫時存放命令執行單元1048的資料(例如,待計算的資料、暫時存放的資料或待存取的資料),暫存器R14可以是一連結暫存器,用來存放一副函式返回位址,及呼叫副函式的下一位返回位址,暫存器R15可以是一程式計數器,用來存放分支命令所需之位址資料,以於命令執行單元1048執行分支命令時,下一個執行之命令跳轉至暫存器R15中的命令位址。
In addition, the internal register 1048_8 further includes registers R1-R15, wherein the registers R1-R13 are used to temporarily store data of the command execution unit 1048 (for example, data to be calculated, data to be temporarily stored or data to be stored) fetched data), register R14 can be a link register, used to store a sub-function return address, and the next return address of calling sub-function, register R15 can be a program counter , which is used to store the address data required by the branch command, so that when the
每一命令執行單元1048的時間控制單元1048_6可用來控制命令送達低延遲介面仲裁單元1050之一先後順序,也就是說,時間控制單元1048_6控制命令的一執行時間,藉以控制存取要求送至低延遲介面仲裁單元1050的時間
點,以平衡多個執行緒欲同時存取外部組件P0-Pn之衝突狀況。舉例來說,當多個執行緒同時要利用低延遲介面仲裁單元1050向外部組件進行資料存取時,時間控制單元1048_6可將各執行緒對外部組件P0-Pn的存取時間錯開,同時將優先權較高之命令以較短時間送達至低延遲介面仲裁單元1050,以平衡多個執行緒及優先權高低不一之命令,進而優化電腦系統10的效能。此外,處理器1048_ALU可用來執行命令執行單元1048的所有邏輯運算、算數運算。如此一來,本發明的命令執行單元1048即可藉由控制命令的執行時間點,以提升電腦系統10之效能。
The time control unit 1048_6 of each
進一步地,關於電腦系統10之控制命令列隊的運作方式可歸納為一控制命令列隊流程20,如第2圖所示。控制命令列隊流程20的步驟包含有:
Further, the operation of the control command queuing of the
步驟202:開始。 Step 202: Start.
步驟204:觸發命令。 Step 204: Trigger the command.
步驟206:確認內部儲存記憶體1044是否具有任一命令。若有,執行步驟208;若無,執行步驟214。
Step 206: Check whether the
步驟208:讀取內部儲存記憶體1044之命令。
Step 208 : Read the command from the
步驟210:檢查命令之型態。 Step 210: Check the type of the command.
步驟212:根據命令之型態,決定以第一模式或第二模式執行命令。 Step 212: Determine to execute the command in the first mode or the second mode according to the type of the command.
步驟214:讀取儲存於外部儲存記憶體102之一第二命令,並執行步驟210。
Step 214 : Read a second command stored in the
步驟216:終止命令。 Step 216: Terminate the command.
步驟218:結束。 Step 218: End.
根據控制命令列隊流程20,於步驟204可由中央處理器106或控制命
令列隊裝置104觸發命令。接著,於步驟206確認內部儲存記憶體1044是否具有任一命令,以於步驟208讀取內部儲存記憶體1044之命令,於步驟210檢查命令的型態,以及步驟212中根據命令的型態,決定以第一模式或第二模式進行解碼以及執行命令。相反地,當步驟206內部儲存記憶體1044不具有任一命令時,則執行步驟214以提取儲存於外部儲存記憶體102的命令,於步驟210檢查命令的型態,並且於步驟212中根據命令的型態,決定以第一模式或第二模式進行解碼以及執行命令。
According to the control
綜上所述,本發明實施例提供一種控制命令列隊的裝置及方法,透過切換處理不同的命令的模式以快速地處理命令、透過資料交換區處理中央處理器與命令執行單元之間的訊息,以及透過時間控制單元排程執行緒的優先順序,進而降低中央處理器的運算量以提升系統的硬體架構的靈活性及彈性,提高整個系統的工作效率。 To sum up, the embodiments of the present invention provide an apparatus and method for controlling command queuing, which can process commands quickly by switching between different command processing modes, and process messages between a central processing unit and a command execution unit through a data exchange area. And the priority order of threads is scheduled through the time control unit, so as to reduce the calculation amount of the central processing unit to improve the flexibility and flexibility of the hardware structure of the system, and improve the work efficiency of the whole system.
以上所述僅為本發明之較佳實施例,凡依本發明申請專利範圍所做之均等變化與修飾,皆應屬本發明之涵蓋範圍。 The above descriptions are only preferred embodiments of the present invention, and all equivalent changes and modifications made according to the scope of the patent application of the present invention shall fall within the scope of the present invention.
10:電腦系統 10: Computer System
102:外部儲存記憶體 102: External storage memory
104:控制命令列隊裝置 104: Control command queuing device
1042:記憶體控制單元 1042: Memory Control Unit
1044:內部儲存記憶體 1044: Internal storage memory
1044A:命令儲存記憶體 1044A: Command storage memory
1044B:資料儲存記憶體 1044B: Data storage memory
1046:命令檢查單元 1046: Command Check Unit
1048:命令執行單元 1048: Command execution unit
1048_2:命令模式切換單元 1048_2: Command mode switching unit
1048_4:命令解碼單元 1048_4: Command decoding unit
1048_6:時間控制單元 1048_6: Time Control Unit
1048_8:內部暫存器 1048_8: Internal scratchpad
1048_ALU:處理器 1048_ALU: Processor
1050:低延遲介面仲裁單元 1050: Low Latency Interface Arbitration Unit
1052:硬體存取管理單元 1052: Hardware Access Management Unit
106:中央處理器 106: CPU
P0-Pn:外部組件 P0-Pn: External components
R1-R15:暫存器 R1-R15: Scratchpad
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TWI416408B (en) * | 2009-07-15 | 2013-11-21 | Via Tech Inc | A microprocessor and information storage method thereof |
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