TWI755695B - Boot method for system on chip - Google Patents

Abstract

The invention discloses a booting method, which may dynamically adapt the booting sequence of system-on-chip without modifying the bootloader in the read-only memory. By reading the external input signal to change the starting address to read the description program, and then the real target program is read by the description program. Since the description program is stored in the external storage device, it can be modified by the user at any time. In this way, the target program can be stored in an external storage device that exists data without modifying the startup program in the read-only memory to achieve the goal of sharing the external storage.

Description

System single chip boot method

The present invention refers to a booting method suitable for SoCs, especially a booting method that can dynamically modify the booting procedure of the SoC without modifying the booting procedure in the ROM.

In an embedded system, the startup program is a piece of code that is executed before the operating system runs. The purpose is to perform hardware initialization before the operating system runs, and finally load the operating system into the memory for execution. In the SoC, the startup program is stored in the read-only memory. Before the operating system runs, execute the startup program, read from the external storage device and execute the target program to complete the boot. Allows the user to update the target program at any time.

However, as electronic products become more and more complex, an electronic product is often composed of multiple SoCs. If each SoC has its own corresponding external storage device, the cost and wiring of the entire system will be reduced. difficulty will increase. Conversely, if multiple SoCs share the same external storage device, it is necessary to modify the boot programs located in the ROMs of the multiple SoCs by modifying the masks of the multiple SoCs and re-offline.

Therefore, there is a real need for improvement in the prior art.

Therefore, the main purpose of the present invention is to provide a booting method that can dynamically modify the booting procedure of the SoC without modifying the booting procedure in the ROM, so as to improve the shortcomings of the prior art.

An embodiment of the present invention discloses a booting method, which is suitable for a booting procedure of a SoC, wherein the SoC includes an input port for providing external input signals, a processing unit for executing programs, and a unique The read memory is used to store an initial boot program, and the boot method includes selecting an initial position of a springboard program; reading the springboard program, and executing the springboard program with the processing unit; and through the springboard program, using the processing The unit executes the target program; wherein, the springboard program and the target program are stored in an external storage device; wherein, the springboard program is used to execute and read the target program, and the target program is used to execute the boot procedure.

10: Conventional SoCs

100: Known Technology Processing Unit

102: Conventional Technology Read-Only Memory

104: Prior Art Random Access Memory

12: Conventional external storage devices

14: Conventional SoCs

140: Conventional Technology Processing Unit

142: Conventional Technology Read-Only Memory

144: Conventional Technology Random Access Memory

16: Prior art external storage devices

30: SoC

300: Processing Unit

302: read-only memory

304: Random Access Memory

306: input port

32: External storage device

34: SoC

340: Processing Unit

342: read-only memory

60: Process

600~612: Steps

FIG. 1A is a schematic diagram of a system-on-chip and its system in the prior art.

FIG. 1B is a schematic diagram of integrating two SoCs into one system in the prior art.

FIGS. 2A and 2B are schematic diagrams of a conventional method for configuring the memory of an external storage device.

Figures 3A and 3B are schematic diagrams of a system-on-chip and its system according to an embodiment of the present invention.

FIG. 4 is a schematic diagram of a memory configuration of an external storage device according to an embodiment of the present invention.

5A and 5B are schematic diagrams of the memory configuration of an external storage device according to an embodiment of the present invention.

FIG. 6 is a schematic diagram of a flow of a system-on-chip power-on method according to an embodiment of the present invention.

FIG. 7 is a schematic diagram of a system-on-a-chip system according to an embodiment of the present invention.

Certain terms are used in the specification and claims to refer to specific elements. It should be understood by those of ordinary skill in the art that hardware manufacturers may refer to the same element by different names. This specification and the scope of the patent application do not use the difference in name as a way to distinguish elements, but use the difference in function of the elements as a criterion for distinguishing. The terms "including" and "including" mentioned in the description and the scope of the patent application are open-ended terms, so they should be interpreted as "including but not limited to". In addition, the term "coupled" herein includes any direct and indirect means of electrical connection. Therefore, if a first device is described as being coupled to a second device, it means that the first device can be directly electrically connected to the second device, or indirectly electrically connected to the second device through other devices or connecting means device.

FIG. 1A is a schematic diagram of a system on chip (SoC) 10 and its system in the prior art. As shown in FIG. 1A , the SoC 10 includes a processing unit 100 , a Read-Only Memory (ROM) 102 and a Random Access Memory (RAM) 104 . 10 is coupled to an external storage device 12 to form a system. In order to initialize the SoC 10, in the boot process, the processing unit 100 first reads and executes the boot program (BootLoader) stored in the ROM 102, and then loads the target program from the external storage device 12 to the random memory through the boot program. In the memory 104, finally the processing unit 100 executes the target program to complete the boot process.

In practical application, the system is not only implemented by one SoC, as shown in FIG. 1B , which is a schematic diagram of integrating two SoCs 10 and 14 into one system in the prior art. In the prior art, two SoCs 10 and 14 are respectively coupled to the external storage devices 12 and 16 used by them and integrated into one system. In short, when a system contains multiple SoCs, the system requires multiple an external storage device to store target programs for multiple SoCs.

For example, FIGS. 2A and 2B are schematic diagrams of the memory configuration of an external storage device in the prior art. As shown in FIG. 2A, if the boot programs stored in the two SoCs 102 and 142 read data from the external storage devices 12 and 16 at the starting positions 0000_0000 and 8000_0000, then FIG. 1B The circuitry in the SoC can be simplified so that the two SoCs 30 and 34 are commonly coupled to an external storage device. On the other hand, if the memory configuration of the external storage device is as shown in FIG. 2B, the start-up programs stored in the two SoC ROMs 102 and 142 will start at 0000_0000 in the external storage devices 12 and 16 If the data is read at 0000_0000, since the positions read by the two SoC startup programs are the same, the circuit in FIG. 1B cannot be further simplified to be commonly coupled to an external storage device. That is to say, two external storage devices 12 and 16 are required at this time, and both the two external storage devices 12 and 16 are wasted of idle space.

After the ROM is taped out, it cannot be modified unless the mask is modified. In other words, if the memory configuration of the two SoCs 10 and 14 in the external storage device is as shown in FIG. 2B, unless the ROM 102 or the only memory in the SoC 10 or 14 is modified by modifying the mask. Read the contents of the memory 142, otherwise two external storage devices 12 and 16 will be used in the entire single-chip system in FIG. 1B.

3A and 3B are schematic diagrams of a system-on-chip 30 and a system thereof according to an embodiment of the present invention. As shown in FIG. 3A, the booting method provided by the present invention utilizes a springboard program and a target program, so that the SoC 30 and other SoCs 34 can share the same external storage device 32; wherein, the external storage device 32 has existing programs or data, and the free space of the external storage device 32 is larger than the size of the springboard program and the target program. The SoC 30 includes a processing unit 300, a ROM 302, a random access memory Memory 304 and an input port 306 . In the embodiment of the present invention, the startup program is stored in the ROM 302, the signal of the input port 306 is judged to determine the position of the springboard program, and then the springboard program is read from the external storage device 32 to the random access memory 304, and then The processing unit 300 executes, and the springboard program describes the location, size and other information of the real target program, and then the processing unit 300 can read the target program from the external storage device 32 to the random access memory 304 and execute it to complete the booting process . In addition, the SoC 30 can be modified differently depending on the scene of use. For example, compared to FIG. 3A, the SoC 30 in FIG. 3B has the random access memory 304 removed to save cost.

Regarding the operation of the SoC 30 , please also refer to FIG. 4 . FIG. 4 is a schematic diagram of an embodiment of the memory configuration of the external storage device 32 . As shown in FIG. 4 , the external storage device 32 has existing data and programs at 4000_0000 to 7FFF_FFFF and C000_0000 to EFFF_FFFF. In this embodiment, a springboard program is stored at F000_0000, and the startup program can first read the input signal of the input port 306 through the processing unit 300 to determine the start position of the springboard program as F000_0000. Next, by loading the springboard program into the random access memory 304 and then executing it by the processing unit 300 , and executing the target program accordingly, the booting process of the SoC 30 is completed.

Since the content in the external storage device 32 can be modified by the user at any time, the user can modify the springboard program stored in the external storage device 32 at any time, so that the processing unit 300 can change accordingly when reading the target program position, so as to realize the booting method that can dynamically modify the booting procedure of the SoC without modifying the booting procedure in the read-only memory.

However, in the boot process, the random access memory 304 is not an indispensable component. For example, in the memory configuration of the external storage device in FIG. 4, the addresses of the external storage device 32 are free space from 0000_0000 to 3FFF_FFFF, and the SoC 30 can access the external storage device 32 by accessing the The instruction part of the formula and the target program are loaded into the processing unit 300 for direct execution, and the intermediate data during the operation of the processing unit 300 are temporarily stored in the external storage device 32 to realize the boot process.

In addition, the target program is loaded through the springboard program, in which the user can modify the springboard program stored in the external storage device at any time according to different usage scenarios. Furthermore, the target program is stored in the memory of the external storage device. The configuration does not need word alignment, nor does it need to include header, end-of-file, checksum or hash value, and is not limited to this. For example, FIG. 5A is a schematic diagram of a memory configuration of an external storage device according to an embodiment of the present invention. In Figure 5A, the starting position of the target program is bit3 of 8000_0002, and it does not include the file header, file end, check code or hash value. Users can still modify the springboard program to complete the loading of the target program. Enter, read and execute. Similarly, the memory configuration of the springboard program in the external storage device does not need to be byte aligned, and details are not repeated here.

FIG. 5B is a schematic diagram of a memory configuration of an external storage device according to an embodiment of the present invention. In FIG. 5B, since the continuous free space from 0000_0000 to 3FFF_FFFF in the memory configuration of the external storage device 32 is not enough to accommodate the target program, in one embodiment, the user can still divide the target program into two parts by modifying the springboard program. The two segments are stored in 0000_0000 to 3FFF_FFFF and 8000_0000 to 8FFF_FFFF respectively. In the boot process of the SoC 32, the two target program segments are loaded into the random access memory 304 successively through the modified springboard program, and then stored in the random access memory 304. The processing unit 300 is executed to complete the booting procedure.

It should be noted that the foregoing embodiments are used to illustrate the concept of the present invention. For example, the springboard program and the target program can be divided into several sections according to the idle space of the external storage device, or the springboard program can be further divided into the primary springboard program and a plurality of Secondary springboard programs, etc., are read by the startup program in the ROM 302 Take the primary springboard program, then read multiple secondary springboard programs through the primary springboard program, and finally complete the reading of multiple target program segments to complete the boot process. Those with ordinary knowledge in the art can make various modifications accordingly, but are not limited to this.

Finally, the operation of the booting method of the SoC 30 can be summarized as a flow 60 of the booting method of the SoC, as shown in FIG. 6 . The SoC booting method process 60 includes the following steps:

Step 600: Start.

Step 602: The SoC 30 determines the starting position of the springboard program through external input.

Step 604 : Read the springboard program from the external storage device 32 and execute the springboard program with the processing unit 300 .

Step 606: Repeat step 604 until all springboard programs have been read and executed.

Step 608 : Read the target program from the external storage device 32 through the springboard program, and use the processing unit 300 to execute the target program.

Step 610: Repeat step 608 until all target programs have been read and executed.

Step 612: End.

In step 602, the SoC 30 obtains an external input signal through the input port 306 to determine the starting position of the jumper program, wherein the external input signal can be the direct address of the starting position, or is stored in the ROM through a The correspondence table in the body 302 corresponds to the starting position. For example, in one embodiment, the input port 306 has a total of one bit. When its input value is 0, it means that the springboard program is located in the starting position of the external storage device 32 as 0000_0000, and when its input value is 1, it means that the springboard is located in the external storage device. The starting position of the device 32 is F000_0000. In addition, the type of input port is not limited to the general-purpose input/output port (General-Purpose Input/Output, GPIO) of the system single chip, and can also be a bonding option (Bonding Option), direct addressing or indirect addressing. There is a common skill of those of ordinary skill in the art, and it is not Repeat.

In step 606 and step 610, due to the memory configuration factor of the external storage device, the springboard program and the target program may not be continuously stored in a space of the external storage device (as shown in Figure 5B), so the springboard program and the target program It may need to be divided into a plurality of segments, so that after the system single chip 30 is at the starting position of the springboard program in step 602, it still needs to read and execute the springboard program several times, and then read and execute the target program through the springboard program, so as to Implement a complete boot process.

As for other steps of the SoC booting method process 60, reference may be made to the foregoing description, and details are not described herein again.

It should be noted that the external input signal refers to the outside of the SoC 30, not the outside of the entire system. If there are multiple SoCs in the entire electronic device, as long as the other SoCs complete the initialization earlier than the SoC 30, the external signal of the SoC 30 can be selected by a wire bond or a programmable controller in the other SoCs. A logic device is coupled, wherein the programmable logic device can be a write-once memory (One-Time Programmable, OTP), a write-once memory (Few-Time Programmable, FTP), A Multiple-Time Programmable (MTP), such as eFuse, Anti-fuse, Read-Only Memory, Random Access Memory, Memory-Only Disc ( CD-ROM), Magnetic Tape, Floppy Disk, Optical Data Storage Device, Non-volatile Memory, but not limited to this.

For example, FIG. 7 is a schematic diagram of a system-on-a-chip system according to an embodiment of the present invention. In FIG. 7, the SoC 30 is integrated into a system with a SoC1, a SoC2 and an eFuse, wherein the SoC1 is If the initialization sequence with the eFuse is completed earlier than the SoC 30 , the output port of the eFuse can be coupled to the input port 306 of the SoC 30 . Those with ordinary knowledge in the art can select an appropriate configuration according to different applicable devices. Such a circuit design method is a common technique of those skilled in the art, and will not be repeated here.

Furthermore, although the SoC 30, external storage device 32 are shown above as different units for illustrative purposes, all or part of these units may be integrated into the same circuit. For example, the external storage device 32 and the SoC 30 can be integrated into the same SoC through a System in a Package (SIP). In one embodiment, the electronic fuses and antifuses may be separate components or integrated with the SoC 30 in the same SoC.

The foregoing embodiments are used to illustrate the concept of the present invention, and those skilled in the art can make various modifications accordingly, but are not limited thereto. Therefore, as long as the booting method of the SoC can dynamically change the read position of the target program in the external storage device by reading a signal, the requirements of the present invention are satisfied and belong to the scope of the present invention.

In summary, the present invention provides a booting method that can dynamically modify the booting procedure of the SoC without modifying the booting program in the ROM. The method changes the booting program and reads the springboard by reading an external input signal. The starting position of the program, and then the real target program is read by the springboard program. Since the springboard program is stored in the external storage device, it can be modified by the user at any time. In this way, without modifying the startup program in the read-only memory, The target program is stored in an external storage device with existing data to achieve the goal of sharing the external storage device. The above descriptions are only preferred embodiments of the present invention, and all equivalent changes and modifications made according to the scope of the patent application of the present invention shall fall within the scope of the present invention.

30: SoC

300: Processing Unit

302: read-only memory

304: Random Access Memory

306: input port

32: External storage device

34: SoC

340: Processing Unit

342: read-only memory

Claims (15)

A booting method is suitable for a booting procedure of a system single chip, wherein the system single chip includes an input port for providing external input signals, a processing unit for executing programs, and a read-only memory for to store an initial boot program, the boot method includes: selecting an initial position of a springboard program; reading the springboard program, and executing the springboard program with the processing unit; and executing a target with the processing unit through the springboard program a program; wherein, the springboard program and the target program are stored in an external storage device; wherein, the springboard program is used to execute and read the target program, and the target program is used to execute the boot procedure. The booting method of claim 1, wherein the read-only memory cannot be modified after being programmed. The booting method of claim 1, wherein the external storage device has existing programs or data, and the sum of the space of the plurality of discontinuous free spaces is greater than the size of the springboard program and the target program. The booting method of claim 1, wherein the SoC further comprises a random access memory for storing program codes for the processing unit to execute; wherein the springboard program is read and executed by the processing unit The step of the program is to read the springboard program, download the springboard program into the random access memory, and execute the springboard program with the processing unit. The booting method of claim 1, wherein the SoC further comprises a random access memory for storing program codes for the processing unit to execute; wherein the target program is executed by the processing unit through the springboard program In the step, the target program is downloaded into the random access memory through the springboard program, and the target program is executed by the processing unit. The booting method of claim 1, wherein the start position of the springboard program is controlled by an external signal input from the input port. The booting method of claim 6, wherein the input port is a general-purpose input and output port. The booting method of claim 1, wherein the SoC further comprises a wire-bonding selection or a programmable logic device for directly or indirectly determining the start position of the springboard program. The booting method of claim 8, wherein the programmable logic device is a write-once memory, a write-once memory, and a write-once memory. The booting method of claim 1, wherein the springboard program is composed of a plurality of sub-springboard programs. The booting method of claim 1, wherein the target program is composed of a plurality of sub-target programs. The booting method of claim 1, wherein the springboard program is not aligned with the location of an external storage device. The booting method of claim 1, wherein the target program is not aligned with a location of an external storage device. The booting method of claim 1, wherein the external storage device is serially addressed or parallel addressed. The booting method of claim 1, wherein the external storage device and the SoC are integrated into one chip.

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