TWI752642B - Semiconductor device and method for manufacturing the same - Google Patents

Abstract

A semiconductor device includes a substrate, a stack, a conductive pillar, a memory layer, and a salicide layer. The stack is disposed on the substrate, wherein the stack includes a plurality of insulating layers and a plurality of conductive layers that are alternately stacked along a first direction. The conductive pillar penetrates the stack along the first direction. The memory layer surrounds the conductive pillar. The salicide layer surrounds the conductive pillar, wherein the memory layer is disposed between the conductive pillar and the salicide layer.

Description

Semiconductor device and method of manufacturing the same

The present invention relates to a semiconductor device, and more particularly, to a three-dimensional semiconductor device.

Recently, various three-dimensional (3D) memory devices have been provided as the demand for more superior memory devices has gradually increased. Generally speaking, a 3D memory device includes a memory array area composed of a plurality of memory cells. However, there is still a leakage current problem in the current memory array area, which makes the 3D memory device unable to perform its normal operation. Therefore, there is a need to propose an improved 3D memory device and a method for fabricating the same to solve the problems faced by the prior art.

The present invention relates to a semiconductor device. Since the semiconductor device of this application includes a metal silicide layer, the metal silicide layer and the conductive layer can form a Schottky diode, and the Schottky diode can be used as a selector, so that the selector is electrically connected to the conductive layer and the conductive layer. The memory layer can provide rectification characteristics in the memory array, and the Schottky diode (selector) can perform unipolar operation on the memory to avoid reverse current. Therefore, the leakage current path in the memory array can be eliminated, thereby solving the leakage current problem faced by the prior art.

According to an embodiment of the present invention, a semiconductor device is provided. The semiconductor device includes a substrate, a stack, a conductive column, a memory layer and a metal silicide layer. The stack is disposed on the substrate, wherein the stack includes a plurality of insulating layers and a plurality of conductive layers alternately stacked along a first direction. The conductive pillars pass through the stack in a first direction. The memory layer surrounds the conductive pillars. The metal silicide layer surrounds the conductive pillar, wherein the memory layer is disposed between the conductive pillar and the metal silicide layer.

According to another embodiment of the present invention, a method for manufacturing a semiconductor device is provided. The method includes the following steps. First, a substrate is provided. Then, a stack is formed on the substrate, wherein the stack includes a plurality of insulating layers and a plurality of conductive layers alternately stacked along a first direction. A conductive pillar is formed, wherein the conductive pillar passes through the stack in a first direction. A memory layer is formed, wherein the memory layer surrounds the conductive pillars. Thereafter, a metal silicide layer is formed, wherein the metal silicide layer surrounds the conductive pillars, and the memory layer is disposed between the conductive pillars and the metal silicide layer.

In order to have a better understanding of the above-mentioned and other aspects of the present invention, the following specific examples are given and described in detail in conjunction with the accompanying drawings as follows:

10, 20, 30: Semiconductor devices

110: Substrate

110a: Upper surface

112: Insulation layer

114: Conductive layer

116: Metal layer

120: Conductive column

122,322: Memory Layer

124: metal silicide layer

226: Sidewall Conductor Layer

A,A',B,B': Hatch line endpoints

BL, BL1, BL2: bit lines

C1: first concentration

C2: Second concentration

RM: memory

SD: Schottky Diode

WL1-WL4: word lines

p1: vertical opening

p2: first lateral opening

p3: groove

p4: second lateral opening

p5: third lateral opening

S1: stack

SS1, SS2: Secondary stack

SW1, SW2: Outer side wall

Fig. 1A shows a partial top view of a semiconductor device according to an embodiment of the present invention; Fig. 1B shows a cross-sectional view along the line AA' of Fig. 1A; A manufacturing flow chart of the semiconductor device of the embodiment; Fig. 2I shows another embodiment of the steps of Fig. 2F; Fig. 3A shows a partial top view of a semiconductor device according to an embodiment of the present invention; Fig. 3B shows along AA' of Fig. 3A 4A~4B show a manufacturing flow diagram of a semiconductor device according to an embodiment of the present invention; Figure 5 shows a cross-sectional view of a semiconductor device according to an embodiment of the present invention; and Figure 6 An equivalent circuit diagram of a semiconductor device according to an embodiment of the present invention is shown.

FIG. 1A shows a partial top view of a semiconductor device 10 according to an embodiment of the present invention. Fig. 1B is a cross-sectional view taken along the line A-A' of Fig. 1A. Fig. 1A shows a cross section corresponding to the line B-B' in Fig. 1B.

Referring to FIGS. 1A and 1B , the semiconductor device 10 includes a substrate 110 , a stack S1 , a plurality of conductive pillars 120 , a plurality of memory layers 122 and a plurality of metal silicide layers 124 . The stack S1 is disposed on an upper surface 110 a of the substrate 110 , wherein the stack S1 includes a plurality of insulating layers 112 and a plurality of conductive layers 114 alternately stacked along a first direction (eg, the Z direction). In this embodiment, the thickness of the bottommost insulating layer 112 is greater than that of the other insulating layers 112 , but the present invention is not limited to this. In this embodiment, only five insulating layers 112 and four conductive layers 114 are illustrated, but the number of insulating layers 112 and conductive layers 114 is not limited thereto.

The conductive pillars 120 pass through the stack S1 along the first direction. There may be a space between the bottoms of the conductive pillars 120 and the upper surface 110 a of the substrate 100 . The memory layers 122 surround the conductive pillars 120 respectively. The metal silicide layer 124 surrounds the conductive pillar 120 , wherein the memory layer 122 is disposed between the conductive pillar 120 and the metal silicide layer 124 . The trench p3 passes through the stack S1 and extends along a second direction (eg, the X direction), dividing the stack S1 into a plurality of sub-stacks SS1 , SS2 . . . in some In an embodiment, the plurality of bit lines BL may extend along the third direction (eg, the Y direction), respectively, and the conductive pillars 120 may be electrically connected to the corresponding bit lines BL, respectively.

In one embodiment, the substrate 110 and the insulating layer 112 may be formed of oxide, such as silicon dioxide.

In one embodiment, the conductive layer 114 may be formed of a semiconductor material, such as doped or undoped polysilicon; in particular, it may be p-type or n-type doped polysilicon. In one embodiment, the conductive layer 114 may function as a word line.

In one embodiment, the material of the conductive pillar 120 is, for example, polysilicon, amorphous silicon, tungsten (W), cobalt (Co), aluminum (Al), tungsten silicide (WSi _X ), cobalt silicide (CoSi _X ) or other suitable materials. s material. The intersection between the conductive pillar 120 and each memory layer 122 can form a memory cell; a plurality of memory cells arranged along the conductive pillar 120 can form a memory string; a plurality of memory strings can form a memory array .

In one embodiment, the memory layer 122 includes a resistive memory material, such as a variable resistance random access memory material or a phase change memory material. When the memory layer 122 includes a variable resistance random access memory material, the material of the memory layer 122 is, for example, titanium silicon oxide (TiSi _X O _Y ) or other suitable variable resistance random access memory materials, so as to A variable resistance random access memory cell is formed at the intersection of the conductive pillar 120 and each memory layer 122 . When the memory layer 122 includes a phase change memory material, the material of the memory layer 122 is, for example, germanium antimony tellurium (Ge2Sb2Te5 (GST)) or other suitable phase change memory materials, so as to form a space between the conductive pillars 120 and each memory layer 122. The intersection between them forms a phase change memory. In this embodiment, the plurality of memory layers 122 are separated from each other by the insulating layer 112 , for example, the conductive pillars 120 are discontinuously surrounded in the first direction, but the invention is not limited to this.

In one embodiment, the material of the metal silicide layer 124 is, for example, titanium silicide (TiSi _X ), cobalt silicide (CoSi _X ) or other suitable metal silicides. In one embodiment, the metal silicide layer 124 and each corresponding conductive layer 114 form a Schottky diode, and the Schottky diode can be used as a selector. Since the metal silicide layer 124 and the conductive layer 114 in this case can form a Schottky diode, and the Schottky diode can be used as a selector, so that the selector is electrically connected to the conductive layer 114 and the memory layer 122, so It can provide rectification characteristics in the memory array, and the Schottky diode (selector) can perform unipolar operation on the memory to avoid the reverse current situation, so it can reduce or eliminate the memory array. A leakage current path is provided, thereby solving the leakage current problem faced by the prior art. In addition, Schottky diodes have fairly fast switching speeds for memory operation.

FIGS. 2A-2H illustrate a manufacturing flow chart of the semiconductor device 10 according to an embodiment of the present invention, for example, corresponding to the cross-sectional positions of the line A-A' in FIG. 1A.

Referring to FIG. 2A , a substrate 110 is provided, and a stack S1 is formed on the substrate 110 (eg, on the upper surface 110 a of the substrate 110 ). The stack S1 includes a plurality of insulating layers 112 and a plurality of conductive layers 114 alternately stacked along a first direction (eg, the Z direction). In this embodiment, the thickness of the bottommost insulating layer 112 is greater than that of the other insulating layers 112 , but the present invention is not limited to this. In one embodiment, the substrate 110 and the insulating layer 112 may be formed of oxide, such as silicon dioxide. The conductive layer 114 can be formed of a semiconductor material, such as doped or undoped polysilicon; in particular, it can be p-type or n-type doped polysilicon.

Referring to FIG. 2B, a vertical opening p1 is formed, wherein the vertical opening p1 passes through the stack S1, and the bottom of the vertical opening p1 can stay in the bottommost insulating layer 112 without exposing the upper surface 110a of the substrate 110, in other words , there may be a gap between the bottom of the vertical opening p1 and the substrate 110 .

Referring to FIG. 2C, through the vertical opening p1, a portion of the conductive layer 114 is removed to form a plurality of first lateral openings p2, wherein the first lateral openings p2 communicate with the vertical opening p1.

Referring to FIG. 2D, a metal layer 116 is deposited (eg, by chemical vapor deposition (CVD)) along the sidewalls of the vertical opening p1 and the first lateral opening p2. The material of the metal layer 116 is, for example, titanium (Ti), cobalt (Co) or other suitable metals.

Thereafter, referring to FIG. 2E , a rapid thermal annealing (RTA) process is performed to form a metal silicide layer 124 on the contact surface between the metal layer 116 and each conductive layer 114 . The material of the metal silicide layer 124 is, for example, titanium silicide (TiSix), cobalt silicide (CoSix) or other suitable metal silicides. In some embodiments, the rapid thermal annealing process may be performed twice, but the present invention is not limited thereto.

Referring to FIG. 2F, after the metal silicide layer 124 is formed, the metal layer 116 is removed by a selective etching process, such as a wet etching process.

Referring to FIG. 2G, after removing the metal layer 116, an oxidation process is performed to form the memory layer 122 between the vertical opening p1 and the metal silicide layer 124; alternatively, a deposition process (eg, chemical vapor phase) may be performed deposition process), depositing memory material in the space between the vertical opening p1 and the metal silicide layer 124 to form the memory layer 122 between the vertical opening p1 and the metal silicide layer 124 . In one embodiment, when the memory layer 122 is formed by an oxidation process, the memory layer 122 includes a variable resistance random access memory material, wherein the memory layer 122 can be an oxide of the metal silicide layer 124 . For example, when the metal silicide layer 124 includes titanium silicide (TiSi _X ), the memory layer 122 may include titanium silicon oxide (TiSi _X O _Y ). In another embodiment, when the memory layer 122 is formed by a deposition process, the memory layer 122 includes a phase change memory material, and the material of the memory layer 122 is, for example, germanium antimony tellurium (Ge2Sb2Te5 (GST)) or other suitable phase Change the memory material. In some embodiments, an etching process may be performed after forming the memory layer 122 to remove excess memory material.

Referring to FIG. 2H , after the memory layer 122 is formed, a conductive material is filled in the vertical opening p1 to form the conductive pillar 120 . The material of the conductive pillar 120 is, for example, platinum (Pt), tungsten (W), cobalt (Co), aluminum (Al), tungsten silicide (WSi _X ), cobalt silicide (CoSi _X ) or other suitable materials.

After the conductive pillars 120 are formed, a trench p3 is formed through the stack S1 and extending along a second direction (eg, the X direction), wherein the second direction and the first direction intersect with each other, and the trench p3 distinguishes the stack S1 For two sub-stacks SS1 and SS2, a semiconductor device 10 as shown in FIGS. 1A and 1B is formed. FIGS. 1A-1B only illustrate one trench p3 and two sub-stacks, but the present invention is not limited to this. The number of trenches p3 may be greater than one, and the number of sub-stacks may be greater than two.

In some embodiments, an insulating material may be filled in the trench p3.

Optionally, after the step of forming the trench p3, a doping process (such as a plasma doping process) may be further performed on the conductive layers 114, so that each conductive layer 114 is doped with a dopant (such as a p-type dopant). or n-type dopant), the dopant has a first concentration C1 in the region adjacent to the metal silicide layer 124, and a second concentration C2 in the region far from the metal silicide layer 124, and the second concentration C2 is greater than the second concentration C2. A concentration C1, in other words, the second concentration C2 of the dopant in the region of the conductive layer 114 adjacent to the trench p3 is greater than the first concentration C1 of the dopant in the region of the conductive layer 114 away from the trench p3, such as As shown in FIG. 1B, the present invention is not limited thereto.

Figure 2I illustrates another embodiment of the steps of Figure 2F.

In some embodiments, after the step of removing the metal layer 116 by the selective etching process, a portion of the metal layer 116 remains in the first lateral opening p2, as shown in FIG. 2I. The subsequent steps of Figure 2I are the same or similar to those of Figures 2G~2H.

FIG. 3A shows a partial top view of the semiconductor device 20 according to an embodiment of the present invention. Fig. 3B is a cross-sectional view taken along the line A-A' of Fig. 3A. Fig. 3A shows a cross section corresponding to the line B-B' in Fig. 3B.

Please refer to FIG. 3A, the semiconductor device 20 is similar to the semiconductor device 10, the difference is that the semiconductor device 20 further includes a sidewall conductor layer 226 adjacent to the conductive layer 114. will not be described in detail. The conductivity of the sidewall conductor layer 226 is greater than that of the conductive layer 114, the sidewall conductor layers 226 are disposed on opposite sides of the trench p3, and the sidewall conductor layers 226 between different layers are separated from each other by the insulating layer 112 (eg, shown in Figure 3B). Compared with the semiconductor device 10, since The semiconductor device 20 has a sidewall conductor layer 226, which can reduce the resistance value of the conductive layer 114, so that a better ohmic contact can be formed at a position adjacent to the trench p3 in the subsequent process.

In this embodiment, the conductive layer 114 can be doped with a dopant (which can be p-type or n-type), and the dopant in the conductive layer 114 has a concentration gradient distribution. For example, the dopant has a first concentration C1 in a region adjacent to the metal silicide layer 124 , and a second concentration C2 in a region remote from the metal silicide layer 124 , and the second concentration C2 is greater than the first concentration C1 . In other words, in the conductive layer 114, the dopant (which may be p-type or n-type) has a first concentration C1 in a region far from the trench p3, a second concentration C2 in a region adjacent to the trench p3, and a second concentration C2 in the region adjacent to the trench p3. The concentration C2 is greater than the first concentration C1, but the present invention is not limited to this. In other embodiments, the dopants in the conductive layer 114 may have the same concentration without the above-mentioned concentration gradient distribution phenomenon.

FIGS. 4A-4B illustrate a manufacturing flow chart of the semiconductor device 20 according to an embodiment of the present invention.

Part of the manufacturing process of the semiconductor device 20 is similar to the manufacturing process of the semiconductor device 10. After performing the process steps shown in FIGS. 2A to 2I, please refer to FIG. 4A, a part of the conductive layer can be removed through the trench p3 114 to form a plurality of second lateral openings p4, wherein the second lateral openings p4 communicate with the trenches p3. After that, a doping process (eg, a plasma doping process) is performed on the conductive layers 114, so that each conductive layer 114 is doped with a dopant (eg, a p-type or n-type dopant), and the dopant is adjacent to The region of the metal silicide layer 124 has a first concentration C1, and the region far from the metal silicide layer 124 has a second concentration C2, and the second concentration C2 is greater than the first concentration C1, that is, in the conductive layer 114, The dopant (which can be p-type or n-type) is adjacent to the The second concentration C2 in the region of the trench p3 may be greater than the first concentration C1 in the region farther from the trench p3.

In the conductive layer 114, the concentration of the dopant in the region adjacent to the metal silicide layer 124 is lower, which is favorable for the formation of Schottky diodes; the concentration of the dopant in the region adjacent to the trench p3 is higher, which is favorable for the formation of Schottky diodes. A better ohmic contact is formed at a position adjacent to the trench p3 (as shown in FIG. 3 ) in the subsequent process.

Thereafter, referring to FIG. 4B, a conductive material is filled in the second lateral opening p4 to form a plurality of sidewall conductor layers 226, wherein the sidewall conductor layers 226 are adjacent to the conductive layer 114, and the conductivity of the sidewall conductor layers 226 is greater than the conductivity of the conductive layer 114 . The material of the sidewall conductor layer 226 is, for example, tungsten (W), cobalt (Co), aluminum (Al), tungsten silicide (WSi _X ) or cobalt silicide (CoSi _X ). Since the sidewall conductor layer 226 is adjacent to the conductive layer 114 , and the conductivity of the sidewall conductor layer 226 is greater than that of the conductive layer 114 , it is more beneficial to form a better ohmic contact adjacent to the trench p3 in the subsequent process.

After that, through an etch back process, part of the sidewall conductor layer 226 can be removed to form a plurality of third lateral openings p5, and the third lateral openings p5 can be communicated with the trench p3 to form as shown in FIG. 3B Semiconductor device 20 . In one embodiment, the outer sidewall SW1 of the insulating layer 112 is farther away from the conductive pillar 120 than the outer sidewall SW2 of the sidewall conductor layer 226 .

In some embodiments, insulating material may be filled in the trenches p3 and the third lateral openings p5.

FIG. 5 is a cross-sectional view of a semiconductor device 30 according to an embodiment of the present invention. The semiconductor device 30 is similar to the semiconductor device 20 , and the difference lies in the structure of the memory layer 322 , and the same components use the same symbols, which will not be described in detail here.

Referring to FIG. 5 , the memory layer 322 surrounds the conductive pillars 120 ; the memory layer 322 extends along the first direction and corresponds to the plurality of conductive layers 114 . For example, the memory layer 322 continuously extends between the stack S1 and the conductive pillars 120 , and has the same height as the conductive pillars 120 in the first direction. The material of the memory layer 322 is, for example, a variable resistance random access memory material (though the invention is not limited to this), wherein the memory layer 322 may include titanium silicon oxide (TiSi _X O _Y ), cobalt silicide ( CoSi _X O _Y ) or other suitable materials. Compared with the comparative example in which the memory layer does not extend along the first direction, the manufacturing process of this embodiment is simpler.

FIG. 6 is an equivalent circuit diagram of the semiconductor devices 10 - 30 according to an embodiment of the present invention.

Please refer to FIG. 6, which exemplarily shows two memory strings, two conductive pillars 120 are electrically connected to bit lines BL1 and BL2, respectively, and four conductive layers 114 can be used as word lines WL1-WL4, respectively , each intersection between the conductive layer 114 and the conductive post 120 has a Schottky diode SD (eg, as a selector) and a memory RM (eg, a resistive memory) connected to each other.

According to an embodiment of the present invention, a semiconductor device is provided. The semiconductor device includes a substrate, a stack, a conductive column, a memory layer and a metal silicide layer. The stack is disposed on the substrate, wherein the stack includes a plurality of insulating layers and a plurality of conductive layers alternately stacked along a first direction. The conductive pillars pass through the stack in a first direction. The memory layer surrounds the conductive pillars. The metal silicide layer surrounds the conductive pillar, wherein the memory layer is disposed between the conductive pillar and the metal silicide layer.

Since the metal silicide layer and the conductive layer in this case can form a Schottky diode, and the Schottky diode can be used as a selector, so that the selector is electrically connected to the conductive layer and the memory layer, so it can be used in the memory Rectifying features are provided in the array, Schottky diodes (select The device) can perform unipolar operation on the memory to avoid the situation of reverse current, so the leakage current path in the memory array can be reduced or eliminated, thereby solving the conventional leakage current problem. Additionally, Schottky diodes have fairly fast switching speeds for memory operation.

To sum up, although the present invention has been disclosed by the above embodiments, it is not intended to limit the present invention. Those skilled in the art to which the present invention pertains can make various changes and modifications without departing from the spirit and scope of the present invention. Therefore, the protection scope of the present invention shall be determined by the scope of the appended patent application.

110: Substrate

110a: Upper surface

112: Insulation layer

114: Conductive layer

120: Conductive column

122: Memory Layer

124: metal silicide layer

A,A',B,B': Hatch line endpoints

C1: first concentration

C2: Second concentration

p3: groove

S1: stack

Claims (9)

A semiconductor device, comprising: a substrate; a stack disposed on the substrate, wherein the stack comprises a plurality of insulating layers and a plurality of conductive layers alternately stacked along a first direction; a conductive column along the first direction direction through the stack; a memory layer surrounding the conductive pillar; a metal silicide layer surrounding the conductive pillar, wherein the memory layer is disposed between the conductive pillar and the metal silicide layer; and a plurality of sidewall conductor layers , the sidewall conductor layers are adjacent to the conductive layers and separated from the memory layer and the metal silicide layer, wherein the conductivity of the sidewall conductor layers is greater than that of the conductive layers. The semiconductor device of claim 1, wherein the metal silicide layer and a corresponding conductive layer among the conductive layers form a Schottky diode. The semiconductor device of claim 1, wherein each of the conductive layers is doped with a dopant, and the dopant has a first concentration in a region adjacent to the metal silicide layer and at a distance away from the metal silicide layer The region has a second concentration that is greater than the first concentration. The semiconductor device of claim 1, further comprising a plurality of the memory layers, the memory layers are separated from each other by the insulating layers. The semiconductor device of claim 1, wherein the memory layer extends along the first direction and corresponds to the conductive layers. A method of manufacturing a semiconductor device, comprising: providing a substrate; forming a stack on the substrate, wherein the stack includes a plurality of insulating layers and a plurality of conductive layers alternately stacked along a first direction; forming a conductive column, wherein the conductive pillar passes through the stack along the first direction; a memory layer is formed, wherein the memory layer surrounds the conductive pillar, a metal silicide layer is formed, wherein the metal silicide layer surrounds the conductive pillar, wherein the memory layer Disposed between the conductive pillar and the metal silicide layer; and forming a plurality of sidewall conductor layers, the sidewall conductor layers are adjacent to the conductive layers and separated from the memory layer and the metal silicide layer, wherein the The conductivity of the sidewall conductor layers is greater than the conductivity of the conductive layers. The method for manufacturing a semiconductor device as claimed in claim 6, wherein the step of forming the metal silicide layer comprises: forming a vertical opening, wherein the vertical opening passes through the stack; removing a portion of the conductive layers to form a plurality of first lateral openings, wherein the first lateral openings communicate with the vertical opening; deposit a metal layer along the vertical opening and the sidewalls of the first lateral openings; and perform a rapid thermal annealing process to The metal silicide layer is formed on a contact surface between the metal layer and each of the conductive layers. The method for manufacturing a semiconductor device as claimed in claim 7, further comprising: after the metal silicide layer is formed, removing the metal layer; and performing an oxidation process to form between the vertical opening and the metal silicide layer forming the memory layer; and filling a conductive material in the vertical opening to form the conductive column. The method for manufacturing a semiconductor device as claimed in claim 7, further comprising: after the metal silicide layer is formed, removing the metal layer; and performing a deposition process to form between the vertical opening and the metal silicide layer forming the memory layer; and filling a conductive material in the vertical opening to form the conductive column.

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