KR20220009470A - Semiconductor device and method of manufacturing the same - Google Patents

Abstract

A semiconductor device according to an embodiment of the present invention comprises: a substrate including a first impurity region and a second impurity region; a bit line structure extending in one direction on the substrate and electrically connected to the first impurity region; a lower conductive pattern disposed on at least one side of the bit line structure to be electrically connected to the second impurity region; an upper conductive pattern disposed on the lower conductive pattern to be electrically connected to the lower conductive pattern; an air gap disposed between the bit line structure and the lower conductive pattern; and a buried insulating pattern disposed between the upper conductive pattern and the bit line structure on the air gap. The buried insulating pattern includes: a first insulating pattern disposed on the upper conductive pattern and a lateral wall of the bit line structure and exposing at least one portion of the lower part of the upper conductive pattern; and a second insulating pattern coming in contact with the upper conductive pattern exposed by the first insulating pattern and disposed on the upper part of the air gap. The present invention can stably implement an air gap structure.

Description

Semiconductor device and method of manufacturing the same

The present invention relates to a semiconductor device and a method for manufacturing the same.

According to the development of the electronic industry and the needs of users, electronic devices are becoming smaller and higher in performance. Accordingly, semiconductor devices used in electronic devices are also required to be highly integrated and high-performance. In order to manufacture a high-performance semiconductor device, a technique capable of minimizing parasitic capacitance between adjacent conductive structures is required so as to minimize a decrease in signal transmission speed due to RC delay.

One of the technical problems to be achieved by the technical idea of the present invention is to provide a semiconductor device in which capacitance between bit lines is reduced by including an air gap in which an insulating layer is not refilled.

One of the technical problems to be achieved by the technical idea of the present invention is to provide a method of manufacturing a semiconductor device that does not have a refill phenomenon when forming an air gap structure and can stably implement an air gap structure even when an aspect ratio is increased.

A semiconductor device according to example embodiments may include: a substrate including a first impurity region and a second impurity region; a bit line structure extending in one direction on the substrate and electrically connected to the first impurity region; a lower conductive pattern disposed on at least one side of the bit line structure and electrically connected to the second impurity region; an upper conductive pattern disposed on the lower conductive pattern and electrically connected to the lower conductive pattern; an air gap disposed between the bit line structure and the lower conductive pattern; and a buried insulating pattern disposed on the air gap between the upper conductive pattern and the bit line structure. The buried insulating pattern may include: a first insulating pattern disposed on sidewalls of the upper conductive pattern and the bit line structure and exposing at least a portion of a lower portion of the upper conductive pattern; and a second insulating pattern in contact with the upper conductive pattern exposed by the first insulating pattern and disposed above the air gap.

A method of manufacturing a semiconductor device according to example embodiments may include forming a first impurity region and a second impurity region in a substrate; forming bit line structures extending in one direction on the substrate and electrically connected to the first impurity region; forming inner spacers on both sidewalls of each of the bit line structures; forming a sacrificial spacer on the inner spacer; forming an outer spacer on the sacrificial spacer; forming a lower conductive pattern electrically connected to the second impurity region between the adjacent outer spacers; forming an upper conductive pattern covering the inner spacer, the sacrificial spacer, the outer spacer, and the lower conductive pattern; forming a first opening in the upper conductive pattern and the bit line structure to expose the sacrificial spacer; conformally forming a first preliminary insulating pattern on the inner surface of the first opening; forming a first insulating pattern by partially removing the first preliminary insulating pattern so that at least a portion of a lower portion of the upper conductive pattern, the inner spacer, the sacrificial spacer, and the outer spacer are exposed; removing the exposed sacrificial spacer to form a second opening; forming a deposition preventing material on surfaces of the inner spacer, the outer spacer, and the first insulating pattern in the first opening and the second opening; forming a second insulating pattern on the upper conductive pattern exposed in the first opening; removing the anti-deposition material; A third insulating pattern in contact with the first insulating pattern and the second insulating pattern may be formed.

Since the semiconductor device includes an air gap in which the insulating layer is not refilled, parasitic capacitance between bit lines may be reduced. Even when the aspect ratio of the air gap increases, the air gap structure may be stably implemented.

Various and advantageous advantages and effects of the present invention are not limited to the above, and will be more easily understood in the course of describing specific embodiments of the present invention.

1 is a schematic layout diagram of a semiconductor device according to example embodiments.
2 is a cross-sectional view of a semiconductor device according to example embodiments.
3 is a cross-sectional view of a semiconductor device according to example embodiments.
4 is a cross-sectional view of a semiconductor device according to example embodiments.
5A to 5D are cross-sectional views illustrating a manufacturing process of a semiconductor device according to example embodiments.

Hereinafter, preferred embodiments of the present invention will be described with reference to the accompanying drawings.

1 is a schematic layout diagram of a semiconductor device according to example embodiments. 2 is a cross-sectional view of a semiconductor device according to example embodiments. FIG. 2 is a cross-sectional view of the semiconductor light emitting device shown in FIG. 1 taken along line I-I'.

1 and 2 , a semiconductor device 100 according to example embodiments includes a substrate 101 , a word line WL that is embedded in the substrate 101 and extends, and a word line (WL) on the substrate 101 . The bit line structure BLS extending to cross the WL, and the spacer structure SS disposed on sidewalls of the bit line structure BLS. A lower conductive pattern 150 disposed on at least one side of the bit line structure BLS, an upper conductive pattern 160 disposed on the lower conductive pattern 150 , and a buried insulating pattern disposed on the spacer structure SS may include

The substrate 101 may include a semiconductor material, for example, a group IV semiconductor, a III-V compound semiconductor, or a group II-IV compound semiconductor. For example, the group IV semiconductor may include silicon, germanium, or silicon-germanium. The substrate 101 may further include impurities. The substrate 101 includes a silicon substrate, a silicon on insulator (SOI) substrate, a germanium substrate, a germanium on insulator (GOI) substrate, a silicon-germanium substrate, or an epitaxial layer. It may be a substrate that

The active regions ACT may be defined in the substrate 101 by the device isolation region 110 . Each of the active regions ACT may have a bar shape, and may be disposed in an island shape extending in one direction within the substrate 101 . The direction in which the active regions ACT extend may be inclined with respect to the extension directions of the word lines WL and the bit lines BL. The active regions ACT may be arranged parallel to each other, and an end of one active region ACT may be arranged adjacent to a center of another active region ACT adjacent thereto.

The active region ACT may have first and second impurity regions 105a and 105b having a predetermined depth from the top surface of the substrate 101 . The first and second impurity regions 105a and 105b may be spaced apart from each other. The first and second impurity regions 105a and 105b may serve as source/drain regions of the transistor formed by the word line WL. For example, a drain region may be formed between two word lines WL crossing one active region ACT, and a source region may be formed outside the two word lines WL, respectively. can The source region and the drain region are formed by the first and second impurity regions 105a and 105b by doping or ion implantation with substantially the same impurities, and may be referred to interchangeably depending on the circuit configuration of the finally formed transistor. may be The impurities may include dopants having a conductivity type opposite to that of the substrate 101 . In example embodiments, depths of the first and second impurity regions 105a and 105b in the source region and the drain region may be different from each other.

The device isolation region 110 may be formed by a shallow trench isolation (STI) process. The device isolation region 110 surrounds the active regions ACT and may electrically isolate them from each other. The device isolation region 110 may be made of an insulating material, for example, silicon oxide, silicon nitride, or a combination thereof. The device isolation region 110 may include a plurality of regions having different bottom depths according to the width of the trench in which the substrate 101 is etched.

The word line WL may be disposed in a gate trench extending in one direction, for example, an X direction in the substrate 101 . The word line WL may be disposed to cross the active area ACT and extend in the X direction. For example, a pair of adjacent word lines WL may be disposed to cross one active area ACT. The word line WL may constitute a gate of a buried channel array transistor (BCAT), but is not limited thereto. In example embodiments, the word lines WL may have a shape disposed on the substrate 101 .

The word line WL may be formed of a conductive material such as polycrystalline silicon (Si), titanium (Ti), titanium nitride (TiN), tantalum (Ta), tantalum nitride (TaN), tungsten (W), or tungsten nitride (WN). ), and at least one of aluminum (Al). For example, the word line WL may include a lower pattern and an upper pattern formed of different materials.

The bit line structure BLS may extend in one direction, for example, a Y direction, perpendicular to the word line WL. The bit line structure BLS may include a bit line BL and a bit line capping pattern BC on the bit line BL.

The bit line BL may include a first conductive pattern 141 , a second conductive pattern 142 , and a third conductive pattern 143 that are sequentially stacked. The bit line capping pattern BC may be disposed on the third conductive pattern 143 . A buffer insulating layer 120 may be disposed between the first conductive pattern 141 and the substrate 101 , and a portion of the first conductive pattern 141 (hereinafter, referred to as a bit line contact pattern) is formed by the buffer insulating layer 120 . may pass through and come into contact with the first impurity region 105a of the active region ACT. The bit line BL may be electrically connected to the first impurity region 105a through a bit line contact pattern. The lower surface of the bit line contact pattern may be positioned at a level lower than the upper surface of the substrate 101 .

The first conductive pattern 141 may include a material such as polycrystalline silicon. The first conductive pattern 141 may directly contact the first impurity region 105a. The second conductive pattern 142 may include a metal-semiconductor compound. The metal-semiconductor compound may be, for example, a layer in which a portion of the first conductive pattern 141 is silicided. For example, the metal-semiconductor compound may include cobalt silicide (CoSi), titanium silicide (TiSi), nickel silicide (NiSi), tungsten silicide (WSi), or other metal silicide. The third conductive pattern 143 may include a metal material such as titanium (Ti), tantalum (Ta), tungsten (W), and aluminum (Al). The number of conductive patterns constituting the bit line BL, the type of material, and/or the stacking order may be variously changed according to exemplary embodiments.

The bit line capping pattern BC may be disposed on the third conductive pattern 143 . Although not shown in FIG. 2 , the bit line capping pattern BC may include a plurality of capping patterns sequentially stacked. Each of the plurality of capping patterns may include an insulating material, for example, a silicon nitride layer. The plurality of capping patterns may be made of different materials, and even if they include the same material, boundaries may be distinguished by differences in physical properties. The number of capping patterns and/or the type of material constituting the bit line capping pattern BC may be variously changed according to embodiments.

The spacer structures SS may be disposed on both sidewalls of each of the bit line structures BLS to extend in one direction, for example, the Y direction. The spacer structures SS may be disposed between the bit line structure BLS and the lower conductive pattern 150 . The spacer structures SS may be disposed to extend along sidewalls of the bit line BL and sidewalls of the bit line capping pattern BC. A pair of spacer structures SS disposed on both sides of one bit line structure BLS may have an asymmetric shape with respect to the bit line structure BLS.

Each of the spacer structures SS may include a plurality of spacer layers. In example embodiments, each of the spacer structures SS may form an inner spacer 171 , an outer spacer 173 , and an air gap AG disposed between the inner spacer 171 and the outer spacer 173 . may include

The inner spacer 171 may be disposed on a sidewall of the bit line structure BLS. The inner spacer 171 may include a portion extending toward the lower conductive pattern 150 along the upper surface of the buffer insulating layer 120 or the buried pattern 135 . The thickness of the inner spacer 171 may be smaller than the thickness of the air gap AG and the outer spacer 173 .

The outer spacer 173 may be disposed on a sidewall of the lower conductive pattern 150 . An upper portion of the outer spacer 173 may include a portion inclined toward the inner spacer 171 to cap the air gap AG. In example embodiments, the outer spacer 173 may be configured as a single layer and may extend to cover a portion of the upper surface of the metal-semiconductor compound layer 155 . However, the shape of the outer spacer 173 is not limited thereto. For example, the outer spacer 173 may include a plurality of layers or may not include a portion extending onto the metal-semiconductor compound layer 155 .

Each of the inner spacer 171 and the outer spacer 173 may include an insulating material. For example, the inner spacer 171 and the outer spacer 173 may include silicon nitride.

The air gap AG may be disposed between the inner spacer 171 and the outer spacer 173 . An upper surface of the air gap AG may be defined by a second insulating pattern 182 and a third insulating pattern 183 . The air gap AG may extend to a level higher than upper surfaces of the inner spacer 171 and the outer spacer 173 . In example embodiments, the air gap AG is formed by the inner spacer 171 , the outer spacer 173 , the first to third insulating patterns 181 , 182 , and 183 , and the bit line capping pattern BC. It may be capped, but is not limited thereto. Depending on the position of the lower surface of the third insulating pattern 183 , the air gap AG does not contact the bit line capping pattern BC and is formed by the first to third insulating patterns 181 , 182 , and 183 . can be capped. The air gap AG may be defined by an inner spacer 171 , an outer spacer 173 , and first to third insulating patterns 181 , 182 , and 183 .

As semiconductor devices are highly integrated, the distance between conductive patterns becomes narrower, cross talk between the conductive patterns may occur, and parasitic capacitance between adjacent conductive patterns electrically separated by an insulating layer may increase. can In particular, when the conductive patterns are bit line structures, a parasitic capacitance between adjacent bit lines may impede the flow of an electrical signal transmitted to a circuit and may reduce a bit line sensing margin.

In the semiconductor device 100 according to exemplary embodiments of the present invention, an air gap AG having a low dielectric constant is formed between the bit line structure BLS and the lower conductive pattern 150 and between the adjacent bit line structures BLS. ), the parasitic capacitance between the conductive patterns may be reduced. Furthermore, by capping a portion of the upper portion of the air gap AG with the second insulating pattern 182 and capping the remaining portion with the third insulating pattern 183 , the insulating material is prevented from being refilled into the air gap AG. can be prevented For this reason, parasitic capacitance of the semiconductor device 100 may be minimized, and operation stability may be increased.

The buried pattern 135 may be disposed under the spacer structure SS to surround sidewalls of the bit line contact pattern. The buried pattern 135 may include an insulating material, for example, silicon nitride. According to embodiments, the shape and position of the spacer structure SS and the buried pattern 135 may be changed. For example, the inner spacer 171 may extend to a lower portion of the bit line contact pattern, and the buried pattern 135 may be disposed on the inner spacer 171 .

The lower conductive pattern 150 may be connected to one region of the active region ACT, for example, the second impurity region 105b. The lower conductive pattern 150 may be disposed between the bit lines BL and between the word lines WL. The lower conductive pattern 150 may pass through the buffer insulating layer 120 to be connected to the second impurity region 105b of the active region ACT. The lower conductive pattern 150 may directly contact the second impurity region 105b. The lower surface of the lower conductive pattern 150 may be located at a level lower than the upper surface of the substrate 101 , and may be located at a higher level than the lower surface of the bit line contact pattern.

The lower conductive pattern 150 may be insulated from the bit line contact pattern by the spacer structure SS and the buried pattern 135 . The lower conductive pattern 150 may include a conductive material, for example, polycrystalline silicon (Si), titanium (Ti), titanium nitride (TiN), tantalum (Ta), tantalum nitride (TaN), or tungsten (W). ), tungsten nitride (WN), and aluminum (Al). In an exemplary embodiment, the lower conductive pattern 150 may include a plurality of layers.

A metal-semiconductor compound layer 155 may be disposed between the lower conductive pattern 150 and the upper conductive pattern 160 . The metal-semiconductor compound layer 155 may be, for example, a layer in which a portion of the lower conductive pattern 150 is silicided when the lower conductive pattern 150 includes a semiconductor material. The metal-semiconductor compound layer 155 may include, for example, cobalt silicide (CoSi), titanium silicide (TiSi), nickel silicide (NiSi), tungsten silicide (WSi), or other metal silicide. In some embodiments, the metal-semiconductor compound layer 155 may be omitted.

The upper conductive pattern 160 may be disposed on the lower conductive pattern 150 . The upper conductive pattern 160 may extend between the spacer structures SS to cover the upper surface of the metal-semiconductor compound layer 155 .

The upper conductive pattern 160 may include a barrier layer 162 and a conductive layer 164 , respectively. The barrier layer 162 may cover a lower surface and sidewalls of the conductive layer 164 . The barrier layer 162 may include a metal nitride, for example, at least one of titanium nitride (TiN), tantalum nitride (TaN), and tungsten nitride (WN). The conductive layer 164 may include a conductive material such as polycrystalline silicon (Si), titanium (Ti), tantalum (Ta), tungsten (W), ruthenium (Ru), copper (Cu), molybdenum (Mo), It may include at least one of platinum (Pt), nickel (Ni), cobalt (Co), aluminum (Al), titanium nitride (TiN), tantalum nitride (TaN), and tungsten nitride (WN).

The upper conductive pattern 160 may constitute the gate contact plug CP together with the lower conductive pattern 150 and the metal-semiconductor compound layer 155 .

The buried insulating pattern may include a first insulating pattern 181 , a second insulating pattern 182 , and a third insulating pattern 183 . The buried insulating pattern may be disposed to penetrate the upper conductive pattern 160 . A plurality of upper conductive patterns 160 may be separated by a buried insulating pattern.

Each of the first to third insulating patterns 181 , 182 , and 183 may include an insulating material, for example, silicon oxide, silicon nitride, silicon oxynitride, silicon carbonitride, silicon oxycarbonitride, or a combination thereof. The first to third insulating patterns 181 , 182 , and 183 may include the same material or different materials.

The first insulating pattern 181 may be disposed to cover the upper conductive pattern 160 and sidewalls of the bit line structure BLS. The first insulating pattern 181 may expose a lower portion of one sidewall of the upper conductive pattern 160 . In example embodiments, the first insulating pattern 181 may expose at least a portion of the barrier layer 162 and the conductive layer 164 .

The second insulating pattern 182 may be disposed on the surface of the upper conductive pattern 160 exposed by the first insulating pattern 181 . The second insulating pattern 182 may contact the upper conductive pattern 160 . In example embodiments, the second insulating pattern 182 may contact at least a portion of the barrier layer 162 and the conductive layer 164 . The upper conductive pattern 160 may include a conductive material, while the second insulating pattern 182 disposed in contact with the upper conductive pattern 160 may include an insulating material. The second insulating pattern 182 may be disposed so as not to overlap the first insulating pattern 181 and the outer spacer 173 disposed on the upper conductive pattern 160 .

The second insulating pattern 182 may contact the upper conductive pattern 160 and extend toward the first insulating pattern 181 disposed on the sidewall of the bit line structure BLS. The second insulating pattern 182 may be disposed so as not to contact the first insulating pattern 181 , the bit line structure BLS, and the inner spacer 171 disposed on the sidewall of the bit line structure BLS. In example embodiments, the second insulating pattern 182 may be separated from the first insulating pattern 181 , the bit line structure BLS, and the inner spacer 171 with an interval greater than about 0 nm and less than or equal to about 2 nm. have. However, the separation interval is not limited thereto, and may be changed in consideration of the molecular size of the deposition prevention pattern IH in a manufacturing process (eg, FIG. 5D ) to be described later.

The third insulating pattern 183 may be disposed on the second insulating pattern 182 to contact the first insulating pattern 181 . The third insulating pattern 183 may be disposed to fill an empty space defined by the first insulating pattern 181 and cover at least a portion of the surface of the second insulating pattern 182 . A lower surface of the third insulating pattern 183 may be disposed between the second insulating pattern 182 and the first insulating pattern 181 disposed on the sidewall of the bit line structure BLS. The lower surface of the third insulating pattern 183 and the upper surface of the substrate 101 may have a flat shape, but is not limited thereto. For example, the lower surface of the third insulating pattern 183 may have a convex, concave, or inclined planar shape toward the top.

The first to third insulating patterns 181 , 182 , and 183 may cap the air gap AG. In example embodiments, the second and third insulating patterns 182 and 183 may define a top surface of the air gap AG. The second insulating pattern 182 may cap an upper portion of the air gap AG, and the remaining portion not capped by the second insulating pattern 182 may be capped by the third insulating pattern 183 . The first insulating pattern 181 may form at least a portion of a side surface of the air gap AG, but is not limited thereto. In some embodiments, when the lower surface of the third insulating pattern 183 is disposed at a level lower than the lower end of the first insulating pattern 181 , the first insulating pattern 181 may not contact the air gap AG. may be

Unlike the embodiment illustrated in FIG. 2 , when the first to third insulating patterns 181 , 182 , and 183 extend to cover upper ends of the inner spacer 171 and the outer spacer 173 , the inner spacer 171 . ) and the sidewall of the outer spacer 173 , an insulating material is unintentionally formed inside the air gap AG, so that the inside of the air gap AG may be refilled. For example, when the first insulating pattern 181 has the shape of a continuous insulating layer, or when the third insulating pattern 183 extends to cover upper portions of the inner spacer 171 and the outer spacer 173 , An insulating material may be formed in the air gap AG, so that the insulating material may be refilled in the air gap AG. Accordingly, the effect of reducing the parasitic capacitance due to the air gap AG may be reduced.

As shown in FIG. 2 , in the case of the semiconductor device 100 according to the exemplary embodiments of the present invention, the first to third insulating patterns 181 , 182 , and 183 are formed on both sides of the air gap AG. It may not come into contact with the inner spacer 171 and the outer spacer 173 disposed on the . The second insulating pattern 182 may be disposed to contact the upper conductive pattern 160 and may have a shape extending toward the bit line structure BLS. Since the first to third insulating patterns 181 , 182 , and 183 have such a shape, they are insulated into the air gap AG between the sidewalls of the inner spacer 171 and the outer spacer 173 . The problem of the material being refilled can be solved.

3 and 4 are cross-sectional views of semiconductor devices according to example embodiments. In the embodiment of FIGS. 3 and 4 , the same reference numerals as in FIGS. 1 and 2 indicate corresponding configurations, and a description overlapping with the above description will be omitted. In the embodiment of Figs. 3 and 4, in the case of having the same reference numerals as those of Figs. 1 and 2, but having a different alphabet, it is for explaining an embodiment different from Figs. 1 and 2, and the same reference numbers described above The features described in may be the same or similar.

The semiconductor device 100a of FIG. 3 is different from the semiconductor device 100 of FIGS. 1 and 2 in the shape of the second insulating pattern 182a and the deposition prevention pattern IHa.

Referring to FIG. 3 , the second insulating pattern 182a may be disposed to contact the first insulating pattern 181 disposed on the bit line structure BLS. The second insulating pattern 182a may contact the upper conductive pattern 150 and the first insulating pattern 181 disposed on the bit line structure BLS, and may cap the air gap AG. The air gap AG may be defined by an inner spacer 171 , an outer spacer 173 , and a second insulating pattern 182a.

3 , the second insulating pattern 182a is disposed to contact the first insulating pattern 181 disposed on the bit line structure BLS, but is not limited thereto. Depending on the length of the first insulating pattern 181 , the height of the spacer structure SS, the shape of the second insulating pattern 182a , etc., the second insulating pattern 182a may be the bit line capping pattern BC or the inner spacer 171 . ) may be placed in contact with

The deposition prevention pattern IHa may be disposed on surfaces of the inner spacer 171 and the outer spacer 173 defining the air gap AG. In an exemplary embodiment, the deposition prevention pattern IHa may be disposed to cover the entire surface inside the air gap AG. The deposition prevention pattern IHa may prevent an insulating material from being deposited on the surfaces of the inner spacer 171 and the outer spacer 173 . Accordingly, refilling of the insulating material in the air gap AG may be more effectively prevented. The type of the material included in the deposition prevention pattern IHa is not limited as long as it prevents the formation of an insulating material. In example embodiments, the material included in the deposition prevention pattern IHa may include aliphatic compounds, aromatic compounds, cyclic compounds, and the like.

The semiconductor device 100b of FIG. 4 is different from the semiconductor device 100a of FIG. 3 in the deposition prevention pattern IHb.

Referring to FIG. 4 , the deposition prevention pattern IHb may be disposed only over the air gap AG. The deposition prevention pattern IHb disposed on the air gap AG may prevent the insulating material from being refilled into the air gap AG. An arrangement range of the deposition prevention pattern IHb is not limited to that illustrated in FIG. 4 . Depending on the type of insulating material included in the first to third insulating patterns 181 , 182 , and 183 and the aspect ratio of the air gap AG, the disposition area of the deposition prevention pattern IHb is expanded or reduced. it might be

5A to 5D are cross-sectional views illustrating a manufacturing process of a semiconductor device according to example embodiments. 5A to 5D are cross-sectional views illustrating a manufacturing process of the semiconductor device 100 illustrated in FIGS. 1 and 2 .

Referring to FIG. 5A , the device isolation region 110 may be formed on the substrate 101 to define the active region ACT. A device isolation trench may be formed in the substrate 101 , and the device isolation region 110 may be formed by filling the device isolation trench. In plan view, the active area ACT may have an elongated bar shape. An impurity region may be formed on the active region ACT by performing an ion implantation process using the device isolation region 110 as an ion implantation mask. A trench extending in the X direction may be formed by patterning the active region ACT and the device isolation region 110 , and a word line WL may be formed in the trench. A pair of word lines WL may cross the active area ACT, but is not limited thereto. The impurity regions may also be separated by the word line WL to form a first impurity region 105a and a second impurity region 105b.

An insulating layer and a conductive layer are sequentially formed and patterned on the entire surface of the substrate 101 to form the sequentially stacked buffer insulating layer 120 and the first conductive pattern 141 . The buffer insulating layer 120 may be formed of at least one of silicon oxide, silicon nitride, and silicon oxynitride. A bit line contact hole may be formed by etching the device isolation region 110 and the substrate 101 using the buffer insulating layer 120 and the first conductive pattern 141 as an etch mask. The bit line contact hole may expose the first impurity region 105a.

A bit line contact pattern may be formed to fill the bit line contact hole. Forming the bit line contact pattern may include forming a conductive layer filling the bit line contact hole and performing a planarization process. For example, the bit line contact pattern may be formed of polysilicon. A second conductive pattern 142 , a third conductive pattern 143 , and a bit line capping pattern BC are sequentially formed on the first conductive pattern 141 , and then the bit line capping pattern BC is used as an etch mask. The first to third conductive patterns 141 , 142 , and 143 may be etched sequentially. As a result, the bit line BL including the first to third conductive patterns 141 , 142 , and 143 and the bit line structure BLS including the bit line capping pattern BC may be formed.

A buried pattern 135 may be formed on side surfaces of the bit line contact pattern. The buried pattern 135 may fill the bit line contact hole. The buried pattern 135 completely fills the bit line contact hole, forms an insulating layer covering sidewalls and top surfaces of the bit line structure BLS, and performs an etching process on the insulating layer, thereby forming the buried pattern 135 in the bit line contact hole. can be formed locally. The buried pattern 135 may include, for example, silicon nitride.

A preliminary spacer structure SS′ may be formed on side surfaces of the bit line structure BLS. The preliminary spacer structure SS′ may be formed of a plurality of layers. In example embodiments, the preliminary spacer structure SS′ may include an inner spacer 171 , a sacrificial spacer 172 , and an outer spacer 173 . An inner spacer 171 , a sacrificial spacer 172 , and an outer spacer 173 may be sequentially conformally formed along the upper surface of the substrate 101 and the surface of the bit line structure BLS. The spacers 171 , 172 , and 173 may include different materials. For example, the inner spacer 171 may include silicon nitride, the sacrificial spacer 172 may include silicon oxide, and the outer spacer 173 may include silicon nitride.

A lower conductive pattern 150 may be formed between the adjacent preliminary spacer structures SS′. By performing an anisotropic etching process using the fence insulating patterns (not shown) as an etch mask to form an opening exposing the second impurity region 105b, and then filling a conductive material such as polycrystalline silicon (Si), the lower portion A conductive pattern 150 may be formed.

A metal-semiconductor compound layer 155 may be formed on the lower conductive pattern 150 . The formation of the metal-semiconductor compound layer 155 may include a metal layer deposition process and a heat treatment process.

A barrier layer 162 and a conductive layer 164 may be sequentially deposited to cover the bit line structure BLS, the spacer structure SS, the lower conductive pattern 150 and the metal semiconductor compound layer 155 . The barrier layer 162 and the conductive layer 164 may constitute the upper conductive pattern 160 .

The upper conductive pattern 160 and the bit line structure BLS may be etched together to form the first opening OP1 . The first opening OP1 may be etched to a depth to which the sacrificial spacer 172 is exposed. The preliminary spacer structure SS′, the barrier layer 162 , the conductive layer 164 , and the bit line capping pattern BC may be exposed through the first opening OP1 . Due to the first opening OP1 , the preliminary spacer structure SS′ may have an asymmetrical shape with respect to the bit line structure BLS.

A first preliminary insulating pattern 181 ′ may be formed to conformally cover surfaces of the first opening OP1 and the upper conductive pattern 160 . The first preliminary insulating pattern 181 ′ may include an insulating material, for example, at least one of silicon oxide, silicon nitride, silicon oxynitride, silicon carbonitride, and silicon oxycarbonitride.

Referring to FIG. 5B , the first insulating pattern 181 may be formed by an etching process of the first preliminary insulating pattern 181 ′. For example, an anisotropic etching process may be performed on the first preliminary insulating pattern 181 ′.

Through the etching process, the upper surface of the upper conductive pattern 160 , at least a portion of the lower portion of the upper conductive pattern 160 , and the preliminary spacer structure ( SS′ of FIG. 5A ) may be exposed. The sacrificial spacer 172 of FIG. 5A exposed by the first opening OP1 may be selectively removed. Accordingly, the second opening OP2 may be formed. Sidewalls of the inner spacer 171 and the outer spacer 173 may be exposed through the second opening OP2 . The sacrificial spacer ( 172 of FIG. 5A ) may have a selective etch ratio with respect to the inner spacer 171 and the outer spacer 173 . The sacrificial spacer 172 of FIG. 5A may be removed by a wet etching process using, for example, hydrofluoric acid (HF).

Referring to FIG. 5C , the first insulating pattern 181 , the inner spacer 171 , the outer spacer 173 , and the bit line capping pattern BC are formed in the first opening OP1 and the second opening OP2 . A deposition prevention pattern IH may be formed on the surface.

Before the deposition prevention pattern IH is formed, a pretreatment process may be performed on the surfaces of the first insulating pattern 181 , the inner spacer 171 , the outer spacer 173 , and the bit line capping pattern BC . The adsorption activation energy of the surfaces of the first insulating pattern 181 , the inner spacer 171 , the outer spacer 173 , and the bit line capping pattern BC is adjusted by the pretreatment process to form the deposition prevention pattern IH This can be facilitated. In exemplary embodiments, a pretreatment process of surface oxidation may be performed. For example, an oxidation process of the surfaces of the first insulating pattern 181 , the inner spacer 171 , the outer spacer 173 , and the bit line capping pattern BC may be performed using oxygen radicals.

Thereafter, a material layer is formed on the surfaces of the first insulating pattern 181 , the inner spacer 171 , the outer spacer 173 , and the bit line capping pattern BC to form a deposition prevention pattern IH through a chemical reaction. can do. In example embodiments, when the first insulating pattern 181 , the inner spacer 171 , the outer spacer 173 , and the bit line capping pattern BC include silicon nitride, aldehyde or alcohol is formed on the surface thereof. A material layer containing (Alcohol) may be formed. A surface amine group of the silicon nitride may react with the material layer to form an alkyl-terminated anti-deposition pattern (IH).

The deposition prevention pattern IH is formed only on the surfaces of the first insulating pattern 181 , the inner spacer 171 , the outer spacer 173 , and the bit line capping pattern BC including the insulating material, and includes an upper conductive pattern. It may not be deposited on (160).

Referring to FIG. 5D , a second insulating pattern 182 may be formed on the surface of the upper conductive pattern 160 exposed in the first opening OP1 .

The second insulating pattern 182 may be formed by depositing an insulating material on the surface of the upper conductive pattern 160 . In an exemplary embodiment, an insulating material is deposited on the surface of the upper conductive pattern 160 by atomic layer deposition (ALD) or chemical vapor deposition (CVD) to form the second insulating pattern 182 can do. Since the deposition prevention pattern IH in the process of FIG. 5C is formed on the surfaces of the first insulating pattern 181 , the inner spacer 171 , the outer spacer 173 , and the bit line capping pattern BC, insulation The material may not be deposited. The second insulating pattern 182 is not formed on the surfaces of the first insulating pattern 181 , the inner spacer 171 , the outer spacer 173 , and the bit line capping pattern BC including the insulating material, and a conductive material is formed thereon. The second insulating pattern 182 may be selectively formed only on the surface of the included upper conductive pattern 160 .

As shown in FIG. 5D , the second insulating pattern 182 may be deposited until it does not come into contact with the first insulating pattern 181 disposed on the bit line structure BLS. The second insulating pattern 182 may be formed to be separated from the first insulating pattern 181 disposed on the bit line structure BLS by a predetermined interval. A separation distance between the second insulating pattern 182 and the first insulating pattern 181 disposed on the bit line structure BLS may be determined by a deposition preventing pattern IH in a process of removing the deposition preventing pattern IH to be described later. It may be greater than or equal to the molecular size of the substance contained in it. Accordingly, in a process of removing the deposition prevention pattern IH to be described later, the deposition prevention pattern IH formed in the second opening OP2 may be easily removed. In example embodiments, a separation interval between the second insulating pattern 182 and the first insulating pattern 181 disposed on the bit line structure BLS may be greater than about 0 nm and less than or equal to about 2 nm. However, the separation interval is not limited thereto, and may vary depending on the type of material included in the deposition prevention pattern IH.

The shape of the second insulating pattern 182 is not limited to that illustrated in FIG. 5D . In other embodiments, the second insulating pattern 182 may be formed to contact the first insulating pattern 181 disposed on the bit line structure BLS. Accordingly, the second insulating pattern 182 may cap the second opening OP2 . In a process of removing the deposition prevention pattern IH to be described later, the deposition prevention pattern IH formed in the first opening OP1 may be removed, but the deposition prevention pattern IH formed in the second opening OP2 may not be removed. have. Accordingly, the semiconductor device 100a shown in FIG. 3 may be manufactured. The second opening OP2 is capped by the second insulating pattern ( 182a of FIG. 3 ) to form an air gap (AG of FIG. 3 ), and a deposition prevention pattern ( FIG. 3 ) is formed inside the air gap (AG of FIG. 3 ). of IHa) may remain.

The shape of the deposition prevention pattern IH is also not limited to that illustrated in FIG. 5D . In other embodiments, the deposition prevention pattern IH may be formed only up to the upper end of the second opening OP2 . In addition, when the second insulating pattern 182 is formed to contact the first insulating pattern 181 disposed on the bit line structure BLS, the semiconductor device 100b shown in FIG. 4 may be manufactured. . The second opening OP2 may be capped by the second insulating pattern 182a of FIG. 4 to form an air gap AG of FIG. 4 . The deposition prevention pattern IHb may remain in the air gap (AG of FIG. 4 ) in a portion including the upper portion.

Referring back to FIGS. 1 and 2 , the deposition prevention pattern IH formed in the first opening OP1 and the second opening OP2 may be removed.

A method of removing the deposition prevention pattern IH may not be limited. In example embodiments, the deposition prevention pattern IH may be removed by annealing. Annealing may be performed, for example, in a temperature range of about 200° C. to about 300° C., but is not limited thereto. The annealing temperature may vary depending on the type of material included in the deposition prevention pattern IH. In other embodiments, the deposition prevention pattern IH may be removed by chemical etching. The deposition prevention pattern IH may be removed by, for example, a plasma treatment process. The plasma treatment process may be performed using, for example, oxygen plasma or hydrogen plasma.

Thereafter, a third insulating pattern 183 may be formed inside the first opening (OP1 of FIG. 5D ). The third insulating pattern 183 may be formed, for example, by forming an insulating material to a level higher than that of the upper conductive pattern 160 and then performing an etch-back process.

The third insulating pattern 183 may be formed to have a lower surface disposed between the second insulating pattern 182 and the first insulating pattern 181 disposed on the bit line structure BLS. After blocking part or all of an upper portion of the second opening ( OP2 in FIG. 5D ) with the second insulating pattern 182 , a third method to fill the first opening ( OP1 in FIG. 5D ) on the second insulating pattern 182 . By forming the insulating pattern 183 , it is possible to prevent the insulating material from being refilled into the air gap AG. Even when the aspect ratio of the air gap AG increases, the air gap AG having a stable structure may be implemented.

The present invention is not limited by the above-described embodiments and the accompanying drawings, but is intended to be limited by the appended claims. Accordingly, various types of substitution, modification and change will be possible by those skilled in the art within the scope not departing from the technical spirit of the present invention described in the claims, and it is also said that it falls within the scope of the present invention. something to do.

100: semiconductor element 101: substrate
ACT: active regions 105A, 105B: first and second source/drain regions
110: device isolation region 120: buffer insulating layer
BLS: bitline structure BL: bitline
BC: bit line capping pattern WL: word line
150: lower conductive pattern 155: metal-semiconductor compound layer
160: upper conductive pattern 162: barrier layer
164: conductive layer SS: spacer structure
SS': preliminary spacer structure 171: inner spacer
172: sacrificial spacer 173: outer spacer
AG: air gaps 181, 182, 183: first to third insulating patterns
OP1, OP2: first and second openings IH: anti-deposition pattern
CP: gate contact plug

Claims (10)

a substrate including a first impurity region and a second impurity region;
a bit line structure extending in one direction on the substrate and electrically connected to the first impurity region;
a lower conductive pattern disposed on at least one side of the bit line structure and electrically connected to the second impurity region;
an upper conductive pattern disposed on the lower conductive pattern and electrically connected to the lower conductive pattern;
an air gap disposed between the bit line structure and the lower conductive pattern; and
a buried insulating pattern disposed between the upper conductive pattern and the bit line structure on the air gap;
The buried insulating pattern is
a first insulating pattern disposed on sidewalls of the upper conductive pattern and the bit line structure and exposing at least a portion of a lower portion of the upper conductive pattern; and
and a second insulating pattern in contact with the upper conductive pattern exposed by the first insulating pattern and disposed above the air gap;
semiconductor device.
According to claim 1,
The upper conductive pattern may include polycrystalline silicon (Si), titanium (Ti), tantalum (Ta), tungsten (W), ruthenium (Ru), copper (Cu), molybdenum (Mo), platinum (Pt), nickel containing at least one of (Ni), cobalt (Co), aluminum (Al), titanium nitride (TiN), tantalum nitride (TaN), and tungsten nitride (WN);
The second insulating pattern includes at least one of silicon oxide, silicon nitride, silicon oxynitride, silicon carbonitride, and silicon oxycarbonitride.
According to claim 1,
The buried insulating pattern may further include a third insulating pattern disposed on the second insulating pattern to be in contact with the first insulating pattern.
4. The method of claim 3,
An upper surface of the air gap is defined by the second insulating pattern and the third insulating pattern.
According to claim 1,
The second insulating pattern is separated from the first insulating pattern disposed on a sidewall of the bit line structure.
6. The method of claim 5,
A distance between the second insulating pattern and the first insulating pattern disposed on a sidewall of the bit line structure is greater than 0 nm and less than or equal to 2 nm.
According to claim 1,
The second insulating pattern may be in contact with the first insulating pattern disposed on a sidewall of the bit line structure.
According to claim 1,
an inner spacer disposed on a sidewall of the bit line structure; and
Further comprising an outer spacer disposed on the sidewall of the lower conductive pattern,
The air gap is disposed between the inner spacer and the outer spacer.
9. The method of claim 8,
the air gap is defined by the inner spacer, the outer spacer, and the second insulating pattern;
The semiconductor device further comprising: a deposition prevention pattern disposed on surfaces of the inner spacer and the outer spacer defining the air gap.
forming a first impurity region and a second impurity region in the substrate;
forming bit line structures extending in one direction on the substrate and electrically connected to the first impurity region;
forming inner spacers on both sidewalls of each of the bit line structures;
forming a sacrificial spacer on the inner spacer;
forming an outer spacer on the sacrificial spacer;
forming a lower conductive pattern electrically connected to the second impurity region between the adjacent outer spacers;
forming an upper conductive pattern covering the inner spacer, the sacrificial spacer, the outer spacer, and the lower conductive pattern;
forming a first opening in the upper conductive pattern and the bit line structure to expose the sacrificial spacer;
conformally forming a first preliminary insulating pattern on the inner surface of the first opening;
forming a first insulating pattern by partially removing the first preliminary insulating pattern so that at least a portion of a lower portion of the upper conductive pattern, the inner spacer, the sacrificial spacer, and the outer spacer are exposed;
removing the exposed sacrificial spacer to form a second opening;
forming a deposition preventing material on surfaces of the inner spacer, the outer spacer, and the first insulating pattern in the first opening and the second opening;
forming a second insulating pattern on the upper conductive pattern exposed in the first opening;
removing the anti-deposition material;
forming a third insulating pattern in contact with the first insulating pattern and the second insulating pattern;
A method of manufacturing a semiconductor device.

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