TWI752458B - Component dynamic addressing system on a bus - Google Patents

Abstract

Present invention is related to a component dynamic addressing system on a bus comprising multiple components parallel connected thereon. A random number within each component begins to countdown when resetting or energizing. When counting to zero, a cease signal will be generated. One of these components records a unique address. The present invention provides a method for rapidly defining the address of the component which could quickly response for replacing a component or adding a new component.

Description

Dynamic Addressing System for Components on Bus Bars

The present invention relates to an addressing system, in particular to an addressing system and method capable of quickly addressing a controlled unit.

In the current development of electronic sports equipment, there is an electronic trend in clothing accessories. For example, smart clothes are provided with a main control unit, a circuit connecting the main control unit, and interfaces for multiple circuits, which can be worn by ordinary people. For smart clothing, a controlled unit is installed at each interface. For example, a heartbeat sensor is installed on the interface corresponding to the left chest to monitor the heartbeat, and a pulse sensor is installed on the node corresponding to the wrist to monitor the pulse.

When the sensors of the above smart clothing are operating, when the main control unit is powered on or reset, it needs to reassign the output and input addresses (I/O addresses) to the controlled units of each interface before it can be controlled. Since the master control unit needs to poll all the interfaces to assign addresses, and each time it has to wait for the controlled unit to respond, and usually the clock of the master control unit is much higher than that of the controlled unit, so this kind of address assignment This method will generate idle time each time an address is allocated, which makes the overall process of allocating addresses more time-consuming.

Since the existing master control unit is powered on or reset, the method of reassigning the output and input addresses of each controlled unit is time-consuming. For this reason, the present invention achieves the effect of assigning addresses at a faster efficiency by actively sending out an interrupt signal to notify the master control unit to allocate addresses through the countdown of each controlled unit.

In order to achieve the above-mentioned creative purpose, the present invention provides a dynamic addressing system for components on a bus bar, wherein a plurality of components are connected in parallel to a bus bar, and each of the components starts to perform a reciprocal count with a random number stored in the reset or power-on. When the countdown reaches zero, an interrupt signal is generated, so that one of the components records a unique address.

Further, the plurality of components include a main control unit, and more than one controlled unit, each controlled unit is provided with a reciprocal module inside, when the main control unit is powered on or reset, trigger the control unit of each controlled unit. The countdown module counts down with random numbers. When each countdown module counts down to zero, the controlled units generate an interrupt signal one by one, and the master control unit generates a corresponding address according to the received interrupt signal to send out The controlled unit of the interrupt signal receives the address and records it in it.

Further, each of the plurality of components counts down with the random number, and generates the interrupt signal when the countdown reaches zero, and generates a unique address to record and publish it to the outside, so that each of the Components get notified that a specific address has been generated and recorded.

When the present invention is used, it can be applied to circuit control structures such as smart clothing, for example, the circuit control structure of smart clothing. The effect of the present invention lies in that, by means of slow countdown of each controlled unit and then sending an interrupt signal, the idle time of waiting for the master control unit to poll each controlled unit can be avoided, and the process of allocating addresses regardless of the number of controlled units Since the countdown process of each controlled unit is carried out at the same time, regardless of the number of controlled units set in the present invention, the address allocation can be completed at the latest after the countdown of the maximum possible random number, which can achieve faster The allocation address effect.

A: circuit

A1: Interface

10: Main control unit

20: Controlled unit

21: Countdown Module

FIG. 1 is a block schematic diagram of a preferred embodiment of the present invention.

In order to understand the technical features and practical effects of the present invention in detail, and to implement it according to the contents of the description, the preferred embodiments shown in the drawings are further described in detail as follows.

The present invention provides a dynamic addressing system for components on a bus bar. A plurality of components are connected in parallel to a bus bar, and each of the components starts to perform a countdown with a random number stored in the reset or power-on, and generates a countdown when the countdown reaches zero. The interrupt signal causes one of the components to record a unique address.

Please refer to FIG. 1 , which is a first preferred embodiment of the present invention. A master control unit 10 and more than one controlled unit 20 are connected to the bus bar, and a circuit A is connected in series with the master control unit 10 . In this preferred embodiment, the circuit A is a bus bar and is provided with a plurality of interfaces A1, and the circuit A is electrically connected to the master control unit 10 to more than one controlled unit 20, as in this preferred embodiment, the electrical connection is There are two controlled units 20, and the two controlled units 20 are respectively connected to one of the interfaces A1 of the plurality of interfaces A1. Each controlled unit 20 is internally provided with a reciprocal module 21. In this preferred embodiment, each reciprocal The module 21 is an eight-bit module. When the main control unit 10 is powered on or reset (REST), the countdown module 21 of each controlled unit 20 is triggered to count down with random numbers. The random numbers can be different according to requirements. The number of bits, for example, a number from 0 to 255. When each countdown module 21 counts down to zero, each controlled unit 20 sends an interrupt signal to the master unit 10. When the master unit 10 receives the interrupt signal Allocate an input/output address (I/O address) to the controlled unit 20 that issued the interrupt signal, thereby assigning different input/output addresses to all the controlled units 20 respectively. The so-called random number can be the residual value in the memory of each controlled unit 20 when the power is turned on, or the random number generation method when the power is turned on.

In practice, when one of the controlled units 20 completes the countdown to generate the interrupt signal such as a low level or a high level, since both the master control unit 10 and the controlled unit are connected to the bus Therefore, when the main control unit 10 detects the interrupt signal of the bus, it can generate The address is generated, so that the controlled unit 20 within the clock cycle of the interrupt signal (ie, the controlled unit 20 that has completed the countdown at the moment) can receive and record the address. When all the controlled units 20 complete the countdown in sequence, the master control unit 20 can quickly complete the address assignment or definition in this way.

In this first embodiment, after each controlled unit 20 has an address, the master control unit 10 can use the address to communicate with the controlled unit 20 and perform signal transmission work respectively. When the interface A1 of the bus bar is connected to another controlled unit 20 during the power-on process, the master control unit 10 generates another unique address to the controlled unit 20 to complete the effect of hot join .

Further, in the second embodiment of the present invention, each element can have the function of receiving the state and value of other elements of the bus bar, so that when reset or power-on, each element can also be counted down as described above, when one of them When the countdown of a component reaches zero, after interrupting all the components on the bus, it will generate a unique address to record it and release it to the outside world, so that each component on the bus will get the notification specific bit. The address has been generated and recorded; and when the next element completes the countdown, an interrupt signal is generated according to the same method, another unique address is generated that is different from the address that has been issued, and then it is issued and recorded and stored. In this way, each component can have master control capability and can communicate with each other, not only passively controlled.

In the present invention, since the countdown process of each controlled unit 20 is a parallel program, no matter the number of controlled units 20 connected to the circuit A is one or more, the countdown will be completed at the latest at the maximum possible number of random numbers. That is, the allocation of addresses is completed. For example, in this preferred embodiment, no matter how many controlled units 20 are added to the circuit A, the process of allocating different output and input addresses to all the controlled units 20 will be completed when the maximum possible random number 255 is counted down. distribute.

The above descriptions are only preferred embodiments of the present invention, and are not intended to limit the scope of rights claimed by the present invention. All other equivalent changes or modifications that do not depart from the spirit disclosed in the present invention shall be included in the present invention. within the scope of the patent application.

S01-S03: Steps

Claims (4)

A dynamic addressing system for components on a bus bar is provided with a plurality of components connected in parallel to a bus bar, each of the components starts to perform a countdown with a random number stored in the reset or power-on, and generates an interrupt signal when the countdown reaches zero, Make one of these elements record a unique address. According to the dynamic addressing system for components on a busbar as described in claim 1, the plurality of components include a master control unit and more than one controlled unit, each of the controlled units is internally provided with a reciprocal module, when the master control unit When the unit is powered on or reset, trigger the countdown module of each controlled unit to count down with the random number, when each countdown module counts down to zero, each controlled unit generates the interrupt signal one by one, the master unit The corresponding address is generated according to the received interrupt signal, so that each controlled unit that sends out the interrupt signal receives the address and records it in the address. According to the dynamic addressing system for components on the busbar as described in claim 1, each component generates a unique address to record and publish it when the countdown reaches zero, so that each component on the busbar can be Get notification that a specific address has been generated and recorded. The dynamic addressing system for components on a bus bar as claimed in claim 2, wherein a plurality of interfaces are provided on the bus bar, each of the controlled units is connected to one interface of the plurality of interfaces, and the other interface is in a power-on state. A newly added element is connected to the interface, and the main control unit generates another unique address for the newly added element.

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