TWI750913B - Computing device and method - Google Patents

Abstract

A computing device includes an array of memory cells, such as 8-transisor SRAM cells, in which the read bit-lines are isolated from the nodes storing the memory states such that simultaneous read activation of memory cells sharing a respective read bit-line would not upset the memory state of any of the memory cells. The computing device also includes an output interface having capacitors connected to respective read bit-lines and have capacitance that differ, such as by factors of powers of 2, from each other. The output interface is configured to charge or discharge the capacitors from the respective read bit-lines and to permit the capacitors to share charge with each other to generate an analog output signal, in which the signal from each read bit-line is weighted by the capacitance of the capacitor connected to the read bit-line. The computing device can be used to compute, for example, sum of input weighted by multi-bit weights.

Description

Computational elements and methods

Embodiments of the present invention relate to memory, and more particularly, to a computing device and method.

Embodiments of the present invention generally relate to memory arrays used for data processing, such as multiply-accumulate operations. A compute-in-memory or in-memory computing system stores information in a computer's primary random-access memory (RAM) and executes at the memory cell level Computation rather than moving large amounts of data between the main RAM and data storage areas for each computational step. Because stored data can be accessed faster when stored in RAM, in-memory computing allows for instant analysis of data, enabling faster reporting and decision-making in enterprise and machine learning applications. Efforts are ongoing to improve the performance of in-memory computing systems.

Embodiments of the present invention provide a computing device including: a memory array including a plurality of memory cells grouped in columns and rows of memory cells, each of the plurality of memory cells including a memory cell for storing data and With read enable input and output a read port at the output end; a plurality of read enable lines, each connected to the read enable input of the read port of the respective row of memory cells and used to transmit input signals to the read An enabling input; a plurality of data output lines, each connected to the output of the read port of the respective row of the memory cells; and an output interface, including a computing module, the computing module including a plurality of capacitors , each capacitor is connectable to a respective one of the plurality of data output lines and has a capacitance, at least two of the plurality of capacitors have capacitances different from each other, the output interface is configured to permit all The plurality of capacitors share the charges stored thereon.

An embodiment of the present invention provides a computing method, comprising: storing a plurality of multi-bit weights in a memory array having a plurality of memory cells, the plurality of memory cells are organized in columns and rows and each has a memory cell for storing at a node Signal memory cell and read port with read enable input and output for generating an instruction store at the output after an activation signal at the read enable input The signal of the signal at the node in the memory cell and isolating the output from the node, the memory array further has a plurality of read enable lines, each read enable Lines are connected to the read enable inputs of the columns of the plurality of memory cells, wherein storing each of the plurality of multi-bit weights includes storing the multi-bit weights in a shared In the row of memory cells of a respective one of the read enable lines, the memory array further has a plurality of data output lines, each data output line connected to the read of the row of the plurality of memory cells taking the output of the port; applying a plurality of pulse signal sequences to the respective one of the plurality of read enable lines to obtain a plurality of the read ports in the respective rows of memory cells generating an output signal on each of the outputs; combining the output signals on the plurality of outputs of the read port of each of the plurality of rows of memory cells, and by salience The combined output signal weighted by the factor, at least two of the significance factors are different from each other; combining the weighted output signals to generate an analog output; and converting the analog output to a digital output.

An embodiment of the present invention provides a computing method, comprising: storing a plurality of multi-bit weights in a memory array having a plurality of memory cells, the plurality of memory cells are organized in columns and rows and each has a memory cell for storing at a node Signal memory cell and read port with read enable input and output for generating an instruction store at the output after an activation signal at the read enable input the signal of the signal at the node in the memory cell and isolating the output from the node; simultaneously multiplying the input signal by the value of each of the plurality of multi-bit weights Each bit generates a plurality of output signals at the output of the read port; for the plurality of memory cells in each row at the output of the read port summing the output signals; weighting each of the sums of the output signals at the outputs of the read ports of the memory cells in each row by a significance factor to generating individual weighted sums, the significance factors being different from each other; and combining the weighted sums to generate an analog output signal.

100: System/Memory Array

110:8 Transistor Static Random Access Memory Cell

120:6T memory cell

122: p-type metal oxide semiconductor field effect transistor

124: n-type MOS field effect transistor

126: first inverter

132: PMOS

134: NMOS

136: Second inverter

142, 144: write access transistor

150: read port

152: read transistor

154: read access transistor

156, 156[0], 156[1], 156[62], 156[63], 156[i]: read word lines

160: write word line

170, 180: write bit lines

190, 190[0], 190[1], 190[2], 190[3], 190[j]: read bit lines

200: CIM System

210: Input interface

212: digital counter

214: Drive

216: read/write interface

220: Output interface

222: Compensation module

224: Computing Module

226: Sense Amplifier

228: analog output

230: four-bit wide segment

260, 260[ i ]: subset

250: FinFET structure

252: p-doped fin

254:n-doped fin

256: polygate

270: Analog to Digital Converter

272[0], 272[7], 272[ 1 ], SA0, SA1, SA2, SA3, SA4, SA5, SA6, SA7, SA8, SA9, SA10, SA11, SA12, SA13, SA14: Comparator

310: Precharge period

320: RBL sampling period

330: charge sharing period

340: ADC evaluation period

500: Calculate

510, 520, 530, 540, 550: Steps

_Cm [0], _Cm [1], _Cm [2], _Cm [3], _Cm [j]: Calculated capacitors

_Cn [1], _Cn [2], _Cn [3], _Cn [j]: Compensation capacitors

C _u : unit capacitor

i : column

I _cell : cell current

j : index

N0, N1, N2, N3, Q: Node

PCH: Precharge signal

QB: output terminal

S0A, S0B, S1, SH: switching elements

VDD: reference voltage

Aspects of embodiments of the invention are best understood from the following detailed description when read in conjunction with the accompanying drawings. It should be noted that, in accordance with standard practice in the industry, the various features are not drawn to scale. In fact, the dimensions of the various features may be arbitrarily increased or decreased for clarity of discussion.

1 is a diagram illustrating a memory cell having a read bit line (RBL) isolated from a write bit line (WBL) in a portion of an in-memory computing system in accordance with some embodiments Schematic diagram of an example.

2A is a block diagram of an in-memory computing system and a more detailed block diagram of a portion of an in-memory computing system showing a four-bit precision weight computing subsystem, according to some embodiments.

2B is a schematic diagram of an eight-transistor (8T) RAM cell labeled "B" in the system depicted in FIG. 2A, according to some embodiments.

2C is a schematic layout of the eight-transistor (8T) RAM cell of FIG. 2B and labeled "C" in the system depicted in FIG. 2A, according to some embodiments.

3A illustrates a portion of an in-memory computing system in an RBL sampling state, according to some embodiments.

3B illustrates a portion of the in-memory computing system depicted in FIG. 3A in a charge sharing state, according to some embodiments.

3C illustrates the temporal evolution of the levels of various signals in a portion of the in-memory computing system depicted in FIGS. 3A and 3B, according to some embodiments.

4 illustrates an analog/digital conversion scheme for processing voltages on the RBL line, according to some embodiments.

Figure 5 is a flow diagram summarizing a computing method in accordance with some embodiments.

The following disclosure provides many different embodiments or examples for implementing different features of the provided subject matter. Specific examples of components and configurations are described below to simplify embodiments of the invention. Of course, these components and configurations are examples only and are not intended to be limiting. For example, in the following description, the formation of a first feature over or on a second feature may include embodiments in which the first feature and the second feature are formed in direct contact, and may also include additional features that may be formed between the first feature and the second feature. formed between the second features such that the first feature and Embodiments where the second feature may not be in direct contact. Additionally, embodiments of the invention may repeat reference numerals and/or letters in various instances. This repetition is for the purpose of simplicity and clarity, and does not in itself indicate a relationship between the various embodiments and/or configurations discussed.

The specific examples shown in the embodiments of the present invention are related to in-memory computing. An example of an application of in-memory computing is a multiply-accumulate operation, where an input array of numbers is multiplied by a respective element (weighted by the respective element) in another array (eg, a row) of numbers (weights), and the products are multiplied together Add up (accumulate) to produce the output sum. This is mathematically analogous to the dot product (or scalar product) of two vectors, in which the components of the two vectors are multiplied pairwise with each other, and the product of the pair of components is summed. In some artificial intelligence (AI) systems, such as artificial neural networks, arrays of numbers may be weighted by multiple rows of weights. The weighting performed by each row yields an individual output sum. The output array of sums is thus generated from the input array of numbers by the weights in the multi-row matrix.

A common type of integrated circuit memory is a static random access memory (SRAM) device. A typical SRAM memory device has an array of memory cells. In some examples, each memory cell uses six transistors (6T) connected between a higher reference potential and a lower reference potential (eg, ground), so that one of the two storage nodes can be Occupied by information to be stored, wherein complementary information is stored at another storage node. Each bit in the SRAM cell is stored on four of the transistors forming the two cross-coupled inverters. The other two transistors are connected to the memory cell word line (WL) to control memory usage during read and write operations by selectively connecting the cell to its bit line (BL) access to cells. When a word line is enabled, a sense amplifier connected to the bit line senses and outputs the stored information. When dealing with memory cell data, usually Use input/output (I/O) circuitry connected to bit lines. When multiple WLs are activated and the bit cells initially store opposite values, the two bit lines can be lower/high.

In multi-bit applications such as in-memory computing, the stability of 6T bit cells is reduced when multiple word lines are activated simultaneously. When multiple word lines are activated at the same time, the two bit line voltages will be pulled low. This can cause the stability of the bit cell to be disturbed and its state to flip. Additionally, using logic-rule-based SRAM bit cells has significant area overhead due, among other things, to the storage required for intermediate computations. Still additionally, using binary inputs/weights/outputs of known memory configurations may be too simplistic for general usage of in-memory computing, since many problems to be solved by algorithms used in in-memory computing require multi-bit computing steps . Certain embodiments disclosed in the embodiments of the present invention provide multi-bit in-memory computations with direct results without intermediate storage space and without disturbing the stability of each cell.

According to some aspects of the present embodiments, a compute-in-memory (CIM) system includes a memory array, wherein each memory cell has mutually isolated read bit lines (RBLs) and write bits Line (WBL), through which the stored information can be read, and through the write bit line, information can be written to the cells. For example, an 8T SRAM cell, which adds to a 6T SRAM a 2T read port connected to the read word line (RWL) and RBL. Since the RBL of the 8T bit cell is decoupled from the 6T memory cell, multiple RWLs turned on simultaneously do not disturb the storage node voltage. Some disclosed embodiments provide a CIM system with an 8T SRAM cell array including multiple RWLs and RBLs.

According to some aspects of embodiments of the present invention, a CIM system with multi-bit inputs can be implemented with multiple RWL pulses. For example, in some embodiments, the input signal in a multiply-accumulate operation may be implemented by a number of RWL pulses proportional to the number of the input. In some examples, a 4-bit input may be used, although other bit widths are within the scope of embodiments of the present invention. For example, input 0 (0000 ₂ ) is represented by 0 RWL pulses, input 3 ₁₀ (0011 ₂ ) is represented by 3 RWL pulses, input 15 ₁₀ (1111 ₂ ) is represented by 15 RWL pulses, etc.

In some embodiments, the input signal may be multiplied by a multi-bit (eg, four-bit) weight (ie, weight value) configured in the row. The accumulation of multi-bit weighted inputs can be accomplished by charging the common RBL from all cells in the row corresponding to each bit of the multi-bit weight; The sum of the currents for each cell of , and thus the sum of the inputs, each weighted by the binary weight associated with the row. A multiply-accumulate function is thus performed on the RBL, and the RBL voltage is proportional to the bit-by-bit product of the weighted bits with the multi-bit input. Then, charge sharing between RBLs is performed for each row of the multi-bit weights using binary-weighted capacitors (ie, capacitors sized according to the respective salience positions in the multi-bit weights). Therefore, the most significant bit (MSB) of the weight contributes more to the final output than the least significant bit (LSB) of the weight. Charge sharing thus produces analog voltages that reflect the correct significance of each RBL. For example, in the case of a four-bit weighted row, the contribution from the majority of the MSBs to the final voltage will be eight ( ²³ ) times the contribution from the LSB; the contribution from the second MSB will be Four (2 ² ) times; and the contribution from the third MSB (or the second LSB) will be two (2 ¹ ) times the contribution from the LSB.

In some other embodiments, an analog-to-digital converter (ADC) such as a flash ADC is used to convert the voltage on RBL (in a binary weighted charge such as described above) after sharing) into a multi-bit digital output. In some embodiments, for an n- bit output, ²ⁿ -1 comparators are used for the ADC implementation. For example, for the 4-bit output example, 15 comparators are used for the flash ADC implementation. In some embodiments, each comparator has its own input capacitor. These input capacitors can be used as the aforementioned binary weighting capacitors for charge sharing. In some embodiments, the number of input capacitors to which each RBL is connected is related (eg, proportional) to the position value of the output bit associated with the RBL. For example, for a 4-bit output, the RBL for the MSB is connected to 8 (2 ³ ) input capacitors; the RBL for the LSB is connected to 1 (2 ⁰ ) input capacitors. The total capacitance connected to each RBL is thus proportional to the position value corresponding to the RBL. Other bit width outputs are within the scope of embodiments of the present invention.

1-4, an overview of some example embodiments is provided before detailed aspects of these embodiments are explained further below. In some applications such as artificial intelligence, a model system is proposed. A set of inputs (eg, numbers) is supplied to a model system that processes the inputs and produces outputs. The output is compared to the desired output, and if the output is not close enough to the desired output, the model system is adjusted and the process repeated until the output of the model system is close enough to the desired output. For example, to have a machine that can read, the model system can be provided with a collection of fragments of letters. The system takes the segment (input) and processes the segment according to the algorithm, and outputs the letter the system determines received. If the output letter is different from the input letter, the system can be adjusted and tested again until the output matches the input a sufficiently high percentage of times.

For some applications, the model system may be a multiply-accumulate system that processes a set of inputs by multiplying each input by a value (sometimes called a "weight") and summing the products together ( cumulative). The system can contain columns and rows A two-dimensional array of configured components, each of which stores a weight and is capable of receiving an input and producing an output that is the arithmetic product of the input and the stored weight. The model system may have each input that supplies an entire column of parts and adds together the outputs of each row of parts.

For example, the system ( 100 ) depicted in FIG. 1 has multiple rows of 8-transistor (8T) static random access memory (SRAM) cells ( 110 ) (only two cells are shown in FIG. 1 ) . Each cell (110) is connected to an input line RWL (156), and both cells are connected to the same output line RBL (190). Each cell also has a node Q, which is maintained by the SRAM cell at a voltage indicative of the value (weight) stored in the cell. As can be easily understood from the diagram in Figure 1, for each cell, for a binary "1" at input RWL, if Q is "1", cell (110) will draw current from RBL, and if Q A '0' draws no current; for a binary '0' at RWL, regardless of the value at Q, the cell (110) draws no current. If an amount of current drawn above a threshold value (ie, a certain amount of charge drawn) in a given time period is considered an output "1", the output of a single cell (110) is thus determined by Table 1 below given:

It is obvious from this table that the output is the product of the input and the weight.

Furthermore, since cells (110) in the same row share the same RBL, the current on the RBL is the sum of the currents of the cells (110) connected to it. Thus, the signal on each RBL represents the binary product of the input (RWL) and the respective stored weight. sum.

Referring to Figure 2A, in a system that uses multi-bit (four-bit in this example) weights for multiply-accumulate operations, each input (RWL) is provided to multiple (eg, four) cells (110), each The cell stores one bit of the multi-bit weight. RBL is connected to each of the values having the same position (i.e., ^{20, 21, 22, 23,} etc.) cell line (110). With further reference to Figure 3A, RBL is connected to each of a pair of capacitors in combination - for RBL [J] is calculated capacitor C _m [j] and the compensation capacitor C _n [j], each connected in parallel with each other and at each acquisition The signal on the RBL is connected to the respective RBL. The total capacitance of the parallel combination of all RBLs is the same, in this example 9*C _u , where C _u is the unit capacitance. For reasons explained below, the computational capacitors for RBL[0], RBL[1], RBL[2], and RBL[3] have capacitances of 1, 2, 4, and 8 times _Cu , respectively, and RBL[0] The compensation capacitors for , RBL[1], RBL[2], and RBL[3] have _{capacitances of 8, 7, 5, and 1 times Cu} , respectively, so that the total capacitance combined in parallel is 9* _Cu .

Given the capacitance on each RBL (9*C _u in this example), each node N0, node N1, node N2, or node N3 due to the current flowing to the cell (110) in the corresponding row (FIG. 3A ) (assuming the capacitor is precharged) is proportional to the sum of the binary products of the input (RWL) and the respective stored binary weights of the row. And since the total capacitance of each RBL is the same, the proportionality constant of each RBL is the same. At the same time, since _{the capacitance of each of the calculation capacitors Cm} is proportional to the position value of the respective RBL, _{the charge loss from each calculation capacitor Cm} is also proportional to the position value of the RBL.

Next, with further reference to FIG. 3B, the calculation capacitor _{Cm is} disconnected from the compensation capacitor _Cn and connected in parallel with each other, ie, node N0, node Nl, node N2, and node N3 are connected together. The charge stored on the capacitor thus calculated common, and N0, N1, N2 and N3 at a stable voltage level to _{the total} V = Q / C _total, where Q is the _total sum of the charges on all capacitors calculated, and _{the total} C is the total capacitance combined in parallel, ie, 15*C _u in this example. Since the calculation capacitor has a capacitance proportional to the position value of the respective RBL, the _total Q and thus V and thus the voltage drop ΔV due to discharge have a contribution from each RBL proportional to the position value of the RBL. I.e., ^{_{△ V = Σ j 2 J I}} j, where I _j is the j-th current RBL, and the second product of the j-th weight of the respective stored weights RBL binary input (RWL) is proportional to the sum. ΔV is thus proportional to the sum of the products between the input and the respective multi-bit weights stored in cell (110).

Finally, with additional reference to FIG. 4, the voltages at node N0, node N1, node N2, and node N3 are converted into digital outputs by analog/digital converters (ADCs) to obtain voltages corresponding to the input and stored in cell (110). Digital output of the sum of the products between the individual multi-bit weights.

To explain the system and its operation outlined above in more detail, in some embodiments, an in-memory computing system includes a memory array (100) that includes columns and rows (110) of memory cells, and other components. It can be physical or logical columns and rows), other components such as a digital input interface (not shown in An output interface (not shown in FIG. 1 ) that accumulates weighted inputs and outputs a digital representation of the accumulated weighted inputs, as explained below.

In this example, each memory cell (110) includes a 6T memory cell (120) and a read port (150). The 6T memory cell (120) includes: a first inverter (126) which is connected between a higher reference voltage (such as VDD) and a lower reference voltage p-type metal-oxide-semiconductor (MOS) field effect transistors (ie, connected in series with series source-drain current paths) between (such as ground) -oxide-semiconductor field-effect transistor; PMOS) (122) and n-type MOS field-effect transistor (NMOS) (124) are made; the second inverter (136), so The second inverter is made of PMOS (132) and NMOS (134) connected in series between a higher reference voltage (such as VDD) and a lower reference voltage (such as ground); and two write access circuits. Crystals (142, 144), the write access transistors are NMOS in this example. The inverters (126, 136) are inversely coupled, ie, the output (Q, QB) of one (ie, the junction between the source/drain current paths) is coupled to the other Inputs (ie, gates) (QB, Q) of ; write access transistors (142, 144) each have their respective junctions connected to back-coupled inverters (126, 136) and The source/drain current paths between the respective write bit lines (WBL ( 170 ), WBLB ( 180 )) and their gates connected to the write word line (WWL) ( 160 ).

In this example, each read port (150) includes read transistors connected in series with each other and between a lower reference voltage and a data output line (sometimes referred to as a read bit line (RBL)) (152) and read access transistor (154). In this example, the read transistor (152) is an NMOS and its gate is connected to the inverting output (QB) of the 6T memory cell (120); in this example, the read access transistor (154) It is an NMOS and its gate is connected to the read word line (RWL). Other types of transistors and connections can be used. For example, a PMOS can be used for both or either of a read transistor (152) and a read access transistor (154); the gate of the read transistor (152) can be connected to a 6T memory cell ( 120) of the non-inverting output (Q).

In operation, bits are written to memory cells (110), data bits (1 or 0) (eg, voltages corresponding to 1 or 0) are applied to WBL and their inverse value is applied to WBLB. A write signal (eg, 1) is applied to the write access transistors (142, 144) to turn the transistors on, thereby storing the data bit at the output (Q) of the 6T memory cell (120) and Store the reverse value of the data bit at (QB). The write access transistors (142, 144) may then be turned off and maintain the value at Q and the inverted value at QB. To read the stored data bits, write access transistors (142, 144) are turned off (WL=0) and read access transistor (154) is turned on by the read signal applied to RWL (on). The cell current (I _cell ) corresponding to the voltage at QB (or Q) (which in turn represents the stored value (1 or 0) in the 6T memory cell (120)) is thus generated in the RBL and via the output interface ( circuit system sensing in FIG. 1 ).

Since the RBL is isolated from the output Q or output QB of the inverters (126, 136) by the read transistor (152) in each read port (150) (ie, the voltage on or in the RBL and current has substantially no effect at Q or QB), and/or since the write access transistors (142, 144) are off (WL=0), multiple RWLs can be active simultaneously (ie, enable multiple reads The access transistor (154) is turned on) without disturbing the voltage at Q or QB.

According to some embodiments, as depicted in Figure 2A, the CIM system (200) includes a memory array such as the memory array (100) described above, the memory array including 8T memory cells (110). In this example, the memory array ( 100 ) is an array of 64×64 8T memory cells ( 110 ), that is, 64 columns (columns i , i = 0 to 63 ) by 64 rows (row j , j = 0 to 63 ) 63) configured memory cells (110), but any other array including two- and three-dimensional arrays of various sizes may be used. Each 8T memory cell (110) may have the structure described above with reference to Figure 1 and further shown in Figure 2B. Each 8T memory cell (110) can have any suitable physical structure. For example, the transistor of each 8T memory cell (110) may be a field effect transistor (FET). In one example, as shown in FIG. 2C, a FET can be formed in a so-called FinFET structure in which a doped semiconductor forms a ridge or "fin" that acts as the active region of the FET and along which Or "fins" may form source and drain regions. A conductive material such as doped polysilicon ("poly") surrounds the top portion of the fin and acts as a gate. For example, as depicted in Figure 2C, the transistors of memory cell (110) may be along p-doped fins (252) (for PMOS) and n-doped fins (254) (for PMOS) in FinFET structure (250). NMOS) is formed with a poly gate (256) formed across the fins (252, 254).

In some embodiments, the memory cells (110) in the array (100) are of the same configuration. In other embodiments, the memory cells (110) in the array (100) may be different from each other. For example, the size ratios between the transistors (152, 154) in the respective read ports (150) may vary from memory cell to cell, such that the currents generated by the same RWL signal vary.

In this example, the CIM system (200) further includes an input interface (210), which in this example includes an array of digital counters (212) and a corresponding array of drivers (214). In this example, there are 64 4-bit counters (212), one for each column in a 64x64 memory cell array (memory cell array 100); each counter (212) loops output per count A number of pulses corresponding to the number (in this case, a 4-bit binary number) at the counter input. For example, _{an input of 0 (0000 2} ) produces 0 pulses, an input of 3 ₁₀ (0011 ₂ ) produces 3 RWL pulses, _{an input of 15 10} (1111 ₂ ) produces 15 RWL pulses, etc. The driver (214) corresponding to each counter (212) drives the corresponding RBL (190[ j ]( j =0 to 63)) according to the output pulse from the counter. A sequence of RWL pulses is thus applied to the corresponding RWL (156[ i ]( i =0 to 63)), the number of said RWL pulses per count cycle indicating the number of digits at the input of the respective counter (212).

In some embodiments, the CIM system (200) further includes a read/write (RW) interface (216) connected to the memory array (100) for conventional read and write operations associated with the memory array .

In some embodiments, the CIM system (200) also includes an output interface (220), which in some instances includes a compensation module (222) connected to the memory array (100) and a compensation module (222) connected to the memory array (100). ) computing module (224). As described in more detail below, the compensation module is used to form a uniform environment with the calculation module (224), that is, the same total capacitance used for precharging and sampling of the RBL; the calculation module (224) is used to calculate the indication The amount of signal value on the RBL or some combination thereof. For example, as described in more detail below, in some embodiments, a calculation module (224) is used to calculate a weighted sum or weighted average of several RBLs. In some embodiments, this is done via charge sharing between capacitors according to the relative significant position (most significant bit (MSB) to least significant bit (LSB)) of the respective RBL in binary digits Set size. For example, in some embodiments, the relative size of the capacitor is from the MSB to the LSB ^{23: 22: 21: 20.} Thus, the amplitude of the resulting signal corresponds to the sum of the multi-bit input signals weighted by the multi-bit weights.

In some embodiments, the compensation module ( 222 ) includes compensation as depicted in FIG. 2A and in more detail in FIGS. 3A and 3B for the four-bit wide segment ( 230 ) of the CIM system ( 200 ). A set of capacitors _Cn [ j ] (j =0 to 3 for each four-bit wide segment (230)), each associated with a respective RBL(190[ j ]( j =0 to 3)) . As described in more detail below, in some embodiments, compensation capacitors are connected pair-wise in parallel with computational capacitors (described below) during certain stages of the computational process. The compensation capacitors are sized so that the total capacitance presented to the RBL is the same so that the same current in any given RBL will cause the same voltage at the RBL. A pair of switching elements (S0A and S0B), such as any switching transistors, are associated with each compensation capacitor _Cn [ j ], where S0A connects the compensation capacitors _Cn [ j ] to the respective RBL(190[ j ]), And the S0B connects the RBL (190[ j ]) to the computing module (224). Each compensation capacitor _Cn [ j ] is connected via SOA to a respective RBL(190[ j ]) at one end and to a voltage reference, such as ground, at the other end.

The calculation module (224) includes a set of integrators for integrating the current on each RBL. In some embodiments, the integrator includes computational capacitors _Cm [ j ] (j = 0 to 3 for each four-bit wide segment (230)), each computational capacitor _Cm [ j ] and a respective RBL (190[ j ] ( j =0 to 3) are _{associated with corresponding compensation capacitors Cn} [ j ]. In some embodiments, the calculation capacitors are used in combination with the compensation capacitors to provide capacitances to the respective RBLs to establish the indicative RBLs The voltage of the sum of the weighted inputs of . As briefly explained above, in some embodiments, computing capacitors are paired with respective compensation capacitors to present the same capacitance to each RBL during certain steps of the computing process. As explained further below, In some embodiments, the compute capacitors are sized relative to each other to impart significance to the respective RBL. A pair of switching elements (SH and S1), such as any switching transistors, are associated with each compute capacitor _Cm [ j ] , where SH connects computational capacitors _Cm [ j ] to respective RBLs (190[ j ]) via S0B, and S1 connects computational capacitors _Cm [ j ] via SH to analog outputs (228). Each computational capacitor _Cm [ j ] is connected at one end to the analog output (228) via respective SH and S1, and at the other end to a voltage reference, such as ground.

In some embodiments, as depicted in Figures 3A and 3B, a subset of memory cells (110) in each column i (eg, 240 of column[62] or 260[ i ] of column[i]) ( i = 0 to 63), each subset corresponding to RWL[ i ]) can store (eg, by writing from WWL to memory cell (110) multi-bit weights. For example, when using four-bit weights embodiment, four memory cells (110) of each subset (260 [i]) can store four yuan weights _{W i = (W i [3} ] W i [2] W i [1] W i _{[0]) 2,} where W is _{i [j]} represents a writing to the memory cell [110] the bit binary number by the i-th RWL (156 [i]), the binary number by the j-th bit of RBL ( 190[ j ]) reads. For example, weights for W ₀ =0101 ₂ (=5 ₁₀ ) in column[0] (260[0]), stored in subset (260[0]) The bits are W _0[3] = 0, W _0[2] = 1, W _0[1] = 0, and W _0[0] = 1. Similarly, for column [1] (260[1]) in The weight of W ₁ =1011 ₂ (=11 ₁₀ ), the bits stored in the subset (260[1]) are W _1[3] =1, W _1[2] =0, W _1[1] =1 and W _1[0] =1.

Thus, the array ( 100 ) of memory cells ( 110 ) in the example CIM system ( 200 ) depicted in FIG. 2 can store 1024 (64×16) nibble weights arranged in 64 columns and 16 rows.

In some embodiments, _{the capacitance of the computing capacitor Cm} [ j ] is selected according to its respective relative position (ie, index j ) in the computing module. For example, in the embodiment shown in FIGS. 3A and 3B , the capacitance of the j- th calculation capacitor C _m [ j ] corresponding to RBL[ j ^{] is 2 j} C _u , where C _u is the unit capacitance , the unit capacitance can have any value suitable for a particular application. From this, the capacitance of capacitor _Cm [0] is calculated _{as 1*Cu , the capacitance of capacitor Cm} [1] is calculated _{as 2*Cu , the capacitance of capacitor Cm} [2] is _{calculated as 4*Cu} , and the calculation The capacitance of the capacitor C _m [3] is 8*C _u .

In some embodiments, _{the capacitance of the compensation capacitor Cn} [ j ] is selected according to its respective relative position (ie, index j ) in the calculation module. In some embodiments, the capacitance of the _{compensation capacitor Cn} [ j _{] is chosen such that Cn} [ j ]+ _Cm [ j ]=constant, that is, when each pair of compensation and calculation capacitors are connected in parallel, the RBL exhibits The same capacitance (constant capacitance), and _Cn [ j ] is the difference between the fixed total capacitance and the individually calculated capacitance _Cm [ j]. For example, in the embodiment depicted in Figures 3A and 3B in which the total capacitance presented to each RBL is chosen to be 9* _Cu , the jth compensation capacitor _Cn [ corresponding to RBL[ j] The capacitance of j ] is 9*C _u - C _m [ j ]. Thus, _{the capacitance of compensation capacitor Cn} [0] is 8* _Cu , the capacitance of compensation capacitor _Cn [1] is 7* _Cu , the capacitance of compensation capacitor _Cn [2] is 5* _Cu , and the compensation The capacitance of the capacitor C _n [3] is 1*C _u .

In some embodiments, the output interface (220) further includes a sense amplifier (226) for each RBL (190) for enhancing the analog signal from the RBL (190). In some embodiments, the output interface (220) further includes analogs/bits for each subset of RBLs associated with a row of multi-bit weights stored in the respective subsets (260) of the memory cells (110) Converter (ADC) (270). In some embodiments, as shown in FIG. 4, flash ADCs may be used, each with several voltage comparators (272[ l ], l =0 to ^{2n -1} , where n weight of a multi-bit binary number is the number of bits), wherein the comparator 2 ^j for the j-th RBL (190 [j]). For example, in an application using four-bit weights, as shown in Figure 4, a 15-comparator flash ADC (272[ l ], l =0 to 14) may be used. Connect the signal from RBL[0] to one comparator SA7 (272[7] in this example); in this example, connect the signal from RBL[1] to two comparators SA6 and SA8 (272[6] and 272[8]); in this example, the signal from RBL[2] is connected to four comparators SA5, SA9, SA4, and SA10 (272[5], 272[9], 272[4], and 272[10]); and in this example, the signal from RBL[3] is connected to eight comparators SA3, comparator SA11, comparator SA2, comparator SA12, Comparator SA1, comparator SA13, comparator SA0, and comparator SA14 (272[3], 272[11], 272[2], 272[12], 272[1], 272[13], 272[0] and 272[14]).

In some embodiments, the comparators ( 272 ) each include input capacitors, and those input capacitors can be used as a calculation capacitor _Cm . For example, in the embodiment depicted in FIG. 4, assuming that the input capacitor of each comparator (272) has a unit capacitance _Cu , the input capacitor of comparator SA7 can then be used as the calculation capacitor _Cm [0] ; the input capacitors of SA6 and SA8 can be used (eg, connected in parallel) as _Cm [1]; the input capacitors of SA5, SA9, SA4 and SA10 can be used (eg, connected in parallel) as _Cm [2]; and SA3, SA11, The input capacitors of SA2, SA12, SA1, SA13, SA0, and SA14 can be used (eg, connected in parallel) as _Cm [3]. As mentioned above, the total capacitance connected to each RBL is thus proportional to the position value corresponding to the RBL. A distribution pattern (that is, a distribution pattern with a subset of connections to each RBL (190[j ]) located away from each other) (such as that depicted in FIG. 4) connects each RBL (190) to a comparator (272 ) distribution pattern) minimizes the voltage dependence of the input capacitor used as the unit capacitor (C _{u ).}

In some embodiments, in-memory computations such as weighted sum computations may be performed using the CIM system disclosed in embodiments of the present invention. More specifically, the sum of the inputs (eg, 64 inputs) X _i may each be weighted by a multi-bit (eg, four-bit) weight ( W _i ) _k , and the weighted inputs Xi ( Wi ) _k may be computed together. and to generate an output S _k, S _k is the weighted sum of the output of multibit heavy weight of the k-th row. That _{is, S k = Σ i X i} (W i) k.

As described above, in some embodiments, the digital input to the CIM system ( 200 ) may be represented by or converted to a pulse sequence, where the number of pulses per count cycle at each RWL indicates the amplitude of the input. Furthermore, since the RBL is decoupled from the 6T memory cell (120), the RWL can be activated simultaneously, and the RWL can be activated simultaneously. Further, as described above, in accordance with some embodiments, as shown in FIG. 3A and 3B depicted, such as a four yuan weights _{W i = (W i [3} ] W i [2] W i [1] W i [0 _] ) ₂ may be stored in subset (260[ i ]) of column (190[ i]) of memory cell (110). In some embodiments, as outlined in FIG. 5, the computation (500) involving applying multi-bit weights to respective inputs may be performed as follows: First (510), the multi-bit weights (eg, W _i =( W _{i [3]} W _{i [2]} W _{i [1]} W _{i [0]} ) ₂ ) The set is stored in an array of memory cells, each memory cell having a memory cell ( such as a 6T SRAM cell) and a read port with a read enable input line (such as RWL) and an output line (such as RBL) for the read enable signal at the output after the read enable signal Signals indicative of signals stored at nodes in the memory cells are generated and output lines are isolated from the nodes.

Then (520), each set of pulse signals is applied to the read enable input of the set of memory cells storing the respective multi-bit weights to generate a set of signals at the output lines of the respective memory cells, each pulse signal indicating The respective input number, output signal set indicates the operation (eg, product) performed on the pulse signal by the stored multi-bit weights.

Then (530), the combined read port output (eg, combined current) from the read output lines of the memory cells sharing each output line is measured (eg, by RBL sampling, described in detail below) and given to significant factor corresponding to the significant properties (i.e., position values) to an output line associated weighting bits (e.g., W _i [j] of j) a. For example, the MSB of a four-bit weight has a position value of 8 (ie, 2 ³ ); the significance factor may be the position value itself or some multiple of the position value. As described above, a significance factor can be given for each RBL by using the relative size of the corresponding calculation capacitors.

Then (step 540), the combined read port outputs from the respective read output lines are combined proportionally to the respective significance factors (eg, by charge sharing, as described in detail below) to generate a computed output signal.

Then (550), the calculated output signal is converted to a digital output (eg, by a 15-comparator analog/digital converter (ADC)).

As shown in Figures 3A and 3B and 3C, in some embodiments, the analog signal on the RBL may be measured and used to calculate the weighted sum of the inputs as follows: First, during the precharge period (310), Precharge signal PCH is applied to each RBL[ j ] and _{parallel combination of calculation capacitor Cm} [ j ] and compensation capacitor _Cn [ j ], i.e., with S0A, S0B, and SH conducting (open) and S1 not conducting (disconnect). Since each combination has the same capacitance (ie, 9×C _u ), all combinations are charged to the same total charge, and the voltages at all four nodes N3, N2, N1, and N0 rise to the same bit quasi- V _PCH . Then, during the RBL sampling period (320) (see Figures 3A and 3C), the PCH is turned off, and the input pulse train is applied to the respective RWL, and for each memory cell having a "1" stored therein (110) , each pulse causes the cell current I RWL respective _cell, the cell current I _cell RBL is discharged by a fixed amount by the duration and the amplitude I of each _cell of the input pulse determined. All memory cells that share the same RBL contribute to the cellular current, and thus the total discharge, to the point where all of the memory cells store "1" second. The voltage at each node N0, node Nl, node N2, and node N3 thus drops by an amount proportional to the bit-by-bit product of weighted bits with multi-bit inputs, determined by the total discharge of the respective RBL.

Then, during the charge sharing period (330) (see FIGS. 3B and 3C ), S0A and S0B are turned off, SH remains turned on, and S1 is turned on. Therefore, the compensation capacitor _Cn [ j ] ( j =0 to 3) is switched off, and the calculation capacitor _Cm [ j ] ( j =0 to 3) is connected in parallel between ground and the output (228). Node N0, Node N1, Node N2, and Node N3 are also connected together and connected to the output (228). Voltage V _out (i.e., calculated across the capacitor C _m [j] of the voltage) at the output (228) is thus stored in the compensation capacitor C _m [j] divided by the total charge of the compensation capacitor C _m [j] The sum of the capacitances.

其中Q[j]為儲存於第j個計算電容器C_m[j]中的電荷。

where Q [ j ] is the charge stored in the jth computing capacitor _Cm [ j].

Since C _m [j] a capacitance of 2 ^j C _u / 9C _u = total capacitance (9C _u) on the j-th RBL 2 ^j / 9, so each computing capacitor C _m [j] from the pre-charge step absorbent ^{2 j} /9 of the total charge stored on each RBL. _Cm [3] thus has, at the end of the precharge period _{, eight times as much charge as the calculation capacitor Cm} [0], four times as much as the calculation capacitor _{Cm [2], and the calculation capacitor Cm} [1] double. For the same reason, _{the charge lost by capacitor Cm} [3] for the same input and same weighted bit value is calculated to be eight times the loss of _Cm [0] and four times the loss of _{Cm[2] during the RBL sampling period} and twice the [1] loss of the _{C m loss.} Thus, at the end of the charge sharing period, C _m [3] of the total charge Σ _j Q _[j] contribution C _m [0] contributed eight, four times the C _m [2] and the contribution of C twice the contribution of _m[1]. The voltage V _out or voltage drop Δ V = V _PCH - V _out thus represents the binary weighted sum, where each RBL is assigned a weight proportional to the RBL's significant position in the binary weight, W _i =( W _{i [ 3] W i [2] W} i [1] W i [0]) 2, or, more _{generally, W i = (... W i} [j] ... W i [2] W i [1 _] W _{i [0]} ) ₂ . For example, in the embodiment depicted in Figures 3A and 3B, the voltages at the analog output (228) and thus at node N3, node N2, node N1, and node N0 after charge sharing are 8/15 of RCL[3] (most significant bit (MSB)), 4/15 of RCL[2], 2/15 of RCL[1], and 1/15 of RCL[0] (least significant bit ( LSB)).

Then, during the ADC evaluation period (340) (SAE signal "on" so that the ADC (270) converts the voltages on the RBL (190) (ie, at N3, N2, N1, and N0) after the above-described charge sharing are digital output signal, in this example, corresponds to a four digit binary number of voltage (0000 _{2-1111 2)} relates to a multibit input and heavy weight multiply-and-accumulate multibit memory thereby completing the calculation of the body.

Since the RBLs are decoupled from the respective 6T memory cells, multiple RWLs can be activated simultaneously to apply the weights stored in the memory cells (110) without disturbing the storage state of any of the memory cells. Computational speed is thereby increased compared to the case where the RWLs have to be applied one at a time.

Thus, according to some disclosed embodiments, a computing element includes a memory array having a set of memory cells grouped in columns and rows of memory cells, each of the memory cells having a memory to store data A body unit and a read port with a read enable input and an output; read enable lines, each read enable line is connected to the read enable input of the read port of the respective row of the memory cells and used to transmit the input signal to the read enabling input end; data output lines, each data output line is connected to the output end of the read port of the respective row of the memory cell; the output interface has a computing module, so The computing module includes a set of capacitors, each capacitor can be connected to a respective one of the data output lines and has a capacitance, at least two of the capacitors have capacitances that are different from each other, and the output interface is configured to allow the capacitors to be stored in common in charge on it.

In a related embodiment, the computing element further includes an input interface connected to the plurality of read enable lines and configured to be in at least a subset of the plurality of read enable lines Multiple pulses are generated on each of the .

In a related embodiment, the input interface includes a plurality of counters, each counter having a binary data input for receiving digital input data and having a data input connected to a respective one of the plurality of read enable lines Output, the counter is configured to generate a number of pulses indicative of the value of the digital input data.

In a related embodiment, the output interface further includes a compensation module, the compensation module includes a plurality of capacitors, and each capacitor can be connected to a respective one of the plurality of data output lines and has a capacitance, so The output interface is configurable to connect, for each of the plurality of data output lines, respective capacitors in the computing module to respective capacitors in the compensation module to form a capacitance having a total capacitance A capacitive combination, the total capacitance of the capacitive combination is the same for at least a subset of the plurality of data output lines.

In a related embodiment, the computing element further includes a digital read connected to the memory array for reading data from and writing data to the plurality of memory cells /Write (RW) interface.

In a related embodiment, each of the plurality of memory cells is an eight-transistor SRAM cell having a six-transistor static random access memory (SRAM) memory cell, the six-transistor SRAM memory cell has two inverters and two access transistors coupled oppositely to each other, each switchably connecting a respective junction between the two inverters to a respective data line, to be written Data into the six-transistor SRAM memory cell is transmitted via the respective data lines, the read port has a first transistor and a second transistor, each transistor having a control electrode and a primary current path, The control electrode is used to control the current flowing through the main current path, the main current path is connected in series between the data output line and a voltage reference point, the one of the first transistors The control electrode is connected to the The read enable line of a memory cell, and the control electrode of one of the first transistors is connected to a junction between the two inverters.

In a related embodiment, the output interface further includes an analog/digital converter (ADC) having a plurality of analog inputs and an input capacitor for each of the plurality of analog inputs , wherein each of the plurality of capacitors in the computing module at least partially comprises a respective one of the input capacitors or a respective subset of the input capacitors, a respective one of the input capacitors The respective one or each of the respective subsets of the input capacitors may be connected to respective data output lines.

In a related embodiment, the plurality of input capacitors of the ADC are configured in a linear array, wherein at least a subset of the plurality of input capacitors connectable to one of the plurality of data output lines includes at least an input capacitor a first subset of and a second subset of input capacitors, each subset connectable to a respective one of the plurality of data output lines, at least two inputs of the first subset of the input capacitors The capacitors are separated by at least one input capacitor in the second subset.

In a related embodiment, the output interface is configured to: connect each data output line to one of the plurality of capacitors in the compensation module and the computing module during a first period of time a parallel combination of a corresponding one of the plurality of capacitors in a group; and during a second period after the first period, dividing each capacitor in the calculation module from a capacitor in the compensation module Respective capacitors are disconnected from respective data output lines, and the plurality of capacitors in the computing module are connected in parallel.

In a related embodiment, the computing element further includes an input interface connected to the plurality of read enable lines and configured to read the plurality of read enable lines during the first period of time Generate multiple on each of at least a subset of enable lines pulse.

In a related embodiment, the plurality of memory cells are identical to each other, and at least two of the plurality of capacitors in the computing module have capacitances that differ from each other by a factor of 2 ⁿ , where n is an integer.

According to some disclosed embodiments, a computing method includes storing a plurality of multi-bit weights in a memory array having memory cells organized in columns and rows and each having a signal for storing a signal at a node A memory cell and a read port having a read enable input and an output, the read port is used to generate an indication at the output at the node stored in the memory cell after an activation signal at the read enable input The output terminal is isolated from the node, the memory array further has a plurality of read enable lines, each read enable line is connected to the read enable input terminal of the row of memory cells, which stores a plurality of read enable lines. Each of the multi-bit weights includes storing the multi-bit weights in a row of memory cells that share a respective one of the read enable lines, the memory array further has data output lines, each data output line connecting to the outputs of the read ports of the rows of cells; applying a sequence of pulse signals to the respective read enable lines to generate on each of the multiple outputs of the read ports of the respective columns of the cells output signal; combining the output signals on the multiple outputs of the read ports of each of the multiple rows of the memory cell, and weighting the combined output signals by a significance factor, at least two of the significance factors are different from each other; combine the weighted output signals to generate an analog output; and convert the analog output to a digital output.

In a related embodiment, storing the plurality of multi-bit weights in the memory array includes storing all bits of the same significance in the plurality of multi-bit weights in the memory cells of the plurality of memory cells and weighting the combined output signal by the significance factor comprises according to all data stored in the lines connected to the respective data output lines Each of the combined output signals is weighted by the significance of the all bits in the row of the plurality of memory cells.

In a related embodiment, weighting the combined output signal by the significance factor includes weighting the combined output signal by a factor of 2 ^j , where j represents the significance of the weighted bits stored in the respective rows sex position, where j = 0 represents the least significant bit.

In a related embodiment, weighting the combined output signal by the significance factor includes charging or discharging a capacitor from a respective one of the plurality of data output lines, the capacitor having a value stored in the significant capacitance of the all bits in the row of the plurality of memory cells connected to respective data output lines.

In a related embodiment, weighting the combined output signal by the significance factor includes charging or discharging a capacitor ^{having capacitance 2j} _Cu , where j represents the weighted bits stored in respective rows where j = 0 represents the least significant bit and _Cu is the unit capacitance.

In a related embodiment, combining the weighted output signals to generate the analog output includes sharing charge among the capacitors.

In a related embodiment, charging or discharging the capacitor from the respective one of the plurality of data output lines includes charging or discharging the capacitor while simultaneously from the plurality of data output line pairs Additional capacitors are charged or discharged, the capacitors charged or discharged by each of the plurality of data output lines have a total capacitance that for the owner of the plurality of data output lines same.

According to some disclosed embodiments, a computing method includes: converting a multi-bit Weights are stored in a memory array having a plurality of memory cells organized in columns and rows and each having a memory cell for storing a signal at a node and a read enable input and output access port, the read port is used to generate at the output a signal indicative of the signal at the node stored in the memory cell after reading the activation signal at the enable input, and isolate the output from the node; make the input The signal is simultaneously multiplied by each bit of each of the multi-bit weights to produce an output signal at the output of each of the read ports; the output of the read port for the memory cells in each row sum the output signals at ; weight each of the sums of the output signals at the outputs of the read ports of the memory cells in each row by a different significance factor to produce an individual weighted sum; and combine the weights summed to produce an analog output signal.

In a related embodiment, simultaneously multiplying the input signal by each bit of each of the plurality of multi-bit weights includes reading via the read of the row connected to the plurality of memory cells Take the read enable line of the enable input end to apply the input signal to each column of the plurality of memory cells simultaneously; to the output end of the read port of the plurality of memory cells in each row Summing the plurality of output signals at includes combining the currents at the outputs of the read ports of the plurality of memory cells in respective data output lines; weighting in each line by a significance factor Each of the sums of the plurality of output signals at the outputs of the read ports of the plurality of memory cells includes charging or discharging a capacitor with capacitance from a respective data output line , the capacitances of the capacitors are different from each other; and combining the weighted sums includes sharing charge among the capacitors.

The foregoing summarizes the features of several embodiments so that those skilled in the art may better understand aspects of the embodiments of the present invention. Those of ordinary skill in the art will appreciate that the embodiments of the invention may be readily employed as designs or modifications for further A basis for other processes and structures that perform the same purposes and/or achieve the same advantages of the embodiments introduced herein. Those skilled in the art should also realize that such equivalent constructions do not depart from the spirit and scope of the embodiments of the present invention, and those skilled in the art can make changes without departing from the spirit and scope of the embodiments of the present invention. Variations, substitutions and alterations are made herein under circumstances.

500: Calculate

510, 520, 530, 540, 550: Steps

Claims (10)

A computing element, comprising: a memory array including a plurality of memory cells grouped in columns and rows of memory cells, each of the plurality of memory cells comprising a memory cell for storing data and having a read enable input and output read ports; a plurality of read enable lines, each connected to the read enable input of the read ports of the respective rows of memory cells and used to transmit input signals to all the read enable input end; a plurality of data output lines, each connected to the output end of the read port of the respective row of the memory cells; and an output interface, including a computing module, the computing module includes a plurality of capacitors, each capacitor connectable to a respective one of the plurality of data output lines and having a capacitance, at least two of the plurality of capacitors having different capacitances from each other, the output interface configured to allow the plurality of capacitors to share the charges stored thereon. The computing element of claim 1 , further comprising an input interface connected to the plurality of read enable lines and configured to have an input interface in at least a subset of the plurality of read enable lines Multiple pulses are generated on each. The computing device of claim 1, wherein the output interface further comprises a compensation module, the compensation module comprising a plurality of capacitors, each capacitor connectable to a respective one of the plurality of data output lines and having capacitors, the output interface is configurable to connect, for each of the plurality of data output lines, respective capacitors in the computing module to respective capacitors in the compensation module to form A capacitive combination having a total capacitance that is the same for at least a subset of the plurality of data output lines. The computing element of claim 1, further comprising a digital read/write device connected to the memory array for reading data from and writing the data to the plurality of memory cells Write (RW) interface. The computing element of claim 1, wherein each of the plurality of memory cells is an eight-transistor SRAM cell having a six-transistor static random access memory (SRAM) memory cell, the six-transistor SRAM cell A crystalline SRAM memory cell has two inverters and two access transistors coupled inversely to each other, each switchably connecting a respective junction between the two inverters to a respective a data line through which data to be written to the six-transistor SRAM memory cell is transmitted via the respective data line, the read port having a first transistor and a second transistor, each transistor having a control electrode and a main current path, the control electrode is used to control the current flowing through the main current path, the main current path is connected in series between the data output line and the voltage reference point, the first transistor in the The control electrode of one is connected to the read enable line for the memory cell, and the control electrode of one of the first transistors is connected to one of the two inverters interface between. The computing element of claim 1, wherein the output interface further comprises an analog/digital converter (ADC) having a plurality of analog inputs and for each of the plurality of analog inputs The input capacitors of one, wherein each of the plurality of capacitors in the computing module comprises at least in part a respective one of the input capacitors or a respective subset of the input capacitors, whereby The respective one of the input capacitors or each of the respective subsets of the input capacitors may be connected to respective data output lines. A computing method comprising: storing a plurality of multi-bit weights in a memory array having a plurality of memory cells, so that The plurality of memory cells are organized in columns and rows and each has a memory cell for storing a signal at a node and a read port with read enable input and output, the read port for The activation signal at the enable input is followed by generating a signal at the output indicative of the signal at the node stored in the memory cell and isolating the output from the node, so The memory array further has a plurality of read enable lines, each read enable line is connected to the read enable input terminals of the rows of the plurality of memory cells, wherein the plurality of multi-bit weights are stored each of which includes storing the multi-bit weights in a row of memory cells that share a respective one of the plurality of read enable lines, the memory array further having a plurality of data output lines, each data output line is connected to the output of the read port of the row of the plurality of memory cells; applying a plurality of pulse signal sequences to the respective ones of the plurality of read enable lines one to generate output signals on each of the multiple outputs of the read ports in respective rows of memory cells; combining the output signals on the plurality of outputs and weighting the combined output signals by a significance factor, at least two of the significance factors being different from each other; combining the weighted output signals to generate an analog output and converting the analog output to a digital output, wherein storing the plurality of multi-bit weights in the memory array comprises storing all bits of the same significance in the plurality of multi-bit weights in in the rows of the plurality of memory cells, wherein weighting the combined output signal by the significance factor includes charging or discharging a capacitor from a respective one of the plurality of data output lines, the Capacitors have memories stored in accordance with the plurality of outputs connected to respective data output lines the significant capacitance of the all bits in the row of cells. The computing method of claim 7, wherein weighting the combined output signal by the significance factor comprises according to data stored in the rows of the plurality of memory cells connected to respective data output lines The significance of the all bits weights each of the combined output signals. A computing method comprising: storing a plurality of multi-bit weights in a memory array having a plurality of memory cells organized in columns and rows and each having a memory cell for storing a signal at a node and a read port having a read enable input and an output for generating an indication at the output to be stored in the memory following an activation signal at the read enable input the signal of the signal at the node in the cell and isolating the output from the node; simultaneously multiplying the input signal by each bit of each of the plurality of multi-bit weights to generating a plurality of output signals at the output of the read port; evaluating the plurality of output signals at the output of the read port for the plurality of memory cells in each row sum; weight each of the sums of the plurality of output signals at the outputs of the read ports of the plurality of memory cells in each row by a significance factor to produce a respective weighted sum , the saliency factors are different from each other; and combining the weighted sums to generate an analog output signal, wherein the outputs of the read ports of the plurality of memory cells in each row are weighted by the saliency factors of the sum of the plurality of output signals at the terminal Each includes charging or discharging capacitors having capacitances from respective data output lines, the capacitances of the capacitors being different from each other. The computing method of claim 9, wherein simultaneously multiplying the input signal by each bit of each of the plurality of multi-bit weights comprises via all memory cells connected to the plurality of memory cells The read enable line of the read enable input of the row applies the input signal to each row of the plurality of memory cells simultaneously; the read of the plurality of memory cells in each row summing the plurality of output signals at the outputs of the ports includes combining currents at the outputs of the read ports of the plurality of memory cells in respective data output lines; and combining all The weighted sum includes sharing charge among the capacitors.

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