TWI749906B - Power system and pulse width modulation method using the same - Google Patents

Abstract

A power system is disclosed. The power system comprises a pulse width modulation device which outputs first to fourth driving signals. The pulse width modulation comprises a control unit, and a pulse width modulation unit. The control unit generates a control signal. The pulse width modulation unit divides the control signal into a positive cycle signal and a negative cycle signal, and clamps a portion of the positive cycle signal greater than or equal to a maximum voltage threshold to the maximum voltage threshold to form a first comparison waveform, and clamping the positive cycle signal to a reference voltage level to form a second comparison waveform. The pulse width modulation unit adds up a low voltage threshold and the first comparison waveform within a first time interval to form a first oblique signal, and adds up the low voltage threshold and the second comparison waveform within the first time interval to form a first pulse width signal. The pulse width modulation unit adjusts the first driving signal and the third driving signal according to the first oblique signal, and adjusts the second driving signal and the fourth driving signal according to the first pulse width signal.

Description

Power supply system and its applicable pulse width modulation method

This case is a power system, especially a power system that can compensate for the output voltage distortion caused by the minimum pulse width limitation and its applicable pulse width modulation method

In various industrial applications, power systems are often used for voltage conversion. The power supply system includes a plurality of transistors, and the power supply system converts the received voltage for use by the load by switching on or off the plurality of transistors respectively.

In addition, the power system further includes a control unit and a pulse width modulation unit. The control unit outputs a control signal so that the output voltage of the power system can be adjusted according to the control signal. The pulse width modulation unit generates a plurality of pulse width signals according to the control signal. , So that a plurality of transistors are switched on and off according to the corresponding pulse width signal.

Each transistor in the power system usually contains a parasitic diode, and the diode has the characteristic of a reverse recovery current (reverse recovery current), that is, the parasitic diode will have a reverse current for a certain period of time. Switching the corresponding transistor to conduction during the reverse recovery current will instantly cut off the reverse current on the parasitic diode. This sudden current cutoff will cause a surge voltage on the circuit, which in turn will cause Damage to the circuit components of the power supply system. In order to avoid the above situation, At present, most power systems add minimum pulse width limitation technology to the realization of the switch to ensure that the reverse recovery current on the parasitic diode of the transistor can be completely ended.

However, due to the additional minimum pulse width limitation technology of the power system, during the period of the minimum pulse width limitation, the output voltage output by the power system will be clamped according to the minimum pulse width limitation and cannot accurately follow the control signal output by the control unit. To adjust, the output power output by the power system has distortion problems during the period of the minimum pulse width limitation.

Therefore, it is necessary to develop an improved power supply system and its applicable pulse width modulation method to solve the problems faced by the above-mentioned conventional technologies.

The purpose of this case is to provide a power system and its applicable pulse width modulation method, so as to solve the problem that the output voltage of the power system cannot be accurately controlled within the period of the minimum pulse width limitation when the traditional power system uses the minimum pulse width limitation technology. The control signal output by the unit is adjusted, which leads to the problem of distortion of the output electric energy.

To achieve the above objective, one of the broader implementation aspects of this case is a power supply system, including a power conversion device and a pulse width modulation device, wherein the pulse width modulation device outputs first to fourth driving signals to operate the power conversion device, And the pulse width modulation device includes: a control unit for generating a control signal, wherein the control signal is a periodic signal; and a pulse width modulation unit, which determines the critical time point of the control signal according to the reference voltage level, and according to the critical time point The control signal is divided into a positive period signal and a negative period signal. The control signal is close to the reference voltage at the critical time point and is within the error range; the pulse width modulation unit clamps the part of the positive period signal greater than or equal to the maximum voltage threshold at the maximum The voltage threshold is used to form the first comparison waveform, and the pulse width modulation unit also clamps the positive period signal at the reference voltage level as the second ratio Compare the waveforms, and the pulse width modulation unit samples the first and second comparison waveforms in the first time interval from the critical time point to the first predetermined time; wherein the pulse width modulation unit superimposes the low voltage threshold and falls into the first time interval A first comparison waveform in a time interval to form a first ramp signal; wherein the pulse width modulation unit superimposes the low voltage threshold and a second comparison waveform falling in the first time interval to form the first pulse width signal; wherein In the first time interval, the pulse width modulation unit compares the first ramp signal with the first triangle wave to adjust the first and third driving signals, and the pulse width modulation unit compares the first pulse width signal with the second triangle wave to adjust The second and fourth driving signals, wherein the phase difference between the first and second triangular waves is 180 degrees.

To achieve the above purpose, another broad implementation aspect of this case is a pulse width modulation method, which includes: receiving a control signal, wherein the control signal is a periodic signal; determining the critical time point of the control signal according to the reference voltage level; The critical time point divides the control signal into a positive cycle signal and a negative cycle signal. The control signal is close to the reference voltage at the critical time point and is within the error range; clamps the part of the positive cycle signal greater than or equal to the maximum voltage threshold at the maximum voltage threshold Value to form the first comparison waveform; clamp the positive periodic signal at the reference voltage level as the second comparison waveform; sample the first and second comparison waveforms in the first time interval from the critical time point to the first predetermined time ; Superimpose the low voltage threshold value and the first comparison waveform falling within the first time interval to form a first ramp signal; superimpose the low voltage threshold value and the second comparison waveform falling within the first time interval to form the first pulse Wide signal; compare the first ramp signal with the first triangle wave in the first time interval to adjust the first and third driving signals; and compare the first pulse width signal with the second pulse width signal in the first time interval The triangular wave is used to adjust the second and fourth driving signals, wherein the phase difference between the first and second triangular waves is 180 degrees.

1: Power system

Vout: output voltage

2: Pulse width modulation device

3: Power conversion device

P1~P4: the first drive signal to the fourth drive signal

30, 30’: Switch module

Q1~Q4, Q1a~Q4a: the first transistor to the fourth transistor

Vdc: DC voltage source

T, T1: output node

D1~D4, D1a~D4a: parasitic diode

D10: The first diode

D20: The second diode

20: control unit

21: Pulse width modulation unit

Sc, Sc’: control signal

Sc+: positive periodic signal

Sc-: negative cycle signal

t0, t1, t2, t1’, t2: time

Vmin: Low voltage threshold

Vmax: Maximum voltage threshold

ePWM1: The first triangle wave

ePWM2: The second triangle wave

S1a: The first ramp signal

S2a: The first pulse width signal

S3a: Second pulse width signal

S4a: Second ramp signal

S1: The first comparison waveform

S2: Second comparison waveform

S3: Third comparison waveform

S4: Fourth comparison waveform

S1’: The first reference waveform

S2’: Second reference waveform

S3’: Third reference waveform

S4’: Fourth reference waveform

△T1: The first time interval

△T2: The second time interval

Vref: Reference voltage level

Figure 1A is a schematic block diagram of the circuit of the power supply system 1 of the preferred embodiment of the present invention; Figure 1B is a schematic diagram of the circuit structure of the first preferred embodiment of the power conversion device 3 shown in Figure 1; Fig. 1C is a schematic diagram of the circuit structure of the second preferred embodiment of the power conversion device 3 shown in Fig. 1; Fig. 2 is a signal timing diagram explaining the operation of the pulse width modulation unit 21 shown in Fig. 1A Fig. 3A is a signal timing diagram explaining the pulse width modulation unit 21 generating the first ramp signal S1a and the first reference waveform S1'; Fig. 3B is explaining the pulse width modulation unit 21 generating the first pulse width signal S2a and The signal timing diagram of the second reference waveform S2'; Figure 4A shows the first triangular wave ePWM1, the second triangular wave ePWM2, the first ramp signal S1a, the first pulse width signal S2a, and the first drive during the first time interval △T1 The signal timing diagram of the signal P1 to the fourth driving signal P4; Figure 4B shows the first triangular wave ePWM1, the second triangular wave ePWM2, the first reference waveform S1', the second reference waveform S2', and the first time interval △T1. A signal timing diagram of the driving signal P1 to the fourth driving signal P4; Fig. 5A is a signal timing diagram explaining the pulse width modulation unit 21 generating the second pulse width signal S3a and the third reference waveform S3'; Fig. 5B is an explanation The pulse width modulation unit 21 generates a signal timing diagram of the second ramp signal S4a and the fourth reference waveform S4'; Figure 6A shows the first triangular wave ePWM1, the second triangular wave ePWM2, and the second pulse width signal during the second time interval S3a, the second ramp signal S4a, the signal timing diagram of the first drive signal P1 to the fourth drive signal P4; Figure 6B shows the first triangular wave ePWM1, the second triangular wave ePWM2, and the third reference waveform S3 in the second time interval ', the fourth reference waveform S4', the signal timing diagram of the first driving signal P1 to the fourth driving signal P4; Figure 7 is a schematic diagram of the output current waveform of the traditional power supply system with the addition of the minimum pulse width limitation technology; Figure 8 is a schematic diagram of the output current output of the power system 1 of this case.

Some typical embodiments embodying the features and advantages of this case will be described in detail in the following description. It should be understood that this case can have various changes in different aspects, all of which do not depart from the scope of this case, and the descriptions and drawings therein are essentially for illustrative purposes, rather than being constructed to limit the case.

Please refer to Fig. 1A, Fig. 1B, Fig. 1C, Fig. 2, Fig. 3A, Fig. 3B, Fig. 4A and Fig. 4B, among which Fig. 1A is the circuit of the power supply system 1 of the preferred embodiment Block diagram, Figure 1B is a schematic diagram of the circuit structure of the first preferred embodiment of the power conversion device 3 shown in Figure 1, and Figure 1C is the second preferred embodiment of the power conversion device 3 shown in Figure 1 Fig. 2 is a signal timing diagram explaining the operation of the pulse width modulation unit 21 shown in Fig. 1A, and Fig. 3A is a diagram explaining the pulse width modulation unit 21 generating the first ramp signal S1a and the first ramp signal S1a. A signal timing diagram of the reference waveform S1', Figure 3B is a diagram explaining the signal timing diagram of the pulse width modulation unit 21 generating the first pulse width signal S2a and the second reference waveform S2', and Figure 4A is the signal timing diagram in the first time interval △ The signal timing diagram of the first triangular wave ePWM1, the second triangular wave ePWM2, the first ramp signal S1a, the first pulse width signal S2a, the first driving signal P1 to the fourth driving signal P4 at T1, Fig. 4B is at the first time The signal timing diagram of the first triangular wave ePWM1, the second triangular wave ePWM2, the first reference waveform S1', the second reference waveform S2', and the first driving signal P1 to the fourth driving signal P4 in the interval ΔT1. As shown in Figures 1A-1C, Figure 2, Figure 3A-3B, and Figure 4A-4B, the power supply system 1 of this embodiment is used to receive input voltages, such as batteries, solar panels, or capacitors. The provided DC voltage is converted into an AC output voltage Vout to be supplied to AC loads, such as motors, For power grids or industrial products, etc., the output voltage Vout may be, but not limited to, a three-phase output voltage. The power supply system 1 includes a pulse width modulation device 2 and a power conversion device 3. The pulse width modulation device 2 can output the first driving signal P1, the second driving signal P2, the third driving signal P3, and the fourth driving signal P4 to the power conversion device 3 to operate the power conversion device 3. The power conversion device 3 may include a switch module 30. The switch module 30 may include a plurality of transistors, such as the four transistors Q1-Q4 shown in Figure 1B. The power conversion device 3 is used to receive the input voltage and When the plurality of transistors of the switch module 30 respectively receive the first drive signal P1, the second drive signal P2, the third drive signal P3, and the fourth drive signal P4 to selectively switch on or off, The input voltage is converted to the output voltage Vout. The switch module 30 is selectively turned on or off according to the first to fourth driving signals P1 to P4, so that the DC voltage is converted into an AC voltage through the switch module 30. Therefore, in this embodiment, the input voltage is a DC voltage source Vdc, and the output voltage Vout is an AC voltage, but the invention is not limited to this.

In some embodiments, as shown in FIG. 1B, the switch module 30 may be an I-type three-level switch module, and the plurality of transistors of the switch module 30 are the first transistor Q1 and the second transistor respectively. Crystal Q2, third transistor Q3, and fourth transistor Q4. The first transistor Q1 includes a control terminal, a first terminal, and a second terminal. The control terminal of the first transistor Q1 is coupled to the first driving signal P1, and the first terminal of the first transistor Q1 is coupled to a direct current Voltage source Vdc. The second transistor Q2 includes a control terminal, a first terminal, and a second terminal. The control terminal of the second transistor Q2 is coupled to the second driving signal P2, and the first terminal of the second transistor Q2 is coupled to the first terminal. The second terminal of a transistor Q1. The third transistor Q3 includes a control terminal, a first terminal, and a second terminal. The control terminal of the third transistor Q3 is coupled to the third driving signal P3, and the first terminal of the third transistor Q3 is coupled to the second terminal. The second terminal of the two transistors Q2 forms an output node T, and the power conversion device 3 outputs the output voltage Vout through the output node T. The fourth transistor Q4 includes a control terminal, a first terminal, and a second terminal. The control terminal of the fourth transistor Q4 is coupled to the fourth driving signal P4, and the first terminal of the fourth transistor Q4 is coupled to The second terminal of the third transistor Q3 is connected, and the second terminal of the fourth transistor Q4 is coupled to the ground terminal of the DC voltage source Vdc. In Figure 3, when the power conversion device 3 receives the input voltage V, the power conversion device 3 adjusts the input voltage to a DC voltage source Vdc acceptable to the switch module 30. In some other embodiments, the DC voltage source Vdc can also be the input voltage directly, but the invention is not limited to this.

In some embodiments, the first transistor Q1 to the fourth transistor Q4 may be respectively formed of Metal-Oxide-Semiconductor Field-Effect Transistor (MOSFET), but it is not limited thereto. It can also be a bipolar junction transistor (BJT), etc. In some embodiments, the first to fourth transistors Q1 to Q4 can be high-voltage conduction semiconductors (such as N-type MOSFET, NPN-type BJT) or low-voltage conduction semiconductors (such as: P-type MOSFET, PNP-type BJT). In order to facilitate the description of the operation of the present invention, only the first to fourth transistors Q1 to Q4 are N-type MOSFETs as an example, but the present invention is not limited to this. In addition, the first end of each of the first to fourth transistors Q1~Q4 represents the drain of the N-type MOSFET, and the second end of each of the first to fourth transistors Q1~Q4 represents the source of the N-type MOSFET , And the control terminal of each of the first to fourth transistors Q1~Q4 represents the gate of the N-type MOSFET.

In addition, the first transistor Q1 to the fourth transistor Q4 may further include parasitic diodes D1-D4, wherein the anode end of the parasitic diode D1 is electrically connected to the second end of the first transistor Q1, and the parasitic diode The cathode terminal of D1 is electrically connected to the first terminal of the first transistor Q1, the anode terminal of the parasitic diode D2 is electrically connected to the second terminal of the second transistor Q2, and the cathode terminal of the parasitic diode D2 is electrically connected to the second transistor. The first terminal of Q2, the anode terminal of the parasitic diode D3 is electrically connected to the second terminal of the third transistor Q3, the cathode terminal of the parasitic diode D3 is electrically connected to the first terminal of the third transistor Q3, the parasitic diode The anode terminal of D4 is electrically connected to the second terminal of the fourth transistor Q4, and the cathode terminal of the parasitic diode D4 is electrically connected to the first terminal of the fourth transistor Q4. In addition, in some embodiments, the switch module 30 may further include a first diode D10 and a second diode D20, where the first and second diodes The cathode terminal of the polar body D10 is electrically connected between the second terminal of the first transistor Q1 and the first terminal of the second transistor Q2, the anode terminal of the first diode D10 and the cathode terminal of the second diode D20 Electrically connected, the anode end of the second diode D20 is electrically connected between the second end of the third transistor Q3 and the first end of the fourth transistor Q4.

Of course, the switch module 30 of the power conversion device 3 can also be a T-type three-level switch module, as shown in FIG. 1C, and the plurality of transistors of the switch module 30 are the first transistors Q1, The second transistor Q2, the third transistor Q3, and the fourth transistor Q4. The first transistor Q1 includes a control terminal, a first terminal, and a second terminal. The control terminal of the first transistor Q1 is coupled to the first driving signal P1, and the first terminal of the first transistor Q1 is coupled to a direct current Voltage source Vdc. The second transistor Q2 includes a control terminal, a first terminal, and a second terminal. The control terminal of the second transistor Q2 is coupled to the second driving signal P2, and the first terminal of the second transistor Q2 is coupled to DC Voltage source Vdc. The third transistor Q3 includes a control terminal, a first terminal, and a second terminal. The control terminal of the third transistor Q3 is coupled to the third driving signal P3, and the second terminal of the third transistor Q3 is coupled to the second terminal. The second terminal of the second transistor Q2. The fourth transistor Q4 includes a control terminal, a first terminal, and a second terminal. The control terminal of the fourth transistor Q4 is coupled to the fourth driving signal P4, and the first terminal of the fourth transistor Q4 is commonly coupled The first terminal of the third transistor Q3 and the second terminal of the first transistor Q1 together form an output node T1, and the power conversion device 3 outputs the output voltage Vout through the output node T1, and the fourth transistor The second terminal of Q4 is coupled to the ground terminal of the DC voltage source Vdc. In addition, the first transistor Q1 to the fourth transistor Q4 may further include parasitic diodes D1a-D4a, wherein the anode end of the parasitic diode D1a is electrically connected to the second end of the first transistor Q1, and the parasitic diode The cathode terminal of D1a is electrically connected to the first terminal of the first transistor Q1, the anode terminal of the parasitic diode D2a is electrically connected to the second terminal of the second transistor Q2, and the cathode terminal of the parasitic diode D2a is electrically connected to the DC voltage source Vdc , The anode terminal of the parasitic diode D3a is electrically connected to the second terminal of the third transistor Q3, the cathode terminal of the parasitic diode D3a is electrically connected to the first terminal of the third transistor Q3, and the anode terminal of the parasitic diode D4a is electrically connected Connect the second end of the fourth transistor Q4, the parasitic diode D4a The cathode terminal is electrically connected to the first terminal of the fourth transistor Q4. Since the operation of the switch module 30 in Figure 1C is the same as that of the switch module 30 shown in Figure 1B, and both can achieve the same effect, the technical content mentioned below is only shown in Figure 1B The switch module 30 is shown as an example.

The first driving signal P1, the second driving signal P2, the third driving signal P3, and the fourth driving signal P4 output by the pulse width modulation device 2 are provided to the first transistor Q1, the second transistor Q2, and the third transistor, respectively. The transistor Q3 and the fourth transistor Q4 enable the first transistor Q1, the second transistor Q2, the third transistor Q3, and the fourth transistor Q4 to switch on or off respectively. In some embodiments, the waveforms of the first driving signal P1 and the third driving signal P3 are complementary, and the waveforms of the second driving signal P2 and the fourth driving signal P4 are complementary. In other words, the operation mode of the first transistor Q1 is The operation mode of the third transistor Q3 is complementary, and the operation mode of the second transistor Q2 is complementary to the operation mode of the fourth transistor Q4.

The pulse width modulation device 2 further includes a control unit 20 and a pulse width modulation unit 21. The control unit 20 is used to generate a control signal Sc to the pulse width modulation unit 21, and the pulse width modulation unit 21 controls the switch module 30 in the power conversion device 3 according to the control signal Sc, wherein the control signal Sc can be but not limited to a period Sex signal. In some embodiments, the control unit 20 further samples the output voltage Vout and the output current of the power conversion device 3 through a voltage sampling element or a current sampling element, etc., to adjust the control signal Sc correspondingly according to the sampling result. The pulse width modulation unit 21 determines the critical time point of the control signal Sc according to the reference voltage level Vref, for example, the reference voltage level Vref shown in Figure 2 as the zero voltage level, and divides the control signal area Sc according to the critical time point Is the positive cycle signal Sc+ for the positive half cycle and the negative cycle signal Sc- for the negative half cycle. As shown in Figure 2, when the critical time point of the control signal Sc is determined by the zero voltage level, the The critical time point is t0, so the control signal Sc is a positive cycle signal Sc+ after time t0, and the control signal Sc is a negative cycle signal Sc- before time t0, where the control signal Sc is close to the reference voltage level Vref at the critical time point t0 Within the allowable error range.

In addition, the pulse width modulation unit 21 clamps the portion of the positive period signal Sc+ that is greater than or equal to the maximum voltage threshold Vmax to the maximum voltage threshold Vmax to form the first comparison waveform S1, and the pulse width modulation unit 21 changes the positive period The signal Sc+ is clamped at the reference voltage level Vref as the second comparison waveform S2. Furthermore, the pulse width modulation unit 21 samples the first comparison waveform S1 and the second comparison waveform S2 in the first time interval ΔT1 from the critical time point (time t0 shown in Figure 2) to the first predetermined time t1 . And the pulse width modulation unit 21 further superimposes the low voltage threshold Vmin and the first comparison waveform S1 falling within the first time interval ΔT1 to form a first ramp signal S1a (as shown in FIG. 3A), and the pulse width The modulation unit 21 also superimposes the low voltage threshold Vmin and the second comparison waveform S2 falling within the first time interval ΔT1 to form the first pulse width signal S2a (as shown in FIG. 3B).

Furthermore, in the first time interval ΔT1, the pulse width modulation unit 21 compares the first ramp signal S1a with the first triangle wave ePWM1 to adjust the first driving signal P1 and the third driving signal P3, and the pulse width modulation The unit 21 compares the first pulse width signal S2a with the second triangular wave ePWM2 to adjust the second driving signal P2 and the fourth driving signal P4 (as shown in Fig. 4A), wherein the phase between the first triangular wave ePWM1 and the second triangular wave ePWM2 The difference is 180 degrees.

In the above embodiment, the first time interval ΔT1 is the time interval during which the power supply system 1 executes the minimum pulse width limitation during the positive half cycle of the control signal area Sc. The low voltage threshold Vmin is the preset value of the output voltage Vout of the power supply system 1 when the power supply system 1 implements the minimum pulse width limitation.

Furthermore, as shown in FIG. 4A, in the first time interval ΔT1, when the pulse width modulation unit 21 determines that the first ramp signal S1a is greater than the first triangle wave ePWM1, the pulse width modulation unit 21 switches the first drive The signal P1 is at a high voltage level, and the third driving signal P3 is switched to a low voltage level, so that the first transistor Q1 is switched on and the third transistor Q3 is switched off; in addition, in the first time interval △T1 , When the pulse width modulation unit 21 determines that the first pulse width signal S2a is smaller than the second triangle wave ePWM2, the pulse width modulation unit 21 Switching the second driving signal P2 to a high voltage level, and switching the fourth driving signal P4 to a low voltage level, so that the second transistor Q2 is switched on and the fourth transistor Q4 is switched off.

In addition, in the first time interval ΔT1, when the pulse width modulation unit 21 determines that the first ramp signal S1a is less than or equal to the first triangular wave ePWM1, the pulse width modulation unit 21 switches the first driving signal P1 to a low voltage level. And switch the third driving signal P3 to the high voltage level, so that the first transistor Q1 is switched off and the third transistor Q3 is switched on; and in the first time interval △T1, when the pulse width modulation unit 21 When determining that the first pulse width signal S2a is greater than or equal to the second triangular wave ePWM2, the pulse width modulation unit 21 switches the second driving signal P2 to a low voltage level and switches the fourth driving signal P4 to a high voltage level, so that the second transistor Q2 is switched off and the fourth transistor Q4 is switched on. It can be seen from Fig. 4A that during the positive half cycle of the control signal Sc, the output voltage Vout is composed of 0, -Vdc/2, and Vdc/2.

It can be seen from the foregoing that the pulse width modulation unit 21 of the power supply system 1 of this case will superimpose the low voltage valve during the positive half cycle of the control signal Sc and the first time interval ΔT1 from the critical time point t0 to the first predetermined time. The value Vmin and the first comparison waveform S1 falling within the first time interval ΔT1 form a first ramp signal S1a, and the low voltage threshold Vmin is superimposed with the second comparison waveform S2 falling within the first time interval ΔT1 In order to form the first pulse width signal S2a, in other words, when the control signal area Sc is in the positive half cycle and the power supply system 1 implements the minimum pulse width limit time interval, the control signal Sc is compensated for the low voltage threshold Vmin, so that , The power system 1 of this case can not only meet the minimum pulse width limit, but also because in the first time interval ΔT1 from the critical time point t0 to the first predetermined time, the first ramp signal S1a is superimposed on the positive half cycle of the control signal Sc , Which cancels out the low voltage threshold Vmin generated by the first pulse width signal S2a, so the ideal control signal Sc is maintained, and the time zone for the power supply system 1 to implement the minimum pulse width limitation is satisfied, so the accuracy of the output voltage Vout can be ensured.

The operation of the power supply system 1 when the control signal Sc is a negative half cycle will be described below. Please refer to Figure 1 and Figure 2 in conjunction with Figure 5A, Figure 5B, Figure 6A and Figure 6B. Figure 5A is for explaining that the pulse width modulation unit 21 generates the second pulse width signal S3a and the third pulse width signal S3a. Referring to the signal timing diagram of the waveform S3', Figure 5B is a diagram explaining the signal timing diagram of the pulse width modulation unit 21 generating the second ramp signal S4a and the fourth reference waveform S4', and Figure 6A is the signal timing diagram in the second time interval. A schematic diagram of the signal timing of a triangular wave ePWM1, a second triangular wave ePWM2, a second pulse width signal S3a, a second ramp signal S4a, and a first driving signal P1 to a fourth driving signal P4. Fig. 6B shows the signal timing in the second time interval. A schematic diagram of the signal timing of a triangular wave ePWM1, a second triangular wave ePWM2, a third reference waveform S3', a fourth reference waveform S4', and the first driving signal P1 to the fourth driving signal P4. In some embodiments, when the negative half cycle of the control signal Sc is controlled, the pulse width modulation unit 21 clamps the negative cycle signal Sc- to the reference voltage level Vref as the third comparison waveform S3, and the pulse width modulation unit 21 Invert the negative period signal Sc-, and clamp the portion of the inverted negative period signal Sc- that is greater than or equal to the maximum voltage threshold Vmax at the maximum voltage threshold Vmax to form a fourth comparison waveform S4.

In addition, the pulse width modulation unit 21 may further sample the third comparison waveform S3 and the fourth comparison waveform S4 within the second time interval ΔT2 from the critical time point t0 to the second predetermined time t2. Furthermore, the pulse width modulation unit 21 further superimposes the low voltage threshold Vmin and the third comparison waveform S3 falling within the second time interval ΔT2 to form the second pulse width signal S3a, and the pulse width modulation unit 21 also superimposes the low voltage The threshold Vmin and the fourth comparison waveform S4 falling within the second time interval ΔT2 form a second ramp signal S4a.

Furthermore, in the second time interval ΔT2, the pulse width modulation unit 21 compares the second pulse width signal S3a with the first triangular wave ePWM1 to adjust the first driving signal P1 and the third driving signal P3, and the pulse width modulation The unit 21 compares the second ramp signal S4a with the second triangle wave ePWM2 to adjust the second driving signal P2 and the fourth driving signal P4. In the above embodiment, the second time interval ΔT2 is the time interval during which the power supply system 1 executes the minimum pulse width limitation when the control signal area Sc is in the negative half cycle.

Furthermore, as shown in FIG. 6A, in the second time interval ΔT2, when the pulse width modulation unit 21 determines that the second pulse width signal S3a is greater than the first triangular wave ePWM1, the pulse width modulation unit 21 switches the first The driving signal P1 is switched to a high voltage level, and the third driving signal P3 is switched to a low voltage level, so that the first transistor Q1 is switched on and the third transistor Q3 is switched off. In addition, in the second time interval ΔT2, when the pulse width modulation unit 21 determines that the second ramp signal S4a is smaller than the second triangle wave ePWM2, the pulse width modulation unit 21 switches the second driving signal P2 to a high voltage level, and The fourth driving signal P4 is switched to the low voltage level, so that the second transistor Q2 is switched on and the fourth transistor Q4 is switched off.

In addition, in the second time interval ΔT2, when the pulse width modulation unit 21 determines that the second pulse width signal S3a is less than or equal to the first triangular wave ePWM1, the pulse width modulation unit 21 switches the first driving signal P1 to a low voltage level. And switch the third driving signal P3 to the high voltage level, so that the first transistor Q1 is switched off and the third transistor Q3 is switched on; and in the second time interval △T2, when the pulse width modulation unit 21 When judging that the second ramp signal S4a is greater than or equal to the second triangular wave ePWM2, the pulse width modulation unit 21 switches the second driving signal P2 to a low voltage level and switches the fourth driving signal P4 to a high voltage level, so that the second transistor Q2 is switched off and the fourth transistor Q4 is switched on. It can be seen from Fig. 6A that during the negative half cycle of the control signal Sc, the output voltage Vout is composed of 0, -Vdc/2, and Vdc/2.

Please refer to Figures 7 and 8 again, in conjunction with Figures 1 to 6B. Figure 7 is a waveform diagram of the output current output by a traditional power system with minimum pulse width limiting technology. Figure 8 is The waveform diagram of the output current output by the power supply system 1 in this case. As shown in the figure, first, as shown in figure 7, when the control signal Sc' output by the control unit of the traditional power system is close to the zero-crossing point, since the traditional power system enters the time interval limited by the minimum pulse width, The output current (including U-phase current, V-phase current and W-phase current) output by the traditional power system will produce distortion. However, because the power system 1 in this case controls the signal area Sc in the positive half cycle and the negative half cycle. The power supply system 1 performs the minimum pulse When the time interval is wide limited, the low voltage threshold Vmin will be compensated for the control signal Sc. Therefore, as shown in Figure 8, the output current (including U-phase current, V-phase current and W-phase current) output by the power supply system 1 in this case ) Can greatly improve the distortion phenomenon.

Please refer to FIGS. 3A-3B and 4B again, and in conjunction with FIG. 2, and in some embodiments, the pulse width modulation unit 21 may sample outside the first time interval ΔT1, for example, as shown in FIG. 3A The first comparison waveform S1 after the time t1 is used as the first reference waveform S1', and the pulse width modulation unit 21 also samples outside the first time interval ΔT1, for example, after the time t1 shown in Figure 3B The second comparison waveform S2 is used as the second reference waveform S2', and as shown in FIG. 4B, the pulse width modulation unit 21 compares the first reference waveform S1' with the first triangular wave ePWM1 to adjust the first driving signal P1 and the second Three driving signals P3. When the pulse width modulation unit 21 determines that the first reference waveform S1' is greater than the first triangular wave ePWM1, the pulse width modulation unit 21 switches the first driving signal P1 to a high voltage level, and drives the third The signal P3 is switched to the low voltage level. In addition, when the pulse width modulation unit 21 determines that the first reference waveform S1' is less than or equal to the first triangular wave ePWM1, the pulse width modulation unit 21 switches the first driving signal P1 to a low voltage level, and switches the third driving signal P3 switches to the high voltage level. Furthermore, when the pulse width modulation unit 21 determines that the second reference waveform S2' is constantly smaller than the second triangular wave ePWM2, the pulse width modulation unit 21 maintains the second driving signal P2 to the high voltage level and maintains the fourth driving signal P4 to low voltage level.

Please refer to FIG. 5A-5B and FIG. 6B again, and in conjunction with FIG. 2, and in some embodiments, the pulse width modulation unit 21 also samples outside the second time interval ΔT2, for example, as shown in FIG. 5A Before the time t2, the third comparison waveform S3 is used as the third reference waveform S3', and the pulse width modulation unit 21 also samples outside the second time interval ΔT2, for example, before the time t2 shown in Fig. 5B, The fourth comparison waveform S4 is used as the fourth reference waveform S4', and as shown in FIG. 6B, the pulse width modulation unit 21 compares the fourth reference waveform S4' with the second triangular wave ePWM2 to adjust the second driving signal P2 and the first Four-drive signal P4, when pulse width modulation When the unit 21 determines that the fourth reference waveform S4' is smaller than the second triangle wave ePWM2, the pulse width modulation unit 21 switches the second driving signal P2 to a high voltage level, and switches the fourth driving signal P4 to a low voltage level. In addition, when the pulse width modulation unit 21 determines that the fourth reference waveform S4' is greater than or equal to the second triangular wave ePWM2, the pulse width modulation unit 21 switches the second driving signal P2 to a low voltage level, and switches the fourth driving signal P4 to high voltage level. Furthermore, when the pulse width modulation unit 21 determines that the third reference waveform S3' is constantly smaller than the first triangular wave ePWM1, the pulse width modulation unit 21 maintains the first driving signal P1 to a low voltage level and maintains the third driving signal P3 to high voltage level.

In some embodiments, the first triangular wave ePWM1 and the second triangular wave ePWM2 are respectively the carrier of the control signal Sc, and the frequency of the first triangular wave ePWM1 and the second triangular wave ePWM2 are at least ten times the frequency of the control signal Sc. Since the frequency of the first triangular wave ePWM1 and the second triangular wave ePWM2 is more than ten times greater than the frequency of the control signal Sc, the enlarged waveform shows that the waveform related to the control signal Sc is a straight line for the carrier, as shown in Figure 4A-4B And as shown in Figure 6A-6B.

The following will explain the steps of the pulse width modulation method of the present application applicable to the pulse width modulation device 2 of the power supply system 1 in the foregoing embodiment. The pulse width modulation method of this case includes the following steps.

First, in step s1, the pulse width modulation unit 21 of the pulse width modulation device 2 receives the control signal Sc output by the control unit 20, wherein the control signal Sc is a periodic signal.

In step s2, the pulse width modulation unit 21 determines the critical time point of the control signal Sc according to the reference voltage level Vref.

In step s3, the pulse width modulation unit 21 divides the control signal Sc into a positive period signal Sc+ and a negative period signal Sc- according to the critical time point, wherein the control signal Sc is close to the reference voltage level Vref at the critical time point within the error range.

In step s4, the pulse width modulation unit 21 clamps the portion of the positive period signal Sc+ that is greater than or equal to the maximum voltage threshold Vmax to the maximum voltage threshold Vmax to form the first comparison waveform S1.

In step s5, the pulse width modulation unit 21 clamps the positive period signal Sc+ at the reference voltage level Vref as the second comparison waveform S2.

In step s6, the pulse width modulation unit 21 samples the first comparison waveform S1 and the first comparison waveform S1 and the first time interval ΔT1 from the critical time point (time t0 shown in Figure 2) to the first predetermined time t1 2. Compare the waveform S2.

In step s7, the pulse width modulation unit 21 superimposes the low voltage threshold Vmin and the first comparison waveform S1 falling within the first time interval ΔT1 to form a first ramp signal S1a (as shown in FIG. 3A).

In step s8, the pulse width modulation unit 21 superimposes the low voltage threshold Vmin and the second comparison waveform S2 falling within the first time interval ΔT1 to form a first pulse width signal S2a (as shown in FIG. 3B).

In step s9, in the first time interval ΔT1, the pulse width modulation unit 21 compares the first ramp signal S1a with the first triangular wave ePWM1 to adjust the first driving signal P1 and the third driving signal P3.

In step s10, in the first time interval ΔT1, the pulse width modulation unit 21 compares the first pulse width signal S2a with the second triangular wave ePWM2 to adjust the second driving signal P2 and the fourth driving signal P4 (as shown in Fig. 4A) Shown). The phase difference between the first triangular wave ePWM1 and the second triangular wave ePWM2 is 180 degrees.

In addition, when the comparison result of step s9 is that the pulse width modulation unit 21 determines that the first ramp signal S1a is greater than the first triangle wave ePWM1, the pulse width modulation unit 21 switches the first driving signal P1 to the high voltage level, and switches the third The signal P3 is driven to a low voltage level, so that the first transistor Q1 is switched on and the third transistor Q3 is switched off. When the comparison result of step s10 is that the pulse width modulation unit 21 determines that the first pulse width signal S2a is smaller than the second triangular wave ePWM2, the pulse width modulation unit 21 switches the second driving signal P2 to a high voltage. And switch the fourth driving signal P4 to a low voltage level, so that the second transistor Q2 is switched on and the fourth transistor Q4 is switched off.

Conversely, when the comparison result of step s9 is that the pulse width modulation unit 21 determines that the first ramp signal S1a is less than or equal to the first triangular wave ePWM1, the pulse width modulation unit 21 switches the first driving signal P1 to a low voltage level and switches The third driving signal P3 reaches the high voltage level, so that the first transistor Q1 is switched off and the third transistor Q3 is switched on. When the comparison result of step s10 is that the pulse width modulation unit 21 determines that the first pulse width signal S2a is greater than or equal to the second triangular wave ePWM2, the pulse width modulation unit 21 switches the second driving signal P2 to a low voltage level and switches the first pulse width signal S2a to a low voltage level. The four driving signal P4 reaches the high voltage level, so that the second transistor Q2 is switched off and the fourth transistor Q4 is switched on.

In some embodiments, the pulse width modulation method of this case further includes the following steps.

In step s1', the pulse width modulation unit 21 clamps the negative period signal Sc- at the reference voltage level Vref as the third comparison waveform S3.

In step s2', the pulse width modulation unit 21 inverts the negative period signal Sc-, and clamps the inverted negative period signal Sc- which is greater than or equal to the maximum voltage threshold Vmax to the maximum voltage threshold Vmax. A fourth comparison waveform S4 is formed.

In step s3', the pulse width modulation unit 21 may sample the third comparison waveform S3 and the fourth comparison waveform S4 within the second time interval ΔT2 from the critical time point t0 to the second predetermined time t2.

In step s4', the pulse width modulation unit 21 superimposes the low voltage threshold Vmin and the third comparison waveform S3 falling within the second time interval ΔT2 to form the second pulse width signal S3a.

In step s5', the pulse width modulation unit 21 superimposes the low voltage threshold Vmin and the fourth comparison waveform S4 falling within the second time interval ΔT2 to form the second ramp signal S4a.

In step s6', in the second time interval ΔT2, the pulse width modulation unit 21 compares the second pulse width signal S3a with the first triangular wave ePWM1 to adjust the first driving signal P1 and the third driving signal P3.

In step s7', the pulse width modulation unit 21 compares the second ramp signal S4a with the second triangle wave ePWM2 to adjust the second driving signal P2 and the fourth driving signal P4.

In addition, in step s6', in the second time interval ΔT2, when the pulse width modulation unit 21 determines that the second pulse width signal S3a is greater than the first triangular wave ePWM1, the pulse width modulation unit 21 switches the first driving signal P1 Highest voltage level. In step s7', in the second time interval ΔT2, when the pulse width modulation unit 21 determines that the second ramp signal S4a is smaller than the second triangle wave ePWM2, the pulse width modulation unit 21 switches the second driving signal P2 to high The fourth driving signal P4 is switched to the low voltage level, so that the second transistor Q2 is switched on and the fourth transistor Q4 is switched off.

Conversely, in step s6', within the second time interval ΔT2, when the pulse width modulation unit 21 determines that the second pulse width signal S3a is less than or equal to the first triangular wave ePWM1, the pulse width modulation unit 21 switches the first The driving signal P1 is switched to a low voltage level and the third driving signal P3 is switched to a high voltage level, so that the first transistor Q1 is switched off and the third transistor Q3 is switched on. Also in step s7', when the pulse width modulation unit 21 determines that the second ramp signal S4a is greater than or equal to the second triangle wave ePWM2, the pulse width modulation unit 21 switches the second driving signal P2 to a low voltage level and switches the first The four driving signal P4 reaches the high voltage level, so that the second transistor Q2 is switched off and the fourth transistor Q4 is switched on.

In some embodiments, the aforementioned control unit may include but is not limited to a microcontroller, and the pulse width modulation unit may include, but is not limited to, a pulse width modulator.

In summary, this project provides a power supply system and its applicable pulse width modulation method. The power supply system of this project can control the signal area in the positive half cycle and the negative half cycle and implement the minimum pulse width limit In the time interval of, the low-voltage threshold is compensated for the control signal, so the output electric energy output by the power system of this case can greatly improve the distortion phenomenon.

It should be noted that the above is only a preferred embodiment for explaining this case, this case is not limited to the described embodiment, and the scope of this case is determined by the attached patent application scope. Moreover, this case can be modified in many ways by those who are familiar with this technology, but it is not deviated from the protection of the scope of the patent application.

Sc: control signal

Sc+: positive periodic signal

S1: The first comparison waveform

S1’: The first reference waveform

Vmax: Maximum voltage threshold

Vmin: Low voltage threshold

t0, t1: time

ΔT1: the first time interval

Vref: Reference voltage level

Claims (18)

A power supply system includes a power conversion device and a pulse width modulation device, wherein the pulse width modulation device outputs a first to fourth driving signal to operate the power conversion device, and the pulse width modulation device includes: A control unit for generating a control signal, wherein the control signal is a periodic signal; and A pulse width modulation unit determines a critical time point of the control signal according to a reference voltage level, and divides the control signal into a positive period signal and a negative period signal according to the critical time point, wherein the control signal is at the The critical time point is close to the reference voltage and is within an error range; The pulse width modulation unit clamps the portion of the positive period signal that is greater than or equal to a maximum voltage threshold to the maximum voltage threshold to form a first comparison waveform, and the pulse width modulation unit also changes the positive period The signal clamp is located at the reference voltage level as a second comparison waveform, and the pulse width modulation unit samples the first and second time intervals falling within a first time interval from the critical time point to a first predetermined time Compare waveforms; The pulse width modulation unit superimposes a low voltage threshold value and the first comparison waveform falling within the first time interval to form a first ramp signal; The pulse width modulation unit superimposes the low voltage threshold value and the second comparison waveform falling within the first time interval to form a first pulse width signal; In the first time interval, the pulse width modulation unit compares the first ramp signal with a first triangular wave to adjust the first and third driving signals, and the pulse width modulation unit compares the first pulse A wide signal and a second triangular wave are used to adjust the second and fourth driving signals, wherein a phase difference between the first and second triangular waves is 180 degrees. The power supply system according to claim 1, wherein in the first time interval, if the pulse width modulation unit determines that the first ramp signal is greater than the first triangular wave, the pulse width modulation unit switches the first Driving the signal to a high voltage level and switching the third driving signal to a low voltage level; In the first time interval, if the pulse width modulation unit determines that the first pulse width signal is smaller than the second triangle wave, the pulse width modulation unit switches the second driving signal to the high voltage level and switches The fourth driving signal reaches the low voltage level. The power supply system according to claim 2, wherein in the first time interval, if the pulse width modulation unit determines that the first ramp signal is less than or equal to the first triangle wave, the pulse width modulation unit switches the The first driving signal is switched to the low voltage level and the third driving signal is switched to the high voltage level; In the first time interval, if the pulse width modulation unit determines that the first pulse width signal is greater than or equal to the second triangular wave, the pulse width modulation unit switches the second driving signal to the low voltage level And switch the fourth driving signal to the high voltage level. The power supply system according to claim 2, wherein the pulse width modulation unit clamps the negative period signal at the reference voltage level as a third comparison waveform; The pulse width modulation unit inverts the negative period signal, and clamps the portion of the inverted negative period signal greater than or equal to the maximum voltage threshold at the maximum voltage threshold to form a fourth comparison waveform. The power supply system according to claim 4, wherein the pulse width modulation unit samples the third and fourth comparison waveforms that fall within a second time interval from the critical time point to a second predetermined time; The pulse width modulation unit superimposes the low voltage threshold value and the third comparison waveform falling within the second time interval to form a second pulse width signal; The pulse width modulation unit superimposes the low voltage threshold value and the fourth comparison waveform falling within the second time interval to form a second ramp signal; In the second time interval, the pulse width modulation unit compares the second pulse width signal with the first triangular wave to adjust the first and third driving signals, and the pulse width modulation unit compares the second slope A wave signal and a second triangular wave are used to adjust the second and fourth driving signals. The power supply system according to claim 5, wherein in the second time interval, if the pulse width modulation unit determines that the second pulse width signal is greater than the first triangular wave, the pulse width modulation unit switches the first Driving the signal to the high voltage level and switching the third driving signal to the low voltage level; In the second time interval, if the pulse width modulation unit determines that the second ramp signal is smaller than the second triangle wave, the pulse width modulation unit switches the second driving signal to the high voltage level and switches The fourth driving signal reaches the low voltage level. The power supply system according to claim 5, wherein in the second time interval, if the pulse width modulation unit determines that the second pulse width signal is less than or equal to the first triangular wave, the pulse width modulation unit switches the The first driving signal is switched to the low voltage level and the third driving signal is switched to the high voltage level; In the second time interval, if the pulse width modulation unit determines that the second ramp signal is greater than or equal to the second triangle wave, the pulse width modulation unit switches the second driving signal to the low voltage level And switch the fourth driving signal to the high voltage level. The power supply system according to claim 2, wherein the pulse width modulation unit further samples the first comparison waveform outside the first time interval as a first reference waveform, and the pulse width modulation unit also samples The second comparison waveform outside the first time interval is used as a second reference waveform; The pulse width modulation unit compares the first reference waveform with the first triangle wave to adjust the first and third driving signals. For the power supply system of claim 8, if the pulse width modulation unit determines that the first reference waveform is greater than the first triangle wave, the pulse width modulation unit switches the first driving signal to the high voltage level and switches The third driving signal to the low voltage level; If the pulse width modulation unit determines that the first reference waveform is less than or equal to the first triangle wave, the pulse width modulation unit switches the first driving signal to the low voltage level and switches the third driving signal to the high Voltage level. The power supply system according to claim 8, wherein if the pulse width modulation unit determines that the second reference waveform is constantly smaller than the second triangular wave, the pulse width modulation unit maintains the second driving signal to the high voltage level And maintain the fourth driving signal to the low voltage level. The power supply system according to claim 5, wherein the pulse width modulation unit further samples the third comparison waveform outside the second time interval as a third reference waveform, and the pulse width modulation unit also samples The fourth comparison waveform outside the second time interval is used as a fourth reference waveform; The pulse width modulation unit compares the fourth reference waveform with the second triangle wave to adjust the second and fourth driving signals. For the power supply system of claim 11, if the pulse width modulation unit determines that the fourth reference waveform is smaller than the second triangle wave, the pulse width modulation unit switches the second driving signal to the high voltage level and switches The fourth driving signal to the low voltage level; If the pulse width modulation unit determines that the fourth reference waveform is greater than or equal to the second triangle wave, the pulse width modulation unit switches the second driving signal to the low voltage level and switches the fourth driving signal to the high Voltage level. The power supply system according to claim 11, wherein if the pulse width modulation unit determines that the third reference waveform is constantly smaller than the first triangular wave, the pulse width modulation unit maintains the first driving signal to the low voltage level And maintain the third driving signal to the high voltage level. The power supply system according to claim 1, wherein the frequencies of the first and second triangular waves are at least ten times of a frequency of the control signal. A pulse width modulation method, including: Receiving a control signal, where the control signal is a periodic signal; Determine a critical time point of the control signal according to a reference voltage level; The control signal is divided into a positive period signal and a negative period signal according to the critical time point, wherein the control signal is within an error range close to the reference voltage at the critical time point; Clamping the portion of the positive period signal greater than or equal to a maximum voltage threshold at the maximum voltage threshold to form a first comparison waveform; Clamping the positive period signal at the reference voltage level as a second comparison waveform; Sampling the first and second comparison waveforms falling within a first time interval from the critical time point to a first predetermined time; Superimposing a low voltage threshold value and the first comparison waveform falling within the first time interval to form a first ramp signal; Superimposing the low voltage threshold value and the second comparison waveform falling within the first time interval to form a first pulse width signal; Comparing the first ramp signal with a first triangular wave in the first time interval to adjust the first and third driving signals; and In the first time interval, the pulse width modulation unit compares the first pulse width signal with a second triangular wave to adjust the second and fourth driving signals, wherein a phase difference between the first and second triangular waves is Is 180 degrees. The pulse width modulation method according to claim 15, wherein in the first time interval, if it is determined that the first ramp signal is greater than the first triangle wave, the first driving signal is switched to a high voltage level and Switch the third driving signal to a low voltage level; In the first time interval, if it is determined that the first pulse width signal is smaller than the second triangular wave, then switch the second drive signal to the high voltage level and switch the fourth drive signal to the low voltage level; In the first time interval, if it is determined that the first ramp signal is less than or equal to the first triangle wave, then switch the first drive signal to the low voltage level and switch the third drive signal to the high voltage level Bit In the first time interval, if it is determined that the first pulse width signal is greater than or equal to the second triangular wave, then switch the second driving signal to the low voltage level and switch the fourth driving signal to the high voltage Level. The pulse width modulation method described in claim 15 further includes: Clamping the negative period signal at the reference voltage level as a third comparison waveform; Inverting the negative period signal and clamping the portion of the inverted negative period signal greater than or equal to the maximum voltage threshold to the maximum voltage threshold to form a fourth comparison waveform; Sampling the third and fourth comparison waveforms falling within a second time interval from the critical time point to a second predetermined time; Superimposing the low voltage threshold value and the third comparison waveform falling within the second time interval to form a second pulse width signal; Superimposing the low voltage threshold value and the fourth comparison waveform falling within the second time interval to form a second ramp signal; Comparing the second pulse width signal with the first triangular wave in the second time interval to adjust the first and third driving signals; and The second ramp signal and a second triangular wave are compared in the second time interval to adjust the second and fourth driving signals. The pulse width modulation method according to claim 17, wherein in the second time interval, if it is determined that the second pulse width signal is greater than the first triangular wave, the first driving signal is switched to a high voltage level and Switch the third driving signal to a low voltage level; In the second time interval, if it is determined that the second ramp signal is smaller than the second triangle wave, switch the second drive signal to the high voltage level and switch the fourth drive signal to the low voltage level; In the second time interval, if it is determined that the second pulse width signal is less than or equal to the first triangular wave, the first driving signal is switched to the low voltage level and the third driving signal is switched to the high voltage level Bit In the second time interval, if it is determined that the second ramp signal is greater than or equal to the second triangle wave, the second driving signal is switched to the low voltage level and the fourth driving signal is switched to the high voltage level Bit.

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