TWI745789B - Semiconductor device and method of manufacturing the same - Google Patents

Abstract

A semiconductor device and method for forming the semiconductor device are provided. A first layer is formed over a semiconductor layer, and a first patterned mask is formed over the first layer. A cyclic etch process is then performed to define a second patterned mask in the first layer. The cyclic etch process includes a first phase to form a polymer layer over the first patterned mask and a second phase to remove the polymer layer and to remove a portion of the first layer. A portion of the semiconductor layer is removed using the second patterned mask to define a fin from the semiconductor layer.

Description

Semiconductor device and manufacturing method thereof

The embodiments of the present invention are related to semiconductor manufacturing technology, and in particular to semiconductor devices and manufacturing methods thereof.

As the semiconductor industry develops towards nanotechnology process nodes (nodes) in pursuit of higher device density, higher performance and lower cost, challenges from both manufacturing and design issues have led to the development of three-dimensional design, such as fins. Fin-like field effect transistors (FinFET) and gate all around (GAA) transistors. The fin-type field effect transistor includes an extended semiconductor fin that rises above the substrate substantially in a direction perpendicular to the plane of the top surface of the substrate. The channel of the fin-type field effect transistor is formed in this fin. Provide and partially cover the fin above the fin. The wrap-around gate transistor includes one or more nano-sheet channel regions, which have a gate surrounding the nano-sheet. Fin-type field-effect transistors and wrap-around gate transistors can reduce short channel effects.

According to some of the embodiments of the present invention, a manufacturing method of a semiconductor device is provided Law. The method includes: forming a first layer over the semiconductor layer; forming a first patterned mask over the first layer; and performing a cyclic etching process to define a second patterned mask in the first layer, wherein: the cyclic etching process Each cycle in includes a first stage and a second stage, the first stage forms a polymer layer above the first patterned mask, and the second stage removes the polymer layer and removes a part of the first layer, and in the During the second stage of each cycle in the cyclic etching process, about 1 angstrom to about 20 angstrom of the first layer is removed; and a second patterned mask is used to remove a portion of the semiconductor layer to define fins from the semiconductor layer.

According to other embodiments of the embodiments of the present invention, methods for manufacturing semiconductor devices are provided. This method includes: forming a first layer over the semiconductor layer; forming a first patterned mask over the first layer, wherein: the first patterned mask includes a plurality of first elements in the first region and the second A plurality of second elements in the zone, and the density of the first elements in the first zone is different from the density of the second elements in the second zone; performing about 120 cycles to about 140 cycles The cyclic etching process to define a second patterned mask in the first layer, wherein: each cycle in the cyclic etching process includes a first stage and a second stage, and the first stage is formed above the first patterned mask A polymer layer, and the second stage removes the polymer layer and removes a part of the first layer, and the second patterned mask includes the first patterned mask from the first layer under the first element A plurality of first elements formed by the first part and a plurality of second elements formed by the second part of the first layer under the second element of the first patterned mask; and the second patterned mask is used to move The plurality of parts of the semiconductor layer are removed to define a plurality of fins from the semiconductor layer, wherein the first subset of the fins is formed by the first part of the semiconductor layer under the first element of the second patterned mask And the second subset of the fins is formed by the second part of the semiconductor layer under the second element of the second patterned mask.

According to still other embodiments of the embodiments of the present invention, semiconductor devices are provided. This semiconductor device includes: a first region having a first density of fins and a first region having a first density different from that of the fins The second area of the second density of the same fins, where: the second density is about 13% to about 82% of the first density, and the average height of the fins in the first area is the same as the fins in the second area The difference between the average heights is less than or equal to 1 nanometer.

100, 200, 300: semiconductor device

102A: District 1

102B: Second District

105: semiconductor layer

110: first layer

115: second layer

120: third layer

125: fourth layer

128,129: distance

130: The first patterned mask

130A, 130B, 140A, 140B: components

131,132: Thickness

133,134: Pitch

135: polymer layer

140: The second patterned mask

140W1, 140W2: width

150A, 150B: fins

151,152: Average height

155A, 155B, 170A, 170B, 200A, 200B: cover layer

160A, 160B: isolation structure

165A, 165B: Sacrificial gate structure

175A, 175B: sidewall spacer

180A, 180B: source/drain region

185: Dielectric layer

190A, 190B: gate cavity

195A, 195B: Replace gate structure

205A, 205B: contact opening

210A, 210B: source/drain contacts

The content of the embodiments of the present invention can be better understood through the following detailed description in conjunction with the accompanying drawings. It should be emphasized that according to industry standard practice, many parts are not drawn to scale. In fact, in order to be able to discuss clearly, the size of various components may be arbitrarily increased or decreased.

FIGS. 1-17 are schematic diagrams of semiconductor devices in various manufacturing stages according to some embodiments.

FIG. 18 is a schematic diagram of the semiconductor device after forming the first patterned mask according to some embodiments.

FIG. 19 is a schematic diagram of the semiconductor device after forming the first patterned mask according to some embodiments.

The following content provides many different embodiments or examples for implementing different components of the provided subject matter. Specific examples of components and configurations are described below to simplify the embodiments of the present invention. Of course, these are only examples and are not intended to limit the embodiments of the present invention. For example, if it is mentioned in the description that the first part is formed on or above the second part, it may include an embodiment in which the first and second parts are in direct contact, or may include additional parts formed on the first and second parts. Between, so that the first and second components do not directly contact the embodiment. In addition, the embodiments of the present invention may reuse reference numbers and/or letters in different examples. This repetition is for the purpose of simplification and clarity, and does not represent the different implementations discussed. There is a specific relationship between examples and/or configurations.

In addition, terms relative to space may be used, such as "below", "below", "below", "above", "above" and similar terms. The spatial relative terms are used to facilitate the description of the relationship between one element(s) or component(s) and another element(s) or component(s) as shown in the figure. In addition to the orientations described in the diagrams, these spatial relative terms are also used to include different orientations of devices in use or operation. When the device is turned in different directions (rotated by 90 degrees or other directions), the spatially relative adjectives used therein will also be interpreted according to the turned position.

Embodiments of the present invention provide one or more techniques for manufacturing semiconductor devices. In some embodiments, multiple film layers are provided above the film layer to be patterned. In some embodiments, the film layer to be patterned includes a semiconductor layer in which fins are to be formed. In some embodiments, the first layer is formed over the semiconductor layer. In some embodiments, a first patterned mask is formed over the first layer. In some embodiments, the first patterned mask includes elements corresponding to fins to be formed in the semiconductor layer. In some embodiments, a cyclic etching process is performed to define a second patterned mask in the first layer. In some embodiments, the cyclic etching process includes a first stage and a second stage. The first stage forms a polymer layer over the first patterned mask, and the second stage removes the polymer layer and removes a portion of the first layer. . In some embodiments, a second patterned mask is used to remove a portion of the semiconductor layer to define fins in the semiconductor layer. According to some embodiments, the cyclic etching process reduces the critical dimension (CD) variation, fin taper and line width roughness of the fin, and makes the depth of the fin more uniform.

FIGS. 1-17 are schematic diagrams of the semiconductor device 100 in various manufacturing stages according to some embodiments. Figures 1 to 16 include plan views showing various cross-sectional views. Referring to Figure 1, the schematic X-X is a cross-sectional view of the semiconductor device 100 in the direction corresponding to the length of the gate through the fin structure. The Y1-Y1 and Y2-Y2 schematic diagrams are cross-sectional views taken through the semiconductor device 100 in a direction corresponding to the gate width direction through the gate structure. Not all the processing aspects shown in the cross-sectional view are depicted in the plan view. In some embodiments, the device shown in the schematic diagram Y1-Y1 is formed in the first region 102A of the semiconductor device 100, and the device shown in the schematic diagram Y2-Y2 is formed in the second region 102B.

According to some embodiments, the regions (also called the first zone) 102A, (also called the second zone) 102B have different device densities. In some embodiments, the different densities result from different pitches, different critical fin sizes, or different fin array sizes. In some embodiments, as shown in FIG. 1, for example, the area 102A includes a dense area, and the area 102B includes a less dense area, sometimes referred to as an isolation area. In some embodiments, the area 102A includes a memory device. In some embodiments, area 102B contains logical devices.

Referring to FIG. 1, a plurality of film layers used in the formation of the semiconductor device 100 are illustrated according to some embodiments. In some embodiments, the semiconductor device 100 includes a fin-based transistor, such as a fin-type field effect transistor. In some embodiments, the semiconductor device includes a nano-chip-based transistor or a wrap-around gate transistor. A plurality of film layers are formed on the semiconductor layer 105. In some embodiments, the semiconductor layer 105 is a part of a substrate, and the substrate includes an epitaxial layer and a single crystal semiconductor material, such as but not limited to Si, Ge, SiGe, InGaAs, GaAs, InSb, GaP, GaSb, InAlAs, GaSbP, GaAsSb And InP, silicon-on-insulator (SOI) structure, wafer, or die formed from wafer. In some embodiments, the semiconductor layer 105 includes crystalline silicon.

In some embodiments, the first layer 110 is formed over the semiconductor layer 105. In some embodiments, the first layer 110 includes a fin-top hard mask. In some embodiments, the first The layer 110 includes silicon carbide nitride (SiCN) or other suitable hard mask materials. In some embodiments, the first layer 110 is formed by using, for example, chemical vapor deposition (CVD), plasma-enhanced CVD (PECVD), low pressure chemical vapor deposition ( low pressure CVD; LPCVD), ultrahigh vacuum CVD (UHVCVD), atomic layer chemical vapor deposition (ALCVD), physical vapor deposition (PVD), pulsed mine Pulsed laser deposition (PLD), sputtering, evaporative deposition, vapor phase epitaxy (VPE), molecular beam epitaxy (MBE), liquid phase At least one of liquid phase epitaxy (LPE), spin-on technology or other applicable technologies.

In some embodiments, the second layer 115 is formed over the first layer 110. In some embodiments, the second layer 115 includes a semiconductor layer, such as silicon or other suitable materials. In some embodiments, the second layer 115 is formed by using, for example, chemical vapor deposition, plasma-assisted chemical vapor deposition, low pressure chemical vapor deposition, ultra-high vacuum chemical vapor deposition, atomic layer chemical vapor deposition, At least one of physical vapor deposition, pulsed laser deposition, sputtering, vapor deposition deposition, vapor phase epitaxy, molecular beam epitaxy, liquid phase epitaxy, spin coating technology or other applicable technologies.

In some embodiments, the third layer 120 is formed over the second layer 115. In some embodiments, the third layer 120 includes a hard mask material, such as silicon nitride or other suitable materials. In some embodiments, the third layer 120 is formed by using, for example, chemical vapor deposition, plasma-assisted chemical vapor deposition, low pressure chemical vapor deposition, ultra-high vacuum chemical vapor deposition, atomic layer chemical vapor deposition, At least one of physical vapor deposition, pulsed laser deposition, sputtering, vapor deposition deposition, vapor phase epitaxy, molecular beam epitaxy, liquid phase epitaxy, spin coating technology or other applicable technologies.

In some embodiments, the fourth layer 125 is formed over the third layer 120. In some embodiments, the fourth layer 125 includes an oxide, such as silicon dioxide or other suitable oxides. In some embodiments, the fourth layer 125 is formed by using, for example, chemical vapor deposition, plasma-assisted chemical vapor deposition, low pressure chemical vapor deposition, ultra-high vacuum chemical vapor deposition, atomic layer chemical vapor deposition, At least one of physical vapor deposition, pulsed laser deposition, sputtering, vapor deposition deposition, vapor phase epitaxy, molecular beam epitaxy, liquid phase epitaxy, spin coating technology or other applicable technologies.

In some embodiments, the first patterned mask 130 is formed over the fourth layer 125. In some embodiments, the first patterned mask 130 includes a hard mask material, such as silicon nitride or other suitable hard mask materials. According to some embodiments, the first patterned mask 130 is formed by forming a plurality of separately formed film layers, which together define a mask stack. In some embodiments, the mask stack includes a hard mask layer formed above the fourth layer 125 by chemical vapor deposition, plasma assisted chemical vapor deposition, low pressure chemical vapor deposition, ultra-high vacuum chemical vapor Phase deposition, atomic layer chemical vapor deposition, physical vapor deposition, pulsed laser deposition, sputtering, vapor deposition deposition, vapor phase epitaxy, molecular beam epitaxy, liquid phase epitaxy, spin coating technology or other applicable technologies At least one technology. In some embodiments, the hard mask layer includes a hard mask material, such as silicon nitride or other suitable hard mask materials. In some embodiments, the mask stack includes a bottom antireflective coating (BARC) formed over the hard mask layer. In some embodiments, the bottom anti-reflective coating is a polymer layer applied using a spin coating process. In some embodiments, an organic planarization layer (OPL) is formed over the bottom anti-reflective coating. In some embodiments, the organic planarization layer includes a photosensitive organic polymer coated using a spin coating process. In some embodiments, the organic planarization layer includes a dielectric layer. According to some embodiments, the mask stack includes a photoresist formed over the organic planarization layer. In some embodiments, the photoresist is formed by at least one of spinning, spraying, or other suitable techniques. Photoresist package Contains electromagnetic radiation sensitive materials, and the properties of the photoresist (such as solubility) are affected by electromagnetic radiation. The photoresist layer is a negative photoresist or a positive photoresist. In some embodiments, by irradiating a portion of the organic planarization layer with electromagnetic radiation patterning the photoresist layer, the portion of the organic planarization layer is affected to change the irradiated portion of the organic planarization layer relative to the non-irradiated portion. Etching selectivity. In some embodiments, the photoresist is patterned, and one or more etching processes are performed to transfer the pattern to the hard mask layer, and the parts other than the hard mask layer in the mask stack are removed, resulting in a hard mask layer. The remaining portion of the mask layer defines the first patterned mask 130.

In some embodiments, the first patterned mask 130 includes elements 130A, 130B that define a pattern for forming fins in the semiconductor layer 105. In some embodiments, because the number of elements 130A per unit area in the first area 102A is different from the number of elements 130B per unit area in the second area 102B, the density of the elements 130A in the area 102A is greater than that in the area 102B. The density of 130B. In some embodiments, the density of the elements 130B in the area 102B is about 13% to about 82% of the density of the elements 130A in the area 102A.

In some embodiments, the distance 128 between the elements 130A in the first region 102A is different from the distance 129 between the elements 130B in the second region 102B. In some embodiments, the distance 128 of the element 130A in the first region 102A is about 8% to about 77% of the distance 129 of the element 130B in the second region 102B. In some embodiments, the distance 128 between the elements 130A in the first region 102A is about 16 nm to about 20 nm. In some embodiments, the distance 129 between the elements 130B in the second region 102B is about 26 nm to about 200 nm. In some embodiments, the distance 128 between the elements 130A in the first region 102A is the same as the distance 129 between the elements 130B in the second region 102B.

In some embodiments, the pitch 133 of the elements 130A in the first zone 102A is different from the pitch 134 of the elements 130B in the second zone 102B. In some embodiments, the elements in the first region 102A The pitch 133 of 130A is about 12% to about 84% of the pitch 134 of the element 130B in the second region 102B. In some embodiments, the pitch 133 of the elements 130A in the first region 102A is about 26 nm to about 30 nm. In some embodiments, the pitch 134 of the elements 130B in the second region 102B is about 36 nm to about 210 nm. In some embodiments, the pitch 133 of the elements 130A in the first zone 102A is the same as the pitch 134 between the elements 130B in the second zone 102B.

Referring to FIGS. 2 to 5, a cyclic etching process is performed to transfer the pattern defined by the first patterned mask 130 to the fourth layer 125. In some embodiments, the cyclic etching process includes a polymer deposition stage, as shown in FIGS. 2 and 4, and a material removal stage, as shown in FIGS. 3 and 5. In some embodiments, the process gas is changed during the cyclic etching process between the polymer deposition stage and the material removal stage. In some embodiments, other parameters can also be changed between the polymer deposition stage and the material removal stage. For example, the plasma power or bias can be changed between the polymer deposition stage and the material removal stage to control the degree of deposition or etching.

Referring to FIG. 2, during the polymer deposition stage, a polymer layer 135 is formed over the first patterned mask 130 and the fourth layer 125. In some embodiments, during the polymer deposition stage, _{at least one of oxygen (O 2} ), sulfur dioxide (SO ₂ ), fluorocarbon, or methane (CH ₄ ) is used as a process gas to form a process gas mixture. In some embodiments, the fluorocarbon is at least one _{of C 4} F ₆ , C ₂ F ₄ , CF ₄ or C _{5 F.} In some embodiments, oxygen and fluorocarbon are used as the process gas mixture. In some embodiments, during the polymer deposition stage, the flow rate of fluorocarbon or methane is about 40-60 standard cubic centimeters per minute (sccm). In some embodiments, during the polymer deposition stage, the flow rate of oxygen or sulfur dioxide is about 50-80 sccm. In some embodiments, the oxygen in the process gas mixture reacts with fluorocarbon or methane in an ambient plasma to form the polymer layer 135. In some embodiments, the polymer layer includes CH ₂ or CF _x , where x is an integer greater than or equal to one. In some embodiments, the polymer deposition stage includes an atomic layer deposition (ALD) process. In some embodiments, the thickness of the polymer layer 135 is specifically based on the time interval of the polymer deposition stage, the plasma power, and the bias voltage. In some embodiments, the time interval of the polymer deposition stage, the plasma power during the polymer deposition stage, and the bias voltage during the polymer deposition stage are set so that the thickness of the polymer layer 135 is 1~10 angstroms or 2~4 angstroms. Angstrom. In some embodiments, the time interval of the polymer deposition stage is about 5 seconds to about 10 seconds. In some embodiments, the plasma power during the polymer deposition stage is about 0W. In some embodiments, the bias voltage during the polymer deposition stage is about 70V to about 90V.

Referring to Figure 3, according to some embodiments, the polymer layer 135 and a portion of the fourth layer 125 are removed during the material removal stage. In some embodiments, an inert gas is used as the process gas during the material removal stage. In some embodiments, the inert gas is argon (Ar), nitrogen (N ₂ ), or other suitable gas. In some embodiments, the flow rate of the inert gas is about 550 to 600 sccm. In some embodiments, the amount of the fourth layer 125 removed during the material removal phase is based in particular on the time interval of the material removal phase, the plasma power, and the bias voltage. In some embodiments, the time interval of the material removal phase, the plasma power during the material removal phase, and the bias voltage during the material removal phase are set so that during the material removal phase, it is not located in the first patterned mask. The thickness 131 of the fourth layer 125 in one or more parts below 130 is reduced by about 10-20 angstroms. In some embodiments, the time interval of the material removal phase is about 5 seconds to about 10 seconds. In some embodiments, the plasma power during the material removal phase is greater than the plasma power during the polymer deposition phase. In some embodiments, the plasma power during the material removal phase is about 70W to about 90W. In some embodiments, the bias voltage during the material removal phase is greater than the bias voltage during the polymer deposition phase. In some embodiments, the bias voltage during the material removal phase is about 100V to about 120V.

In some embodiments, during the material removal phase, a part of the first patterned mask 130 is also removed. For example, during the material removal stage, the thickness 132 of the first patterned mask 130 or the elements of the first patterned mask 130 may be reduced by about 1-20 angstroms.

In some embodiments, in addition to the process gas, other process parameters are also changed between the polymer deposition stage and the material removal stage. For example, in some embodiments, plasma parameters are also changed between the polymer deposition stage and the material removal stage. In some embodiments, during the polymer deposition phase, the plasma power is high and the bias voltage is low. In some embodiments, during the material removal phase, the plasma power is low and the bias voltage is high. In some embodiments, the high plasma power is about 1000~3000W, and the low plasma power is about 300~500W. In some embodiments, the high bias voltage is about 500~1500V, and the low bias voltage is about 0~100V.

In some embodiments, a purge stage is included in the cyclic etching process between the polymer deposition stage and the material removal stage to allow the process gas to be changed between the polymer deposition stage and the material removal stage. In some embodiments, the semiconductor device 100 is placed in the chamber during the polymer deposition phase and the material removal phase, and during the purge phase, an inert gas (such as argon, nitrogen, or other suitable gas) is applied to This chamber is a chamber for purging process gas. In some embodiments, during the purge phase, no plasma power is provided and no bias is applied.

Referring to Figures 4 and 5, repeat the above-mentioned cyclic etching process. For example, in some embodiments, during the polymer deposition stage, the polymer layer 135 is again formed over the remaining first patterned mask 130 and the remaining fourth layer 125, as shown in FIG. 4. In some embodiments, as shown in FIG. 5, the polymer layer 135 and another part of the fourth layer 125 are removed during the material removal stage to further reduce the fourth layer that is not under the first patterned mask 130 The thickness of one or more parts of 125 is 131. In some embodiments, another part of the first patterned mask 130 is also removed during the material removal stage to The thickness 132 of the first patterned mask 130 is further reduced.

In some embodiments, the process parameters are kept constant during each polymer deposition stage, and are kept constant during each material removal stage. For example, the flow rate of the process gas applied during each polymer deposition stage, the time interval of each polymer deposition stage, the plasma power during each polymer deposition stage, and the amount of plasma during each polymer deposition stage The bias voltage can be the same. Similarly, the flow rate of the process gas applied during each material removal phase, the time interval of each material removal phase, the plasma power during each material removal phase, and the bias during each material removal phase The pressure can be the same. In some embodiments, one or more process parameters can be changed between polymer deposition stages, or one or more process parameters can be changed between material removal stages. For example, in some embodiments, when the fourth layer 125 is relatively thick, the flow rate of the process gas applied during the material removal phase, the time interval of the material removal phase, and the plasma during the material removal phase can be selected. The power, and the bias voltage during the material removal phase to remove the first amount or thickness of the fourth layer during each cycle in the material removal phase. In some embodiments, when the fourth layer 125 is thinner (that is, after several or more cycles), the process gas flow rate applied during the material removal phase, the time interval of the material removal phase, and the material The plasma power during the removal phase and the bias voltage during the material removal phase to remove the second amount or thickness of the fourth layer 125 during each cycle in the material removal phase. In some embodiments, the second number or thickness is less than the first number or thickness.

Referring to Fig. 6, according to some embodiments, the polymer deposition stage of Figs. 2 and 4 and the material removal stage of Figs. 3 and 5 are repeated in a cyclic manner until the fourth layer 125 is patterned to define a second patterning The mask 140 includes elements 140A and 140B. In some embodiments, the cyclic etching process is terminated in response to exposing the third layer 120. In some embodiments, the thickness of the first patterned mask 130 is provided so that the time spent on the first patterned mask 130 is about the same as that of removing the fourth layer 125. The etching process of the third layer 120 is exposed. Therefore, in some embodiments, at the end of the cyclic etching, the top surface of a portion of the fourth layer 125 under the elements 130A, 130B of the first patterned mask 130 is exposed. According to some embodiments, the number of cycles is changed according to the thickness of the fourth layer 125. In some embodiments, the number of cycles in the cyclic etching process is about 120 to 140 cycles.

In some embodiments, the cyclic etching process described with reference to FIGS. 2 to 5 preserves the width 140W1 of the element 140A and the width 140W2 of the element 140B. In some embodiments, the atomic layer deposition process used to form the polymer layer 135 provides a relatively thin polymer layer 135 that has a substantially uniform thickness in the first region 102A and the second region 102B. Conversely, if a thicker polymer layer is used, the polymer layer 135 can be in the middle of the first area 102A compared to the element 130A in the outer area of the first area 102A or the element 130B in the second area 102B. The element 130A exhibits a reduced thickness. In some embodiments, elements with a polymer layer of reduced thickness will be consumed at a greater rate, causing the different regions 102A, 102B to change width relative to the critical dimension and increased taper. In some embodiments, a cyclic etching process using a partially etched thin polymer layer 135 and a fourth layer 125 having a substantially uniform thickness during the material removal phase reduces the cross-area caused by the different densities of the regions 102A, 102B. 102A, 102B etching load. In some embodiments, the etch load across the regions 102A, 102B is less than or equal to about 2 nm. In some embodiments, the etch load across the regions 102A, 102B is less than or equal to about 1 nm. According to some embodiments, the cyclic etching process results in reduced fin taper and improved line width roughness.

Referring to FIG. 7, according to some embodiments, the third layer 120, the second layer 115, the first layer 110, and a portion of the semiconductor layer 105 are removed to form the fins 150A, 150B in the semiconductor layer 105. In some embodiments, the second patterned mask 140 is used as an etching template to perform an etching process to form the fins 150A and 150B. In some embodiments, the third layer 120, the second layer 115, and the first layer are etched After 110 and a part of the semiconductor layer 105, the second patterned mask 140 is removed. In some embodiments, due to the above-mentioned process of forming the second patterned mask 140, the average height 151 of the fins 150A with the first density of fins in the first region 102A and the average height 151 of the fins 150A in the second region 102B with the fins The difference between the average height 152 of the fins 150B of one density is less than or equal to 2 nanometers, or less than or equal to 1 nanometer.

In some embodiments, the remaining portions of the third layer 120, the second layer 115, and the first layer 110 define cap layers 155A, 155B on the upper surface of the fins 150A, 150B. Generally speaking, the fins 150A, 150B define an active area for forming devices such as fin-type field effect transistors.

Referring to FIG. 8, according to some embodiments, isolation structures 160A, 160B are formed between the fins 150A, 150B, respectively, and the cap layers 155A, 155B are removed. In some embodiments, the isolation structure 160A, 160B includes a shallow trench isolation (STI) structure. In some embodiments, the isolation structure 160A, 160B is formed by depositing a dielectric layer between the fins 150A, 150B, and etching the dielectric layer to expose at least a portion of the sidewalls of the fins 150A, 150B. It is hidden during the deposition of the dielectric layer. In some embodiments, the isolation structures 160A, 160B include silicon and oxygen or other suitable materials. In some embodiments, a portion of the isolation structure 160A separates the regions 102A, 102B. In some embodiments, one or more etching processes are performed to etch the dielectric layer and remove the cap layers 155A, 155B.

Referring to FIG. 9, according to some embodiments, sacrificial gate structures 165A, 165B are formed above the fins 150A, 150B and above the isolation structures 160A, 160B, respectively. In some embodiments, the sacrificial gate structures 165A, 165B include a gate dielectric layer and a sacrificial gate electrode (not shown separately). In some embodiments, the gate dielectric layer includes a high-k dielectric material. As used herein, the term "high-permittivity dielectric material" refers to a material having a dielectric constant (k) greater than or equal to about 3.9 (the dielectric constant value of _{SiO 2).} The material of the high-k dielectric layer can be any suitable material. Examples of materials for the high-k dielectric layer include, but are not limited to, Al ₂ O ₃ , HfO ₂ , ZrO ₂ , La ₂ O ₃ , TiO ₂ , SrTiO ₃ , LaAlO ₃ , Y ₂ O ₃ , Al ₂ O _x N _y , HfO _x N _y , ZrO _x N _y , La ₂ O _x N _y , TiO _x N _y , SrTiO _x N _y , LaAlO _x N _y , Y ₂ O _x N _y , SiON, SiN _x , the aforementioned silicic acid Salt, or the aforementioned alloys. Each value of x is independently 0.5 to 3, and each value of y is independently 0 to 2. In some embodiments, the gate dielectric layer includes a native oxide layer. The native oxide layer is formed by exposing the semiconductor device 100 to oxygen at various points in the process flow, so that the exposed surfaces of the fins 150A, 150B Forms silicon dioxide. In some embodiments, an additional layer of dielectric material (such as silicon dioxide or other suitable materials) is formed over the native oxide to form a gate dielectric layer. In some embodiments, the sacrificial gate electrode includes polysilicon.

According to some embodiments, the sacrificial gate structures 165A, 165B are formed by forming a sacrificial material and a hard mask layer over the fins 150A, 150B and the isolation structures 160A, 160B. In some embodiments, a patterning process is performed to pattern the hard mask layer, wherein the hard mask layer corresponds to the pattern of the gate structure to be formed, and the patterned hard mask layer is used for the etching process to etch the sacrifice The layers define the sacrificial gate structures 165A, 165B. In some embodiments, the remaining part of the hard mask layer forms cap layers 170A, 170B over the sacrificial gate electrodes of the sacrificial gate structures 165A, 165B.

Referring to FIG. 10, sidewall spacers 175A, 175B are formed adjacent to the sacrificial gate structures 165A, 165B, and after the sidewall spacers 175A, 175B are formed, they are formed in the fins 150A, 150B or above the fins 150A, 150B, respectively Source/drain regions 180A, 180B. In some embodiments, the sidewall spacers 175A, 175B are formed by depositing a spacer layer on the sacrificial gate structures 165A, 165B and performing an etching process (such as an anisotropic etching process or other suitable etching process) to remove A part of the spacer layer located on the horizontal plane of the isolation structure 160A, 160B, the fins 150A, 150B, and the cap layer 170A, 170B. In some embodiments, the sidewall spacers 175A, 175B include a cap layer 170A and 170B have the same material composition. In some embodiments, the sidewall spacers 175A, 175B include nitrogen and silicon or other suitable materials.

In some embodiments, the source/drain regions 180A, 180B are formed by etching the fins 150A, 150B adjacent to the sidewall spacers 175A, 175B, and performing an epitaxial growth process to form the source/drain regions. Drain regions 180A, 180B. In some embodiments, the source/drain regions 180A, 180B are doped in-situ during the epitaxial growth process. In some embodiments, the source/drain regions 180A, 180B are formed by implanting dopants into the fins 150A, 150B. In some embodiments, the source/drain regions 180A, 180B include a different silicon alloy than the fins 150A, 150B. For example, the fins 150A, 150B include silicon, and the source/drain regions 180A, 180B include silicon germanium, silicon tin, or other silicon alloys. In some embodiments, the source/drain regions 180A, 180B and the fins 150A, 150B are the same silicon alloy, but the concentration of the alloy material is between the source/drain regions 180A, 180B and the fins 150A, 150B different. For example, the concentration of the alloy material in the source/drain regions 180A, 180B may be greater than the concentration of the alloy material in the fins 150A, 150B.

Referring to FIG. 11, according to some embodiments, a dielectric layer 185 is formed on the fins 150A, 150B and adjacent to the sacrificial gate structures 165A, 165B. In some embodiments, a portion of the dielectric layer 185 is removed to expose the cap layers 170A, 170B. In some embodiments, the dielectric layer 185 is planarized to expose the capping layers 170A, 170B. In some embodiments, the dielectric layer 185 includes silicon dioxide or a low-k material. In some embodiments, the dielectric layer 185 includes one or more layers of low-k dielectric materials. The k value (dielectric constant) of the low-k dielectric material is less than about 3.9. Some low-permittivity dielectric materials have a dielectric constant value lower than about 3.5, and the dielectric constant value may be lower than about 2.5. In some embodiments, the dielectric layer 185 includes at least one of Si, O, C, or H, such as SiCOH and SiOC or other suitable materials. In some embodiments, organic materials such as polymers are used for the dielectric layer 185. In some embodiments Wherein, the dielectric layer 185 includes one or more layers of carbon-containing materials, organic silicate glass, porogen-containing materials, or a combination of the foregoing. In some embodiments, the dielectric layer 185 includes nitrogen. In some embodiments, the dielectric layer 185 may be formed by using, for example, at least one of plasma-assisted chemical vapor deposition, low pressure chemical vapor deposition, atomic layer chemical vapor deposition, or spin coating technology.

Referring to FIG. 12, according to some embodiments, the capping layers 170A, 170B are removed, and the heights of the sidewall spacers 175A, 175B and the dielectric layer 185 are reduced. In some embodiments, a planarization process is performed to remove the cap layers 170A, 170B and reduce the height of the sidewall spacers 175A, 175B and the dielectric layer 185. In some embodiments, the planarization process exposes the sacrificial gate structures 165A, 165B. In some embodiments, the planarization process is a continuation of the process performed to planarize the dielectric layer 185.

Referring to FIG. 13, according to some embodiments, the sacrificial gate structures 165A, 165B are removed to define the gate cavities 190A, 190B. In some embodiments, the gate dielectric layer and gate electrode material of the sacrificial gate structures 165A, 165B are removed, and a part of the fins 150A, 150B are exposed. In some embodiments, one or more etching processes are performed to remove the sacrificial gate structures 165A, 165B. In some embodiments, the etching process is a wet etching process that is selective to the materials of the sacrificial gate structures 165A and 165B.

Referring to FIG. 14, according to some embodiments, replacement gate structures 195A and 195B are formed in the gate cavities 190A and 190B, respectively. In some embodiments, the replacement gate structure 195A, 195B includes a gate dielectric layer. In some embodiments, the gate dielectric layer includes a high-k dielectric material. In some embodiments, due to exposure to oxygen at various points in the process flow, native oxide exists on the exposed surfaces of the fins 150A and 150B, and a gate dielectric layer is formed on the native oxide. In some embodiments, the natural oxide is removed before forming the gate dielectric layer. In some embodiments, a square shape function material layer is on the gate dielectric layer. In some embodiments, the work function material layer includes a p-type work function material layer, such as TiN, TaN, Ru, Mo, Al, WN, ZrSi ₂ , MoSi ₂ , TaSi ₂ , NiSi ₂ , WN or other suitable p-type At least one of the work function materials. In some embodiments, the work function material layer includes an n-type work function metal, such as at least one of Ti, Ag, TaAl, TaAlC, TiAlN, TaC, TaCN, TaSiN, Mn, Zr, or other suitable n-type work function materials . In some embodiments, the work function material layer includes multiple film layers. In some embodiments, the material of the work function material layer is changed between the regions 102A, 102B. For example, the work function material layer in one region 102A, 102B includes p-type work function metal, and the work function material layer in the other region 102A, 102B includes n-type work function material. In some embodiments, the first material of the work function material layer is formed in the two regions 102A and 102B. A mask layer is formed and patterned to expose the selected area 102B, and an etching process is performed to remove the first material of the work function material layer from the selected area 102B. Remove the mask layer, and square the second material of the work function material layer on the first material of the work function material layer. In some embodiments, removing the second material of the work function material layer from the area 102A removes the second material of the work function material layer from the area 102A by shielding the area 102B and performing an etching process. In some embodiments, the second material of the work function material layer remains in a position above the first material of the work function material layer.

In some embodiments, a conductive filling layer is formed over the work function material layer. In some embodiments, the conductive filling layer includes tungsten (W) or other suitable conductive materials.

Referring to FIG. 15, according to some embodiments, the gate structures 195A, 195B are replaced by etchback, and the capping layers 200A, 200B are formed over the replaced gate structures 195A, 195B. In some embodiments, an etching process is used to etch back the gate structures 195A and 195B. In some embodiments, a deposition process is used to form the cap layers 200A, 200B. In some embodiments, the capping layers 200A, 200B include a dielectric material. In some embodiments, the capping layers 200A, 200B include silicon and nitrogen, silicon and oxygen, or other suitable materials. In some embodiments, the cap layer 200A, 200B includes the same as the sidewall spacers 175A, 175B s material.

Referring to FIG. 16, according to some embodiments, contact openings 205A, 205B are formed in the dielectric layer 185 to expose a portion of the source/drain regions 180A, 180B, respectively. In some embodiments, a patterned etching mask is formed to expose a portion of the dielectric layer 185 where the contact openings 205A, 205B are to be formed. In some embodiments, a patterned etching mask is used to perform an etching process to remove a portion of the dielectric layer 185.

Referring to FIG. 17, according to some embodiments, source/drain contacts 210A, 210B are formed in the contact openings 205A, 205B. In some embodiments, a deposition process is performed to form source/drain contacts 210A, 210B. In some embodiments, the source/drain contacts 210A, 210B include metal silicide. In some embodiments, the source/drain contacts 210A, 210B are linear structures that extend substantially the entire length of the active region in a direction corresponding to the gate width direction of the device.

Referring to FIG. 18, another embodiment for forming a semiconductor device 200 is shown. The semiconductor device 200 is similar to the semiconductor device 100 shown in FIG. 1 except that the semiconductor device 200 does not include the first layer 110, the second layer 115, and the third layer 120. Therefore, the fourth layer 125 is formed directly on the semiconductor layer 105. The process described with reference to FIGS. 1-17 may be similar to forming the semiconductor device 200, so for the sake of brevity, this process will not be repeated.

Referring to FIG. 19, another embodiment for forming a semiconductor device 300 is shown. The semiconductor device 300 is similar to the semiconductor device 100 shown in FIG. 1 except that the semiconductor device 300 does not have the first layer 110 and the second layer 115. Therefore, the third layer 120 is formed directly on the semiconductor layer 105. In some embodiments, the third layer 120 has an etching stop function during the cyclic etching process, so as to alleviate the possibility of etching the semiconductor layer 105 during the cyclic etching process. The process described with reference to FIGS. 1-17 may be similar to forming the semiconductor device 300, so for the sake of brevity, this process will not be repeated.

Using a cyclic etching process including a first stage and a second stage, the polymer layer is formed over the first patterned mask in the first stage, and the polymer layer is removed in the second stage and the second patterned mask formed therein is removed. A part of the other layer of the mask protects the first patterned mask during the transfer of the pattern to the other film layer. Subsequently, a second patterned mask is used to define the fins in the semiconductor layer, so that the fins have reduced fin critical size variation and taper and improved line width roughness.

According to some embodiments, a method for forming a semiconductor device is provided. The method includes forming a first layer over the semiconductor layer, forming a first patterned mask over the first layer, and performing a cyclic etching process to define a second patterned mask in the first layer. Each cycle in the cyclic etching process includes a first stage and a second stage. The first stage forms a polymer layer above the first patterned mask, and the second stage removes the polymer layer and removes part of the first layer. And during the second stage of each cycle in the cyclic etching process, about 1 angstrom to about 20 angstrom of the first layer is removed. The method also includes using the second patterned mask to remove a portion of the semiconductor layer to define fins from the semiconductor layer.

According to some embodiments, a first process gas is used for the first stage, and a second process gas different from the first process gas is used for the second stage.

According to some embodiments, the first process gas includes fluorocarbon and oxygen.

According to some embodiments, the fluorocarbon is carbon hexafluoride.

According to some embodiments, the second process gas includes argon.

According to some embodiments, this method includes performing a purge phase between the first phase and the second phase.

According to some embodiments, the method includes forming a hard mask layer over the semiconductor layer before forming the first layer, and the forming of the first layer includes forming a first layer over the hard mask layer. This side The method also includes using a second patterned mask to remove a portion of the hard mask layer.

According to some embodiments, the hard mask layer is silicon carbide nitride.

According to some embodiments, the method includes forming a second layer over the hard mask layer before forming the first layer, and the forming of the first layer includes forming the first layer over the second layer. The method also includes terminating the cyclic etching process in response to exposing the second layer.

According to some embodiments, the second layer includes silicon.

According to some embodiments, this method includes using a second patterned mask to remove a portion of the second layer.

According to some embodiments, a method for forming a semiconductor device is provided. The method includes forming a first layer over the semiconductor layer, and forming a first patterned mask over the first layer. The first patterned mask includes the first elements in the first region and the second elements in the second region, and the density of the first elements in the first region is different from that of the second elements in the second region Density. The method also includes performing a cyclic etching process including about 120 cycles to about 140 cycles to define a second patterned mask in the first layer. Each cycle in the cyclic etching process includes a first stage and a second stage. The first stage forms a polymer layer over the first patterned mask, and the second stage removes the polymer layer and removes a part of the first layer . The second patterned mask includes a first element formed by the first part of the first layer located under the first element of the first patterned mask, and a first layer formed by the second element located under the second element of the first patterned mask The second part forms the second element. The method also includes using the second patterned mask to remove a portion of the semiconductor layer to define fins from the semiconductor layer. The first subset of fins is formed by the first part of the semiconductor layer under the first element of the second patterned mask, and the second subset of fins is formed by the second element of the second patterned mask The second part of the underlying semiconductor layer is formed.

According to some embodiments, the first process gas is used for the first stage, and the The second process gas, which is different from the first process gas, undergoes the second stage.

According to some embodiments, the first process gas includes at least one of oxygen and fluorocarbon or methane, and the second process gas includes an inert gas.

According to some embodiments, the first stage is performed using a first bias voltage, and the second stage is performed using a second bias voltage different from the first bias voltage.

According to some embodiments, the first stage is performed using a first plasma power, and the second stage is performed using a second plasma power different from the first plasma power.

According to some embodiments, this method includes performing a purge phase between the first phase and the second phase.

According to some embodiments, a semiconductor device is provided. The semiconductor device includes a first region having a first density of fins and a second region having a second density of fins different from the first density of fins. The second density is about 13% to about 82% of the first density, and the difference between the average height of the fins in the first zone and the average height of the fins in the second zone is less than or equal to 1 nanometer.

According to some embodiments, the first fin in the first region is separated from the second fin in the first region by a first distance, and the first fin in the second region is separated from the second fin in the second region The pieces are separated by a second distance different from the first distance.

The components of several embodiments are summarized above, so that those with ordinary knowledge in the technical field of the invention can better understand the aspect of the embodiments of the present invention. Those with ordinary knowledge in the technical field of the invention should understand that they can design or modify other processes and structures based on the embodiments of the present invention to achieve the same purpose as the various embodiments described herein and/or achieve The various embodiments presented have the same advantages. Those with ordinary knowledge in the technical field to which the invention belongs should also understand that such equivalent structures do not depart from the spirit and scope of the invention, and they can do so without departing from the spirit and scope of the invention. Surround yourself with all kinds of changes, substitutions and replacements.

Although the subject matter has been described in the language of specific structural components or method actions, it should be understood that the attached subject matter in the scope of the patent application is not limited to the above-mentioned specific components or actions. On the contrary, the specific components and actions described above are disclosed as exemplary forms implementing at least some of the patented scope.

Various operations of the embodiment are provided here. Describing some or all of the order of operations should not be interpreted as implying that these operations must be related to the order. It should be understood that this description can produce the order of substitutions. In addition, it should be understood that not all operations must be present in every embodiment provided herein. In addition, it should be understood that in some embodiments, not all operations are necessary.

It should be understood that, in some embodiments, for example, for the purpose of simplicity and ease of understanding, the film layers, components, elements, etc. herein are depicted in a manner having specific dimensions (such as structural dimensions or orientation) relative to each other, and Their actual sizes are substantially different from those shown here. In addition, for example, there are multiple technologies for forming the film layers, regions, components, elements, etc. mentioned herein, such as etching technology, planarization technology, implantation technology, doping technology, spin coating technology, sputtering technology , Growth technology, or deposition technology (such as chemical vapor deposition) at least one.

In addition, "exemplary" is used herein to mean as an example, instance, explanation, etc., and is not necessarily advantageous. As used in this manual, "or" is used to mean an inclusive "or" rather than an exclusive "or". In addition, "a" and "an" used in the scope of this specification and the appended patent applications are usually interpreted as referring to "one or more" unless otherwise stated or clearly pointing to the singular form from the content. Moreover, at least one of A and B and/or the like generally represents A or B or both. In addition, to a certain extent, the terms "include", "have", "have", "with" or the foregoing variations are used in an inclusive way, similar to the term "include". In addition, unless otherwise stated, "first", "second" or similar terms are not used to imply time Surface, spatial aspect, order, etc. On the contrary, such terms only serve as identification symbols, names, etc. of parts, elements, items, and the like. For example, the first element and the second element generally correspond to the element A and the element B or two different elements or two identical elements or the same element.

In addition, although the embodiments of the present invention have been shown and described with respect to one or more embodiments, based on the reading and understanding of this specification and the accompanying drawings, those with ordinary knowledge in the technical field to which the invention belongs will think of equivalent changes and modifications. . The embodiments of the present invention include all such modifications and changes, and the embodiments of the present invention are only limited by the scope of the attached patent application. Especially with regard to the various functions performed by the above-mentioned components (such as elements, resources, etc.), even if they are not structurally equivalent to the disclosed structure, unless otherwise specified, the terms used to describe such components are used to correspond to the performance of the components. Any component of the specified function of the component (e.g., functionally equivalent). In addition, although a specific component of an embodiment of the present invention may have been disclosed for only one of several embodiments, because it may be desirable and advantageous for any given or specific application, such components can be combined with other One or more other components of the embodiment are combined.

100: Semiconductor device

102A: District 1

102B: Second District

105: semiconductor layer

150A, 150B: fins

160A: isolation structure

175A, 175B: sidewall spacer

180A, 180B: source/drain region

185: Dielectric layer

195A, 195B: Replace gate structure

200A, 200B: cover layer

210A, 210B: source/drain contacts

Claims (13)

A method for manufacturing a semiconductor device includes: forming a first layer above a semiconductor layer; forming a first patterned mask above the first layer; performing a cyclic etching process to define a first layer in the first layer Two patterned masks, wherein: each cycle in the cyclic etching process includes a first stage and a second stage, the first stage forms a polymer layer above the first patterned mask, and the second stage The polymer layer is removed in two stages and a part of the first layer is removed. During the second stage of each cycle in the cyclic etching process, about 1 angstrom to about 20 angstrom of the first layer is removed, And cyclically performing each cycle of the cyclic etching process until the bottom of the first layer is exposed; and using the second patterned mask to remove a part of the semiconductor layer to define a fin from the semiconductor layer. The method of manufacturing a semiconductor device according to claim 1, wherein: a first process gas is used to perform the first stage, and a second process gas different from the first process gas is used to perform the second stage. The method for manufacturing a semiconductor device according to claim 2, wherein the first process gas includes fluorocarbon and oxygen. The method for manufacturing a semiconductor device according to claim 3, wherein the fluorocarbon is carbon hexafluoride. For example, the method for manufacturing a semiconductor device according to any one of claims 1 to 4 includes: A blow-off stage is performed between the first stage and the second stage. The method for manufacturing a semiconductor device according to any one of claims 1 to 4, comprising: before forming the first layer, forming a hard mask layer over the semiconductor layer, wherein the formation of the first layer includes The first layer is formed over the mask layer, and the second patterned mask is used to remove a part of the hard mask layer. The method of manufacturing a semiconductor device according to claim 6, comprising: before forming the first layer, forming a second layer above the hard mask layer, wherein the forming of the first layer includes forming the first layer above the second layer. The first layer; and the cyclic etching process is terminated in response to exposing the second layer. The method for manufacturing a semiconductor device according to claim 7, wherein the second layer includes silicon. According to claim 7, the method for manufacturing a semiconductor device includes: using the second patterned mask to remove a part of the second layer. A method for manufacturing a semiconductor device includes: forming a first layer above a semiconductor layer; forming a first patterned mask above the first layer, wherein: the first patterned mask includes a first region A plurality of first elements in and a plurality of second elements in a second area, and the density of the first elements in the first area is different from that of the second elements in the second area A cyclic etching process including about 120 cycles to about 140 cycles is performed to define a second patterned mask in the first layer, wherein: each cycle in the cyclic etching process includes a first A stage and a second stage, the first stage The section forms a polymer layer above the first patterned mask, and the second stage removes the polymer layer and removes a part of the first layer, and repeats each cycle of the cyclic etching process until exposed The bottom of the first layer, and the second patterned mask includes a plurality of first elements formed by a first portion of the first layer under the first elements of the first patterned mask, and A plurality of second elements formed by a second portion of the first layer under the second elements of the first patterned mask; and the plurality of semiconductor layers are removed using the second patterned mask Portions to define a plurality of fins from the semiconductor layer, wherein a first subset of the fins is formed by a first portion of the semiconductor layer under the first elements of the second patterned mask And a second subset of the fins is formed by a second part of the semiconductor layer under the second element of the second patterned mask. The method for manufacturing a semiconductor device according to claim 10, wherein: a first process gas is used to perform the first stage, and a second process gas different from the first process gas is used to perform the second stage. The method for manufacturing a semiconductor device according to claim 11, wherein: the first process gas includes at least one of oxygen, fluorocarbon or methane, and the second process gas includes an inert gas. The method for manufacturing a semiconductor device according to any one of claims 10 to 12, wherein the first stage is performed using a first bias voltage and/or a first plasma power, and a different voltage from the first bias voltage is used The second stage is performed with a second bias voltage and/or a second plasma power different from the first plasma power.

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