TW202029280A - Semiconductor device and method of manufacturing the same - Google Patents
Semiconductor device and method of manufacturing the same Download PDFInfo
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- TW202029280A TW202029280A TW108142445A TW108142445A TW202029280A TW 202029280 A TW202029280 A TW 202029280A TW 108142445 A TW108142445 A TW 108142445A TW 108142445 A TW108142445 A TW 108142445A TW 202029280 A TW202029280 A TW 202029280A
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Abstract
Description
本發明實施例是關於半導體製造技術,特別是有關於半導體裝置及其製造方法。The embodiments of the present invention are related to semiconductor manufacturing technology, and particularly to semiconductor devices and manufacturing methods thereof.
隨著半導體產業向奈米技術製程節點(nodes)發展以追求更高的裝置密度、更高的效能和更低的成本,來自製造和設計兩方面的問題的挑戰造成三維設計的發展,例如鰭式場效電晶體(fin-like field effect transistor;FinFET)和環繞式閘極(gate all around;GAA)電晶體。鰭式場效電晶體包含延伸的半導體鰭片,其大致上沿著垂直於基底的頂表面的平面的方向在基底上方升高。在這個鰭片中形成鰭式場效電晶體的通道。在鰭片上方提供並部分地包覆鰭片。環繞式閘極電晶體包含一或多個奈米片(nano-sheet)通道區,其具有圍繞奈米片的閘極。鰭式場效電晶體和環繞式閘極電晶體可以降低短通道效應(short channel effect)。As the semiconductor industry develops towards nanotechnology process nodes (nodes) in pursuit of higher device density, higher performance and lower costs, challenges from both manufacturing and design issues have led to the development of three-dimensional design, such as fins. Fin-like field effect transistor (FinFET) and gate all around (GAA) transistor. The fin-type field effect transistor includes an extended semiconductor fin that rises above the substrate substantially in a direction perpendicular to the plane of the top surface of the substrate. In this fin, a channel for the fin field effect transistor is formed. Provide and partially cover the fin above the fin. The wrap-around gate transistor contains one or more nano-sheet channel regions, which have a gate surrounding the nano-sheet. Fin-type field-effect transistors and wrap-around gate transistors can reduce short channel effects.
根據本發明實施例中的一些實施例,提供半導體裝置的製造方法。此方法包含:在半導體層上方形成第一層;在第一層上方形成第一圖案化遮罩;以及進行循環蝕刻製程以在第一層中界定第二圖案化遮罩,其中:循環蝕刻製程中的每個循環包含第一階段和第二階段,第一階段在第一圖案化遮罩上方形成聚合物層,且第二階段移除聚合物層並移除第一層的一部分,以及在循環蝕刻製程中的每個循環的第二階段期間,移除第一層的約1埃至約20埃;以及使用第二圖案化遮罩移除半導體層的一部分以從半導體層界定鰭片。According to some of the embodiments of the present invention, a method of manufacturing a semiconductor device is provided. The method includes: forming a first layer over the semiconductor layer; forming a first patterned mask over the first layer; and performing a cyclic etching process to define a second patterned mask in the first layer, wherein: the cyclic etching process Each cycle in includes a first stage and a second stage. The first stage forms a polymer layer over the first patterned mask, and the second stage removes the polymer layer and removes part of the first layer, and During the second stage of each cycle in the cyclic etching process, about 1 angstrom to about 20 angstrom of the first layer is removed; and a second patterned mask is used to remove a portion of the semiconductor layer to define fins from the semiconductor layer.
根據本發明實施例中的另一些實施例,提供半導體裝置的製造方法。此方法包含:在半導體層上方形成第一層;在第一層上方形成第一圖案化遮罩,其中:第一圖案化遮罩包含在第一區中的複數個第一元件以及在第二區中的複數個第二元件,以及在第一區中的所述第一元件的密度不同於在第二區中的所述第二元件的密度;進行包含約120個循環至約140個循環的循環蝕刻製程,以在第一層中界定第二圖案化遮罩,其中:循環蝕刻製程中的每個循環包含第一階段和第二階段,第一階段在第一圖案化遮罩上方形成聚合物層,且第二階段移除聚合物層並移除第一層的一部分,以及第二圖案化遮罩包含由位於第一圖案化遮罩的所述第一元件下方的第一層的第一部分形成的複數個第一元件以及由位於第一圖案化遮罩的所述第二元件下方的第一層的第二部分形成的複數個第二元件;以及使用第二圖案化遮罩移除半導體層的複數個部分以從半導體層界定複數個鰭片,其中所述鰭片的第一子集係由位於第二圖案化遮罩的所述第一元件下方的半導體層的第一部分形成,且所述鰭片的第二子集係由位於第二圖案化遮罩的第二元件下方的半導體層的第二部分形成。According to some other embodiments of the embodiments of the present invention, methods for manufacturing semiconductor devices are provided. The method includes: forming a first layer over the semiconductor layer; forming a first patterned mask over the first layer, wherein: the first patterned mask includes a plurality of first elements in the first region and the second A plurality of second elements in the zone, and the density of the first elements in the first zone is different from the density of the second elements in the second zone; performing about 120 cycles to about 140 cycles The cyclic etching process to define a second patterned mask in the first layer, wherein: each cycle in the cyclic etching process includes a first stage and a second stage, and the first stage is formed above the first patterned mask The polymer layer, and the second stage removes the polymer layer and removes a part of the first layer, and the second patterned mask includes the first layer of the first patterned mask under the first element A plurality of first elements formed by the first part and a plurality of second elements formed by the second part of the first layer under the second element of the first patterned mask; and the second patterned mask is used to move The plurality of portions of the semiconductor layer are removed to define a plurality of fins from the semiconductor layer, wherein the first subset of the fins is formed by the first portion of the semiconductor layer under the first element of the second patterned mask And the second subset of the fins is formed by the second part of the semiconductor layer under the second element of the second patterned mask.
根據本發明實施例中的又另一些實施例,提供半導體裝置。此半導體裝置包含:具有鰭片的第一密度的第一區以及具有與鰭片的第一密度不同之鰭片的第二密度的第二區,其中:第二密度是第一密度的約13%至約82%,以及第一區中的鰭片的平均高度與第二區中的鰭片的平均高度之間的差小於或等於1奈米。According to still other embodiments of the embodiments of the present invention, semiconductor devices are provided. This semiconductor device includes: a first region having a first density of fins and a second region having a second density of fins different from the first density of fins, wherein the second density is about 13 of the first density % To about 82%, and the difference between the average height of the fins in the first zone and the average height of the fins in the second zone is less than or equal to 1 nanometer.
以下內容提供了許多不同的實施例或範例,用於實施所提供的標的之不同部件。組件和配置的具體範例描述如下,以簡化本發明實施例。當然,這些僅僅是範例,並非用以限定本發明實施例。舉例來說,敘述中若提及第一部件形成於第二部件上或上方,可能包含形成第一和第二部件直接接觸的實施例,也可能包含額外的部件形成於第一和第二部件之間,使得第一和第二部件不直接接觸的實施例。此外,本發明實施例在不同範例中可重複使用參考數字及/或字母,此重複是為了簡化和清楚之目的,並非代表所討論的不同實施例及/或組態之間有特定的關係。The following content provides many different embodiments or examples for implementing different components of the provided subject matter. Specific examples of components and configurations are described below to simplify the embodiments of the present invention. Of course, these are only examples and are not intended to limit the embodiments of the present invention. For example, if the description mentions that the first part is formed on or above the second part, it may include an embodiment where the first and second parts are in direct contact, or may include additional parts formed on the first and second parts. In between, an embodiment in which the first and second components are not in direct contact. In addition, the embodiments of the present invention may reuse reference numbers and/or letters in different examples. The repetition is for the purpose of simplification and clarity, and does not represent a specific relationship between the different embodiments and/or configurations discussed.
此外,其中可能用到與空間相對用語,例如「在……之下」、「在……下方」、「下方的」、「在……上方」、「上方的」及類似的用詞,這些空間相對用語係為了便於描述如圖所示之一個(些)元件或部件與另一個(些)元件或部件之間的關係。除了圖式中所描述的方位,這些空間相對用語也用於包含使用中或操作中的裝置之不同方位。當裝置被轉向不同方位時(旋轉90度或其他方位),則其中所使用的空間相對形容詞也將依轉向後的方位來解釋。In addition, terms relative to space may be used, such as "below", "below", "below", "above", "above" and similar terms. Spatial relative terms are used to facilitate the description of the relationship between one element or component(s) and another element(s) or component as shown in the figure. In addition to the orientations described in the diagrams, these spatial relative terms are also used to include different orientations of devices in use or operation. When the device is turned in different directions (rotated by 90 degrees or other directions), the spatially relative adjectives used in it will also be interpreted according to the turned position.
本發明實施例提供一或多種用於製造半導體裝置的技術。在一些實施例中,在要圖案化的膜層上方提供多個膜層。在一些實施例中,要圖案化的膜層包含要在其中形成鰭片的半導體層。在一些實施例中,在半導體層上方形成第一層。在一些實施例中,在第一層上方形成第一圖案化遮罩。在一些實施例中,第一圖案化遮罩包含對應於要在半導體層中形成的鰭片的元件。在一些實施例中,進行循環蝕刻製程以在第一層中界定第二圖案化遮罩。在一些實施例中,循環蝕刻製程包含第一階段和第二階段,第一階段在第一圖案化遮罩上方形成聚合物層,第二階段移除聚合物層並移除第一層的一部分。在一些實施例中,使用第二圖案化遮罩移除半導體層的一部分以在半導體層中界定鰭片。根據一些實施例,循環蝕刻製程降低鰭片臨界尺寸(critical dimension;CD)變化、鰭片錐度(tapering)和線寬粗糙度,並使鰭片的深度更均勻。Embodiments of the present invention provide one or more techniques for manufacturing semiconductor devices. In some embodiments, multiple film layers are provided above the film layer to be patterned. In some embodiments, the film layer to be patterned includes a semiconductor layer in which fins are to be formed. In some embodiments, the first layer is formed over the semiconductor layer. In some embodiments, a first patterned mask is formed over the first layer. In some embodiments, the first patterned mask includes elements corresponding to fins to be formed in the semiconductor layer. In some embodiments, a cyclic etching process is performed to define a second patterned mask in the first layer. In some embodiments, the cyclic etching process includes a first stage and a second stage. The first stage forms a polymer layer over the first patterned mask, and the second stage removes the polymer layer and part of the first layer. . In some embodiments, a second patterned mask is used to remove a portion of the semiconductor layer to define fins in the semiconductor layer. According to some embodiments, the cyclic etching process reduces the critical dimension (CD) variation of the fins, fin taper (tapering) and line width roughness, and makes the depth of the fins more uniform.
第1~17圖是根據一些實施例的各個製造階段之半導體裝置100的示意圖。第1~16圖包含繪示截取各種剖面圖的平面圖。參照第1圖, X-X示意圖是在對應於經由鰭片結構的閘極長度方向的方向上經由半導體裝置100截取的剖面圖,而Y1-Y1和Y2-Y2示意圖是在對應於經由閘極結構的閘極寬度方向的方向上經由半導體裝置100截取的剖面圖。並未在平面圖中描繪所有剖面圖所示之處理的面向。在一些實施例中, Y1-Y1示意圖所示之裝置形成於半導體裝置100的第一區102A中,而Y2-Y2示意圖所示之裝置形成於第二區102B中。FIGS. 1-17 are schematic diagrams of the
根據一些實施例,區域(又稱為第一區)102A、(又稱為第二區)102B具有不同的裝置密度。在一些實施例中,不同的密度來自於不同的節距(pitches)、不同的鰭片臨界尺寸或不同的鰭片陣列尺寸。在一些實施例中,例如第1圖所示,區域102A包含密集區域,而區域102B包含較不密集的區域,有時稱為隔離區。在一些實施例中,區域102A包含記憶體裝置。在一些實施例中,區域102B包含邏輯裝置。According to some embodiments, the regions (also called the first zone) 102A, (also called the second zone) 102B have different device densities. In some embodiments, the different densities result from different pitches, different critical fin sizes, or different fin array sizes. In some embodiments, such as shown in Figure 1, the
參照第1圖,根據一些實施例繪示在半導體裝置100的形成中使用的多個膜層。在一些實施例中,半導體裝置100包含以鰭片為主的電晶體,例如鰭式場效電晶體。在一些實施例中,半導體裝置包含以奈米片為主的電晶體或環繞式閘極電晶體。在半導體層105上方形成多個膜層。在一些實施例中,半導體層105是基底的一部分,基底包含磊晶層、單晶半導體材料,例如但不限於Si、Ge、SiGe、InGaAs、GaAs、InSb、GaP、GaSb、InAlAs、GaSbP、GaAsSb和InP、絕緣體上覆矽(silicon-on-insulator;SOI)結構、晶圓、或由晶圓形成的晶粒(die)。在一些實施例中,半導體層105包含結晶矽。Referring to FIG. 1, a plurality of film layers used in the formation of the
在一些實施例中,在半導體層105上方形成第一層110。在一些實施例中,第一層110包含鰭片頂部(fin-top)硬遮罩。在一些實施例中,第一層110包含氮碳化矽(SiCN)或其他合適的硬遮罩材料。在一些實施例中,第一層110的形成藉由使用例如化學氣相沉積(chemical vapor deposition;CVD)、電漿輔助化學氣相沉積(plasma-enhanced CVD;PECVD)、低壓化學氣相沉積(low pressure CVD;LPCVD)、超高真空化學氣相沉積(ultrahigh vacuum CVD;UHVCVD)、原子層化學氣相沉積(atomic layer CVD;ALCVD)、物理氣相沉積(physical vapor deposition;PVD)、脈衝雷射沉積(pulsed laser deposition;PLD)、濺鍍(sputtering)、蒸鍍沉積(evaporative deposition)、氣相磊晶(vapor phase epitaxy;VPE)、分子束磊晶(molecular beam epitaxy;MBE)、液相磊晶(liquid phase epitaxy;LPE)、旋塗(spin-on)技術或其他適用技術中的至少一種。In some embodiments, the
在一些實施例中,在第一層110上方形成第二層115。在一些實施例中,第二層115包含半導體層,例如矽或其他合適的材料。在一些實施例中,第二層115的形成藉由使用例如化學氣相沉積、電漿輔助化學氣相沉積、低壓化學氣相沉積、超高真空化學氣相沉積、原子層化學氣相沉積、物理氣相沉積、脈衝雷射沉積、濺射、蒸鍍沉積、氣相磊晶、分子束磊晶、液相磊晶、旋塗技術或其他適用的技術中的至少一種。In some embodiments, the
在一些實施例中,在第二層115上方形成第三層120。在一些實施例中,第三層120包含硬遮罩材料,例如氮化矽或其他合適的材料。在一些實施例中,第三層120的形成藉由使用例如化學氣相沉積、電漿輔助化學氣相沉積、低壓化學氣相沉積、超高真空化學氣相沉積、原子層化學氣相沉積、物理氣相沉積、脈衝雷射沉積、濺射、蒸鍍沉積、氣相磊晶、分子束磊晶、液相磊晶、旋塗技術或其他適用的技術中的至少一種。In some embodiments, the
在一些實施例中,在第三層120上方形成第四層125。在一些實施例中,第四層125包含氧化物,例如二氧化矽或其他合適的氧化物。在一些實施例中,第四層125的形成藉由使用例如化學氣相沉積、電漿輔助化學氣相沉積、低壓化學氣相沉積、超高真空化學氣相沉積、原子層化學氣相沉積、物理氣相沉積、脈衝雷射沉積、濺射、蒸鍍沉積、氣相磊晶、分子束磊晶、液相磊晶、旋塗技術或其他適用的技術中的至少一種。In some embodiments, the
在一些實施例中,在第四層125上方形成第一圖案化遮罩130。在一些實施例中,第一圖案化遮罩130包含硬遮罩材料,例如氮化矽或其他合適的硬遮罩材料。根據一些實施例,第一圖案化遮罩130的形成藉由形成多個單獨形成的膜層,這些膜層共同界定遮罩堆疊。在一些實施例中,遮罩堆疊包含在第四層125上方形成的硬遮罩層,其藉由化學氣相沉積、電漿輔助化學氣相沉積、低壓化學氣相沉積、超高真空化學氣相沉積、原子層化學氣相沉積、物理氣相沉積、脈衝雷射沉積、濺射、蒸鍍沉積、氣相磊晶、分子束磊晶、液相磊晶、旋塗技術或其他適用技術中的至少一種技術。在一些實施例中,硬遮罩層包含硬遮罩材料,例如氮化矽或其他合適的硬遮罩材料。在一些實施例中,遮罩堆疊包含在硬遮罩層上方形成的底部抗反射塗層(bottom antireflective coating;BARC)。在一些實施例中,底部抗反射塗層是使用旋塗製程塗佈的聚合物層。在一些實施例中,在底部抗反射塗層上方形成有機平坦化層(organic planarization layer;OPL)。在一些實施例中,有機平坦化層包含使用旋塗製程塗佈的光敏有機聚合物。在一些實施例中,有機平坦化層包含介電層。根據一些實施例,遮罩堆疊包含在有機平坦化層上方形成的光阻。在一些實施例中,光阻的形成藉由旋轉、噴塗或其他適用技術中的至少一種。光阻包含電磁輻射敏感材料,並且光阻的性質(例如溶解度)受電磁輻射影響。光阻層是負光阻或正光阻。在一些實施例中,藉由使光阻層圖案化的電磁輻射照射有機平坦化層的一部分,有機平坦化層的所述部分被影響以相對於非照射部分改變有機平坦化層的照射部分的蝕刻選擇性。在一些實施例中,將光阻圖案化,以及進行一或多個蝕刻製程以將圖案轉移至硬遮罩層,並移除遮罩堆疊中的硬遮罩層之外的部分,產生由硬遮罩層的保留部分界定之第一圖案化遮罩130。In some embodiments, the first
在一些實施例中,第一圖案化遮罩130包含元件130A、130B,其界定用於在半導體層105中形成鰭片的圖案。在一些實施例中,因為第一區102A中每單位面積的元件130A的數量不同於第二區102B中每單位面積的元件130B的數量,區域102A中的元件130A的密度大於區域102B中的元件130B的密度。在一些實施例中,區域102B中的元件130B的密度為區域102A中的元件130A的密度之約13%至約82%。In some embodiments, the first
在一些實施例中,第一區102A中的元件130A之間的距離128不同於第二區102B中的元件130B之間的距離129。在一些實施例中,第一區102A中的元件130A的距離128為第二區102B中的元件130B的距離129之約8%至約77%。在一些實施例中,第一區102A中的元件130A之間的距離128為約16 nm至約20 nm。在一些實施例中,第二區102B中的元件130B之間的距離129為約26 nm至約200 nm。在一些實施例中,第一區102A中的元件130A之間的距離128與第二區102B中的元件130B之間的距離129相同。In some embodiments, the
在一些實施例中,第一區102A中的元件130A的節距133不同於第二區102B中的元件130B的節距134。在一些實施例中,第一區102A中的元件130A的節距133為第二區102B中的元件130B的節距134之約12%至約84%。在一些實施例中,第一區102A中的元件130A的節距133為約26 nm至約30 nm。在一些實施例中,第二區102B中的元件130B的節距134為約36 nm至約210 nm。在一些實施例中,第一區102A中的元件130A的節距133與第二區102B中的元件130B之間的節距134相同。In some embodiments, the
參照第2~5圖,進行循環蝕刻製程以將由第一圖案化遮罩130界定的圖案轉移到第四層125。在一些實施例中,循環蝕刻製程包含聚合物沉積階段,如第2和4圖所示,以及材料移除階段,如第3和5圖所示。在一些實施例中,在聚合物沉積階段和材料移除階段之間的循環蝕刻製程中改變製程氣體。在一些實施例中,也可以在聚合物沉積階段和材料移除階段之間改變其他參數。舉例來說,可以在聚合物沉積階段和材料移除階段之間改變電漿功率或偏壓,以控制沉積或蝕刻的程度。Referring to FIGS. 2 to 5, a cyclic etching process is performed to transfer the pattern defined by the first
參照第2圖,在聚合物沉積階段期間,在第一圖案化遮罩130和第四層125上方形成聚合物層135。在一些實施例中,在聚合物沉積階段期間,氧氣(O2
)、二氧化硫(SO2
)、氟碳化物(fluorocarbon)或甲烷(CH4
)中的至少一種作為製程氣體以形成製程氣體混合物。在一些實施例中,氟碳化物是C4
F6
、C2
F4
、CF4
或C5
F中的至少一種。在一些實施例中,氧氣和氟碳化物作為製程氣體混合物。在一些實施例中,在聚合物沉積階段期間,氟碳化物或甲烷的流速為約40~60標準立方公分每分鐘(sccm)。在一些實施例中,在聚合物沉積階段期間,氧氣或二氧化硫的流率為約50~80 sccm。在一些實施例中,製程氣體混合物中的氧氣與氟碳化物或甲烷在環境電漿中反應以形成聚合物層135。在一些實施例中,聚合物層包含CH2
或CFx
,其中x是大於或等於1的整數。在一些實施例中,聚合物沉積階段包含原子層沉積(atomic layer deposition;ALD)製程。在一些實施例中,聚合物層135的厚度特別是基於聚合物沉積階段的時間間隔、電漿功率和偏壓。在一些實施例中,設定聚合物沉積階段的時間間隔、聚合物沉積階段期間的電漿功率以及聚合物沉積階段期間的偏壓,使得聚合物層135的厚度為1~10埃或2~4埃。在一些實施例中,聚合物沉積階段的時間間隔為約5秒至約10秒。在一些實施例中,在聚合物沉積階段期間的電漿功率為約0 W。在一些實施例中,在聚合物沉積階段期間的偏壓為約70 V至約90 V。Referring to Figure 2, during the polymer deposition stage, a
參照第3圖,根據一些實施例,在材料移除階段期間移除聚合物層135和第四層125的一部分。在一些實施例中,在材料移除階段期間,惰性氣體作為製程氣體。在一些實施例中,惰性氣體是氬氣(Ar)、氮氣(N2
)或其他合適的氣體。在一些實施例中,惰性氣體的流速為約550~600 sccm。在一些實施例中,在材料移除階段期間移除的第四層125的量特別是基於材料移除階段的時間間隔、電漿功率和偏壓。在一些實施例中,設定材料移除階段的時間間隔、材料移除階段期間的電漿功率以及材料移除階段期間的偏壓,使得在材料移除階段期間,不位於第一圖案化遮罩130下方的一或多個部分的第四層125的厚度131降低約10~20埃。在一些實施例中,材料移除階段的時間間隔為約5秒至約10秒。在一些實施例中,在材料移除階段期間的電漿功率大於在聚合物沉積階段期間的電漿功率。在一些實施例中,在材料移除階段期間的電漿功率為約70 W至約90 W。在一些實施例中,材料移除階段期間的偏壓大於聚合物沉積階段期間的偏壓。在一些實施例中,在材料移除階段期間的偏壓為約100 V至約120 V。Referring to Figure 3, according to some embodiments, the
在一些實施例中,在材料移除階段期間,也移除第一圖案化遮罩130的一部分。舉例來說,在材料移除階段期間,第一圖案化遮罩130或第一圖案化遮罩130的元件的厚度132可以降低約1~20埃。In some embodiments, during the material removal phase, a portion of the first
在一些實施例中,除了製程氣體之外,也在聚合物沉積階段和材料移除階段之間改變製程的其他參數。舉例來說,在一些實施例中,也在聚合物沉積階段和材料移除階段之間改變電漿參數。在一些實施例中,在聚合物沉積階段期間,電漿功率高且偏壓低。在一些實施例中,在材料移除階段期間,電漿功率低且偏壓高。在一些實施例中,高電漿功率為約1000~3000 W,且低電漿功率為約300~500 W。在一些實施例中,高偏壓為約500~1500 V,且低偏壓為約0~100 V。In some embodiments, in addition to the process gas, other process parameters are also changed between the polymer deposition stage and the material removal stage. For example, in some embodiments, plasma parameters are also changed between the polymer deposition phase and the material removal phase. In some embodiments, during the polymer deposition phase, the plasma power is high and the bias voltage is low. In some embodiments, during the material removal phase, the plasma power is low and the bias voltage is high. In some embodiments, the high plasma power is about 1000-3000 W, and the low plasma power is about 300-500 W. In some embodiments, the high bias voltage is about 500-1500 V, and the low bias voltage is about 0-100 V.
在一些實施例中,在聚合物沉積階段和材料移除階段之間的循環蝕刻製程中包含吹淨(purge)階段,以允許在聚合物沉積階段和材料移除階段之間改變製程氣體。在一些實施例中,在聚合物沉積階段和材料移除階段期間將半導體裝置100設置在腔室中,在吹淨階段期間,將惰性氣體(例如氬氣、氮氣或其他合適的氣體)施加到此腔室以吹淨製程氣體的腔室。在一些實施例中,在吹淨階段期間,不提供電漿功率且不施加偏壓。In some embodiments, a purge stage is included in the cyclic etching process between the polymer deposition stage and the material removal stage to allow the process gas to be changed between the polymer deposition stage and the material removal stage. In some embodiments, the
參照第4和5圖,重複上述循環蝕刻製程。舉例來說,在一些實施例中,在聚合物沉積階段期間,在剩餘的第一圖案化遮罩130和剩餘的第四層125上方再次形成聚合物層135,如第4圖所示。在一些實施例中,如第5圖所示,在材料移除階段期間移除聚合物層135和第四層125的另一部分,以進一步降低不在第一圖案化遮罩130下方的第四層125的一或多個部分的厚度131。在一些實施例中,材料移除階段期間也移除第一圖案化遮罩130的另一部分,以進一步降低第一圖案化遮罩130的厚度132。Referring to Figures 4 and 5, repeat the above cyclic etching process. For example, in some embodiments, during the polymer deposition stage, the
在一些實施例中,製程參數在每個聚合物沉積階段期間保持恆定,並且在每個材料移除階段期間保持恆定。舉例來說,在每個聚合物沉積階段期間施加的製程氣體的流速、每個聚合物沉積階段的時間間隔、每個聚合物沉積階段期間的電漿功率、以及每個聚合物沉積階段期間的偏壓可以是相同的。類似地,在每個材料移除階段期間施加的製程氣體的流速、每個材料移除階段的時間間隔、每個材料移除階段期間的電漿功率、以及每個材料移除階段期間的偏壓可以是相同的。在一些實施例中,可以在聚合物沉積階段之間改變、或者可以在材料移除階段之間改變一或多個製程參數。舉例來說,在一些實施例中,當第四層125相對厚時,可以選擇在材料移除階段期間施加的製程氣體的流速、材料移除階段的時間間隔、材料移除階段期間的電漿功率、以及材料移除階段期間的偏壓,以在材料移除階段中的每個循環期間移除第四層的第一數量或厚度。在一些實施例中,當第四層125較薄時(亦即,在數次或多次循環之後),可以選擇材料移除階段期間施加的製程氣體流速、材料移除階段的時間間隔、材料移除階段期間的電漿功率、以及材料移除階段期間的偏壓,以在材料移除階段中的每個循環期間移除第四層125的第二數量或厚度。在一些實施例中,第二數量或厚度小於第一數量或厚度。In some embodiments, the process parameters remain constant during each polymer deposition stage, and remain constant during each material removal stage. For example, the flow rate of the process gas applied during each polymer deposition stage, the time interval of each polymer deposition stage, the plasma power during each polymer deposition stage, and the The bias voltage can be the same. Similarly, the flow rate of the process gas applied during each material removal phase, the time interval of each material removal phase, the plasma power during each material removal phase, and the bias during each material removal phase The pressure can be the same. In some embodiments, one or more process parameters may be changed between polymer deposition stages, or may be changed between material removal stages. For example, in some embodiments, when the
參照第6圖,根據一些實施例,以循環方式重複第2和4圖的聚合物沉積階段以及第3和5圖的材料移除階段,直到將第四層125圖案化以界定第二圖案化遮罩140,其包含元件140A、140B。在一些實施例中,對於暴露出第三層120的回應終止循環蝕刻製程。在一些實施例中,提供第一圖案化遮罩130的厚度,使得消耗第一圖案化遮罩130的時間大約相同於藉由移除第四層125來暴露出第三層120的蝕刻製程。因此,在一些實施例中,在循環蝕刻結束時,暴露出在第一圖案化遮罩130的元件130A、130B下方的第四層125的一部分的頂表面。根據一些實施例,根據第四層125的厚度來改變循環數。在一些實施例中,循環蝕刻製程中的循環數為約120~140個循環。Referring to FIG. 6, according to some embodiments, the polymer deposition stage of FIGS. 2 and 4 and the material removal stage of FIGS. 3 and 5 are repeated in a cyclic manner until the
在一些實施例中,參照第2~5圖描述的循環蝕刻製程保留了元件140A的寬度140W1和元件140B的寬度140W2。在一些實施例中,用於形成聚合物層135的原子層沉積製程提供了相對薄的聚合物層135,其在第一區102A和第二區102B中具有大致上均勻的厚度。相反地,如果使用較厚的聚合物層,則相較於第一區102A的外部區域中的元件130A或位於第二區102B中的元件130B,聚合物層135可以在第一區102A的中間的元件130A上表現出降低的厚度。在一些實施例中,具有降低的厚度的聚合物層的元件將以較大的速率被消耗,使得不同區域102A、102B相對於臨界尺寸和增加的錐度改變寬度。在一些實施例中,在材料移除階段期間使用具有大致上均勻厚度的薄聚合物層135和第四層125的部分蝕刻的循環蝕刻製程降低由區域102A、102B的不同密度引起之橫跨區域102A、102B的蝕刻負荷。在一些實施例中,橫跨區域102A、102B的蝕刻負荷小於或等於約2 nm。在一些實施例中,橫跨區域102A、102B的蝕刻負荷小於或等於約1 nm。根據一些實施例,循環蝕刻製程造成降低的鰭片錐度和改善的線寬粗糙度。In some embodiments, the cyclic etching process described with reference to FIGS. 2 to 5 preserves the width 140W1 of the
參照第7圖,根據一些實施例,移除第三層120、第二層115、第一層110和半導體層105的一部分以在半導體層105中形成鰭片150A、150B。在一些實施例中,使用第二圖案化遮罩140作為蝕刻模板來進行蝕刻製程以形成鰭片150A、150B。在一些實施例中,在蝕刻第三層120、第二層115、第一層110和半導體層105的一部分之後,移除第二圖案化遮罩140。在一些實施例中,由於上述形成第二圖案化遮罩140的製程,第一區102A中具有鰭片的第一密度之鰭片150A的平均高度151與第二區102B中具有鰭片的第一密度之鰭片150B的平均高度152之間的差小於或等於2奈米、或者小於或等於1奈米。Referring to FIG. 7, according to some embodiments, the
在一些實施例中,第三層120、第二層115和第一層110的剩餘部分在鰭片150A、150B的上表面上界定蓋層155A、155B。通常而言,鰭片150A、150B界定用於形成例如鰭式場效電晶體的裝置的主動區。In some embodiments, the remaining portions of the
參照第8圖,根據一些實施例,分別在鰭片150A、150B之間形成隔離結構160A、160B,並且移除蓋層155A、155B。在一些實施例中,隔離結構160A、160B包含淺溝槽隔離(shallow trench isolation;STI)結構。在一些實施例中,隔離結構160A、160B的形成藉由在鰭片150A、150B之間沉積介電層,並且凹蝕介電層以暴露出鰭片150A、150B的側壁的至少一部分,此側壁在沉積介電層時被隱藏。在一些實施例中,隔離結構160A、160B包含矽和氧或其他合適的材料。在一些實施例中,隔離結構160A的一部分隔開區域102A、102B。在一些實施例中,進行一或多個蝕刻製程以凹蝕介電層並移除蓋層155A、155B。Referring to FIG. 8, according to some embodiments,
參照第9圖,根據一些實施例,分別在鰭片150A、150B上方和隔離結構160A、160B上方形成犧牲閘極結構165A、165B。在一些實施例中,犧牲閘極結構165A、165B包含閘極介電層和犧牲閘極電極(未分別繪示)。在一些實施例中,閘極介電層包含高介電常數介電材料。如本文使用的,用語「高介電常數介電材料」指的是介電常數(k)大於或等於約3.9(SiO2
的介電常數值)的材料。高介電常數介電層的材料可以是任何合適的材料。高介電常數介電層的材料的範例包含但不限於Al2
O3
、HfO2
、ZrO2
、La2
O3
、TiO2
、SrTiO3
、LaAlO3
、Y2
O3
、Al2
Ox
Ny
、HfOx
Ny
、ZrOx
Ny
、La2
Ox
Ny
、TiOx
Ny
、SrTiOx
Ny
、LaAlOx
Ny
、Y2
Ox
Ny
、SiON、SiNx
、前述之矽酸鹽、或前述之合金。x的每個值獨立地為0.5至3,並且y的每個值獨立地為0至2。在一些實施例中,閘極介電層包含原生氧化物層,原生氧化物層的形成藉由在製程流程的各個點將半導體裝置100的暴露於氧,使得在鰭片150A、150B的露出表面上形成二氧化矽。在一些實施例中,在原生氧化物上方形成介電材料的額外層(例如二氧化矽或其他合適的材料)以形成閘極介電層。在一些實施例中,犧牲閘極電極包含多晶矽。Referring to FIG. 9, according to some embodiments,
根據一些實施例,藉由在鰭片150A、150B和隔離結構160A、160B上方形成一層犧牲材料和硬遮罩層來形成犧牲閘極結構165A、165B。在一些實施例中,進行圖案化製程以將硬遮罩層圖案化,其中硬遮罩層對應於將要形成的閘極結構的圖案,並且使用圖案化的硬遮罩層進行蝕刻製程以蝕刻犧牲層以界定犧牲閘極結構165A、165B。在一些實施例中,硬遮罩層的剩餘部分在犧牲閘極結構165A、165B的犧牲閘極電極上方形成蓋層170A、170B。According to some embodiments, the
參照第10圖,形成側壁間隔物175A、175B分別鄰近犧牲閘極結構165A、165B,並且在形成側壁間隔物175A、175B之後,分別在鰭片150A、150B中或在鰭片150A、150B上方形成源極/汲極區180A、180B。在一些實施例中,側壁間隔物175A、175B的形成藉由在犧牲閘極結構165A、165B上方沉積間隔層並進行蝕刻製程(例如非等向性蝕刻製程或其他合適的蝕刻製程)以移除位於隔離結構160A、160B、鰭片150A、150B和蓋層170A、170B的水平面上的間隔層的一部分。在一些實施例中,側壁間隔物175A、175B包含與蓋層170A、170B相同的材料組成。在一些實施例中,側壁間隔物175A、175B包含氮和矽或其他合適的材料。Referring to FIG. 10,
在一些實施例中,源極/汲極區180A、180B的形成藉由進行蝕刻製程以凹蝕鄰近側壁間隔物175A、175B的鰭片150A、150B,並且進行磊晶成長製程以形成源極/汲極區180A、180B。在一些實施例中,在磊晶成長製程期間原位(in-situ)摻雜源極/汲極區180A、180B。在一些實施例中,源極/汲極區180A、180B的形成藉由將摻質佈植至鰭片150A、150B中。在一些實施例中,源極/汲極區180A、180B包含與鰭片150A、150B不同的矽合金。舉例來說,鰭片150A、150B包含矽,且源極/汲極區180A、180B包含矽鍺、矽錫或其他矽合金。在一些實施例中,源極/汲極區180A、180B和鰭片150A、150B是相同的矽合金,但是合金材料的濃度在源極/汲極區180A、180B和鰭片150A、150B之間不同。舉例來說,源極/汲極區180A、180B中的合金材料的濃度可以大於鰭片150A、150B中的合金材料的濃度。In some embodiments, the source/
參照第11圖,根據一些實施例,在鰭片150A、150B上方形成介電層185並鄰近犧牲閘極結構165A、165B。在一些實施例中,移除介電層185的一部分以暴露出蓋層170A、170B。在一些實施例中,將介電層185平坦化以暴露出蓋層170A、170B。在一些實施例中,介電層185包含二氧化矽或低介電常數材料。在一些實施例中,介電層185包含一或多層低介電常數介電材料。低介電常數介電材料的k值(介電常數)低於約3.9。一些低介電常數介電材料的介電常數值低於約3.5,並且介電常數值可以低於約2.5。在一些實施例中,介電層185包含Si、O、C或H中的至少一種,例如SiCOH和SiOC或其他合適的材料。在一些實施例中,例如聚合物的有機材料用於介電層185。在一些實施例中,介電層185包含一或多層含碳材料、有機矽酸鹽玻璃、含致孔劑(porogen)的材料或前述之組合。在一些實施例中,介電層185包含氮。在一些實施例中,介電層150的形成可以藉由使用例如電漿輔助化學氣相沉積、低壓化學氣相沉積、原子層化學氣相沉積或旋塗技術中的至少一種。Referring to FIG. 11, according to some embodiments, a
參照第12圖,根據一些實施例,移除蓋層170A、170B,並且降低側壁間隔物175A、175B和介電層185的高度。在一些實施例中,進行平坦化製程以移除蓋層170A、170B並降低側壁間隔物175A、175B和介電層185的高度。在一些實施例中,平坦化製程暴露出犧牲閘極結構165A、165B。在一些實施例中,平坦化製程是進行以平坦化介電層185的製程的延續。Referring to FIG. 12, according to some embodiments, the capping layers 170A, 170B are removed, and the heights of the sidewall spacers 175A, 175B and the
參照第13圖,根據一些實施例,移除犧牲閘極結構165A、165B以界定閘極腔190A、190B。在一些實施例中,移除犧牲閘極結構165A、165B的閘極介電層和閘極電極材料,並且暴露出鰭片150A、150B的一部分。在一些實施例中,進行一或多個蝕刻製程以移除犧牲閘極結構165A、165B。在一些實施例中,蝕刻製程是對犧牲閘極結構165A、165B的材料具有選擇性的濕式蝕刻製程。Referring to FIG. 13, according to some embodiments, the
參照第14圖,根據一些實施例,分別在閘極腔190A、190B中形成取代閘極結構195A、195B。在一些實施例中,取代閘極結構195A、195B包含閘極介電層。在一些實施例中,閘極介電層包含高介電常數介電材料。在一些實施例中,由於在製程流程中的各個點暴露於氧氣,所以在鰭片150A、150B的露出表面上存在原生氧化物,並且在原生氧化物上方形成閘極介電層。在一些實施例中,在形成閘極介電層之前移除自然氧化物。在一些實施例中,在閘極介電層上方形成功函數材料層。在一些實施例中,功函數材料層包含p型功函數材料層,例如TiN、TaN、Ru、Mo、Al、WN、ZrSi2
、MoSi2
、TaSi2
、NiSi2
、WN或其他合適的p型功函數材料中的至少一個。在一些實施例中,功函數材料層包含n型功函數金屬,例如Ti、Ag、TaAl、TaAlC、TiAlN、TaC、TaCN、TaSiN、Mn、Zr或其他合適的n型功函數材料中的至少一個。在一些實施例中,功函數材料層包含多個膜層。在一些實施例中,在區域102A、102B之間改變功函數材料層的材料。舉例來說,一個區域102A、102B中的功函數材料層包含p型功函數金屬,而另一區域102A、102B中的功函數材料層包含n型功函數材料。在一些實施例中,功函數材料層的第一材料形成於兩區域102A、102B中。形成遮罩層並將遮罩層圖案化以暴露出選擇的區域102B,並且進行蝕刻製程以從選擇的區域102B移除功函數材料層的第一材料。移除遮罩層,並且在功函數材料層的第一材料上方形成功函數材料層的第二材料。在一些實施例中,從區域102A移除功函數材料層的第二材料藉由遮蔽區域102B並進行蝕刻製程以從區域102A移除功函數材料層的第二材料。在一些實施例中,功函數材料層的第二材料保持在功函數材料層的第一材料上方的位置。Referring to FIG. 14, according to some embodiments,
在一些實施例中,在功函數材料層上方形成導電填充層。在一些實施例中,導電填充層包含鎢(W)或其他合適的導電材料。In some embodiments, a conductive filling layer is formed over the work function material layer. In some embodiments, the conductive filling layer includes tungsten (W) or other suitable conductive materials.
參照第15圖,根據一些實施例,凹蝕取代閘極結構195A、195B,並且在取代閘極結構195A、195B上方形成蓋層200A、200B。在一些實施例中,使用蝕刻製程凹蝕取代閘極結構195A、195B。在一些實施例中,使用沉積製程形成蓋層200A、200B。在一些實施例中,蓋層200A、200B包含介電材料。在一些實施例中,蓋層200A、200B包含矽和氮、矽和氧、或其他合適的材料。在一些實施例中,蓋層200A、200B包含與側壁間隔物175A、175B相同的材料。Referring to FIG. 15, according to some embodiments, the
參照第16圖,根據一些實施例,在介電層185中形成接觸開口205A、205B以分別暴露出源極/汲極區180A、180B的一部分。在一些實施例中,形成圖案化的蝕刻遮罩以暴露出介電層185之要形成接觸開口205A、205B的一部分。在一些實施例中,使用圖案化蝕刻遮罩進行蝕刻製程以移除介電層185的一部分。Referring to FIG. 16, according to some embodiments,
參照第17圖,根據一些實施例,在接觸開口205A、205B中形成源極/汲極接觸件210A、210B。在一些實施例中,進行沉積製程以形成源極/汲極接觸件210A、210B。在一些實施例中,源極/汲極接觸件210A、210B包含金屬矽化物。在一些實施例中,源極/汲極接觸件210A、210B是線型結構,其在對應於裝置的閘極寬度方向的方向上在主動區的大致上整個長度上延伸。Referring to FIG. 17, according to some embodiments, source/drain contacts 210A, 210B are formed in the
參照第18圖,繪示用於形成半導體裝置200的另一實施例。半導體裝置200類似於第1圖所示的半導體裝置100,除了半導體裝置200不存在第一層110、第二層115和第三層120。因此,第四層125直接形成於半導體層105上。參照第1~17圖所描述的製程可以類似於形成半導體裝置200,因此為簡潔起見,將不重複此製程。Referring to FIG. 18, another embodiment for forming a
參照第19圖,繪示用於形成半導體裝置300的另一實施例。半導體裝置300類似於第1圖所示的半導體裝置100,除了半導體裝置300不存在第一層110和第二層115。因此,第三層120直接形成於半導體層105上。在一些實施例中,第三層120在循環蝕刻製程期間具有蝕刻停止的作用,以緩解在循環蝕刻製程期間蝕刻半導體層105的可能性。參照第1~17圖所描述的製程可以類似於形成半導體裝置300,因此為簡潔起見,將不重複此製程。Referring to FIG. 19, another embodiment for forming a
使用包含第一階段和第二階段的循環蝕刻製程,第一階段在第一圖案化遮罩上方形成聚合物層,且第二階段移除聚合物層並移除其中形成有第二圖案化遮罩的另一層的一部分,在將圖案轉移至其他膜層期間保護第一圖案化遮罩。隨後,使用第二圖案化遮罩以在半導體層中界定鰭片,使得鰭片具有降低的鰭片臨界尺寸變化和錐度以及改善的線寬粗糙度。Using a cyclic etching process including a first stage and a second stage, the polymer layer is formed over the first patterned mask in the first stage, and the polymer layer is removed in the second stage and the second patterned mask formed therein is removed. A part of the other layer of the mask protects the first patterned mask during the transfer of the pattern to the other film layer. Subsequently, a second patterned mask is used to define the fins in the semiconductor layer, so that the fins have reduced fin critical size variation and taper and improved line width roughness.
根據一些實施例,提供一種用於形成半導體裝置的方法。此方法包含在半導體層上方形成第一層、在第一層上方形成第一圖案化遮罩、以及進行循環蝕刻製程以在第一層中界定第二圖案化遮罩。循環蝕刻製程中的每個循環包含第一階段和第二階段,第一階段在第一圖案化遮罩上方形成聚合物層,第二階段移除聚合物層並移除第一層的一部分,以及在循環蝕刻製程中的每個循環的第二階段期間,移除第一層的約1埃至約20埃。此方法還包含使用第二圖案化遮罩移除半導體層的一部分以從半導體層界定鰭片。According to some embodiments, a method for forming a semiconductor device is provided. The method includes forming a first layer over the semiconductor layer, forming a first patterned mask over the first layer, and performing a cyclic etching process to define a second patterned mask in the first layer. Each cycle in the cyclic etching process includes a first stage and a second stage. The first stage forms a polymer layer above the first patterned mask, and the second stage removes the polymer layer and part of the first layer. And during the second stage of each cycle in the cyclic etching process, about 1 angstrom to about 20 angstrom of the first layer is removed. This method also includes using the second patterned mask to remove a portion of the semiconductor layer to define the fin from the semiconductor layer.
根據一些實施例,使用第一製程氣體進行第一階段,以及使用與第一製程氣體不同的第二製程氣體進行第二階段。According to some embodiments, a first process gas is used for the first stage, and a second process gas different from the first process gas is used for the second stage.
根據一些實施例,第一製程氣體包含氟碳化物和氧氣。According to some embodiments, the first process gas includes fluorocarbon and oxygen.
根據一些實施例,氟碳化物是六氟化碳(carbon hexafluoride)。According to some embodiments, the fluorocarbon is carbon hexafluoride.
根據一些實施例,第二製程氣體包含氬氣。According to some embodiments, the second process gas includes argon.
根據一些實施例,此方法包含在第一階段和第二階段之間進行吹淨階段。According to some embodiments, this method includes performing a purge phase between the first phase and the second phase.
根據一些實施例,此方法包含在形成第一層之前,在半導體層上方形成硬遮罩層,並且第一層的形成包含在硬遮罩層上方形成第一層。此方法還包含使用第二圖案化遮罩來移除硬遮罩層的一部分。According to some embodiments, the method includes forming a hard mask layer over the semiconductor layer before forming the first layer, and the forming of the first layer includes forming a first layer over the hard mask layer. This method also includes using a second patterned mask to remove a portion of the hard mask layer.
根據一些實施例,硬遮罩層是氮碳化矽。According to some embodiments, the hard mask layer is silicon carbide nitride.
根據一些實施例,此方法包含在形成第一層之前,在硬遮罩層上方形成第二層,並且第一層的形成包含在第二層上方形成第一層。此方法還包含對暴露出第二層回應而終止循環蝕刻製程。According to some embodiments, the method includes forming a second layer over the hard mask layer before forming the first layer, and the forming of the first layer includes forming the first layer over the second layer. The method also includes terminating the cyclic etching process in response to exposing the second layer.
根據一些實施例,第二層包含矽。According to some embodiments, the second layer includes silicon.
根據一些實施例,此方法包含使用第二圖案化遮罩移除第二層的一部分。According to some embodiments, this method includes using a second patterned mask to remove a portion of the second layer.
根據一些實施例,提供一種用於形成半導體裝置的方法。此方法包含在半導體層上方形成第一層、以及在第一層上方形成第一圖案化遮罩。第一圖案化遮罩包含在第一區中的第一元件以及在第二區中的第二元件,以及在第一區中的第一元件的密度不同於在第二區中的第二元件的密度。此方法還包含進行包含約120個循環至約140個循環的循環蝕刻製程,以在第一層中界定第二圖案化遮罩。循環蝕刻製程中的每個循環包含第一階段和第二階段,第一階段在第一圖案化遮罩上方形成聚合物層,且第二階段移除聚合物層並移除第一層的一部分。第二圖案化遮罩包含由位於第一圖案化遮罩的第一元件下方的第一層的第一部分形成的第一元件以及由位於第一圖案化遮罩的第二元件下方的第一層的第二部分形成的第二元件。此方法還包含使用第二圖案化遮罩移除半導體層的一部分以從半導體層界定鰭片。鰭片的第一子集係由位於第二圖案化遮罩的第一元件下方的半導體層的第一部分形成,並且鰭片的第二子集係由位於第二圖案化遮罩的第二元件下方的半導體層的第二部分形成。According to some embodiments, a method for forming a semiconductor device is provided. The method includes forming a first layer over the semiconductor layer, and forming a first patterned mask over the first layer. The first patterned mask includes first elements in the first area and second elements in the second area, and the density of the first elements in the first area is different from that of the second elements in the second area Density. The method also includes performing a cyclic etching process including about 120 cycles to about 140 cycles to define a second patterned mask in the first layer. Each cycle in the cyclic etching process includes a first stage and a second stage. The first stage forms a polymer layer above the first patterned mask, and the second stage removes the polymer layer and removes a part of the first layer . The second patterned mask includes a first element formed by the first part of the first layer under the first element of the first patterned mask and a first layer formed by the second element under the first patterned mask The second part forms the second element. This method also includes using the second patterned mask to remove a portion of the semiconductor layer to define the fin from the semiconductor layer. The first subset of fins is formed by the first part of the semiconductor layer under the first element of the second patterned mask, and the second subset of fins is formed by the second element of the second patterned mask The second part of the underlying semiconductor layer is formed.
根據一些實施例,使用第一製程氣體進行第一階段,以及使用與第一製程氣體不同的第二製程氣體進行第二階段。According to some embodiments, a first process gas is used for the first stage, and a second process gas different from the first process gas is used for the second stage.
根據一些實施例,第一製程氣體包含氧氣和氟碳化物或甲烷中的至少一種,且第二製程氣體包含惰性氣體。According to some embodiments, the first process gas includes at least one of oxygen and fluorocarbon or methane, and the second process gas includes an inert gas.
根據一些實施例,使用第一偏壓進行第一階段,且使用與第一偏壓不同的第二偏壓進行第二階段。According to some embodiments, the first stage is performed using a first bias voltage, and the second stage is performed using a second bias voltage different from the first bias voltage.
根據一些實施例,使用第一電漿功率進行第一階段,且使用與第一電漿功率不同的第二電漿功率進行第二階段。According to some embodiments, the first stage is performed using a first plasma power, and the second stage is performed using a second plasma power different from the first plasma power.
根據一些實施例,此方法包含在第一階段和第二階段之間進行吹淨階段。According to some embodiments, this method includes performing a purge phase between the first phase and the second phase.
根據一些實施例,提供一種半導體裝置。半導體裝置包含具有鰭片的第一密度的第一區以及具有與鰭片的第一密度不同之鰭片的第二密度的第二區。第二密度是第一密度的約13%至約82%,以及第一區中的鰭片的平均高度與第二區中的鰭片的平均高度之間的差小於或等於1奈米。According to some embodiments, a semiconductor device is provided. The semiconductor device includes a first region having a first density of fins and a second region having a second density of fins different from the first density of fins. The second density is about 13% to about 82% of the first density, and the difference between the average height of the fins in the first zone and the average height of the fins in the second zone is less than or equal to 1 nanometer.
根據一些實施例,第一區中的第一鰭片與第一區中的第二鰭片以第一距離隔開,以及第二區中的第一鰭片與第二區中的第二鰭片以不同於第一距離之第二距離隔開。According to some embodiments, the first fin in the first region is separated from the second fin in the first region by a first distance, and the first fin in the second region is separated from the second fin in the second region The pieces are separated by a second distance different from the first distance.
以上概述數個實施例之部件,使得在發明所屬技術領域中具有通常知識者可以更加理解本發明實施例的面向。發明所屬技術領域中具有通常知識者應該理解,他們能以本發明實施例為基礎,設計或修改其他製程和結構,以實現與在此介紹的各種實施例相同之目的及/或達到與在此介紹的各種實施例相同之優勢。發明所屬技術領域中具有通常知識者也應該理解到,此類等效的結構並未悖離本發明的精神與範圍,且他們能在不違背本發明之精神和範圍下,做各式各樣的改變、取代和置換。The components of the several embodiments are summarized above, so that those with ordinary knowledge in the technical field of the invention can better understand the aspects of the embodiments of the invention. Those with ordinary knowledge in the technical field of the invention should understand that they can design or modify other processes and structures based on the embodiments of the present invention to achieve the same purpose as the various embodiments introduced herein and/or achieve The various embodiments presented have the same advantages. Those with ordinary knowledge in the technical field to which the invention belongs should also understand that such equivalent structures do not depart from the spirit and scope of the invention, and they can do various things without departing from the spirit and scope of the invention. Changes, substitutions and replacements.
雖然已用特定結構部件或方法動作的語言描述標的,但應理解的是,後附的申請專利範圍的標的不限於上述特定部件或動作。相反地,上述特定部件和動作被揭示為實施至少一些申請專利範圍的範例形式。Although the subject matter has been described in the language of specific structural components or method actions, it should be understood that the attached subject matter in the scope of the patent application is not limited to the specific components or actions described above. On the contrary, the specific components and actions described above are disclosed as example forms implementing at least some of the patented scope.
在此提供實施例的各種操作。描述一些或所有操作順序不應解釋為暗示這些操作必定與順序有關。應理解此描述可產生的替代的順序。此外,應理解的是,並非在此提供的每個實施例中必須存在所有操作。另外,應理解的是,在一些實施例中,並非所有操作都是必需的。Various operations of the embodiment are provided here. Describing some or all of the order of operations should not be interpreted as implying that these operations must be related to the order. It should be understood that this description can produce the order of substitutions. Furthermore, it should be understood that not all operations must be present in every embodiment provided herein. In addition, it should be understood that in some embodiments, not all operations are necessary.
應理解的是,在一些實施例中,例如出於簡化和易於理解的目的,以具有相對於彼此的特定尺寸(例如結構尺寸或取向)的方式描繪本文的膜層、部件、元件等,且它們的實際尺寸實質上不同於在此所繪示的。另外,舉例來說,存在用於形成本文提及的膜層、區域、部件、元件等的多種技術,例如蝕刻技術、平坦化技術、佈植技術、摻雜技術、旋塗技術、濺鍍技術、成長技術、或沉積技術(例如化學氣相沉積)中的至少一種。It should be understood that, in some embodiments, for example, for the purpose of simplicity and ease of understanding, the film layers, components, elements, etc. herein are depicted in a manner having specific dimensions (such as structural dimensions or orientation) relative to each other, and Their actual sizes are substantially different from those shown here. In addition, for example, there are multiple technologies for forming the film layers, regions, components, elements, etc. mentioned herein, such as etching technology, planarization technology, implantation technology, doping technology, spin coating technology, sputtering technology , Growth technology, or deposition technology (such as chemical vapor deposition) at least one.
此外,「例示性」在此用於表示作為範例、實例、說明等,並且不一定是有利的。如在本說明書中使用的,「或」用於表示包含性的「或」而不是排他性的「或」。另外,在本說明書和後附申請專利範圍中使用的「一」和「一個」通常被解釋為指的是「一個或多個」,除非另有說明或從內文清楚地指向單數形式。而且,A和B及/或類似物中的至少一個通常表示A或B或A和B兩者。此外,在一定程度上,「包含」、「具有」、「有」、「帶有」或前述之變化,這樣的用語係用於包含性的方式,類似於用語「包括」。另外,除非另有說明,「第一」、「第二」或類似的用語並非用於暗示時間方面、空間方面、順序等。相反地,這樣的用語僅作為部件、元素、項目等的識別符號、名稱等。舉例來說,第一元件和第二元件通常對應於元件A和元件B或兩個不同的元件或兩個相同的元件或同一元件。In addition, "exemplary" is used herein to mean as an example, instance, explanation, etc., and is not necessarily advantageous. As used in this manual, "or" is used to mean an inclusive "or" rather than an exclusive "or". In addition, "a" and "an" used in the scope of this specification and the appended patent application are usually interpreted as referring to "one or more" unless otherwise stated or the content clearly refers to the singular form. Moreover, at least one of A and B and/or the like generally represents A or B or both. In addition, to a certain extent, the terms "include", "have", "have", "with" or the foregoing variations are used in an inclusive way, similar to the term "include". In addition, unless otherwise stated, "first", "second" or similar terms are not used to imply time, space, order, etc. On the contrary, such terms only serve as identification symbols, names, etc. of parts, elements, items, etc. For example, the first element and the second element generally correspond to the element A and the element B or two different elements or two identical elements or the same element.
此外,雖然已經相對於一或多個實施方式顯示和描述本發明實施例,但是基於對本說明書和所附圖式的閱讀和理解,發明所屬技術領域中具有通常知識者將想到等同的變更和修改。本發明實施例包含所有這樣的修改和變更,並且本發明實施例僅由後附申請專利範圍的範圍限制。特別是關於上述組件(例如元件、資源等)進行的各種功能,即使在結構上不等同於所揭示的結構,除非另有說明,否則用於描述此類組件的用語係用於對應於進行所述組件(例如在功能上等效)之指定功能的任何組件。另外,雖然可能已經僅針對幾種實施例中的一種實施例揭示本發明實施例的特定部件,但因為對於任何給定的或特定的應用可能是期望的及有利的,這種部件可以與其他實施方式的一或多個其他部件結合。In addition, although the embodiments of the present invention have been shown and described with respect to one or more embodiments, based on the reading and understanding of this specification and the accompanying drawings, those with ordinary knowledge in the technical field to which the invention belongs will think of equivalent changes and modifications . The embodiments of the present invention include all such modifications and changes, and the embodiments of the present invention are only limited by the scope of the attached patent application. Especially with regard to the various functions performed by the above-mentioned components (such as components, resources, etc.), even if they are not structurally equivalent to the disclosed structure, unless otherwise specified, the terms used to describe such components are used to correspond to the performance of the components. Any component of the specified function of the component (for example, functionally equivalent). In addition, although a specific component of an embodiment of the present invention may have been disclosed for only one of several embodiments, because it may be desirable and advantageous for any given or specific application, this component can be combined with other One or more other components of the embodiment are combined.
100,200,300:半導體裝置
102A:第一區
102B:第二區
105:半導體層
110:第一層
115:第二層
120:第三層
125:第四層
128,129:距離
130:第一圖案化遮罩
130A,130B,140A,140B:元件
131,132:厚度
133,134:節距
135:聚合物層
140:第二圖案化遮罩
140W1,140W2:寬度
150A,150B:鰭片
151,152:平均高度
155A,155B,170A,170B,200A,200B:蓋層
160A,160B:隔離結構
165A,165B:犧牲閘極結構
175A,175B:側壁間隔物
180A,180B:源極/汲極區
185:介電層
190A,190B:閘極腔
195A,195B:取代閘極結構
205A,205B:接觸開口
210A,210B:源極/汲極接觸件100, 200, 300:
藉由以下的詳細描述配合所附圖式,可以更加理解本發明實施例的內容。需強調的是,根據產業上的標準慣例,許多部件並未按照比例繪製。事實上,為了能清楚地討論,各種部件的尺寸可能被任意地增加或減少。 第1~17圖是根據一些實施例的各個製造階段之半導體裝置的示意圖。 第18圖是根據一些實施例之在形成第一圖案化遮罩之後的半導體裝置的示意圖。 第19圖是根據一些實施例之在形成第一圖案化遮罩之後的半導體裝置的示意圖。The content of the embodiments of the present invention can be better understood through the following detailed description in conjunction with the accompanying drawings. It should be emphasized that according to industry standard practice, many parts are not drawn to scale. In fact, in order to be able to discuss clearly, the size of various components may be arbitrarily increased or decreased. Figures 1-17 are schematic diagrams of semiconductor devices in various manufacturing stages according to some embodiments. FIG. 18 is a schematic diagram of the semiconductor device after forming the first patterned mask according to some embodiments. FIG. 19 is a schematic diagram of the semiconductor device after forming the first patterned mask according to some embodiments.
100:半導體裝置 100: Semiconductor device
102A:第一區 102A: District 1
102B:第二區 102B: District 2
105:半導體層 105: semiconductor layer
150A,150B:鰭片 150A, 150B: fins
160A:隔離結構 160A: isolation structure
175A,175B:側壁間隔物 175A, 175B: sidewall spacer
180A,180B:源極/汲極區 180A, 180B: source/drain region
185:介電層 185: Dielectric layer
195A,195B:取代閘極結構 195A, 195B: Replace gate structure
200A,200B:蓋層 200A, 200B: cover layer
210A,210B:源極/汲極接觸件 210A, 210B: source/drain contacts
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US16/682,163 US11177177B2 (en) | 2018-11-30 | 2019-11-13 | Semiconductor device and method of manufacture |
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