TWI741882B - Active clamp flyback converter - Google Patents

Abstract

An active clamp flyback converter includes a transformer, a main switch, a clamp switch, a switching current indication circuit and a controller. The switching current indication circuit generates a switching current indication signal according to a switching voltage of a primary circuit of the transformer. The controller includes a parameter generation circuit, a delay control circuit and an on-time control circuit. The parameter generation circuit is configured to measure a target current value, a harmonic extremum value and a switching current value. The delay control circuit is configured to adjust a delay time signal according to the switching current value and the harmonic extremum value, and turn on the main switch according to the delay time signal upon applying an enabling pulse to the clamp switch. The on-time control circuit is configured to adjust a pulse width of the enabling pulse according to the target current value the harmonic extremum value, and apply the enabling pulse to the clamp switch in the next harmonic period.

Description

Active clamp flyback converter

The present invention relates to power supply, in particular to an active clamp flyback converter.

A flyback converter is a voltage converter whose input and output are isolated from each other, and is suitable for various power supplies. In general, the flyback converter is controlled by a power switch to store and transfer energy. When the power switch is turned on, the primary circuit in the flyback converter will store energy, and the secondary circuit will be set in a reverse bias state without charging. When the power switch is open, the primary circuit in the flyback converter will transfer energy to the secondary circuit, and the secondary circuit will be set in a forward bias state for charging.

The flyback converter can be equipped with a clamping device and a clamping switch to reduce the voltage difference between the two ends of the power switch, thereby reducing the clamping loss. However, when the power switch and the clamp switch are turned on or off, the switching loss will still be caused.

The embodiment of the present invention provides an active clamp flyback converter for providing output voltage to a load, including a transformer, a main switch, a clamp switch, a clamp capacitor, and a controller. The transformer includes a primary circuit and a secondary coil. The primary circuit includes a primary coil, including a first terminal for receiving an input voltage, and a second terminal. The secondary coil includes a first terminal for outputting an output voltage, and a second terminal. The main switch includes a control terminal, a first terminal, a second terminal coupled to the primary coil, and a second terminal. The clamp switch contains the control terminal, The first end and the second end are coupled to the second end of the primary coil. The clamp capacitor includes a first terminal, which is coupled to the first terminal of the primary coil, and a second terminal, which is coupled to the first terminal of the clamp switch. The switching current indicating circuit is coupled to the transformer and used for generating a switching current indicating signal according to the switching voltage of the primary circuit. The controller is coupled to the voltage divider, the control terminal of the main switch and the control terminal of the clamp switch, and includes a parameter generation circuit and a delay control circuit. The parameter generation circuit is used to measure one of the resonant extremes of the switch current indicator signal after the clamp switch is applied with the enabling pulse during the resonance period, and to generate the main switch when the main switch is turned off from the off state to the on state. The last measured switching current in the state indicates the switching current value of the signal. The delay control circuit is used for adjusting the delay time signal according to the switching current value and the resonance extreme value. After another enabling pulse is applied to the clamp switch, the main switch is turned on according to the delay time signal.

The embodiment of the present invention provides another active clamp flyback converter for providing output voltage to the load, including a transformer, a main switch, a clamp switch, a clamp capacitor, and a controller. The transformer includes a primary circuit and a secondary coil. The primary circuit includes a primary coil, including a first terminal for receiving an input voltage, and a second terminal. The secondary coil includes a first terminal for outputting an output voltage, and a second terminal. The main switch includes a control terminal, a first terminal, a second terminal coupled to the primary coil, and a second terminal. The clamp switch includes a control terminal, a first terminal, and a second terminal, which is coupled to the second terminal of the primary coil. The clamp capacitor includes a first terminal, which is coupled to the first terminal of the primary coil, and a second terminal, which is coupled to the first terminal of the clamp switch. The switching current indicating circuit is coupled to the transformer and used for generating a switching current indicating signal according to the switching voltage of the primary circuit. The controller is coupled to the voltage divider, the control terminal of the main switch and the control terminal of the clamp switch, and includes a parameter generation circuit and an on-time control circuit. The parameter generation circuit is used to measure the target current value of the switch current indicator signal when the main switch is turned on, and to measure the resonance extreme value of the switch current indicator signal after the enable pulse is applied to the clamp switch during the resonance period. The on-time control circuit is used for adjusting a pulse width of another enabling pulse according to the target current value and the resonance extreme value, and applying another enabling pulse to the clamp switch in the next resonance period.

The embodiment of the present invention provides another active clamp flyback converter for providing output voltage to the load, including a transformer, a main switch, a clamp switch, a clamp capacitor, and a controller. The transformer includes a primary circuit and a secondary coil. The primary circuit includes a primary coil, including a first terminal for receiving an input voltage, and a second terminal. The secondary coil includes a first terminal for outputting an output voltage, and a second terminal. The main switch includes a control terminal, a first terminal, a second terminal coupled to the primary coil, and a second terminal. The clamp switch includes a control terminal, a first terminal, and a second terminal, which is coupled to the second terminal of the primary coil. The clamp capacitor includes a first terminal, which is coupled to the first terminal of the primary coil, and a second terminal, which is coupled to the first terminal of the clamp switch. The switching current indicating circuit is coupled to the transformer and used for generating a switching current indicating signal according to the switching voltage of the primary circuit. The controller is coupled to the voltage divider, the control terminal of the main switch, and the control terminal of the clamp switch, and includes a parameter generation circuit, a delay control circuit, and an on-time control circuit. The parameter generating circuit is used to measure the target current value of the switch current indicator signal when the main switch is turned on. After the enable pulse is applied to the clamp switch during the resonance period, the resonance extreme value of the switch current indicator signal is measured and used In the process that the main switch is switched from off to on state, the switching current value of the switch current indicating signal that is finally measured when the main switch is in the off state is generated. The delay control circuit is used for adjusting the delay time signal according to the switching current value and the resonance extreme value. After another enabling pulse is applied to the clamp switch, the main switch is turned on according to the delay time signal. The on-time control circuit is used for adjusting a pulse width of another enabling pulse according to the target current value and the resonance extreme value, and applying another enabling pulse to the clamp switch in the next resonance period.

1: Active clamp flyback converter

10: Transformer

11: Voltage source

12: Controller

120: Parameter generation circuit

122: On-time control circuit

124: Delay control circuit

13: Rectifier

14,16: Ground terminal

18: Switch current indicating circuit

40, 50: Comparison voltage circuit

400,406,420,500,506,520: current generator

402, 404, 422, 424, 502, 504, 522, 524: switch

42,52: Delay voltage circuit

44, 54: clamp

46: Enabling pulse circuit

56: Delay time circuit

Cc: Clamping capacitance

Cin1, Cin2, Cout, C1, C2, CA, CR: capacitance

GH, GL, GSR: control signal

GH2S: Pulse start signal

GH2R, Vcp: comparison signal

Im: Magnetizing current

I1: first current

I2: second current

I3, Isct, ITD: predetermined current

IVS: Switch current indication signal

IVS_GL: target current value

IVS_GLR: Switch current value

IVSP: resonance extreme value

L: load

Lp1: a mutual inductance

Ls: secondary mutual inductance

Mc: clamp switch

Mm: main switch

Msr: Synchronous rectifier

Pm11 to Pm41, Pc11, Pc12, Pc21, Pc22, Pc31, Pc32: pulse

Ps: short pulse signal

R1, R2, Rs: resistance

Sdly: Delay time signal

SGH2: enabling pulse

SGH2B: Reverse enabling pulse

TD, TD1 to TD3: delay time

TGH1, TGH2, TGH12 to TGH32: pulse width

Tdis1 to Tdis3: during discharge

Tglon1 to Tglon3: during charging

Tres1 to Tres3: during resonance

t1 to t24: time point

VA: auxiliary coil voltage

VA’: Partial Pressure

Vc1, VCR: compare voltage

Vc1’,VRTD: Clamping voltage

Vc2, VCA: Delay voltage

VD: Switching voltage

VIN: input voltage

Vsrc: voltage

VH1, VH: upper limit

VL1, VL: lower limit

VOUT: output voltage

WP: Primary coil

WS: Secondary coil

WA: auxiliary coil

Figure 1 is a circuit diagram of an active clamp flyback converter in an embodiment of the invention.

Figure 2 is a signal waveform diagram of an operating setup of the active clamp flyback converter in Figure 1.

Figure 3 is a signal waveform diagram of another operating setup of the active clamp flyback converter in Figure 1.

Figure 4 is a circuit diagram of the on-time control circuit in Figure 1.

Figure 5 is a circuit diagram of the delay control circuit in Figure 1.

FIG. 1 is a circuit diagram of an active clamp flyback converter 1 according to an embodiment of the present invention. The active clamp flyback converter 1 can receive the voltage Vsrc from the voltage source 11 to perform step-down or step-up conversion to generate the output voltage VOUT, and provide the output voltage VOUT to the load L. The voltage Vsrc is an AC voltage. The output voltage VOUT may be a DC voltage.

The active clamp flyback converter 1 includes a capacitor Cin1, a capacitor Cin2, a rectifier 13, a transformer 10, a main switch Mm, a clamp switch Mc, a clamp capacitor Cc, a controller 12, a resistor Rs, a synchronous rectifier Msr, a capacitor Cout, Grounding terminals 14 and 16, and switching current indicating circuit 18. The controller 12 can control the switching of the main switch Mm and the clamp switch Mc. When the main switch Mm is switched between on and off, and each time the main switch Mm is switched on for a fixed period of time, substantially the same electric energy can be transmitted from the primary side of the flyback converter 1 to the converter 1 Secondary side; when the load L is light load and draws less power, the controller 12 can control the main switch Mm to operate at a lower switching frequency, that is, a longer switching period, and the main switch Mm is turned on and conducted in a less number of times per unit time When the load L extracts more power for the heavy load, the controller 12 can control the main switch Mm to operate at a higher switching frequency, that is, with a shorter switching period, and the main switch Mm is turned on and conducted more times per unit time. The controller 12 can determine the on time of the clamp switch Mc and the on time of the main switch Mm, so as to achieve zero voltage switching of the main switch Mm to reduce switching loss.

The transformer 10 includes a primary winding WP, including a first terminal N1 for receiving the input voltage VIN, and a second terminal N2; an auxiliary winding WA, including a first terminal, and a second terminal; and a secondary winding WS, including the first terminal , Used to output the output voltage VOUT, and the second terminal. The primary coil WP and the auxiliary coil WA belong to the primary circuit, and the secondary coil WS belongs to the secondary circuit. The main switch Mm includes a first control terminal, a first terminal, a second terminal N2 coupled to the primary coil WP, and a second terminal. The resistor Rs is coupled between the second terminal of the main switch Mm and the ground terminal 14. The first terminal of the main switch Mm has a switching voltage VD, and the first terminal of the auxiliary coil WA has an auxiliary coil voltage VA. The switching voltage VD can be 600 ^~ 700V. The clamp switch Mc includes a second control terminal, a first terminal, and a second terminal, which is coupled to the second terminal N2 of the primary coil WP. The clamp capacitor Cc is coupled between the first terminal N1 of the primary winding WP and the first terminal of the clamp switch Mc. The switching current indicating circuit 18 includes a first terminal coupled to the first terminal of the auxiliary coil WA, a second terminal for outputting a switching current indicating signal IVS, and a third terminal coupled to the ground terminal 14. The controller 12 is coupled to the first control terminal of the main switch Mm, the second terminal of the switch current indicating circuit 18 and the second control terminal of the clamp switch Mc. The capacitor Cin1 is coupled to the ground terminal 14. The rectifier 13 includes a first terminal coupled to the capacitor Cin1 and a second terminal coupled to the ground terminal 14. The capacitor Cin2 is coupled between the rectifier 13 and the ground terminal 14. The synchronous rectifier Msr includes a third control terminal, a first terminal coupled to the second terminal of the secondary winding WS, and a second terminal coupled to the ground terminal 16. The capacitor Cout is coupled between the first terminal of the secondary winding WS and the ground terminal 16. The ground terminals 14 and 16 may not be coupled to each other to maintain isolation between the primary side and the secondary side.

The capacitor Cin1 can filter high frequency noise in the voltage Vsrc, the rectifier 13 can rectify the voltage Vsrc, and the capacitor Cin2 can smooth the rectified voltage Vsrc to generate the input voltage VIN. The turns ratio of the primary coil WP and the secondary coil WS can be P:1, and P is a positive number. In some embodiments, P may be greater than 1, and the transformer 10 may be a step-down transformer 10. The polarity of the primary coil WP and the polarity of the secondary coil WS can be reversed. The turns ratio of the primary coil WP and the auxiliary coil WA can be Q:1, and Q is a positive number greater than 1. The primary coil WP has a primary mutual inductance Lp1 and leakage inductance, the secondary coil WS has a secondary mutual inductance Ls, and the auxiliary coil WA has an auxiliary mutual inductance Lp2. Because the primary coil WP and the auxiliary coil WA have a turns ratio relationship, when the switching voltage VD changes, the auxiliary coil WA can generate the auxiliary coil voltage VA according to the turns ratio Q:1. auxiliary The polarity of the auxiliary coil voltage VA and the switching voltage VD can be reversed, and the auxiliary coil voltage VA can be positively correlated with the absolute value of the switching voltage VD according to the ratio of 1/Q (VA=-VD/Q).

The switching current indicating circuit 18 can establish a divided voltage VA' according to the auxiliary coil voltage VA, and provide a switching current indicating signal IVS to the controller 12 according to the divided voltage VA'. The switch current indicating circuit 18 can be a voltage divider, including resistors R1 and R2. The resistor R1 can be coupled to the switch current indicating circuit 18. The resistor R2 can be coupled between the resistor R1 and the ground terminal 14.

The controller 12 can control the main switch Mm and the clamp switch Mc according to the current indicating signal IVS. In the following paragraphs, the current indicating signal IVS is used to control the main switch Mm and the clamp switch Mc to illustrate the operation of the active clamp flyback converter 1. Compared with directly using the switching voltage VD to generate the current indicating signal IVS, since the maximum absolute value of the auxiliary coil voltage VA is less than the maximum absolute value of the switching voltage VD, the controller 12 can use a semiconductor device with a smaller withstand voltage to receive current Instruct the signal IVS to perform switch control, thereby saving circuit area.

The main switch Mm and the clamp switch Mc can be realized by an N-type metal-oxide-semiconductor field-effect transistor (MOSFET). The synchronous rectifier Msr can be realized by N-type MOSFET, NPN-type bipolar junction transistor (BJT), insulated-gate bipolar transistor (IGBT) or other types of switching elements. In some embodiments, the synchronous rectifier Msr can be replaced by a diode.

The main switch Mm can control the storage and transfer of energy. The clamp switch Mc can control the recovery of energy stored in the leakage inductance and generate a negative magnetizing current Im (from the second end N2 of the primary mutual inductance Lp1 to the first end N1 of the primary mutual inductance Lp1).

(1) Charging period: When the controller 12 turns on the main switch Mm for a predetermined period of time by the control signal GL to generate the main switching pulse, the current and magnetic flux on the primary side of the transformer 10 increase, and energy is stored in the transformer inductance; That is, the forward magnetizing current Im through the primary mutual inductance Lp1 (from the first terminal N1 of the primary mutual inductance Lp1 to the second terminal N2 of the primary mutual inductance Lp1) increases; at the same time, the controller 12 turns off the synchronous rectifier Msr on the secondary side of the transformer 10, so The secondary mutual inductance Ls does not generate a secondary induced current, but the output voltage VOUT is provided to the load L by the capacitor Cout. The period during which energy is stored in the transformer 10 can be referred to as a charging period. During the charging period, the controller 12 can turn off the clamp switch Mc by the control signal GH.

(2) Discharge period: When the forward magnetizing current Im has reached a predetermined value, or the main switch Mm conduction time has reached a predetermined period of time, the controller 12 can turn off the main switch Mm by the control signal GL, so that the primary side of the transformer 10 When the current and magnetic flux are reduced, the polarities of the primary coil WP and the secondary coil WS will be reversed; and the secondary side controller (not shown) turns on the synchronous rectifier Msr to generate a secondary induced current on the secondary side. In this way, the energy stored in the primary winding WP of the transformer 10 can be transferred to the secondary side, and the secondary induced current charges the capacitor Cout and provides the output voltage VOUT to the load L. The period during which energy is released from the transformer 10 for energy transfer can also be referred to as a discharge period. The synchronous rectifier Msr can be controlled by the control signal GSR, which can be generated according to the voltage of the second end of the secondary winding WS.

(3) Resonance period: After the discharge period, when the energy stored in the primary coil WP of the transformer 10 is released, the switching voltage VD will oscillate up and down around the input voltage VIN to generate multiple peaks, which can be called During resonance.

Once the main switch Mm is turned off, the active clamp flyback converter 1 enters the discharge period, the switch voltage VD will increase first, and later may experience multiple harmonic oscillations with a voltage level as the center value. When the switching voltage VD reaches the voltage level (VIN+Vclamp), the positive magnetizing current Im will flow through the leakage inductance, the primary mutual inductance Lp1, the clamp switch Mc, and the internal diode (body diode) and the clamp capacitor Cc. The energy stored in the leakage inductance is transferred to the clamping capacitor Cc, and then the clamping capacitor Cc is charged to the voltage level (VIN+N*VOUT), and the voltage Vclamp is the clamping voltage. After the multiple harmonic oscillations are over, the switching voltage VD will be maintained at a substantially fixed voltage level (VIN+N*VOUT). For example, in Figure 2, after the end of the main switching pulse Pm11 (time t2), the switching voltage VD will increase first, and then it will experience multiple harmonics with the voltage level (VIN+N*VOUT) as the center value. Shock. After the multiple harmonic oscillations are over (time point t3), the switching voltage VD will be maintained at a substantially fixed voltage level (VIN+N*VOUT).

During the discharge period, the controller 12 can insert an energy recovery pulse into the control signal GH to turn on the clamp switch Mc to transfer the energy stored in the leakage inductance to the clamp capacitor Cc. The controller 12 can insert an energy recovery pulse when detecting that the switching voltage VD reaches a steady state or at a fixed time point during the discharge period. The energy recovery pulse wave may have a substantially fixed pulse width. The fixed time point may be a predetermined time after the main switch Mm is turned off.

During the resonance period, when the auxiliary coil voltage VA is close to the peak, the controller 12 can apply an enabling pulse to the clamp switch Mc to turn on the clamp switch Mc to generate a negative magnetizing current Im, and use this negative magnetizing current Im to Pull down the switch voltage VD, and when the switch voltage VD approaches 0V, the controller 12 can apply a main switch pulse to the main switch Mm, so that the main switch Mm achieves zero voltage switching at the beginning of the subsequent charging period. During the discharge period and the resonance period, the controller 12 can turn off the main switch Mm by the control signal GL. The controller 12 can adjust the pulse width of the enabling pulse to control the magnitude of the negative magnetizing current Im. When the pulse width of the enabling pulse is too small, the negative magnetizing current Im will be too small to pull the switching voltage VD down to 0V, making the main switch Mm unable to achieve zero voltage switching and increasing the switching loss. When the pulse width of the enabling pulse is too large, the negative magnetizing current Im will pull the switching voltage VD down to 0V prematurely and continue to generate energy consumption, increasing energy loss. control The device 12 can adjust the pulse width of the enabling pulse to generate a suitable negative magnetization current Im, so that when the main switch Mm achieves zero voltage switching, the switching voltage VD is not too early to reduce the switch voltage VD to 0V, which greatly reduces the switching main switch Mm and the negative magnetization Energy loss caused by current Im. After the enabling pulse ends, the controller 12 can delay the main switching pulse for a delay time to turn on the main switch Mm when the switching voltage VD is substantially equal to or close to 0V, achieving zero voltage switching and reducing switching loss.

Fig. 2 is a signal waveform diagram of the active clamp flyback converter 1 under one configuration, showing sequentially the first charging period Tglon1, the discharging period Tdis1, the resonance period Tres1, and the second charging period Tglon2. The first charging period Tglon1, the discharging period Tdis1, and the resonance period Tres1 constitute the first conversion period, and the second charging period Tglon2 belongs to the subsequent second conversion period. For the first conversion cycle, the controller 12 inserts the main switching pulse Pm11 into the control signal GL from time points t1 to t2, inserts the energy recovery pulse Pc11 into the control signal GH from time points t3 to t4, and at time point t6 To t7, the enable pulse Pc12 is inserted into the control signal GH. For the second conversion cycle, the controller 12 inserts the main switch pulse Pm21 into the control signal GL from time t9 to t10, and then inserts an energy recovery pulse and an enable pulse (not shown) in the control signal GH. The controller 12 can adjust: (1) the pulse width TGH2 of the enabling pulse Pc12, and (2) a delay time TD between the end of the enabling pulse Pc12 and the main switching pulse Pm21. By adjusting the delay time TD, it can be ensured that the main switch Mm is turned on again when the switch voltage VD approaches 0V (time t9). The pulse width TGH2 of the enabling pulse Pc12, the pulse width TGH1 of the energy recovery pulse Pc11, and the pulse widths of the main switching pulses Pm11, Pm21 do not have a certain magnitude relationship with each other; the second figure is only an example of the relationship: the enabling pulse The pulse width TGH2 of Pc12 can be larger than the pulse width TGH1 of the energy recovery pulse Pc11, and can be smaller than the pulse widths of the main switching pulses Pm11 and Pm21, but not limited to this.

The controller 12 may include a parameter generation circuit 120, an on-time control circuit 122 and a delay control circuit 124. The parameter generating circuit 120 can generate a switching current indication signal according to the switching current indication signal IVS No. IVS target current value, resonance extreme value and switching current value. Specifically, the parameter generating circuit 120 can measure the target current value of the switch current indicator signal IVS when the main switch Mm is turned on, and after the clamp switch Mc is applied with an enabling pulse during the resonance period, the switch current indicator signal IVS can be measured The resonant extreme value of the main switch Mm is converted from the off state to the on state, and the switching current value of the switch current indicating signal IVS is finally measured when the main switch Mm is in the off state.

Refer to Figure 2 to explain the current values of the three parameters:

(1) Target current value IVS_GL: For example, it can be the switch current indication signal measured when the main switch Mm is turned on and the switch voltage VD drops to a minimum voltage during the first charging period Tglon1 or the second charging period Tglon2 The current value of IVS.

(2) Resonance extreme value IVSP: For example, it can be the maximum value of the switch current indicator signal IVS measured after the clamp switch Mc is applied with the enable pulse Pc12 with the pulse width TGH2 in the resonance period Tres1, as shown in the time point shown in the figure. The maximum value of the waveform of t8, that is, the resonance extreme value IVSP, represents the minimum voltage value Vmin that the corresponding switching voltage VD can reach. When the pulse width TGH2 of the enabling pulse Pc12 is adjusted, the resonance extreme value IVSP will also change accordingly. When the resonance extreme value IVSP is equal to the target current value IVS_GL, it means that the enabling pulse Pc12 has a sufficient pulse width TGH2 to pull the switching voltage VD down to the lowest potential.

(3) Switching current value IVS_GLR: For example, it can be the switching current indication signal IVS that is finally measured when the main switch Mm is turned off immediately before the main switch Mm is turned on by the main switch pulse Pm21 at the time point t9. With (1) (2) conditions-the resonance extreme value IVSP will be close to the target current value IVS_GL, when the switching current value IVS_GLR is close to the target current value IVS_GL, it also represents the time point when the main switch Mm is turned on (corresponding to the switching current value IVS_GLR) It is close to the point in time when the resonance extreme value IVSP occurs. In this way, the time point of the self-resonance extreme value IVSP can be prevented from being delayed for a long time, and the main switch Mm is turned on after the switch current indicating signal IVS is greatly attenuated.

The on-time control circuit 122 can adjust the pulse width of another enabling pulse according to the target current value IVS_GL and the resonance extreme value IVSP, and apply this adjusted another enabling pulse to the clamp switch Mc in the next resonance period of the later conversion period. pulse. The on-time control circuit 122 can adjust the pulse width of another enable pulse to make the resonance extreme value IVSP substantially equal to the target current value IVS_GL, so that the negative magnetizing current Im is sufficient to pull the switching voltage VD down to 0V and achieve the main switch Mm Zero voltage switching.

The delay control circuit 124 can adjust the delay time signal according to the switching current value IVS_GLR and the resonance extreme value IVSP. In the later conversion period, after another enabling pulse is applied to the clamp switch Mc, the main switch is turned on according to the adjusted delay time signal Mm. The delay time signal can be used to determine the delay time TD. The delay control circuit 124 can adjust the delay time signal so that the switching current value IVS_GLR is substantially equal to the resonance extreme value IVSP, thereby reducing the switching loss of the main switch Mm.

Figure 3 is the signal waveform diagram of the active clamp flyback converter 1 in another setting, including 3 conversion cycles, the first conversion cycle is between time points t1 to t9, and the second conversion The period is between t9 and t17, and the third conversion period is between t17 and t24.

In the first conversion cycle, the controller 12 applies the main switch pulse Pm11 to the main switch Mm between time points t1 and t2 according to a preset setting, and applies an energy recovery pulse to the clamp switch Mc from time points t3 to t4. Wave Pc11 and apply an enabling pulse Pc12 to the clamp switch Mc between time points t6 and t7; the parameter generating circuit 120 measures the target current value IVS_GL between time points t1 and t2, and measures the resonance extreme value at time point t8 IVSP, and the switching current value IVS_GLR measured before time t9. The resonance extreme value IVSP is significantly smaller than the target current value IVS_GL, and the switching current value IVS_GLR is significantly smaller than the resonance extreme value IVSP.

In the second conversion cycle, the controller 12 applies the main switch Mm between time points t9 to t10. The main switch pulse Pm21 is added and the energy recovery pulse Pc21 is applied to the clamp switch Mc between the time points t11 and t12; because the resonance extreme value IVSP measured at the time point t8 in the first conversion cycle is less than the target current value IVS_GL , The on-time control circuit 122 increases the pulse width TGH22 of the enabling pulse Pc22 applied to the clamp switch Mc, so that the pulse width TGH22 is greater than the pulse width TGH12. At the same time, since the switching current value IVS_GLR measured at the time point t9 in the first conversion cycle is less than the resonance extreme value IVSP, the delay control circuit 124 will shorten the pulse width of the delay time signal so that the delay time TD2 is less than the delay time TD1. When the delay time TD2 passes after the enable pulse Pc22, the main switch pulse Pm31 is applied to the main switch Mm, thus reducing the time between the main switch Mm's turn-on time point (time point t17) and the resonance extreme value IVSP time point (time point t16) interval. The parameter generating circuit 120 measures the target current value IVS_GL again between time points t9 and t10 in the second conversion cycle, measures the resonance extreme value IVSP again at time point t16, and measures the switching current again before time point t17 The value IVS_GLR. It is determined that the resonance extreme value IVSP in the second conversion cycle is less than the target current value IVS_GL, and the switching current value IVS_GLR is less than the resonance extreme value IVSP. Therefore, in the third conversion cycle, it is necessary to further increase the pulse width TGH32 of the enabling pulse Pc32 and shorten the delay Time TD3.

In the third conversion cycle, the controller 12 applies the main switch pulse Pm31 to the main switch Mm between time points t17 and t18, and applies the energy recovery pulse Pc31 to the clamp switch Mc between time points t19 and t20; The resonance extreme value IVSP in the second conversion cycle is less than the target current value IVS_GL, and the on-time control circuit 122 increases the pulse width TGH32 of the enable pulse Pc32 applied to the clamp switch Mc from time t22 to t23 to make the pulse width TGH32 Is greater than the pulse width TGH22; since the switching current value IVS_GLR in the second conversion cycle is less than the resonance extreme value IVSP, the delay control circuit 124 will shorten the pulse width of the delay time signal so that the delay time TD3 is less than the delay time TD2, and the enable pulse is applied When the delay time TD3 elapses after Pc32, the main switch pulse Pm41 is applied to the main switch Mm, which further reduces the time interval between the on-time point of the main switch Mm and the resonance extreme value IVSP time point, so that both are almost at the time point t24. ; The parameter generating circuit 120 measures the target current value IVS_GL again between time points t17 and t18 in the third conversion cycle, and at time The resonance extreme value IVSP is measured again at point t24, and the switching current value IVS_GLR is measured again before time point t24. It is determined that the resonance extreme value IVSP in the third conversion cycle is substantially equal to the target current value IVS_GL, and the switching current value IVS_GLR is substantially equal to the resonance extreme value IVSP, that is, according to the current enable pulse width and delay time settings, the negative direction The magnetizing current Im is sufficient to pull the switching voltage VD down to 0V and the main switch Mm can perform zero voltage switching. Therefore, in the later conversion period, the on-time control circuit 122 can substantially maintain the pulse width of the currently set enable pulse, and the delay control circuit 124 can substantially maintain the pulse width of the currently set delay time signal.

FIG. 4 is a circuit diagram of the on-time control circuit 122 in FIG. 1. FIG. The on-time control circuit 122 includes a comparison voltage circuit 40, a delay voltage circuit 42, a clamp 44 and an enable pulse circuit 46. The comparison voltage circuit 40 is coupled to the clamp 44, and the clamp 44 and the delay voltage circuit 42 are coupled to the enable pulse circuit 46. The on-time control circuit 122 can generate the enabling pulse SGH2 (such as the enabling pulses Pc12, Pc22, Pc32 in Figure 3) according to the triggering of the enabling pulse start signal GH2S, and determine the result according to the target current value IVS_GL and the resonance extreme value IVSP The end time point of SGH2 can be pulsed. The on-time control circuit 122 can adjust the end time point of the enabling pulse SGH2, and further adjust the pulse width of the enabling pulse SGH2, so that the resonance extreme value IVSP is substantially equal to the target current value IVS_GL.

The comparison voltage circuit 40 can establish the comparison voltage Vc1 according to the target current value IVS_GL and the resonance extreme value IVSP. Specifically, the comparison voltage circuit 40 can multiply the target current value IVS_GL by N to generate the offset target current value (IVS_GL*N), and continue to adjust the comparison voltage Vc1 until the resonance extreme value IVSP is substantially equal to the offset target current value ( IVS_GL*N), N is a positive number less than or equal to 1, and the offset target current value (IVS_GL*N) is the proportional reduction or equal value of the target current value IVS_GL. For example, N can be selected between 0.97 ^~ 0.98 The range interval value, so that there is a 2% ^~ 3% difference between the continuous retention and the target current value IVS_GL, and it also ensures that the resonance extreme value IVSP will not exceed the target current value IVS_GL. When the resonance extreme value IVSP is less than the offset target current value (IVS_GL*N), the comparison voltage circuit 40 will increase the comparison voltage Vc1; when the resonance extreme value IVSP is greater than the offset target current value (IVS_GL*N), the comparison voltage circuit 40 The comparison voltage Vc1 will be reduced; when the resonance extreme value IVSP is substantially equal to the offset target current value (IVS_GL*N), the comparison voltage circuit 40 will maintain the comparison voltage Vc1. When the comparison voltage circuit 40 uses the offset target current value (IVS_GL*N) to generate the comparison voltage Vc1, and N is a value in the range of 0.97 ^to 0.98, the pulse width of the enable pulse SGH2 gradually increases to make the resonance pole When the value IVSP reaches the target current value IVS_GL*0.99, the comparison voltage circuit 40 will start to adjust the pulse width of the enabling pulse SGH2, so as to ensure that there is a voltage interval for callback to reduce the pulse width of the enabling pulse SGH2.

The comparison voltage circuit 40 may include current generators 400 and 406, switches 402 and 404, and a capacitor C1. The current generator 400 is coupled to the power supply terminal 41, the current generator 406 is coupled to the ground terminal 14, and the power supply terminal 41 can provide the first current I1. The switch 402 includes a first terminal, which is coupled to the current generator 400, and a second terminal. The switch 404 includes a first terminal and a second terminal, which are coupled to the current generator 406. The capacitor C1 includes a first terminal, which is coupled to the second terminal of the switch 402 and the first terminal of the switch 404, and a second terminal, which is coupled to the ground terminal 14. The current generators 400 and 406 can be current controlled current sources. The current generator 400 can generate the first difference current according to the offset target current value (IVS_GL*N) and the first current I1. The current generator 406 can generate a second difference current according to the resonance extreme value IVSP and the second current I2. The switches 402 and 404 can be turned on or off according to the short pulse signal Ps. When the switches 402 and 404 are turned on, the current generator 400 can generate a first difference current between the offset target current value (IVS_GL*N) and the first current, and the current generator 406 can generate the resonance extreme value IVSP and the first difference current. The second difference current between the two currents I2, the first difference current can charge the capacitor C1 and the second difference current can discharge the capacitor C1 to establish a comparison voltage Vc1 on the capacitor C1. If the first current I1 is substantially equal to the second current I2, the comparison voltage Vc1 can be positively correlated with the difference between the offset target current value (IVS_GL*N) and the resonance extreme value IVSP. When the switches 402 and 404 are turned off, the capacitor C1 can maintain the comparison voltage Vc1. Using the short pulse signal Ps to control the switches 402 and 404 can reduce the capacitance value of the capacitor C1, and gradually adjust the comparison voltage Vc1 Adjust to a stable value without adjusting too much at once. In some embodiments, the switches 402 and 404 can be removed from the voltage comparison circuit 40, and the first end of the capacitor C1 is coupled to the current generator 400 and the current generator 406. The clamp 44 is coupled to the first terminal of the capacitor C1, and can limit the comparison voltage Vc1 within the clamp range to generate the clamp voltage Vc1'. The clamp range can be a range between the upper voltage limit VH1 and the lower voltage limit VL1, and is used to define the range of the pulse width of the enable pulse SGH2. In some embodiments, the clamp 44 can also be omitted from the on-time control circuit 122 so that the first end of the capacitor C1 is coupled to the enable pulse circuit 46.

The delay voltage circuit 42 can establish a delay voltage Vc2, and the delay voltage Vc2 starts to increase from the start time point of the enabling pulse SGH2 until the delay voltage Vc2 is substantially equal to the clamp voltage Vc1'. The delay voltage circuit 42 includes a current generator 420, switches 422 and 424, and a capacitor C2. The switch 422 includes a first terminal, which is coupled to the current generator 420, and a second terminal. The switch 424 includes a first terminal, which is coupled to the second terminal of the switch 422, and a second terminal, which is coupled to the ground terminal 14. The capacitor C2 includes a first terminal, which is coupled to the second terminal of the switch 422, and a second terminal, which is coupled to the ground terminal.

The current generator 420 may generate a predetermined current I3, and the predetermined current I3 may be the same as or different from the first current I1. The switch 422 can be turned on or off according to the enabling pulse SGH2, the switch 424 can be turned on or off according to the reverse enabling pulse SGH2B, and the enabling pulse SGH2 and the reverse enabling pulse SGH2B may be opposite to each other. When the switch 422 is turned on by the enabling pulse SGH2 and the switch 424 is turned off by the reverse enabling pulse SGH2B, the predetermined current I3 can charge the capacitor C2 to establish the comparison voltage Vc2; when the switch 422 is turned off by the enabling pulse SGH2 and the switch 424 is turned off When the reverse enabling pulse SGH2B is turned on, the capacitor C2 is discharged through the switch 424. Since C2*Vc2=I3*t, C2 is the capacitance value of the capacitor C2, Vc2 is the comparison voltage, I3 is the charging current of the capacitor C2, and the charging time t of the capacitor C2 can be positively correlated with the comparison voltage Vc2. The larger the comparison voltage Vc2, the longer the charging time t.

The enabling pulse circuit 46 can determine the end time point of the enabling pulse SGH2 according to the clamping voltage Vc1' and the delay voltage Vc2. The enabling pulse circuit 46 includes a comparator 460 and a flip-flop 462. The comparator 460 includes a first input terminal, coupled to the delay voltage circuit 42, a second input terminal, coupled to the comparison voltage circuit 40, and an output terminal for outputting a comparison signal GH2R. The flip-flop 462 includes an input terminal S that can receive a pulse start signal GH2S, a reset terminal R is coupled to the output terminal of the comparator 460, and is used to reset the flip-flop 462 according to the comparison signal GH2R, and the output terminal is coupled to The control terminal of the switch 422 is used to output the enabling pulse SGH2. The start time of the pulse start signal GH2S can be determined according to the energy consumed by the load L or the load impedance. In some embodiments, the start time of the pulse start signal GH2S can be determined according to the energy consumed by the load L. When the energy consumed by the load L decreases, the start time of the pulse start signal GH2S is also delayed; As the energy consumed increases, the start time of the pulse start signal GH2S also advances. In other embodiments, the start time of the pulse start signal GH2S can be determined according to the load impedance of the load L. When the output voltage VOUT is a substantially fixed value, if the load impedance is larger, the current drawn by the load L is smaller , The start time of the pulse start signal GH2S is also delayed; when the load impedance is small, the current drawn by the load L is larger, and the start time of the pulse start signal GH2S is also advanced. The comparator 460 can generate the comparison signal GH2R according to the delay voltage Vc2 and the clamp voltage Vc1'. The flip-flop 462 can be triggered by the enabling pulse start signal GH2S to generate the enabling pulse SGH2, and the comparison signal GH2R can reset the enabling pulse SGH2. After receiving the enabling pulse start signal GH2S, the flip-flop 462 can generate the enabling pulse SGH2 until reset by the comparison signal GH2R.

When the offset target current value (IVS_GL*N) is less than the resonance extreme value IVSP, the first difference current will be smaller than the second difference current, the comparison voltage Vc1 will decrease, the comparison signal GH2R will occur earlier, and the enable pulse SGH2 will be enabled. The pulse width is shortened; when the offset target current value (IVS_GL*N) is greater than the resonance extreme value IVSP, the first difference current will be greater than the second difference current, the comparison voltage Vc1 will rise, and the comparison signal GH2R will occur later, and then Increase the pulse width of the enable pulse SGH2; when the offset target current value (IVS_GL*N) is equal to the resonance extreme value In IVSP, the first difference current will be equal to the second difference current, and the comparison voltage Vc1 will remain substantially stable, so that the pulse width of the enabling pulse SGH2 remains unchanged.

FIG. 5 is a circuit diagram of the delay control circuit 124 in FIG. 1. FIG. The delay control circuit 124 includes a comparison voltage circuit 50, a delay voltage circuit 52, a clamp 54 and a delay time circuit 56. The delay control circuit 124 can generate the delay time signal Sdly according to the trigger of the reverse enabling pulse SGH2B, and determine the end time point of the delay time signal Sdly according to the resonance extreme value IVSP and the switching current value IVS_GLR. The delay control circuit 124 can adjust the end time point of the delay time signal Sdly so that the switching current value IVS_GLR is substantially equal to the resonance extreme value IVSP.

The comparison voltage circuit 50 includes a current generator 500, a switch 502, a switch 504, a current generator 506, and a capacitor CR. The current generator 500 is coupled to the power supply terminal 41, and the current generator 506 is coupled to the ground terminal 14. The switch 502 includes a first terminal, which is coupled to the current generator 500, and a second terminal. The switch 504 includes a first terminal, which is coupled to the second terminal of the switch 502, and a second terminal, which is coupled to the current generator 506. The capacitor CR includes a first terminal, which is coupled to the second terminal of the switch 502 and the first terminal of the switch 504, and a second terminal, which is coupled to the ground terminal 14. The current generator 500 can generate a predetermined current Iset. The current generator 506 can be a current control current source, and can generate a difference current (IVSP-IVS_GLR) according to the resonance extreme value IVSP and the switching current value IVS_GLR. The switches 502 and 504 can be turned on or off according to the short pulse signal Ps. When the switches 502 and 504 are turned on, the current generator 500 can generate a predetermined current Iset, and the current generator 506 can generate a difference current (IVSP-IVS_GLR) between the resonance extreme value IVSP and the switching current value IVS_GLR. The predetermined current Iset can Charging the capacitor CR and the difference current (IVSP-IVS_GLR) can discharge the capacitor CR to establish a comparison voltage VCR on the capacitor CR. When the switches 502 and 504 are turned off, the capacitor CR can maintain the comparison voltage VCR. Using the short pulse signal Ps to control the switches 502 and 504 can reduce the required capacitance value of the capacitor CR, and gradually adjust the comparison voltage VCR to a stable value without adjusting too much at one time. In some embodiments, the switches 502 and 504 can be moved from the comparison voltage circuit 50 In addition, the first end of the capacitor CR is coupled to the current generator 500 and the current generator 506. The clamp 54 is coupled to the first terminal of the capacitor CR, and can limit the comparison voltage VCR within the clamp range to generate the clamp voltage VRTD. The clamp range can be a range between the upper voltage limit VH and the lower voltage limit VL, and is used to define the range of the pulse width of the delay time signal Sdly. In some embodiments, the clamp 54 can also be omitted from the delay control circuit 124 so that the first end of the capacitor CR is coupled to the delay time circuit 56.

The delay voltage circuit 52 can establish a delay voltage VCA, and the delay voltage VCA starts to increase from the end time point of the enable pulse SGH2 (the start time point of the reverse enable pulse SGH2) until the delay voltage VCA is substantially equal to the clamp voltage VRTD. The delay voltage circuit 52 includes a current generator 520, a switch 522, a switch 524, and a capacitor CA. The current generator 520 may generate a predetermined current ITD. The switch 522 includes a first terminal, which is coupled to the current generator 520, a second terminal, and a control terminal. The switch 524 includes a first terminal coupled to the second terminal of the switch 522 and a second terminal coupled to the ground terminal 14. The capacitor CA can establish a delay voltage according to a predetermined current ITD, and includes a first terminal, which is coupled to the second terminal of the switch 522, and a second terminal, which is coupled to the ground terminal 14. The switch 524 can receive the enable pulse SGH2 to control its on and off. The control terminal of the switch 522 is coupled to the input terminal of the flip-flop 562 of the delay time circuit 56. The control terminal of the switch 522 and the input terminal of the flip-flop 562 both receive the reverse enabling pulse SGH2B. The reverse enabling pulse SGH2B and the enabling pulse SGH2 are opposite to each other. Since CA*VCA=ITD*t, CA is the capacitance value of the capacitor CA, VCA is the delay voltage, ITD is the charging current of the capacitor CA, and the charging time t of the capacitor CA can be positively correlated with the comparison voltage VCA. The larger the comparison voltage VCA, the longer the charging time t.

The delay time circuit 56 is coupled to the delay voltage circuit 52 and the clamper 54, and can generate the delay time signal Sdly according to the clamp voltage VRTD and the delay voltage VCA. The delay time circuit 56 includes a comparator 560 and a flip-flop 562. The comparator 560 can generate a comparison signal Vcp according to the delay voltage VCA and the clamp voltage VRTD, and includes a first input terminal coupled to the delay voltage circuit 52, and a second input terminal coupled to the clamp 54. And the output terminal is used to output the comparison signal Vcp. The comparison signal Vcp can be positively correlated with the difference between the delay voltage VCA and the clamp voltage VRTD. The flip-flop 562 includes an input terminal for receiving the reverse enabling pulse SGH2B, a reset terminal, coupled to the output terminal of the comparator 560, for resetting the flip-flop 562 according to the comparison signal Vcp, and an output terminal, To output the delay time signal Sdly. The delay time signal Sdly starts from the end time point of the enabling pulse SGH2 and lasts until the delay voltage VCA increases to be greater than the clamp voltage VRTD.

When the difference current (IVSP-IVS_GLR) is equal to the predetermined current Iset, the comparison voltage VCR remains substantially stable, and the pulse width of the delay time signal Sdly remains substantially unchanged; when the difference current (IVSP-IVS_GLR) is greater than the predetermined current Iset, compare When the voltage VCR drops, the comparison signal Vcp occurs earlier, thereby shortening the pulse width of the delay time signal Sdly; when the difference current (IVSP-IVS_GLR) is less than the predetermined current Iset, the comparison voltage VCR rises, and the comparison signal Vcp occurs later, and then Make the delay time signal Sdly longer. For example, when the difference current (IVSP-IVS_GLR) is equal to 0A, the predetermined current Iset will increase the comparison voltage VCR, thereby increasing the pulse width of the delay time signal Sdly; this ensures that the main switch Mm is turned on at the resonance pole. After the value IVSP occurs, there is at least a delay time interval corresponding to the predetermined current Iset; to avoid the pulse width of the delay time signal Sdly being too short, causing the main switch Mm to open and close and the switch current indicator signal after the enable pulse has been applied Before the IVS rises to the maximum value, the main switching pulse Pm is applied prematurely.

The embodiments in Figures 1 to 5 generate the switching current indication signal IVS according to the auxiliary coil voltage VA, and adjust the pulse of the enable pulse applied to the clamp switch according to the target current value IVS_GL and the resonance extreme value IVSP of the switching current indication signal IVS The delay time is adjusted according to the resonance extreme value IVSP of the switch current indication signal IVS and the switching current value IVS_GLR to apply the main switch pulse to the main switch after the delay time, so as to achieve the zero voltage switching of the main switch and reduce the active clamp return The energy loss of the freewheeling converter.

The above are only preferred embodiments of the present invention, and all changes made in accordance with the scope of the patent application of the present invention are equal And modifications should fall within the scope of the present invention.

GH, GL: control signal

IVS: Switch current indication signal

IVS_GL: target current value

IVS_GLR: Switch current value

IVSP: resonance extreme value

Pm11 to Pm41, Pc11, Pc12, Pc21, Pc22, Pc31, Pc32: pulse

TD1 to TD3: Delay time

TGH12 to TGH32: pulse width

Tdis1 to Tdis3: during discharge

Tglon1 to Tglon3: during charging

Tres1 to Tres3: during resonance

t1 to t24: time point

VD: Switching voltage

Claims (20)

An active clamp flyback converter for providing an output voltage to a load, including: a transformer, including: a primary circuit, including: a primary coil, including a first terminal for receiving an input Voltage, and a second terminal; and a secondary coil, including a first terminal for outputting an output voltage, and a second terminal; a main switch, including a control terminal, a first terminal, coupled to The second end of the primary coil, and a second end, the first end of the main switch has a switching voltage; a clamp switch includes a control end, a first end, and a second end, coupled Connected to the second terminal of the primary coil; a clamp capacitor, including a first terminal, coupled to the first terminal of the primary coil, and a second terminal, coupled to the first terminal of the clamp switch Terminal; a switching current indicating circuit, coupled to the transformer, used to generate a switching current indicating signal according to the switching voltage; and a controller, coupled to the switching current indicating circuit, the control terminal of the main switch and the The control terminal of the clamp switch includes: a parameter generating circuit for measuring a resonance extreme value of the switch current indicator signal after the clamp switch is applied with a uniform energy pulse during a resonance period, and in the main In the process of switching the switch from off to on state, one of the switching current indication signals that the main switch is finally measured in the off state is generated; a switching current value; and a delay control circuit is used to generate the switching current value according to the switching current value and the switching current value. The resonant extreme value adjusts a delay time signal, after another enable pulse is applied to the clamp switch, according to the delay time The signal turns on the main switch. The active clamp flyback converter according to claim 1, wherein the delay control circuit includes: a comparison voltage circuit for generating a difference current according to the resonance extreme value and the switching current value, and according to the difference The value current establishes a comparison voltage; a delay voltage circuit for establishing a delay voltage that starts to increase from the end time point of the enabling pulse; and a delay time circuit coupled to the comparison voltage circuit and the delay voltage The circuit is used to generate the delay time signal according to the comparison voltage and the delay voltage. The active clamp flyback converter of claim 2, wherein the comparison voltage circuit includes: a first current generator for generating a first predetermined current; and a second current generator for generating a first predetermined current according to the The resonance extreme value and the switching current value generate the difference current; and a first capacitor for establishing the comparison voltage according to the first predetermined current and the difference current, including a first terminal coupled to the first The current generator, the second current generator, and a second terminal are coupled to a ground terminal. The active clamp flyback converter according to claim 3, wherein: when the difference current is equal to the first predetermined current, the comparison voltage remains substantially stable; when the difference current is greater than the first predetermined current , The comparison voltage drops, thereby shortening the delay time signal; When the difference current is less than the first predetermined current, the comparison voltage rises, and the delay time signal is lengthened. According to the active clamp flyback converter of claim 3, the voltage comparison circuit further includes: a first switch, including a first terminal, coupled to the first current generator, and a second terminal, Coupled to the first terminal of the first capacitor; and a second switch, including a first terminal, coupled to the first terminal of the first capacitor, and a second terminal, coupled to the second A current generator; wherein the first switch and the second open relationship are turned on or off according to a short pulse signal. The active clamp flyback converter according to claim 2, wherein the delay voltage circuit includes: a third current generator for generating a second predetermined current; a third switch including a first terminal, Coupled to the third current generator, a second terminal, and a control terminal; a fourth switch, including a first terminal, coupled to the second terminal of the third switch, and a second terminal, Coupled to a ground terminal; and a second capacitor for establishing the delay voltage according to the second predetermined current, including a first terminal, the second terminal coupled to the third switch, and a second terminal , Coupled to the ground terminal. The active clamp flyback converter according to claim 6, wherein: the control terminal of the third switch is coupled to the input terminal of the flip-flop; and the enable pulse is used to control the first The turn-on and turn-off of the four switches. The active clamp flyback converter according to claim 2, wherein the delay time circuit includes: a comparator for generating a comparison signal according to the delay voltage and the comparison voltage, including a first input terminal, coupled Connected to the delay voltage circuit, a second input terminal, coupled to the comparison voltage circuit, and an output terminal for outputting the comparison signal; and a flip-flop including an input terminal for receiving a reverse Enabling pulse, a reset terminal, coupled to the output terminal of the comparator, for resetting the flip-flop according to the comparison signal, and an output terminal for outputting the delay time signal, the reverse The enabling pulse and the enabling pulse are in opposite phases to each other. The active clamp flyback converter according to claim 2, wherein the delay time signal starts from an end time point of the enabling pulse and lasts until the delay voltage increases to be greater than the comparison voltage. An active clamp flyback converter for providing an output voltage to a load, including: a transformer, including: a primary circuit, including: a primary coil, and a first terminal for receiving an input voltage , And a second terminal; and a secondary coil, including a first terminal for outputting an output voltage, and a second terminal; a main switch, including a control terminal, a first terminal, coupled to the The second end and a second end of the primary coil, the first end of the main switch has a switching voltage; a clamp switch, including a control end, a first end, and a second end, coupled In the primary coil The second terminal; a clamping capacitor, including a first terminal, coupled to the first terminal of the primary coil, and a second terminal, coupled to the first terminal of the clamp switch; a switching current An indicating circuit coupled to the transformer for generating a switching current indicating signal according to the switching voltage; and a controller coupled to the switching current indicating circuit, the control terminal of the main switch, and the clamp switch The control terminal includes: a parameter generating circuit for measuring a target current value of the switch current indication signal when the main switch is turned on, and measuring after the clamp switch is applied with a consistent energy pulse during a resonance period Obtain a resonance extreme value of the switching current indicator signal; and an on-time control circuit for adjusting a pulse width of another enable pulse (TGH2) according to the target current value and the resonance extreme value, and in the next resonance period The other enabling pulse is applied to the clamp switch. The active clamp flyback converter according to claim 10, wherein the on-time control circuit includes: a comparison voltage circuit for establishing a comparison voltage according to the target current value and the resonance extreme value; and a delay voltage circuit , For establishing a delay voltage, the delay voltage starts to increase from the start time point of the enabling pulse; and a uniform energy pulse circuit, coupled to the comparison voltage circuit and the delay voltage circuit, for starting the signal according to the uniform energy pulse Another enabling pulse is generated by triggering, and an end time point of the another enabling pulse is determined according to the comparison voltage and the delay voltage. The active clamp flyback converter according to claim 11, wherein the comparison voltage circuit Including: a first current generator for generating a first difference current according to the target current value and a first current; a second current generator for generating a first difference current according to the resonance extreme value and a second current A second difference current; and a first capacitor for establishing the comparison voltage, including a first terminal coupled to the first current generator and the second current generator, and a second terminal coupled to On a ground terminal. The active clamp flyback converter according to claim 12, wherein: the comparison voltage circuit is used to multiply the target current value by N to generate an offset target current value, and N is one less than or equal to 1 A positive number; and the first current generator is used to generate the first difference current between the offset target current value and the first current. According to the active clamp flyback converter of claim 12, the voltage comparison circuit further includes: a first switch including a first terminal, coupled to the first current generator, and a second terminal, Coupled to the first terminal of the first capacitor; and a second switch, including a first terminal, coupled to the first terminal of the first capacitor, and a second terminal, coupled to the second A current generator; wherein the first switch and the second open relationship are turned on or off according to a short pulse signal. The active clamp flyback converter according to claim 12, wherein: when the first difference current is equal to the second difference current, the comparison voltage remains substantially stable; When the first difference current is less than the second difference current, the comparison voltage drops, thereby shortening the pulse width of the other enabling pulse; when the first difference current is greater than the second difference current, The comparison voltage rises, thereby increasing the pulse width of the other enabling pulse. The active clamp flyback converter according to claim 11, wherein the delay voltage circuit includes: a third current generator for generating a predetermined current; a third switch including a first terminal coupled to At the third current generator, and a second terminal; a fourth switch, including a first terminal, coupled to the second terminal of the third switch, and a second terminal, coupled to the ground terminal And a second capacitor for establishing the delay voltage, including a first terminal, coupled to the second terminal of the third switch, and a second terminal, coupled to the ground terminal; wherein the enable The pulse and a reverse enabling pulse are respectively used to control the on and off of the third switch and the fourth switch, and the enabling pulse and the reverse enabling pulse are opposite to each other. The active clamp flyback converter according to claim 11, wherein the enabling pulse circuit includes: a comparator for generating a comparison signal according to the delay voltage and the comparison voltage, and including a first input terminal, Coupled to the delay voltage circuit, a second input terminal, coupled to the comparison voltage circuit, and an output terminal for outputting the comparison signal; and a flip-flop including an input terminal for receiving a pulse A start signal, a reset terminal, is coupled to the output terminal of the comparator, for resetting the flip-flop according to the comparison signal, and an output terminal for outputting the other enabling pulse. The active clamp flyback converter according to claim 1 or 10, wherein: the switching current indicating circuit includes an auxiliary coil and a voltage divider; the auxiliary coil includes a first terminal for providing an auxiliary coil The auxiliary coil voltage is positively related to the switching voltage, and a second terminal is coupled to a ground terminal; and the voltage divider includes a first impedance and includes a first terminal for receiving the auxiliary coil Voltage, and a second terminal; and a second impedance, including a first terminal, coupled to the second terminal of the first impedance, and a second terminal, coupled to a ground terminal, the auxiliary coil voltage The switch current indicating signal is outputted at the first end of the voltage divider through the voltage divider. An active clamp flyback converter for providing an output voltage to a load, including: a transformer, including: a primary circuit, including: a primary coil, and a first terminal for receiving an input voltage , And a second terminal; and a secondary coil, including a first terminal for outputting an output voltage, and a second terminal; a main switch, including a control terminal, a first terminal, coupled to the The second end and a second end of the primary coil; a clamp switch, including a control end, a first end, and a second end, coupled to the second end of the primary coil; a clamp The capacitor includes a first terminal, coupled to the first terminal of the primary coil, and a second terminal, coupled to the first terminal of the clamp switch; a switch current indicating circuit, coupled to the transformer, For generating a switching current indicating signal according to a switching voltage of the primary circuit; and A controller, coupled to the switch current indicating circuit, the control terminal of the main switch, and the control terminal of the clamp switch, includes: a parameter generation circuit for measuring the switch when the main switch is turned on A target current value of the current indicating signal. After the clamp switch is applied with a uniform energy pulse during a resonance period, a resonance extreme value of the switching current indicating signal is measured, and it is used to convert the main switch from off to During the on-state process, one of the switching current indication signals obtained by the last measurement of the main switch in the off-state is generated; a delay control circuit is used to adjust a delay time according to the switching current value and the resonance extreme value Signal, after another enabling pulse is applied to the clamp switch, the main switch is turned on according to the delay time signal; and an on-time control circuit is used to adjust another enabling pulse according to the target current value and the resonance extreme value A pulse width, and the other enabling pulse is applied to the clamp switch in the next resonance period. The active clamp flyback converter according to claim 19, wherein: the delay control circuit includes a first comparison voltage circuit, and the first comparison voltage circuit generates a first comparison voltage circuit according to the resonance extreme value and the switching current value Difference current, the delay control circuit adjusts the first difference current to approach a first predetermined current, thereby changing the delay time signal; and the on-time control circuit includes a second comparison voltage circuit, the second comparison voltage The circuit generates a second difference current according to the resonance extreme value and the target current value, and the on-time control circuit adjusts the second difference current to be smaller than a fixed ratio of the target current value, thereby changing the other enabling pulse A pulse width.

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