TWI741781B - Nitride epitaxial wafer and method for manufacturing the same - Google Patents

Abstract

This invention discloses a nitride epitaxial wafer with low lattice mismatch and low leakage current and method for manufacturing the same, which includes a substrate, an initial nucleation layer, a lattice mismatch modulation layer, at least one aluminum indium gallium nitride buffer layer, a high resistance layer, an intrinsic gallium nitride layer, an electron supply layer, and a cover layer. This invention uses indium nitride as the material of the initial nucleation layer, combined with the lattice mismatch modulation layer formed by aluminum indium nitride, thereby reducing the occurrence of lattice mismatch; and the initial nucleation layer further has at least one stack formed by the P-type indium nitride layer and the N-type indium nitride layer in the structure, the depletion region between the P-type indium nitride layer and the N-type indium nitride layer can block leakage current from the substrate.

Description

Nitride epitaxy wafer and its manufacturing method

The invention relates to a nitride epitaxial wafer, and particularly relates to a nitride epitaxial wafer with low lattice mismatch and low leakage current and a manufacturing method thereof.

During the wafer manufacturing process, when gallium nitride is grown on the silicon substrate, the gallium and the silicon substrate will react with each other, resulting in the phenomenon of gallium melting back to the silicon substrate. In order to overcome this phenomenon, the silicon Aluminum nitride is grown on the substrate to prevent gallium atoms from affecting the performance of the silicon substrate when gallium nitride is directly grown.

However, although the use of aluminum nitride can prevent the metal reflow phenomenon caused by gallium atoms when using gallium nitride, there is a large lattice mismatch between aluminum nitride and the silicon substrate.

In addition, when operating an electronic device with a nitride epitaxial wafer, the leakage current generated by the substrate will flow to the device operation area through the nucleation layer, which reduces the performance of the device during operation.

Therefore, in order to solve the above-mentioned problems of the prior art, the object of the present invention is to provide a nitride epitaxial wafer with low lattice mismatch and low leakage current and a method for manufacturing the same, in which indium nitride is substituted for aluminum nitride As the material of the initial nucleation layer, combined with the lattice mismatch modulation layer formed of aluminum indium nitride to improve the lattice mismatch.

Based on the above objective, the present invention provides a nitride epitaxial wafer, comprising: a base substrate; an initial nucleation layer, which is arranged on the base substrate; a lattice mismatch modulation layer, which is arranged on the initial nucleation layer; and at least one aluminum nitride The indium gallium buffer layer is arranged on the lattice mismatch modulation layer; the high resistance layer is arranged on at least one aluminum indium gallium nitride buffer layer; the intrinsic gallium nitride layer is arranged on the high resistance layer; the electron supply layer, It is arranged on the intrinsic gallium nitride layer; and the covering layer is arranged on the electron supply layer.

Preferably, the base substrate may be a silicon substrate, an aluminum nitride substrate, a diamond substrate, a silicon carbide substrate, a gallium oxide substrate, a boron nitride substrate, or a silicon crystal insulator substrate.

Preferably, the initial nucleation layer may be an indium nitride layer.

Preferably, the initial nucleation layer may have a structure formed by stacking a P-type indium nitride layer and an N-type indium nitride layer, and a void is formed between the P-type indium nitride layer and the N-type indium nitride layer. Zone to block leakage current through.

Preferably, the initial nucleation layer may have a structure in which a P-type indium nitride layer and an N-type indium nitride layer are used as stacked groups, and a plurality of stacked groups are repeatedly stacked, and the P-type indium nitride layer and the N-type indium nitride layer are stacked. A depletion region is formed between the indium nitride layers to prevent leakage current from passing through.

Preferably, the P-type indium nitride layer can be doped with magnesium, and the magnesium concentration is 1E16~1E23 atoms/cm ³ , and the N-type indium nitride layer can be doped with silicon, and the silicon concentration is 1E16~1E21 atoms/cm ³ .

Preferably, the aluminum content of the lattice mismatch modulation layer (Al _f In _1-f N) can gradually increase along the growth direction, and 0≦f<1.

Preferably, the at least one aluminum indium gallium nitride buffer layer may include a first aluminum indium gallium nitride buffer layer, a second aluminum indium gallium nitride buffer layer, and a third aluminum indium gallium nitride buffer layer, and the first nitrogen The chemical composition of the aluminum indium gallium buffer layer may be In _g Al _e Ga _1-eg N, and 0.75≦e<1, 0<g≦0.25; the chemical composition of the second aluminum indium gallium nitride buffer layer may be In _h Al _d Ga _1-dh N, and 0.5≦d≦0.75, 0.25<h<0.5; and the chemical composition of the third aluminum indium gallium nitride buffer layer may be In _i Al _c Ga _1-ci N, and 0.3≦c ≦0.5, 0.5<i<0.7.

Preferably, the first aluminum indium gallium nitride buffer layer, the second aluminum indium gallium nitride buffer layer, and the third aluminum indium gallium nitride buffer layer may be undoped, or be doped with carbon or iron, respectively. , And at least one of magnesium doping and combinations thereof.

Preferably, when the first aluminum indium gallium nitride buffer layer, the second aluminum indium gallium nitride buffer layer, and the third aluminum indium gallium nitride buffer layer are doped with carbon, the carbon concentration is between 1E16~1E21 atoms/cm ³ ; When the first aluminum indium gallium nitride buffer layer, the second aluminum indium gallium nitride buffer layer, and the third aluminum indium gallium nitride buffer layer are doped with iron, the iron concentration is between 1E16~1E20 atoms/cm ³ ; When the first aluminum indium gallium nitride buffer layer, the second aluminum indium gallium nitride buffer layer, and the third aluminum indium gallium nitride buffer layer are doped with magnesium, the magnesium concentration is between 1E16-1E20 atoms/cm ³ .

Preferably, the chemical composition of the high resistance layer can be In _j Al _b Ga _1-bj N, and 0≦b≦0.1, 0<j≦0.9, and the high resistance layer can be carbon doped, iron doped, and Magnesium is doped with at least one of them and a combination thereof.

Preferably, when the high resistance layer is doped with carbon, the carbon concentration is between 1E16~1E21 atoms/cm ³ ; when the high resistance layer is doped with iron, the iron concentration is between 1E16~1E20 atoms/cm ³ ; when the high resistance layer is doped In the case of magnesium doping, the magnesium concentration is between 1E16~1E20 atoms/cm ³ .

Preferably, the chemical composition of the electron supply layer may be In _x Al _y Ga _1-xy N, and 0≦y≦0.3, 0≦x≦0.3.

Preferably, the chemical composition of the covering layer may be Al _z Ga _1-z N, and 0≦z≦0.3, and the covering layer may be undoped or P-type doped. When the covering layer is P-type doped, The doping element is magnesium, and the magnesium concentration is between 1E16~1E23 atoms/cm ³ .

Preferably, a defect barrier layer may be further provided between the initial nucleation layer and the lattice mismatch modulation layer, and the defect barrier layer may be silicon nitride or magnesium nitride.

Preferably, in the nitride epitaxy wafer, there may be an initial nucleation layer and a defect barrier layer or a defect barrier layer and a lattice mismatch modulation layer as a stack group, and multiple stack groups are repeatedly stacked To form the structure.

Based on the above objective, the present invention further provides a method for manufacturing a nitride epitaxial wafer, which includes the following steps.

(1) Provide a base substrate.

(2) Form an initial nucleation layer on the base substrate.

(3) A lattice mismatch modulation layer is formed on the initial nucleation layer.

(4) At least one aluminum indium gallium nitride buffer layer is formed on the lattice mismatch modulation layer.

(5) A high resistance layer is formed on at least one aluminum indium gallium nitride buffer layer.

(6) An essential gallium nitride layer is formed on the high resistance layer.

(7) An electron supply layer is formed on the intrinsic gallium nitride layer.

(8) A covering layer is formed on the electron supply layer.

Preferably, the base substrate is a silicon substrate, an aluminum nitride substrate, a diamond substrate, a silicon carbide substrate, a gallium oxide substrate, a boron nitride substrate, or a silicon crystal insulator substrate.

Preferably, the step of forming the initial nucleation layer on the base substrate may further include the following steps: the first step, the growth temperature is 500-550°C, and the indium nitride is grown at the first V/III ratio; the second step , The growth temperature is 700~750°C, and indium nitride is grown with the second V/III ratio; and the third step, the growth temperature is 500~550°C, and the third The V/III ratio grows indium nitride, and the range of the first V/III ratio and the third V/III ratio is 0.5-50, and the range of the second V/III ratio is 500-3000.

Preferably, the step of forming the initial nucleation layer may further include a step of stacking a P-type indium nitride layer and an N-type indium nitride layer to form the initial nucleation layer, or a P-type indium nitride layer and N The type indium nitride layer is used as a stacked group, and the step of stacking a plurality of stacked groups to form an initial nucleation layer is repeated.

Preferably, in the step of forming the lattice mismatch modulation layer on the initial nucleation layer, the growth temperature can gradually increase from 500 to 550 degrees to 900 to 1100 degrees over time, and the lattice mismatch modulation layer is formed The aluminum content can gradually increase along its growth direction.

Preferably, in the step of forming the lattice mismatch modulation layer on the initial nucleation layer, the growth temperature has a temperature rise slope, and the temperature rise slope can be 30-100°C/min

Preferably, the manufacturing method of the nitride epitaxial wafer may further include a step of forming a defect barrier layer between the initial nucleation layer and the lattice mismatch modulation layer, and the defect barrier layer is silicon nitride or magnesium nitride.

Preferably, the method for manufacturing a nitride epitaxial wafer may further include a stacking group of an initial nucleation layer and a defect barrier layer or a defect barrier layer and a lattice mismatch modulation layer, and repeatedly stacking a plurality of stacked groups step.

Preferably, the method for forming each layer includes chemical vapor deposition or physical vapor deposition.

As mentioned above, the nitride epitaxial wafer and its manufacturing method of the present invention are improved by using indium nitride as the material of the initial nucleation layer and combining with the lattice mismatch modulation layer formed by aluminum indium nitride. The case of lattice mismatch. Moreover, through the structure of stacking the P-type indium nitride layer and the N-type indium nitride layer of the initial nucleation layer, the depletion region between the P-type indium nitride layer and the N-type indium nitride layer The leakage current generated by the substrate can be prevented from flowing into the device operation area, thereby preventing performance degradation during device operation, so that the nitride epitaxial wafer of the present invention has the effects of low lattice mismatch and low leakage current.

In addition, the present invention improves the crystal quality of each layer by controlling the temperature and the content ratio of each element in the process, and further reduces the lattice mismatch between the layers. Moreover, in the present invention, a defect barrier layer is provided between the initial nucleation layer and the lattice mismatch modulation layer to prevent the defects of the initial nucleation layer from extending upward through the defect barrier layer, thereby avoiding the initial nucleation layer The defects affect the crystal quality of the lattice mismatch modulation layer.

100, 101, 102: Nitride epitaxy wafer

1: base substrate

2: Initial nucleation layer

21: P-type indium nitride layer

22: N-type indium nitride layer

3: Lattice mismatch modulation layer

4: Aluminum indium gallium nitride buffer layer

41: The first aluminum indium gallium nitride buffer layer

42: The second aluminum indium gallium nitride buffer layer

43: The third aluminum indium gallium nitride buffer layer

5: High resistance layer

6: Essential GaN layer

7: Electronic provision layer

8: Covering layer

9: Defect barrier layer

S1, S2, S21, S22, S23, S24, S25, S3, S4, S5, S6, S7, S8, S9: steps

In order to explain the technical solution of the present invention more clearly, the following will briefly introduce the drawings that need to be used in the embodiments; Figure 1 is a schematic diagram of a nitride epitaxial wafer according to an embodiment of the present invention; Figure 2 is A schematic diagram of an initial nucleation layer in a nitride epitaxial wafer according to an embodiment of the present invention; FIG. 3 is a flowchart of a method for manufacturing a nitride epitaxial wafer according to an embodiment of the present invention; FIG. 4A is an embodiment according to the present invention The detailed flowchart of step S2 in the method of manufacturing an epitaxial nitride wafer; FIG. 4B is a detailed flowchart of another embodiment of step S2 in the method of manufacturing an epitaxial nitride wafer according to an embodiment of the present invention; FIG. 5 It is a schematic diagram of a nitride epitaxial wafer with a repeated stack structure of an initial nucleation layer/defect barrier layer according to another embodiment of the present invention; FIG. 6 is a diagram of a defect barrier layer/crystal according to still another embodiment of the present invention A schematic diagram of a nitride epitaxial wafer with a repeated stacked structure of lattice mismatch modulation layers.

Hereinafter, the present invention will be further described in detail with reference to the accompanying drawings. These drawings are simplified schematic diagrams, which merely illustrate the basic structure of the present invention in a schematic manner, and exaggerate the proportions and sizes of elements for clarity, and therefore are not intended to limit the present invention.

Please refer to FIG. 1 and FIG. 2. FIG. 1 is a schematic diagram of an epitaxial nitride wafer according to an embodiment of the present invention; FIG. 2 is an initial formation of an epitaxial nitride wafer according to an embodiment of the present invention. Schematic diagram of the nuclear layer.

As shown in Figure 1, the present invention provides a nitride epitaxial wafer 100 with low lattice mismatch and low leakage current, which includes: a base substrate 1; an initial nucleation layer 2 provided on the base substrate 1; The lattice mismatch modulation layer 3 on the nucleation layer 2; the first aluminum indium gallium nitride buffer layer 41 disposed on the lattice mismatch modulation layer 3; the first aluminum indium gallium nitride buffer layer 41 disposed on the lattice mismatch modulation layer 3 The second aluminum indium gallium nitride buffer layer 42 on the upper part; the third aluminum indium gallium nitride buffer layer 43 arranged on the second aluminum indium gallium nitride buffer layer 42; the third aluminum indium gallium nitride buffer layer 43 arranged on the third aluminum indium gallium nitride buffer layer 43 The high resistance layer 5 on the high resistance layer 5; the intrinsic gallium nitride layer 6 provided on the high resistance layer 5; the electron supply layer 7 provided on the intrinsic gallium nitride layer 6; and the cover layer 8 provided on the electron supply layer 7.

In this embodiment, the base substrate 1 is a silicon substrate, but the present invention is not limited to this. For example, in other embodiments, an aluminum nitride substrate, a diamond substrate, a silicon carbide substrate, a gallium oxide substrate, and a boron nitride substrate can be used. , Or other types of substrates such as silicon insulator substrates as base substrates.

The initial nucleation layer 2 is an indium nitride layer, which is disposed on the base substrate 1 and has a total thickness of 3-50 nm. It is worth mentioning that, as shown in FIG. 2, the initial nucleation layer 2 may have a structure in which a P-type indium nitride layer 21 and an N-type indium nitride layer 22 are stacked to form a structure, or It may have a structure in which a P-type indium nitride layer 21 and an N-type indium nitride layer 22 are used as a stack group, and a plurality of stack groups are repeatedly stacked to form a structure. In the initial nucleation layer 2, a depletion region is formed between the P-type indium nitride layer 21 and the N-type indium nitride layer 22. The depletion region can block the leakage current generated by the base substrate when the device is operated to prevent leakage current. Cause the performance of the component to decrease.

In this embodiment, five sets of the above-mentioned stacks (P-type indium nitride layer/N-type indium nitride layer) are repeatedly stacked to form the initial nucleation layer 2, but the present invention is not limited to this, in other embodiments , The number of stacking groups that can be repeatedly stacked is between 1 and 10 groups. Moreover, in this embodiment, the P-type indium nitride layer 21 is formed first and then the N-type indium nitride layer 22 is formed. However, in other embodiments, the N-type indium nitride layer 22 may be formed first and then the P-type indium nitride layer 22 is formed. -Type indium nitride layer 21. In other words, the P-type indium nitride layer 21 and the N-type indium nitride layer 22 only need to be alternately formed, and the order of their formation does not affect the formation of the initial nucleation layer 2.

Further, in this embodiment, the P-type indium nitride layer 21 is doped with magnesium, and the magnesium concentration is 1E16~1E23 atoms/cm ³ , and the N-type indium nitride layer 22 is doped with silicon, and the silicon concentration is 1E16~ 1E21atoms/cm ³ .

Please refer to FIG. 1 again to continue the description of the structure of the nitride epitaxial wafer 100 with low lattice mismatch and low leakage current. Wherein, the lattice mismatch modulation layer 3 is disposed on the initial nucleation layer 2, and _{the aluminum content of the lattice mismatch modulation layer 3 (Al f} In _1-f N) gradually increases along the growth direction, and 0≦f <1. Further, by adjusting the aluminum content when forming the lattice mismatch modulation layer 3, the lattice constant of the lattice mismatch modulation layer 3 at the end of the growth can be matched to the first aluminum indium gallium nitride buffer layer 41. To reduce the occurrence of lattice mismatch. In addition, the thickness of the lattice mismatch modulation layer 3 is between 10 nm and 500 nm.

It is worth mentioning that a defect barrier layer 9 can be further provided between the initial nucleation layer 2 and the lattice mismatch modulation layer 3, and the thickness of the defect barrier layer 9 is between 2-20 nm. In this embodiment, silicon nitride is used as the defect barrier layer 9, but the present invention is not limited to this. In other embodiments, Magnesium nitride is used as the defect barrier layer 9. The defect barrier layer 9 is used to block the defects of the initial nucleation layer 2 from extending upward, so as to prevent the defects of the initial nucleation layer 2 from affecting the crystal quality of the lattice mismatch modulation layer 3. In this embodiment, only a defect barrier layer 9 is provided between the initial nucleation layer 2 and the lattice mismatch modulation layer 3. However, the present invention is not limited to this. In other embodiments, a plurality of defects may be provided. Layer defect barrier layer, or no defect barrier layer. Other implementations of the defect barrier layer will be described in detail in other embodiments below.

At least one aluminum indium gallium nitride buffer layer 4 may be provided on the lattice mismatch modulation layer 3. In this embodiment, three aluminum indium gallium nitride buffer layers 4 are provided, which are the first aluminum indium gallium nitride buffer layer 41, the second aluminum indium gallium nitride buffer layer 42, and the third aluminum indium gallium nitride buffer layer. The gallium buffer layer 43, but the present invention is not limited thereto. In other embodiments, the number of the aluminum indium gallium nitride buffer layer 4 can be increased or decreased according to the needs of the user or considering the process cost. Specifically, the first aluminum indium gallium nitride buffer layer 41 is disposed on the lattice mismatch modulation layer 3, and the second aluminum indium gallium nitride buffer layer 42 is disposed on the first aluminum indium gallium nitride buffer layer 41, And the third aluminum indium gallium nitride buffer layer 43 is disposed on the second aluminum indium gallium nitride buffer layer 42. Further, the chemical composition of the first aluminum indium gallium nitride buffer layer 41 is In _g Al _e Ga _1-eg N, and 0.75≦e<1, 0<g≦0.25; the second aluminum indium gallium nitride buffer layer 42 The chemical composition of In _h Al _d Ga _1-dh N, and 0.5≦d≦0.75, 0.25<h<0.5; and the chemical composition of the third aluminum indium gallium nitride buffer layer 43 is In _i Al _c Ga _1-ci N, and 0.3≦c≦0.5, 0.5<i<0.7, that is, the aluminum content of each aluminum indium gallium nitride buffer layer 4 decreases sequentially.

In addition, the first aluminum indium gallium nitride buffer layer 41, the second aluminum indium gallium nitride buffer layer 42, and the third aluminum indium gallium nitride buffer layer 43 may be undoped, or carbon-doped, iron-doped, respectively. At least one of doping, and magnesium doping, and combinations thereof. That is, each aluminum indium gallium nitride buffer layer 4 can be doped with a single element, such as carbon, iron, or magnesium, or can be doped with two elements, such as carbon and iron, carbon and magnesium, or iron and magnesium. Doping at the same time, or can be doped at the same time three elements of carbon, iron, and magnesium.

Further, when the first aluminum indium gallium nitride buffer layer 41, the second aluminum indium gallium nitride buffer layer 42, and the third aluminum indium gallium nitride buffer layer 43 are doped with carbon, the carbon concentration is between 1E16~1E21 atoms. /cm ³ ; when the first aluminum indium gallium nitride buffer layer 41, the second aluminum indium gallium nitride buffer layer 42, and the third aluminum indium gallium nitride buffer layer 43 are doped with iron, the iron concentration is between 1E16~ 1E20 atoms/cm ³ ; when the first aluminum indium gallium nitride buffer layer 41, the second aluminum indium gallium nitride buffer layer 42, and the third aluminum indium gallium nitride buffer layer 43 are doped with magnesium, the magnesium concentration is between 1E16 ~1E20atoms/cm ³ . In addition, the thickness of each aluminum indium gallium nitride buffer layer 4 is between 50 nm and 1000 nm.

The high resistance layer 5 is disposed on the third aluminum indium gallium nitride buffer layer 43, and the chemical composition of the high resistance layer 5 is In _j Al _b Ga _1-bj N, and 0≦b≦0.1, 0<j≦0.9, which The aluminum content is lower than that of the third aluminum indium gallium nitride buffer layer 43. In addition, the high-resistance layer 5 may be at least one of carbon doping, iron doping, and magnesium doping and combinations thereof, that is, the high-resistance layer 5 may be doped with a single element, such as carbon, iron, or magnesium, Alternatively, two elements can be doped at the same time, for example, carbon and iron, carbon and magnesium, or iron and magnesium can be doped at the same time, or three elements of carbon, iron, and magnesium can be doped at the same time.

Moreover, when the high resistance layer 5 is doped with carbon, the carbon concentration is between 1E16~1E21 atoms/cm ³ ; when the high resistance layer 5 is doped with iron, the iron concentration is between 1E16~1E20 atoms/cm ³ ; When 5 is doped with magnesium, the magnesium concentration is between 1E16~1E20 atoms/cm ³ . In addition, the thickness of the high resistance layer 5 is between 500 nm and 3000 nm.

The essential gallium nitride layer 6 is disposed on the high resistance layer 5, which is composed of gallium nitride and is not doped with other elements, and the thickness of the essential gallium nitride layer 6 is between 50-800 nm.

The electron supply layer 7 is disposed on the intrinsic gallium nitride layer 6, and the chemical composition of the electron supply layer 7 is In _x Al _y Ga _1-xy N, and 0≦y≦0.3, 0≦x≦0.3. In addition, the thickness of the electron supply layer 7 is between 8 and 30 nm.

The covering layer 8 is disposed on the electron supply layer 7, and the chemical composition of the covering layer 8 is Al _z Ga _1-z N, and 0≦z≦0.3, and the covering layer 8 may be undoped or P-type doped. When the covering layer 8 is P-type doped, the doping element is magnesium, the magnesium concentration is between 1E16-1E23 atoms/cm ³ , and the thickness is between 10-200 nm. In addition, when the covering layer 8 is undoped, its thickness is between 0.5 and 20 nm, and _{the optimum content of the covering layer 8 (Al z} Ga _1-z N) is z=0.

Please refer to FIG. 3, FIG. 4A, and FIG. 4B. FIG. 3 is a flowchart of a method for manufacturing a nitride epitaxy wafer according to an embodiment of the present invention; FIG. 4A is a nitride epitaxy according to an embodiment of the present invention The detailed flowchart of step S2 in the wafer manufacturing method; FIG. 4B is a detailed flowchart of another implementation of step S2 in the method for manufacturing an epitaxial nitride wafer according to an embodiment of the present invention.

Hereinafter, a method of manufacturing a nitride epitaxial wafer according to an exemplary embodiment will be described with reference to FIG. 3. It includes: step S1, providing a base substrate; step S2, forming an initial nucleation layer on the base substrate; step S3, forming a defect barrier layer on the initial nucleation layer; step S4, forming a lattice mismatch modulation layer on the defect On the barrier layer; step S5, forming at least one aluminum indium gallium nitride buffer layer on the lattice mismatch modulation layer; step S6, forming a high resistance layer on the at least one aluminum indium gallium nitride buffer layer; step S7, An essential gallium nitride layer is formed on the high resistance layer; step S8, an electron supply layer is formed on the essential gallium nitride layer; step S9, a covering layer is formed on the electron supply layer.

Referring to Figure 3, first, a base substrate is provided (as shown in step S1). In this embodiment, a silicon substrate is used as the base substrate, but the present invention is not limited to this. In other embodiments, an aluminum nitride substrate, Diamond substrates, silicon carbide substrates, gallium oxide substrates, boron nitride substrates, or silicon crystal insulator substrates and other types of substrates are used as base substrates.

Next, an initial nucleation layer is formed on the base substrate (as shown in step S2), and the step S2 of forming the initial nucleation layer may further include the following three steps: The first step is to use an organometallic chemical gas on the base substrate. The phase deposition method (MOCVD, Metal Organic Chemical-Vapor Deposition) grows indium nitride, and its growth temperature is set at 500~550℃, In addition, indium nitride is grown with a lower first V/III ratio, where the first V/III ratio is between 0.5 and 50. The above-mentioned process conditions facilitate the formation of indium nitride, and the nitrogen formed in the first step The thickness of indium is 1~10nm; in the second step, MOCVD is also used to grow indium nitride on the indium nitride formed in the first step. The growth temperature is increased to 700~750℃, and the second V /III ratio grows indium nitride, where the second V/III ratio is between 500 and 3000. The high growth temperature in the second step is used to alloy the indium nitride formed in the first step to improve Its crystal quality, and the high V/III ratio can slow down its growth rate, so that the indium nitride grown in the second step can maintain the crystal quality of the alloyed indium nitride, and the nitrogen formed in the second step The thickness of indium is 1~5nm; in the third step, MOCVD is also used to successively grow indium nitride on the indium nitride formed in the second step. The growth temperature is set at 500~550°C and the third V /III ratio grows indium nitride, where the third V/III ratio is between 0.5~50. The third step is based on the indium nitride layer with better crystal quality grown in the second step to continuously increase its In addition, the thickness of the indium nitride is 1~35nm. Therefore, the total thickness of the initial nucleation layer is 3-50nm.

Please refer to FIGS. 4A and 4B together. The step of forming the initial nucleation layer may further include using a P-type indium nitride layer and an N-type indium nitride layer as a stack group, and repeatedly stacking a plurality of stack groups, To form the initial nucleation layer 2 with a plurality of P-type indium nitride layers 21 and a plurality of N-type indium nitride layers 22 as shown in FIG. 2 (as shown in FIG. 4A); or just stack A P-type indium nitride layer and an N-type indium nitride layer to form an initial nucleation layer (as shown in Figure 4B). Further, in this embodiment, the P-type indium nitride layer is doped with magnesium, and the N-type indium nitride layer is doped with silicon. In addition, a depletion region is formed between the P-type indium nitride layer and the N-type indium nitride layer. The depletion region can block the leakage current generated by the base substrate when the device is operated, so as to prevent the leakage current from degrading the performance of the device.

Referring to Figure 4A, specifically, in the step of forming the initial nucleation layer, a P-type indium nitride layer can be formed on the base substrate (as shown in step S21), and the P-type indium nitride layer An N-type indium nitride layer is formed on the N-type indium nitride layer (as shown in step S22), and then a P-type indium nitride layer is formed on the N-type indium nitride layer (as shown in step S23). An N-type indium nitride layer is formed on the indium layer (as shown in step S24), and step S23 and step S24 can be repeatedly performed as required to repeatedly stack a P-type indium nitride layer and an N-type indium nitride layer, and the stacking is repeated The number of groups can be 1~10 groups. In addition, in other embodiments, the P-type indium nitride layer and the N-type indium nitride layer only need to be alternately formed, and the order of their formation does not affect the formation of the initial nucleation layer 2. In other words, although the P-type indium nitride layer is formed first and then the N-type indium nitride layer is formed in this embodiment, in other embodiments, the N-type indium nitride layer may be formed first and then the P-type nitride layer is formed. Indium layer.

In addition, in the step of forming the initial nucleation layer, as shown in FIG. 4B, a P-type indium nitride layer may be formed on the base substrate (as shown in step S21), and formed on the P-type indium nitride layer The N-type indium nitride layer (as shown in step S22), that is, the step of forming the initial nucleation layer is completed, and only the initial nucleation layer having a P-type indium nitride layer and an N-type indium nitride layer is formed.

Please refer to Figure 3 again to continue the description of the manufacturing method of the nitride epitaxial wafer. After the initial nucleation layer is formed on the base substrate, MOCVD is then used to form a defect barrier layer on the initial nucleation layer (as shown in step S3). The defect barrier layer is silicon nitride or magnesium nitride, and its thickness is between In 2~20nm. The defect barrier layer is used to prevent the defects of the initial nucleation layer from extending upward to prevent them from affecting the crystal quality of the lattice mismatch modulation layer.

It is worth mentioning that in other embodiments, the defect barrier layer may not be provided, and the lattice mismatch modulation layer may be directly formed on the initial nucleation layer. Alternatively, a plurality of defect barrier layers may be provided. Other implementations of the defect barrier layer will be described in detail in other embodiments below.

After the defect barrier layer is formed, MOCVD is then used to form a lattice mismatch modulation layer on the defect barrier layer (as shown in step S4). In addition, in embodiments where the defective barrier layer is not formed, the lattice mismatch modulation layer may be directly formed on the initial nucleation layer. In step S4, the growth temperature of the lattice mismatch modulation layer (Al _f In _1-f N) gradually increases from 500 to 550 degrees to 900 to 1100 degrees over time, and the aluminum of the lattice mismatch modulation layer is formed The content can gradually increase along its growth direction, and 0≦f<1. Further, by adjusting the aluminum content when forming the lattice mismatch modulation layer, the lattice constant of the lattice mismatch modulation layer at the end of the growth can be matched with the aluminum indium gallium nitride buffer layer to reduce the lattice mismatch. The situation happened. In addition, the thickness of the lattice mismatch modulation layer is between 10 nm and 500 nm.

It is worth mentioning that in the step S4 of forming the lattice mismatch modulation layer on the defect barrier layer, _{when the growth temperature of the lattice mismatch modulation layer (Al f} In _1-f N) is increased, the growth temperature is It can have a specific ramp rate. Specifically, the heating slope can be 30-100° C./min, and the growth temperature gradually increases from 500 to 550 degrees to 900 to 1100 degrees over time according to the heating slope.

After the lattice mismatch modulation layer is formed, MOCVD is then used to form at least one aluminum indium gallium nitride buffer layer on the lattice mismatch modulation layer (as shown in step S5). In step S5, the growth temperature of each aluminum indium gallium nitride buffer layer is between 950 and 1300 degrees, and at least one aluminum indium gallium nitride buffer layer can be formed as required. In addition, the aluminum content of each aluminum indium gallium nitride buffer layer may be different, for example, the aluminum content of each aluminum indium gallium nitride buffer layer may gradually decrease along the growth direction. Moreover, each aluminum indium gallium nitride buffer layer may be undoped, or at least one of carbon doping, iron doping, and magnesium doping and a combination thereof, and the thickness of each aluminum indium gallium nitride buffer layer is between At 50~1000nm.

After forming at least one aluminum indium gallium nitride buffer layer, MOCVD is then used to form a high resistance layer on the at least one aluminum indium gallium nitride buffer layer (as shown in step S6), and the chemical composition of the high resistance layer is In _j Al _b Ga _1-bj N, and 0≦b≦0.1, 0<j≦0.9. In step S6, the growth temperature of the high resistance layer is between 950 and 1300 degrees and is formed on the uppermost aluminum indium gallium nitride buffer layer. In addition, the high resistance layer may be at least one of carbon doping, iron doping, and magnesium doping and a combination thereof, and the thickness of the high resistance layer is 500-3000 nm.

After forming the high-resistance layer, continue to use MOCVD to form the essence on the high-resistance layer Gallium nitride layer (as shown in step S7). In step S7, the growth temperature of the intrinsic gallium nitride layer is between 950 and 1300 degrees and is formed on the high resistance layer. In addition, the thickness of the intrinsic GaN layer is between 50 and 800 nm.

After the essential gallium nitride layer is formed, an electron supply layer is subsequently formed on the essential gallium nitride layer by MOCVD (as shown in step S8). The chemical composition of the electron supply layer is In _x Al _y Ga _1-xy N, and 0 ≦y≦0.3, 0≦x≦0.3. In step S8, the growth temperature of the electron supply layer is between 950 and 1300 degrees and is formed on the intrinsic gallium nitride layer. In addition, the thickness of the electron supply layer ranges from 8 to 30 nm.

After the electron supply layer is formed, a cover layer is subsequently formed on the electron supply layer by MOCVD (as shown in step S9), the chemical composition of the cover layer is Al _z Ga _1-z N, and 0≦z≦0.3. In step S9, the growth temperature of the covering layer is between 950 and 1300 degrees and is formed on the electron supply layer. In addition, the cover layer can be undoped or P-type doped. When the cover layer is undoped, its thickness is between 0.5 and 20 nm; when the cover layer is P-type doped, its doping element is magnesium, and Its thickness is between 10 and 200 nm.

Furthermore, although the metal-organic chemical vapor deposition method is used in the above steps, in other embodiments, other types of chemical vapor deposition process or physical vapor deposition process can be used to achieve the same effect. For example, the use of plasma enhanced chemical vapor deposition (PECVD, Plasma Enhanced Chemical Vapor Deposition), hybrid physical chemical vapor deposition (HPCVD, Hybrid Physical Chemical Vapor Deposition), vacuum evaporation deposition (Vacuum Evaporation Deposition), and sputtering deposition ( Sputter Deposition) etc., but the present invention is not limited to this.

Please refer to FIG. 5, which is a schematic diagram of a nitride epitaxial wafer with a repeated stack structure of an initial nucleation layer/defect barrier layer according to another embodiment of the present invention.

As shown in the figure, an epitaxial nitride wafer 101 according to another embodiment of the present invention has a similar structure to that of the epitaxial nitride wafer 100 in the first embodiment. However, in this embodiment, the initial nucleation layer 2 and the defect barrier layer 9 are repeatedly stacked in a superlattice manner to further block the defects of the initial nucleation layer 2 from extending upward through the plurality of defect barrier layers 9 It is avoided to affect the crystal quality of the lattice mismatch modulation layer 3. Specifically, the initial nucleation layer 2 is formed by MOCVD on the base substrate 1, and the defect barrier layer 9 is also formed on the initial nucleation layer 2 by MOCVD. In this embodiment, the initial nucleation layer 2 is repeatedly formed. And the defect barrier layer 9 to stack five sets of initial nucleation layer/defect barrier layer on the base substrate 1, but the present invention is not limited to this. For example, in other embodiments, 2-10 sets of initial nucleation layer/defect barrier layer may be stacked repeatedly. After repeatedly stacking a plurality of initial nucleation layers/defect barrier layers, a lattice mismatch modulation layer 3, at least one aluminum indium gallium nitride buffer layer 4, and a high resistance layer 5 are successively formed on the defect barrier layer 9. The intrinsic gallium nitride layer 6, the electron supply layer 7, and the cover layer 8 are structured to form a nitride epitaxial wafer 101 with low lattice mismatch and low leakage current. In addition, in this embodiment, silicon nitride is used as the defect barrier layer 9, but the present invention is not limited to this. In other embodiments, magnesium nitride may be used as the defect barrier layer.

Please refer to FIG. 6, which is a schematic diagram of a nitride epitaxial wafer with a repeated stack structure of defect barrier layer/lattice mismatch modulation layer according to still another embodiment of the present invention.

As shown in the figure, an epitaxial nitride wafer 102 according to still another embodiment of the present invention has a similar structure to that of the epitaxial nitride wafer 100 in the first embodiment. However, in this embodiment, the defect barrier layer 9 and the lattice mismatch modulation layer 3 are repeatedly stacked in a superlattice manner, so as to further block the defects of the initial nucleation layer 2 through the plurality of defect barrier layers 9 Extension, thereby avoiding its influence on the crystal quality of the lattice mismatch modulation layer 3. Specifically, MOCVD is used to form the initial nucleation layer 2 on the base substrate 1, and MOCVD is used to form the defect barrier layer 9 on the initial nucleation layer 2, and MOCVD is also used to form the lattice defect on the defect barrier layer 9. The configuration modulation layer 3, in this embodiment, the defect barrier layer 9 and the lattice mismatch modulation are repeatedly formed Layer 3 is to stack five groups of defect barrier layers/lattice mismatch modulation layers on the initial nucleation layer 2, but the present invention is not limited to this. For example, in other embodiments, 2-10 sets of defect barrier layers/lattice mismatch modulation layers can be stacked repeatedly. After repeatedly stacking a plurality of defect barrier layers/lattice mismatch modulation layers, at least one aluminum indium gallium nitride buffer layer 4, high resistance layer 5, and intrinsic gallium nitride layer 6 are successively formed on the defect barrier layer 9 , The electron supply layer 7, and the cover layer 8, to form a nitride epitaxial wafer 102 with low lattice mismatch and low leakage current. In addition, in this embodiment, silicon nitride is used as the defect barrier layer 9, but the present invention is not limited to this. In other embodiments, magnesium nitride may be used as the defect barrier layer.

In summary, the present invention provides a nitride epitaxial wafer with low lattice mismatch and low leakage current and a method for manufacturing the same. Indium nitride is used instead of aluminum nitride as the material for the initial nucleation layer, combined with aluminum nitride The lattice mismatch modulating layer formed by indium can improve the situation of lattice mismatch. In addition, the initial nucleation layer has a structure formed by stacking a P-type indium nitride layer and an N-type indium nitride layer. The depletion region between the P-type indium nitride layer and the N-type indium nitride layer can prevent leakage from the substrate. Current flows into the operating area of the component, thereby preventing performance degradation during component operation.

In addition, the present invention further improves the crystal quality of each layer and reduces the lattice mismatch between the layers by controlling the temperature and the content ratio of each element in the process. In addition, by providing a defect barrier layer between the initial nucleation layer and the lattice mismatch modulation layer, the defect barrier layer can prevent the defects of the initial nucleation layer from extending upward, thereby avoiding the effect of the defects of the initial nucleation layer Lattice mismatch modulates the crystal quality of the layer.

The present invention has been described with reference to exemplary embodiments. Those with ordinary knowledge in the art can understand that, without departing from the concept and scope of the present invention defined by the scope of the patent application, it can be described in form and detail. Various changes and equivalent arrangements, therefore, the scope of protection of the present invention shall be subject to those defined by the attached patent scope.

100: Nitride epitaxy wafer

1: base substrate

2: Initial nucleation layer

3: Lattice mismatch modulation layer

4: Aluminum indium gallium nitride buffer layer

41: The first aluminum indium gallium nitride buffer layer

42: The second aluminum indium gallium nitride buffer layer

43: The third aluminum indium gallium nitride buffer layer

5: High resistance layer

6: Essential GaN layer

7: Electronic provision layer

8: Covering layer

9: Defect barrier layer

Claims (23)

A nitride epitaxial wafer, comprising: a base substrate; an initial nucleation layer arranged on the base substrate; a lattice mismatch modulation layer arranged on the initial nucleation layer; at least one aluminum indium gallium nitride A buffer layer arranged on the lattice mismatch modulation layer; a high resistance layer arranged on the at least one aluminum indium gallium nitride buffer layer; an intrinsic gallium nitride layer arranged on the high resistance layer; An electron supply layer is provided on the intrinsic gallium nitride layer; and a covering layer is provided on the electron supply layer; wherein a defect barrier is further provided between the initial nucleation layer and the lattice mismatch modulation layer Layer, and the defect barrier layer is silicon nitride or magnesium nitride; wherein the initial nucleation layer and the defect barrier layer or the defect barrier layer and the lattice mismatch modulation layer are used as a stack group, And repeat the stacking of 2 to 10 sets of the stack to form a structure. The nitride epitaxial wafer according to claim 1, wherein the base substrate is a silicon substrate, an aluminum nitride substrate, a diamond substrate, a silicon carbide substrate, a gallium oxide substrate, a boron nitride substrate, or a silicon crystal insulator substrate. The nitride epitaxial wafer according to claim 1, wherein the initial nucleation layer is an indium nitride layer. The nitride epitaxial wafer according to claim 3, wherein the initial nucleation layer has a structure formed by stacking a P-type indium nitride layer and an N-type indium nitride layer, and the P A depletion region is formed between the N-type indium nitride layer and the N-type indium nitride layer to prevent leakage current from passing through. The nitride epitaxial wafer according to claim 3, wherein the initial nucleation layer has a P-type indium nitride layer and an N-type indium nitride layer as a stack group, and multiple groups of the stack group are repeatedly stacked to form A depletion region is formed between the P-type indium nitride layer and the N-type indium nitride layer to prevent leakage current from passing through. The nitride epitaxial wafer according to claim 5, wherein the P-type indium nitride layer is doped with magnesium, and the magnesium concentration is 1E16~1E23 atoms/cm ³ , the N-type indium nitride layer is doped with silicon, and The concentration is 1E16~1E21atoms/cm ³ . The nitride epitaxial wafer according to claim 1, wherein the _{aluminum content of the lattice mismatch modulation layer (Al f} In _1-f N) gradually increases along the growth direction, and 0≦f<1. The nitride epitaxial wafer according to claim 1, wherein the at least one aluminum indium gallium nitride buffer layer includes a first aluminum indium gallium nitride buffer layer, a second aluminum indium gallium nitride buffer layer, and a third Aluminum indium gallium nitride buffer layer, and the chemical composition of the first aluminum indium gallium nitride buffer layer is In _g Al _e Ga _1-eg N, and 0.75≦e<1, 0<g≦0.25; the second nitrogen The chemical composition of the aluminum indium gallium buffer layer is In _h Al _d Ga _1-dh N, and 0.5≦d≦0.75, 0.25<h<0.5; and the chemical composition of the third aluminum indium gallium nitride buffer layer is In _i Al _c Ga _1-ci N, and 0.3≦c≦0.5, 0.5<i<0.7. The nitride epitaxial wafer according to claim 8, wherein the first aluminum indium gallium nitride buffer layer, the second aluminum indium gallium nitride buffer layer, and the third aluminum indium gallium nitride buffer layer are respectively undoped Doped, or at least one of carbon doping, iron doping, and magnesium doping, and a combination thereof. The nitride epitaxial wafer according to claim 9, wherein when the first aluminum indium gallium nitride buffer layer, the second aluminum indium gallium nitride buffer layer, and the third aluminum indium gallium nitride buffer layer are carbon-doped When miscellaneous, the carbon concentration is between 1E16~1E21 atoms/cm ³ ; when the first aluminum indium gallium nitride buffer layer, the second aluminum indium gallium nitride buffer layer, and the third aluminum indium gallium nitride buffer layer are made of iron When doped, the iron concentration is between 1E16~1E20 atoms/cm ³ ; when the first aluminum indium gallium nitride buffer layer, the second aluminum indium gallium nitride buffer layer, and the third aluminum indium gallium nitride buffer layer are When magnesium is doped, the magnesium concentration is between 1E16~1E20 atoms/cm ³ . The nitride epitaxial wafer according to claim 1, wherein the chemical composition of the high resistance layer is In _j Al _b Ga _1-bj N, and 0≦b≦0.1, 0<j≦0.9, and the high resistance layer is At least one of carbon doping, iron doping, and magnesium doping and combinations thereof. The nitride epitaxial wafer according to claim 11, wherein when the high resistance layer is doped with carbon, the carbon concentration is between 1E16~1E21 atoms/cm ³ ; when the high resistance layer is doped with iron, the concentration of iron is between 1E16 ~ 1E20atoms / cm ^3; when the high resistance layer is doped with magnesium, a magnesium concentration of between 1E16 ~ 1E20atoms / cm ^3. The nitride epitaxial wafer according to claim 1, wherein the chemical composition of the electron supply layer is In _x Al _y Ga _1-xy N, and 0≦y≦0.3, 0≦x≦0.3. The nitride epitaxial wafer according to claim 1, wherein the chemical composition of the covering layer is Al _z Ga _1-z N, and 0≦z≦0.3, and the covering layer is undoped or P-type doped, when When the covering layer is P-type doped, the doping element is magnesium, and the magnesium concentration is between 1E16~1E23 atoms/cm ³ . A method for manufacturing a nitride epitaxial wafer includes the following steps: providing a base substrate; forming an initial nucleation layer on the base substrate and forming a lattice mismatch modulation layer on the initial nucleation layer; A defect barrier layer is formed between the initial nucleation layer and the lattice mismatch modulation layer, and the defect barrier layer is silicon nitride or magnesium nitride; and at least one aluminum indium gallium nitride buffer layer is formed on On the lattice mismatch modulation layer; forming a high-resistance layer on the at least one aluminum indium gallium nitride buffer layer; forming an intrinsic gallium nitride layer on the high-resistance layer; forming an electron supply layer on the intrinsic On the gallium nitride layer; and forming a cover layer on the electron supply layer; wherein the initial nucleation layer and the defect barrier layer or the defect barrier layer and the lattice mismatch modulation layer are used as a stack , And repeatedly stack 2 to 10 sets of the stack to form a structure. The method for manufacturing a nitride epitaxial wafer according to claim 15, wherein the base substrate is a silicon substrate, an aluminum nitride substrate, a diamond substrate, a silicon carbide substrate, a gallium oxide substrate, a boron nitride substrate, or a silicon crystal insulator substrate. The method for manufacturing a nitride epitaxial wafer according to claim 15, wherein the step of forming the initial nucleation layer on the base substrate further includes the following steps: the first step, the growth temperature is 500-550°C, and the first step is A V/III ratio grows indium nitride; the second step, the growth temperature is 700~750℃, and the second V/III ratio grows indium nitride; and the third step, the growth temperature is 500~550℃, In addition, indium nitride is grown at the third V/III ratio, and the range of the first V/III ratio and the third V/III ratio is 0.5-50, and the range of the second V/III ratio is 500-3000. The method for manufacturing a nitride epitaxial wafer according to claim 15, wherein the step of forming the initial nucleation layer further includes stacking a P-type indium nitride layer and an N-type indium nitride layer to form the initial nucleation layer Steps, or take the p-type indium nitride The layer and the N-type indium nitride layer are used as a stacked group, and the step of stacking a plurality of the stacked groups to form the initial nucleation layer is repeated. The method for manufacturing a nitride epitaxial wafer according to claim 15, wherein in the step of forming the lattice mismatch modulation layer on the initial nucleation layer, the growth temperature is gradually increased from 500 to 550 degrees to 900 with time ~1100 degrees, and the aluminum content forming the lattice mismatch modulation layer gradually increases along its growth direction. The method for manufacturing a nitride epitaxial wafer according to claim 19, wherein in the step of forming the lattice mismatch modulation layer on the initial nucleation layer, the growth temperature has a temperature rise slope, and the temperature rise slope is 30 ~100°C/minute. The method for manufacturing a nitride epitaxial wafer according to claim 15, further comprising a step of forming a defect barrier layer between the initial nucleation layer and the lattice mismatch modulation layer, the defect barrier layer being Silicon nitride or magnesium nitride. The method for manufacturing a nitride epitaxial wafer according to claim 21, further comprising using the initial nucleation layer and the defect barrier layer or the defect barrier layer and the lattice mismatch modulation layer as a stack set , And repeat the steps of stacking a complex group of the stacking group. The method for manufacturing a nitride epitaxial wafer according to claim 15, wherein the method of forming each layer includes chemical vapor deposition or physical vapor deposition.

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