TWI741243B - Semiconductor devices and manufacturing methods thereof - Google Patents

Abstract

A semiconductor device is provided, having a composite silicon substrate and a nucleation layer. The composite silicon substrate includes a first silicon pad layer and a second silicon pad layer, where the second silicon pad layer is formed on the first silicon pad layer. The second silicon pad layer has a second resistance higher than a first resistance of the first silicon pad layer. The second silicon pad layer has a patterned top surface. The nucleation layer is formed on the patterned top surface, and has a top surface. The nucleation layer includes a group-III element.

Description

Semiconductor element and its manufacturing method

This specification is about a semiconductor device and its manufacturing method, especially a semiconductor device with a composite silicon substrate and its related manufacturing method.

Gallium nitride (GaN) power transistors are mainly used in power circuits as switches. They have the characteristics of high temperature resistance, high voltage, high current density, and high frequency operation. In the process of manufacturing GaN power devices, it is necessary to epitaxially grow some semiconductor layers on a substrate, and the quality of the epitaxial semiconductor layers will affect the characteristics of the GaN power devices. For example, when there is a lattice constant difference (lattice mismatch) between the substrate and the epitaxially grown semiconductor layer, it is easy to cause stress and the appearance of dislocations in the semiconductor layer material, and the dislocations easily deteriorate the semiconductor device significantly. Electrical performance. In addition, when there is a difference in thermal expansion coefficient between the substrate and the epitaxially grown semiconductor layer, stress will also be generated in the semiconductor layer material. Moreover, if the substrate has a good thermal conductivity, the heat generated during the operation of the semiconductor element can be quickly dissipated through the substrate, and the temperature of the semiconductor element is maintained not to be too high. Therefore, under ideal circumstances, the substrate should be the same material as the semiconductor layer on which the epitaxial growth will be made. When the substrate and the epitaxially grown semiconductor layer have the same material, it is called homoepitaxy.

In the prior art, non-GaN substrates are used to epitaxially manufacture GaN devices. When the substrate and the epitaxially grown semiconductor layer have different materials, it is called heteroepitaxy. However, it is not easy to completely eliminate the adverse effects caused by the difference in lattice constants and the difference in thermal expansion coefficient. In order to reduce these unwanted adverse effects, semiconductor templates for heteroepitaxial wafers have been developed. These semiconductor templates are generally multi-layer epitaxial structures, and the purpose is to optimize the characteristics of the semiconductor structures that are subsequently grown on them. For example, the GaN semiconductor layer in a GaN power transistor can be epitaxially formed on a silicon substrate through a semiconductor template. The relatively good thermal conductivity of the silicon substrate is used to reduce the operating temperature of the GaN power transistor. Although the semiconductor template can improve the subsequent epitaxial growth of the semiconductor layer and suppress the adverse effects caused by the difference in thermal expansion coefficient between the semiconductor template and the substrate, it is still one of the goals of continuous research and development by those skilled in the art.

In addition, when a GaN device is formed on a silicon substrate, the conductive properties of the silicon substrate can easily provide a leakage current path for the GaN device, which reduces the breakdown voltage of the GaN device.

The embodiment of the present invention provides a semiconductor device including a composite silicon substrate and a nucleation layer. The composite silicon substrate includes a first silicon liner layer and a second silicon liner layer, and the second silicon liner layer is disposed on the first silicon liner layer. The second resistance value of the second silicon liner layer is higher than the first resistance value of the first silicon liner layer. The second silicon liner layer has a patterned surface, and the nucleation layer is formed on the patterned surface and has an upper surface. And the nucleation layer contains a first element, which belongs to the third group.

An embodiment of the present invention provides a method for manufacturing a semiconductor device, including: providing a first silicon liner layer having a first resistance value; forming a second silicon liner layer on the first silicon liner layer, wherein the first silicon liner layer The second silicon liner layer includes a second resistance value greater than the first resistance value, and the second silicon liner layer includes a patterned surface; and a nucleation layer is formed on the patterned surface to produce an upper surface, wherein The core layer contains a first element, which belongs to the third group.

Hereinafter, exemplary embodiments of the present invention will be described in detail with reference to the drawings, so that those skilled in the art of the present invention can fully understand the spirit of the present invention. The present invention is not limited to the following embodiments, but can be implemented in other forms. In this specification, there are some same symbols, which represent elements with the same or similar structure, function, and principle, and those with general knowledge in the industry can infer it based on the teaching of this specification. For the sake of simplicity in the description, the elements with the same symbols will not be repeated.

FIG. 1 is a cross-sectional view of a semiconductor device 10a in an embodiment of the application. The semiconductor device 10a includes a composite silicon substrate 12a. A nucleation layer 16, a buffer structure 18, a channel layer 20, and a barrier layer 22, a source electrode 26, and a gate electrode 28 are sequentially formed on the composite silicon substrate 12a. , And a drain electrode 30 are formed on the barrier layer 22.

The composite silicon substrate 12a includes a stacked low-resistance silicon liner layer 12aa and a high-resistance silicon liner layer 12ab. Compared with the low-resistance silicon liner layer 12aa, the high-resistance silicon liner 12ab has a higher resistance value. In one embodiment, the low-resistance silicon liner layer 12aa has a flat surface Saa, and the high-resistance silicon liner layer 12ab has a patterned surface Sab.

The nucleation layer 16 is formed on the high resistance silicon liner layer 12ab, and substantially fills the patterned surface Sab. In one embodiment, the nucleation layer 16 has a substantially flat upper surface S16.

In one embodiment, the buffer structure 18 is from bottom to top and includes a buffer layer 18a, an interlayer 18b, and a buffer layer 18c. In one embodiment, the sheet resistance of the interlayer 18b is greater than the two sheet resistances of the buffer layers 18a and 18c. In another embodiment, the band gap of the interlayer 18b is larger than the band gap of the buffer layers 18a and 18c.

The channel layer 20 and the barrier layer 22 are sequentially formed on the buffer structure 18. The energy band gap of the barrier layer 22 is larger than the energy band gap of the channel layer 20. For example, the channel layer 20 includes indium gallium nitride (In _x Ga _(1-x) N), 0≦x<1, and the barrier layer 22 includes aluminum indium gallium nitride (Al _y In _z Ga _{(1-z) )} N), 0<y<1, 0≦z<1. Between the barrier layer 22 and the channel layer 20, because of the formation of spontaneous polarization (spontaneous polarization) and the different lattice constants of the two, the piezoelectric polarization effect (piezoelectric polarization) is formed, which is close to the barrier layer in the channel layer 20. At the interface 22, two-dimensional electron gas (2DEG) 24 is generated. The source electrode 26, the gate electrode 28 and the drain electrode 30 are respectively located on the barrier layer 22. The source electrode 26 and the drain electrode 30 form an ohmic contact with the barrier layer 22 and are electrically short-circuited to the two-dimensional electron gas 24. A schottky contact with a rectifying effect is formed between the gate 28 and the barrier layer 22. Applying a negative voltage to the gate 28 can deplete the two-dimensional electron gas 24 under the gate 28 and turn off the semiconductor device 10a.

The low-resistance silicon liner layer 12aa can be used to increase the strength of the composite silicon substrate 12a to avoid chipping during the temperature change of the epitaxial process.

The high energy band gap nucleation layer 16 and the high energy band gap and/or high resistance interlayer 18b in the buffer structure 18 can reduce the leakage current in the semiconductor device 10a and increase the breakdown voltage of the semiconductor device 10a. The high-resistance silicon lining layer 12ab can further block the leakage current flowing to the low-resistance silicon lining layer 12aa in the semiconductor device 10a, and increase the breakdown voltage of the semiconductor device 10a.

The patterned surface Sab of the high-resistance silicon liner layer 12ab can reduce the stress caused by the difference in thermal expansion coefficient between the nitride semiconductor stack (such as the aforementioned buffer structure 18, channel layer 20, and barrier layer 22, etc.) and the silicon substrate. Avoid cracks, substrate warping, or chipping in the semiconductor stack above it, so as to achieve high-thickness, high-quality epitaxial growth and large-size substrate growth.

Figure 2 shows a manufacturing method that can be used to manufacture the semiconductor device 10a of Figure 1.

Step 62 in Figure 2 provides a low-resistance silicon liner layer 12aa. In step 64, a high-resistance silicon liner layer 12ab is formed on the low-resistance silicon liner layer 12aa, and the resistance value of the high-resistance silicon liner layer 12ab is higher than that of the low-resistance silicon liner layer 12aa. For example, the high-resistance silicon liner layer 12ab has a sheet resistance value of 100 to 20000 Ω-cm, and the low-resistance silicon liner layer 12aa has a sheet resistance value of 0.001 to 10 Ω-cm.

Please refer to FIG. 3A and FIG. 3B, which respectively show two methods of forming a high-resistance silicon liner layer 12ab on a low-resistance silicon liner layer 12aa.

In FIG. 3A, the high-resistance silicon liner layer 12ab is originally independent of the low-resistance silicon liner layer 12aa. For example, originally the high-resistance silicon liner layer 12ab and the low-resistance silicon liner layer 12aa are two separate wafers. In FIG. 3A, the high-resistance silicon liner layer 12ab is fixed on the low-resistance silicon liner layer 12aa through an adhesive layer 11. The adhesive layer 11 includes a metal material, an insulating material, or the like. The metal material includes gold, copper, indium, tin, their alloys and/or their laminated layers. The insulating material includes oxide materials, such as aluminum oxide (Al ₂ O ₃ ), silicon nitride (SiN _x ), silicon _{oxide (SiO 2} ), aluminum nitride (AlN), titanium dioxide (TiO ₂ ), tantalum pentoxide (Tantalum Pentoxide, Ta ₂ O ₅ ) and other materials or combinations thereof. The insulating material can also be an organic polymer transparent plastic material, such as polyimide (polyimide), benzocyclobutene polymer (BCB), perfluorocyclobutyl polymer (PFCB), epoxy resin (Epoxy ), acrylic resin (Acrylic Resin), polyester resin (PET), polycarbonate resin (PC) and other materials or combinations thereof.

In another embodiment, FIG. 3B shows that the high-resistance silicon liner layer 12ab directly contacts the low-resistance silicon liner layer 12aa without an adhesive layer in between. For example, the high-resistance silicon lining layer 12ab and the low-resistance silicon lining layer 12aa are butted and pressed together, and after high-temperature annealing, the high-resistance silicon lining layer 12ab and the low-resistance silicon lining layer 12aa are joined. In another embodiment, a silicon substrate is doped and diffused so that the dopants are diffused to a depth in the silicon substrate to form a low-resistance silicon liner layer 12aa underneath and a high-resistance silicon liner above it. The composite silicon substrate 12a of the layer 12ab. Dopants may include, but are not limited to, boron, phosphorus, carbon, germanium, nitrogen, arsenic, gallium, or aluminum. By controlling the surface concentration of the dopant on the surface of the silicon substrate, the diffusion conditions (such as heating temperature and diffusion time), etc., the dopant can be diffused to a specific depth in the silicon substrate.

Next, proceed to step 66 of FIG. 2 to pattern the high-resistance silicon liner layer 12ab to produce a patterned surface Sab; refer to FIGS. 4A and 4B, which show the process of patterning the high-resistance silicon liner layer 12ab. First, a photoresist layer 82 is formed on the high resistance silicon liner layer 12ab by coating. Next, a lithography process is used to form a pattern on the photoresist layer 82, as shown in FIG. 4A. The pattern can be regular or irregular. The etching process can transfer the pattern on the photoresist layer 82 to the high-resistance silicon liner layer 12ab to produce a patterned surface Sab. In one embodiment, the patterned high-resistance silicon liner layer 12ab, as shown in FIG. 4B, has a pattern including regularly arranged convex structures P and concave structures H. Please refer to FIG. 4B. In one embodiment, the recessed structure H does not pass through the high-resistance silicon liner layer 12ab and exposes the low-resistance silicon liner layer 12aa, but the present invention is not limited to this.

For example, the average roughness (average maximum height drop) of the flat surface Saa of the low-resistance silicon liner layer 12aa is less than the average roughness of the patterned surface Sab of the high-resistance silicon liner 12ab. The average roughness of the flat surface Saa is less than 1 nanometer, and the average roughness of the patterned surface Sab is between 0.1 and 100 nanometers.

Then, step 68 of FIG. 2 is performed to form the nucleation layer 16 on the high resistance silicon liner layer 12ab to produce a substantially flat upper surface S16, as shown in FIG. 4C. For example, the average roughness of the upper surface S16 is less than 1 nanometer. In one embodiment, a metal organic chemical vapor deposition (MOCVD) or sputtering process may be used to deposit the nucleation layer 16 on the high resistance silicon liner layer 12ab. In one embodiment, the nucleation layer 16 is an aluminum nitride (AlN) layer with a thickness greater than 500 nm. In one embodiment, the nucleation layer 16 having a thickness of 500 nm or more can substantially fill the patterned surface Sab.

Step 70 in FIG. 2 selectively forms the buffer structure 18 on the nucleation layer 16, as shown in FIG. 4D. The buffer layer 18a, the interlayer 18b, and the buffer layer 18c are epitaxially formed on the nucleation layer 16 in sequence. The interlayer 18b may be AlN or AlGaN, AlGaN doped with carbon and/or iron, or GaN doped with carbon and/or iron. The buffer layers 18a and 18b may be AlGaN. The Al content of the buffer layer 18a is greater than the Al content of the buffer layer 18b. Although the buffer structure 18 in FIG. 4D only shows an interlayer 18b, the present invention is not limited to this. The buffer structure in another embodiment of the present invention has more than two interlayers, and each interlayer is sandwiched by two buffer layers.

Step 74 in FIG. 2 forms the channel layer 20, the barrier layer 22 and the electrodes (source 26, gate 28 and drain 30) on the buffer structure 18, as shown in FIG.

Figures 5A and 5B respectively illustrate top views of two embodiments of the photoresist layer 82 of Figure 4A, respectively, with regular patterns 84a and 84b. In FIG. 5A, the regular pattern 84a of the photoresist layer 82 has square holes 86 regularly arranged. According to the high-resistance silicon liner layer 12ab formed by the photoresist layer 82 in Figure 5A, the convex structures P in Figure 4B are connected to each other. In a top view, a recessed structure H is surrounded to isolate the recessed structures H from each other. . In FIG. 5B, the regular pattern 84a of the photoresist layer 82 has square pillars 88 arranged regularly. According to the high-resistance silicon liner layer 12ab formed by the photoresist layer 82 in Figure 5B, the recessed structures H in Figure 4B are connected to each other. P are isolated from each other.

Although the holes 86 and the posts 88 in FIGS. 5A and 5B all have a square appearance, the present invention is not limited to this. The holes 86 and the posts 88 can have any appearance, for example, they can be triangular, pentagonal, polygonal, circular, elliptical, and the like. The concave structure H and the convex structure P of the high-resistance silicon liner layer 12ab formed by the photoresist layer 82 are also triangular, pentagonal, polygonal, circular, or elliptical when viewed from above. In another embodiment, the holes 86 (or posts 88) are not connected to each other. For example, the holes 86 and the pillars 88 are all elongated and arranged in a staggered manner. In this way, the concave structure H and the convex structure P of the high-resistance silicon liner layer 12ab formed by the photoresist layer 82 are also elongated staggered as viewed from the top.

In one embodiment, the depth of the concave structure H and/or the height of the convex structure P is between 50-200 nm. In one embodiment, the maximum thickness of the high resistance silicon liner layer 12ab is smaller than the thickness of the low resistance silicon liner layer 12ba.

The patterned surface Sab of the high-resistance silicon liner layer 12ab in Figure 1 can be produced through a photolithography process, but the present invention is not limited to this. In another embodiment, an irregular patterned surface can be produced without the need for a lithography process.

Fig. 6 illustrates a cross-sectional view of a semiconductor device 10b. The semiconductor device 10b includes a composite silicon substrate 12b. The composite silicon substrate 12b has a nucleation layer 16, a buffer structure 18, a channel layer 20, a barrier layer 22, and electrodes (source 26, gate 28, and drain 30). The similar or the same parts of the semiconductor element 10b and the semiconductor element 10a can be known from the previous explanation of the semiconductor element 10a and will not be repeated here. The composite silicon substrate 12b includes a stacked low-resistance silicon liner layer 12ba and a high-resistance silicon liner layer 12bb. The difference from the high-resistance silicon liner layer 12ab in FIG. 1 is that the patterned surface Sbb of the high-resistance silicon liner layer 12bb in FIG. 6 is composed of irregular patterns.

FIGS. 7A to 7D show cross-sectional views of the semiconductor device 10b in FIG. 6 during some manufacturing processes.

FIG. 7A shows that the photoresist layer 90 is coated on the flat high-resistance silicon liner layer 12bb. At this time, the photoresist layer 90 has a flat surface. The material of the photoresist layer 90 can be an organic compound material, which is an organic layer.

The high-resistance silicon liner layer 12bb and the low-resistance silicon liner layer 12ba in FIG. 7A can be bonded to each other by an adhesive layer (not shown) according to the method shown in FIG. 3A; or according to the method shown in FIG. 3B, It is formed by bonding or thermal diffusion of dopants.

Next, a patterning step is performed on the high-resistance silicon liner layer 12bb. In one embodiment, a dry etching process is first performed on the photoresist layer 90, and the composite silicon substrate 12b in Figure 7A is placed in an inductively coupled plasma reactive ion etcher (ICP etcher), A carbonization step is performed on the surface of the photoresist layer 90. For example, the thermal energy generated by the particle bombardment in the ICP process is used to scorch the surface of the photoresist layer 90, thereby roughening the surface of the photoresist layer 90, as shown in FIG. 7B. In this way, the rough surface of the photoresist layer 90 will be composed of irregular patterns.

Then, the photoresist layer 90 and the high-resistance silicon lining layer 12bb can be etched continuously in the same ICP machine, and the rough surface of the photoresist layer 90 can be at least partially transferred to the high-resistance silicon lining layer 12bb. The surface, as shown in Figure 7C. In an embodiment of this step, the etching rate ratio RA of the ICP bombardment to the photoresist layer 90 and the high-resistance silicon liner layer 12bb may be between 0.9 and 1.1. When RA is equal to 1, it means that under ICP bombardment, the etching rate of the photoresist layer 90 is approximately equal to the etching rate of the high-resistance silicon liner layer 12bb. In this way, the rough surface of the photoresist layer 90 can be faithfully transferred to the high-resistance silicon liner layer 12bb to produce a patterned surface Sbb. At this time, the patterned surface Sbb of the high-resistance silicon liner layer 12bb will also be composed of irregular patterns.

In FIG. 7D, a nucleation layer 16 is formed on the high-resistance silicon liner layer 12bb, resulting in a substantially flat upper surface S16. The nucleation layer 16 may substantially fill the patterned surface Sbb.

Following the continuation of FIG. 7D, the semiconductor device 10b in FIG. 6 can be fabricated according to steps 70 and 74 in FIG. 2. The semiconductor element 10b also has a high-strength composite silicon substrate 12b and a high breakdown voltage, and can reduce the stress caused by the difference in thermal expansion coefficient between the semiconductor laminate and the composite silicon substrate 12b.

The low-resistance silicon liner layers 12aa and 12ba in FIGS. 1 and 6 have flat surfaces Saa and Sba, respectively, but the invention is not limited to this. In an embodiment of the present invention, both the low-resistance silicon liner layer and the high- and low-resistance silicon liner layer in the composite silicon substrate have a patterned surface.

Fig. 8 illustrates a cross-sectional view of a semiconductor device 10c. The semiconductor device 10c includes a composite silicon substrate 12c. The composite silicon substrate 12c has a nucleation layer 16, a buffer structure 18, a channel layer 20, a barrier layer 22, and electrodes (source 26, gate 28, and drain 30). The similar or the same parts of the semiconductor element 10c and the semiconductor element 10a can be known from the previous description of the semiconductor element 10a, and will not be repeated here. The composite silicon substrate 12c includes a low-resistance silicon lining layer 12ca and a high-resistance silicon lining layer 12cb. The difference between the flat surface Saa of the low resistance silicon liner layer 12aa in Figure 1 is that the low resistance silicon liner layer 12ca in Figure 8 has a patterned surface Sca, and the high resistance silicon liner layer 12cb is patterned above it. The patterned surface Sca conforms to the patterned surface Sca lined by the low-resistance silicon liner layer 12ca.

9A to 9D show cross-sectional views of the semiconductor device 10c in FIG. 8 during some manufacturing processes.

Figure 9A provides a low-resistance silicon liner layer 12ca. In FIG. 9B, a photoresist layer 96 after exposure and development is formed on the low-resistance silicon liner layer 12ca. The photoresist layer 96 has a patterned surface. The patterned surface of the photoresist layer 96 is transferred to the low-resistance silicon liner layer 12ca through an etching process, and the result is as shown in FIG. 9C. At this time, the low-resistance silicon liner layer 12ca has a patterned surface.

Next, the patterned low-resistance silicon liner layer 12ca in Figure 9C is ion-implanted or doped with impurities, and then through a diffusion process, the ions or impurities are diffused from the surface to a depth into the low-resistance silicon liner 12ca , And further forming a low-resistance silicon lining layer 12ca above and near the surface is a high-resistance silicon lining layer 12cb, and the upper and lower high- and low-resistance silicon lining layers constitute a composite silicon substrate 12c, as shown in FIG. 9D. In one embodiment, when high-resistance ions or impurities are isotropically implanted, doped and diffused, the patterned surface Scb of the high-resistance silicon liner layer 12cb will also conform to the pattern of the low-resistance silicon liner 12ca化surface Sca.

After continuation of FIG. 9D, steps 68, 70, and 74 in FIG. 2 can be followed to produce the semiconductor device 10c in FIG. 8. The semiconductor device 10c has a high-strength composite silicon substrate 12c and a high breakdown voltage, and can reduce the stress caused by the difference in thermal expansion coefficient between the semiconductor laminate and the composite silicon substrate 12c.

The patterned surface Sca of the low-resistance silicon liner layer 12ca in Figure 8 is defined by photolithography, but the invention is not limited to this. In another embodiment of the present invention, the surface of the low-resistance silicon liner layer can be roughened by a method similar to the roughening of the surface of the high-resistance silicon liner layer 12bb in Figures 7A, 7B, and 7C to produce a pattern化面。 The surface. Then, a high-resistance silicon liner layer is conformably formed on the low-resistance silicon liner layer.

The foregoing descriptions are only preferred embodiments of the present invention, and all equivalent changes and modifications made in accordance with the scope of the patent application of the present invention shall fall within the scope of the present invention.

10a, 10b, 10c: semiconductor element 11: adhesive layer 12a, 12b, 12c: composite silicon substrate 12aa, 12ba, 12ca: low resistance silicon liner 12ab, 12bb, 12cb: high resistance silicon liner 16: nucleation layer 18: Buffer structure 18a, 18c: buffer layer 18b: interlayer 20: channel layer 22: barrier layer 24: two-dimensional electron gas 26: source 28: gate 30: drain 62, 64, 66, 68, 70, 74: Step 82: photoresist layer 84a, 84b: regular pattern 86: hole 88: pillar 90, 96: photoresist layer H: recessed structure P: convex structure S16: upper surface Saa, Sba, Sca: flat surface Sab, Sbb, Scb: patterned surface

[Figure 1] is a cross-sectional view of a semiconductor device 10a according to an embodiment of the application. [Figure 2] This is a method of manufacturing a semiconductor device 10a according to an embodiment of the application. [FIG. 3A and FIG. 3B] respectively show a method of forming a high-resistance silicon liner layer 12ab on a low-resistance silicon liner layer 12aa. [Figures 4A and 4B] show the patterning process of the high-resistance silicon liner layer 12ab. [Figure 4C and Figure 4D] respectively show the formation of the nucleation layer 16 and the buffer structure 18. [FIG. 5A and FIG. 5B] are top views of two embodiments of the photoresist layer 82 in FIG. 4A, respectively. [Figure 6] is a cross-sectional view of a semiconductor device 10b according to an embodiment of the application. [FIG. 7A to FIG. 7D] shows cross-sectional views of the semiconductor device 10b in FIG. 6 in some manufacturing processes. [Figure 8] is a cross-sectional view of a semiconductor device 10c according to an embodiment of the application. [FIG. 9A to FIG. 9D] show cross-sectional views of the semiconductor device 10c in FIG. 8 during some manufacturing processes.

10a: Semiconductor components

12a: Composite silicon substrate

12aa: low resistance silicon liner

12ab: high resistance silicon liner

16: Nucleation layer

18: Buffer structure

18a, 18c: buffer layer

18b: mezzanine

20: Channel layer

22: barrier layer

24: Two-dimensional electron gas

26: Source

28: Gate

30: Dip pole

S16: Upper surface

Saa: flat surface

Sab: patterned surface

Claims (9)

A semiconductor device includes: a composite silicon substrate, which includes: a first silicon pad layer having a first resistance value; and a second silicon pad layer ( second silicon pad layer), disposed on the first silicon liner layer, having a second resistance value higher than the first resistance value, wherein the second silicon liner layer has a patterned surface; and a nucleation layer (nucleation layer), formed on the patterned surface, has an upper surface, the nucleation layer includes a first element, belonging to the third group; wherein, the patterned surface includes a plurality of convex structures or a plurality of depressions The structure, and/or the patterned surface is composed of irregular patterns. The semiconductor device described in claim 1, wherein the nucleation layer substantially fills the patterned surface and the thickness of the nucleation layer is greater than 500 nm, and/or the nucleation layer is made of aluminum nitride Floor. The semiconductor device described in item 1 of the scope of the patent application further includes: a buffer structure formed on the nucleation layer; and a channel layer formed on the buffer structure. The semiconductor device described in claim 3, wherein the buffer structure includes a first buffer layer, an interlayer, and a second buffer layer, and the interlayer is provided between the first buffer layer and the Between the second buffer layers, wherein the interlayer has a third resistance value greater than a fourth resistance value of the first buffer layer and a fifth resistance value of the second buffer layer; and/or, the interlayer has A band gap is larger than one of the first buffer layer and the second buffer layer. The semiconductor device described in item 4 of the scope of patent application, wherein the interlayer contains AlN or AlGaN; or contains AlGaN doped with carbon or GaN doped with carbon. The semiconductor device described in claim 1 further includes an adhesive layer located between the second silicon liner layer and the first silicon liner layer. The semiconductor device described in claim 1, wherein the patterned surface is a second patterned surface, the first silicon liner layer includes a first patterned surface, and the second patterned surface conforms to ( conformable to) the first patterned surface. A method for manufacturing a semiconductor device includes: providing a first silicon liner layer having a first resistance value; forming a second silicon liner layer on the first silicon liner layer, wherein the second silicon liner layer It includes a second resistance value greater than the first resistance value, and the second silicon liner layer includes a patterned surface; a nucleation layer is formed on the patterned surface to produce an upper surface, wherein the nucleation layer Containing a first element belonging to the third group; forming a buffer structure on the nucleation layer; and forming a channel layer on the buffer structure. The method for manufacturing a semiconductor device according to claim 8, wherein the method for forming the second silicon liner layer on the first silicon liner layer includes method one, method two, method three, or method four, wherein the method The step one includes: providing the second silicon liner layer; and fixing the second silicon liner layer on the first silicon liner layer; wherein, the step of the second method includes: on the second silicon liner layer Forming a photoresist layer; using a photolithography process to form a regular pattern on the photoresist layer; and using an etching process to transfer the regular pattern to the second silicon liner layer to produce the patterned surface; Wherein, the steps of method three include: forming a photoresist layer on the second silicon liner layer; using an ion bombardment process to coke the photoresist layer to form an irregular pattern; and using an etching process to The irregular pattern is transferred to the second silicon liner layer; wherein, the steps of the fourth method include: forming a photoresist layer on the first silicon liner layer with a patterned photoresist surface; and the patterned photoresist The surface is transferred to the first silicon liner layer; and the second silicon liner layer is formed on the first silicon liner layer.

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